Display device, method of manufacturing display device, and electronic device

Abstract

Disclosed are a display device, a method for manufacturing the display device, and an electronic device including the display device. The display device according to an embodiment includes: a substrate; a semiconductor layer on the substrate; a gate electrode overlapping a portion of the semiconductor layer; and a source electrode and a drain electrode electrically connected to another portion of the semiconductor layer, in which the semiconductor layer includes a first region including polycrystalline silicon and a second region including polycrystalline silicon and a first doping element, and the first region and the second region are disposed in a thickness direction of the substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. BACKGROUND

[0002] Generally, transistors are used in many electronic device fields for various purposes. For example, transistors are used as switching devices, driving devices, and light sensing devices, and can be used as components in various suitable electronic circuits. SUMMARY

[0003] Embodiments of the present disclosure provide a display device having reduced protrusions included on a polycrystalline semiconductor layer. Embodiments of the present disclosure provide a method for manufacturing a display device having reduced protrusions included on a polycrystalline semiconductor layer.

[0004] Embodiments of the present disclosure provide a display device including a substrate, a semiconductor layer on the substrate, a gate electrode superposed with a portion of the semiconductor layer, and a source electrode and a drain electrode electrically connected to another portion of the semiconductor layer, wherein the semiconductor layer includes a first region including polycrystalline silicon and a second region including polycrystalline silicon and a first doped element, and the first region and the second region are disposed in a thickness direction of the substrate.

[0005] The first doped element can include carbon.

[0006] A surface roughness (RMS) of an upper surface of the semiconductor layer can be about 2 nm to about 5 nm.

[0007] The first region can include the first doped element.

[0008] A content of the first doped element included in the first region can be less than a content of the first doped element included in the second region.

[0009] The semiconductor layer can further include a third region on the second region, and the third region can include polycrystalline silicon and a second doped element.

[0010] The second doped element can include argon.

[0011] At least one selected from the first region and the second region can further include the second doped element.

[0012] A content of the second doped element included in at least one selected from the first region and the second region can be less than a content of the second doped element included in the third region.

[0013] The display device can further include a light emitting element electrically connected to the drain electrode.

[0014] Another embodiment of the present disclosure provides a method for manufacturing a display device, the method including forming an amorphous silicon layer on a substrate; forming a polysilicon layer by irradiating a laser beam on the amorphous silicon layer; forming a sacrificial layer on the polysilicon layer; doping a first doping element to a first doped region of the polysilicon layer including an upper region; doping a second doping element to a second doped region located on an upper side of the first doped region; and etching the sacrificial layer and a portion of the polysilicon layer.

[0015] The first doping element can include carbon.

[0016] The second doping element can include argon.

[0017] In the step of forming the polysilicon layer by irradiating the laser beam, the polysilicon layer can include protrusions.

[0018] The protrusions can be doped with the second doping element.

[0019] The sacrificial layer can include silicon oxide.

[0020] The thickness of the sacrificial layer can be about 500 angstroms to about 1000 angstroms.

[0021] The etching process can use a buffer oxide etchant (BOE) solution.

[0022] The etching rate of the polysilicon layer doped with the second doping element can be faster than the etching rate of the polysilicon layer doped with the first doping element.

[0023] The acceleration voltage used in the process for doping the first and second doping elements can be about 20 KeV to about 40 keV.

[0024] According to embodiments of the present disclosure, a display device in which protrusions included in a polysilicon semiconductor layer are reduced can be provided. Further, embodiments can provide a method for manufacturing a display device that reduces protrusions in a polysilicon semiconductor layer of a display device. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, together with the specification, illustrate embodiments of the present disclosure and serve to explain the principles of embodiments of the present disclosure.

[0026] Figure 1 is a cross-sectional view of a display device according to an embodiment.

[0027] Figure 2 is a cross-sectional view of a semiconductor layer according to an embodiment.

[0028] Figure 3 is a cross-sectional view of a semiconductor layer according to an embodiment.

[0029] Figure 4 is a cross-sectional view of a semiconductor layer according to an embodiment.

[0030] Figures 5 to 15 Each of in FIGS. 1 to 3 is a cross-sectional view of a semiconductor layer generated by a manufacturing method according to an embodiment.

[0031] Figures 16 to 23 Each of in FIGS. 4 to 6 shows a characteristic according to an embodiment and a comparative example.

[0032] Figure 24 is a block diagram of an electronic device according to an embodiment.

[0033] Figure 25 shows a schematic view of an electronic device according to various embodiments. DETAILED DESCRIPTION

[0034] The subject matter of the present disclosure will now be described more fully with reference to the accompanying drawings in which embodiments of the disclosure are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various suitable ways, all without departing from the spirit or scope of the present disclosure.

[0035] Portions unrelated to the description are omitted in order to clearly describe the subject matter of the present disclosure, and the same elements are denoted by the same reference numerals throughout the specification.

[0036] The size and thickness of each configuration shown in the drawings can be arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, and the like can be exaggerated for clarity. The thickness of some layers and regions can be exaggerated for ease of description.

[0037] It should be understood that if an element such as a layer, film, region, or substrate is referred to as being "on" another element, such as a substrate, another element, including interposed elements, can also be present. In some embodiments, if an element such as a layer, film, region, or substrate is referred to as being "directly on" another element, such as a substrate, no interposed elements are present.

[0038] Unless explicitly stated otherwise, the words "comprise", "comprising", and variations such as "comprises" or "comprising" shall not be interpreted as implying any other element than those stated.

[0039] The phrase "in plan view" means viewing the target portion from the top, and the phrase "in cross-sectional view" means viewing a cross-section of the target portion cut vertically from the side.

[0040] Reference will now be made to Figure 1 and Figure 2A display device according to an embodiment is described. Figure 1 A cross-sectional view of a display device according to an embodiment is illustrated, Figure 2 A cross-sectional view of a semiconductor layer according to an embodiment is illustrated.

[0041] Referring to Figure 1 , the display device includes a substrate SUB. The substrate SUB can include a flexible material (such as plastic) that can be easily bent, folded, and / or rolled. Without being limited, the substrate SUB can include a rigid material.

[0042] A buffer layer BF can be on the substrate SUB. According to an embodiment, the buffer layer BF can be omitted. The buffer layer BF can include silicon nitride (SiN x ), silicon oxide (SiO2), and / or silicon oxynitride. The buffer layer BF can be located between the substrate SUB and the semiconductor layer ACT, can block impurities from the substrate SUB (e.g., to protect the substrate SUB from impurities) to improve characteristics of the polysilicon in a crystallization process of forming the polysilicon, and can planarize the substrate SUB to reduce stress of the semiconductor layer ACT located on the buffer layer BF.

[0043] The semiconductor layer ACT is on the buffer layer BF. The semiconductor layer ACT can include polysilicon. The semiconductor layer ACT includes a channel region CA, a source region SA, and a drain region DA. The source region SA and the drain region DA are on respective sides of the channel region CA.

[0044] The semiconductor layer ACT according to an embodiment will now be described in more detail with reference to Figure 1 and Figure 2 .

[0045] The semiconductor layer ACT can include a first region R1, a second region R2, and a third region R3. The first region R1 can be disposed closest to the substrate SUB, and the second region R2 and the third region R3 can be sequentially disposed on the first region R1. The first region R1, the second region R2, and the third region R3 can be distanced from the substrate SUB in the order of the first region R1, the second region R2, and the third region R3.

[0046] The first region R1, the second region R2, and the third region R3 can include polysilicon. The second region R2 can further include a first doping element doped into the polysilicon. The third region R3 can further include a second doping element doped into the polysilicon. The first doping element can include carbon (C), and the second doping element can include argon (Ar). If the first doping element and the second doping element are doped into the semiconductor layer ACT (e.g., when the first doping element and the second doping element are doped into the semiconductor layer ACT), the first doping element and the second doping element can not change characteristics of the semiconductor layer ACT.

[0047] According to embodiments, the first region R1, the second region R2, and the third region R3 can include the first dopant element. The content of the first dopant element included by the first region R1 and the third region R3 according to embodiments can be minimal, and can include very little of the first dopant element. For example, the first region R1 and the third region R3 according to embodiments can be substantially free of the first dopant element, such that the first dopant element is present only as incidental impurities as to the extent to which the first dopant element is present in the first region R1 and the third region R3. In some embodiments, the first region R1 and the third region R3 are completely free of the first dopant element.

[0048] The content of the first dopant element in the first region R1, the second region R2, and the third region R3 can differ from one another. For example, the content of the first dopant element in the second region R2 can be greater than the content of the first dopant element in the first region R1. The content of the first dopant element in the second region R2 can be greater than the content of the first dopant element in the third region R3.

[0049] According to embodiments, each of the first region R1, the second region R2, and the third region R3 can include the second dopant element. The content of the second dopant element in the first region R1 and the second region R2 according to embodiments can be minimal, and can include very little of the second dopant element. For example, the first region R1 and the second region R2 according to embodiments can be substantially free of the second dopant element, such that the second dopant element is present only as incidental impurities as to the extent to which the second dopant element is present in the first region R1 and the second region R2. In some embodiments, the first region R1 and the second region R2 are completely free of the second dopant element.

[0050] The content of the second dopant element in each of the first region R1, the second region R2, and the third region R3 can differ. For example, the content of the second dopant element in the third region R3 can be greater than the content of the second dopant element in the second region R2. The content of the second dopant element in the third region R3 can be greater than the content of the second dopant element in the first region R1.

[0051] The first region R1 can include polysilicon, and can include a sparse amount of the first dopant element and the second dopant element. The second region R2 can include polysilicon, and can include a relatively large amount of the first dopant element. The third region R3 can include polysilicon, and can include a relatively large amount of the second dopant element.

[0052] The upper surface of the semiconductor layer ACT can include protrusions or include protrusions and recesses. The surface roughness (RMS) of the upper surface of the semiconductor layer ACT can be about 2 nm to about 5 nm. The semiconductor layer ACT can provide an upper surface that is substantially planarized. Thus, the reliability of a transistor including the semiconductor layer ACT can be improved, and its characteristics can be improved.

[0053] Referring toFigure 1 A gate insulating layer GI is on the semiconductor layer ACT. The gate insulating layer GI can be a single layer or a multilayer including at least one selected from silicon nitride (SiN x ), silicon oxide (SiO2), and silicon oxynitride.

[0054] A gate electrode GE can be on the gate insulating layer GI, and the gate electrode GE can be a multilayer in which a metal layer including one selected from copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), and a molybdenum alloy is stacked (e.g., stacked in a thickness direction DR3).

[0055] An interlayer insulating layer IL1 is on the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer IL1 can include silicon nitride (SiN x ), silicon oxide (SiO2), and / or silicon oxynitride. An opening exposing both the source region SA and the drain region DA is provided in the interlayer insulating layer IL1.

[0056] A source electrode SE and a drain electrode DE are on the interlayer insulating layer IL1. The source electrode SE and the drain electrode DE are connected to the source region SA and the drain region DA of the semiconductor layer ACT through the openings formed in the interlayer insulating layer IL1.

[0057] A passivation layer IL2 is on the interlayer insulating layer IL1, the source electrode SE, and the drain electrode DE.

[0058] The passivation layer IL2 can cover and planarize the interlayer insulating layer IL1, the source electrode SE, and the drain electrode DE, and thereby a first electrode E1 is formed on the passivation layer IL2 without a step (or substantially with a step that can also be referred to as a step defect). The passivation layer IL2 can be made of an organic material such as a polyacrylate resin and / or a polyimide resin, or a stacked film of an organic material and an inorganic material.

[0059] A first electrode E1 is on the passivation layer IL2. The first electrode E1 is connected to the drain electrode DE through an opening of the passivation layer IL2.

[0060] A drive transistor configured with the gate electrode GE, the semiconductor layer ACT, the source electrode SE, and the drain electrode DE is connected to the first electrode E1, and supplies a drive current to the light emitting device ED. In addition to the drive transistor shown in Figure 1 In addition to the drive transistor shown in, the display device can include a switching transistor connected to a data line and transmitting a data voltage in response to a scan signal, and a compensation transistor connected to the drive transistor and compensating for a threshold voltage of the drive transistor in response to the scan signal.

[0061] A pixel definition layer PDL can be on the passivation layer IL2 and the first electrode E1, and can have a pixel opening superposed with the first electrode E1 and defining a light emitting area. The pixel definition layer PDL can include an organic material such as a polyacrylate resin and / or a polyimide resin and / or an inorganic material based on silicon dioxide. The pixel opening can have a planar shape substantially similar to the first electrode E1, can have a rhombic shape or an octagonal shape similar to a rhombic shape in a plan view, and is not limited thereto, can have various suitable shapes such as a quadrilateral other than a rhombic shape or another suitable polygon.

[0062] A light emitting layer EML is on the first electrode E1 and superposed with the pixel opening. The light emitting layer EML can be made of a low molecular organic material (e.g., a low molecular weight organic material) and / or a polymeric organic material such as PEDOT (poly 3,4-ethylenedioxythiophene). The light emitting layer EML can be a multi-layer further including at least one selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0063] The light emitting layer EML can be disposed mostly in the pixel opening, and can be disposed on or at a lateral side of the pixel definition layer PDL.

[0064] The second electrode E2 is on the light emitting layer EML. The second electrode E2 can be on the pixel, and can receive a common voltage through a common voltage transmitter of the non-display area.

[0065] The first electrode E1, the light emitting layer EML, and the second electrode E2 can constitute (e.g., be disposed) the light emitting device ED.

[0066] The first electrode E1 can be an anode as a hole injection electrode, and the second electrode E2 can be a cathode as an electron injection electrode. However, embodiments are not limited thereto, according to embodiments of a method of driving a display apparatus, the first electrode E1 can be a cathode, and the second electrode E2 can be an anode.

[0067] Holes and electrons are injected from the first electrode E1 and the second electrode E2 into the light emitting layer EML, and excitons as a combination of the injected holes and electrons fall from an excited state to a ground state and thus emit light.

[0068] An encapsulation layer (not shown) is on the second electrode E2. The encapsulation layer can cover side surfaces and an upper surface of the light emitting device ED to seal the display layer.

[0069] The light emitting element is susceptible to moisture and / or oxygen, and thus the encapsulation layer seals the display layer to block or reduce inflow of moisture and / or oxygen from the outside. The encapsulation layer can include multiple layers, can be made of a composite film including an inorganic film and an organic film, or can be made of three layers (e.g., three layers) in which a first inorganic film, an organic film, and a second inorganic film are sequentially formed.

[0070] A semiconductor layer according to an embodiment will now be described with reference to Figure 3 and Figure 4 A semiconductor layer according to an embodiment will now be described with reference to Figure 3 A cross-sectional view of a semiconductor layer according to an embodiment is shown, Figure 4 A cross-sectional view of a semiconductor layer according to an embodiment is shown.

[0071] With reference to Figure 3 , the semiconductor layer ACT can include a first region R1 and a second region R2. The first region R1 can be disposed closest to the substrate SUB, and the second region R2 can be sequentially on the first region R1. The first region R1 and the second region R2 can be sequentially farther from the substrate SUB.

[0072] The first region R1 and the second region R2 can include polysilicon. The second region R2 can further include a first doping element doped into the polysilicon. The first doping element can include carbon (C). The carbon can not affect physical properties of the semiconductor layer ACT including the polysilicon.

[0073] The first region R1 can further include a rare amount of the first doping element doped into the polysilicon. In a process for doping the first doping element into the second region R2, the rare amount of the first doping element can remain in the first region R1.

[0074] According to an embodiment, the first region R1 can not include the first doping element. For example, the first region R1 according to an embodiment can be substantially free of the first doping element, such that the first doping element exists only as an incidental impurity in terms of the extent to which the first doping element exists in the first region R1. In some embodiments, the first region R1 is completely free of the first doping element. The content of the first doping element in the second region R2 can be greater than the content of the first doping element in the first region R1.

[0075] The first region R1 and the second region R2 can further include a rare amount of a second doping element doped into the polysilicon. The second doping element can be doped into the polysilicon layer during a manufacturing process, and a region to which the second doping element is doped can be removed according to the manufacturing process. However, a rare amount of the second doping element can remain in the first region R1 and the second region R2. According to an embodiment, the first region R1 and the second region R2 can not include the second doping element. For example, the first region R1 and the second region R2 according to an embodiment can be substantially free of the second doping element, such that the second doping element exists only as incidental impurities in terms of the extent to which the second doping element exists in the first region R1 and the second region R2. In some embodiments, the first region R1 and the second region R2 are completely free of the second doping element.

[0076] The upper surface of the semiconductor layer ACT can include protrusions or recesses. The surface roughness (RMS) of the upper surface of the semiconductor layer ACT can be about 2 nm to about 5 nm. The semiconductor layer ACT can provide an upper surface that is substantially planarized. Accordingly, the reliability of a transistor including the semiconductor layer ACT can be improved, and characteristics can be improved.

[0077] Referring to Figure 4 The semiconductor layer ACT can include a first region R1. The first region R1 can include polysilicon.

[0078] The first region R1 can further include a rare amount of a first doping element doped into the polysilicon. The first doping element can be doped into a portion of the polysilicon layer during a process of manufacturing the semiconductor layer ACT, and the portion can be removed. However, a rare amount of the first doping element can remain in the first region R1 during a process for doping the first doping element. According to an embodiment, the first region R1 can not include the first doping element. For example, the first region R1 according to an embodiment can be substantially free of the first doping element, such that the first doping element exists only as incidental impurities in terms of the extent to which the first doping element exists in the first region R1. In some embodiments, the first region R1 is completely free of the first doping element.

[0079] The first region R1 can further include a rare amount of a second doping element doped into the polysilicon. The second doping element can be doped into a set region or a predetermined region of the polysilicon layer during a process of manufacturing the semiconductor layer ACT, and the set region or the predetermined region can be removed. However, a rare amount of the second doping element can remain in the first region R1 during a process of doping the second doping element. According to an embodiment, the first region R1 can not include the second doping element. For example, the first region R1 according to an embodiment can be substantially free of the second doping element, such that the second doping element exists only as incidental impurities in terms of the extent to which the second doping element exists in the first region R1. In some embodiments, the first region R1 is completely free of the first doping element.

[0080] The upper surface of the semiconductor layer ACT may include protrusions and / or depressions. The surface roughness (RMS) of the upper surface of the semiconductor layer ACT can be from about 2 nm to about 5 nm. The semiconductor layer ACT can provide a substantially planar upper surface. Therefore, the reliability of transistors including the semiconductor layer ACT can be improved, and their characteristics can be enhanced.

[0081] Now refer to Figures 5 to 15 A method for manufacturing a semiconductor layer according to an embodiment is described. Figures 5 to 15 Each of the figures shows a cross-sectional view of a semiconductor layer produced by the manufacturing method according to the embodiment. Descriptions of structures identical to those described above may be omitted.

[0082] Reference Figure 5 An amorphous silicon layer a-Si is formed on the buffer layer BF. For example... Figure 6 As shown in the figure, the laser beam irradiates the amorphous silicon layer a-Si.

[0083] like Figure 7 As shown, an amorphous silicon layer a-Si can be crystallized into a polycrystalline silicon layer p-Si according to a laser beam irradiation process. The laser beam irradiation process uses instantaneous high laser energy generated by applying a high-voltage discharge to a gas laser source, and uses this laser energy to thermally treat the amorphous silicon layer a-Si. The amorphous silicon layer a-Si undergoes a phase transition from solid to liquid and back to solid through the laser beam. During the liquid-to-solid phase transition, heat is released and a polycrystalline silicon layer p-Si, including protrusions PR, is formed.

[0084] like Figure 8 As shown, a sacrificial layer SL is formed on a polycrystalline silicon layer p-Si. The sacrificial layer SL may cover the upper surface of the polycrystalline silicon layer p-Si. The upper surface of the sacrificial layer SL may be planar. The sacrificial layer SL may, for example, comprise a silicon oxide material.

[0085] The thickness of the sacrificial layer SL can be from about 500 angstroms to about 1000 angstroms. However, the thickness is not limited to this and can be changed to any suitable thickness value in order to cover the upper surface of the polysilicon layer p-Si in a planar manner and perform an etching process.

[0086] like Figure 9 As shown, a first dopant element is doped into a first doped region DP1. The first dopant element may include carbon (C). The first doped region DP1 may include an upper surface S1 where the protrusions PR are removed from the polysilicon layer p-Si. The upper region of the polysilicon layer p-Si excluding the protrusions PR can be considered the first doped region DP1. The first doped region DP1 may include some of the protrusions PR.

[0087] The process for doping the first dopant element can be performed using an ion implantation apparatus. The doping process can be carried out at accelerating voltages from about 5 keV to about 80 keV and doping amounts from about 1.0E. 15 ions / cm 2 From approximately 1.0E 20 ions / cm 2 The acceleration voltage can be adjusted based on the thickness of the sacrificial layer SL, and is not limited to doping process conditions.

[0088] If carbon is doped into the first doped region DP1 (e.g., when carbon is doped into the first doped region DP1), the carbon can reduce the etching rate in the first doped region DP1 in the etching process described herein.

[0089] like Figure 10 As shown, a second dopant element is doped into the second doped region DP2. The second dopant element may include argon (Ar). If argon is doped into polysilicon (e.g., when argon is doped into polysilicon), the etching rate of the p-Si polysilicon layer can be increased. This can be achieved at an accelerating voltage of approximately 5 keV to approximately 80 keV and a doping amount of 1.0E. 15 ions / cm 2 To 1.0E 20 ions / cm 2 The doping process is performed under the specified conditions.

[0090] The second doped region DP2 may include protrusions PR of the p-Si polysilicon layer. The second doped region DP2 may include a sacrificial layer SL between adjacent protrusions PR. The second doped region DP2 may include the ends of the protrusions PR.

[0091] According to an embodiment, at least a portion of the first doped region DP1 and the second doped region DP2 may overlap. The first doped region DP1 and the second doped region DP2 may overlap each other on the upper surface of the polysilicon layer p-Si excluding the protrusion PR and the bottom surface of the protrusion PR. However, this is not a limitation; the first doped region DP1 and the second doped region DP2 may not overlap.

[0092] like Figure 11 As shown, if a doping process is performed on the first doped region DP1 and the second doped region DP2 (for example, when a doping process is performed on the first doped region DP1 and the second doped region DP2), the polysilicon layer may include a first region R1 containing polysilicon, a second region R2 in which a first doping element is doped, and a third region R3 in which a second doping element is doped.

[0093] However, a small or sparse amount of the first dopant element can be doped into the first region R1 and the third region R3, and a small or sparse amount of the second dopant element can be doped into the first region R1 and the second region R2.

[0094] As shown in Figure 12 , an etching process is performed using an etchant. The etching process can use a buffered oxide etchant (BOE). The BOE solution can be a mixed solution of 0.95% HF and 10% NH4F.

[0095] As shown in Figure 13 , a portion of the sacrificial layer SL and the protrusions PR can be removed according to the etching process. In some embodiments, referring to Figure 12 , the etching rate of the third region R3 including the protrusions PR in which argon is doped into the polysilicon can be relatively high. Accordingly, the protrusions PR can be easily etched. The etching rate of the second region R2 including the polysilicon in which carbon is doped can be relatively low. Accordingly, the semiconductor layer having a flat upper surface can be provided by selectively etching the protrusions PR protruding from the flat upper surface without significantly reducing the thickness of the semiconductor layer. Thereby, the semiconductor layer ACT as shown in Figure 2 can be provided. In some embodiments, the thickness of the semiconductor layer can be maintained by selectively etching the protrusions PR.

[0096] As shown in Figure 14 , if the etching process is performed (e.g., when the etching process is performed), the third region R3 can be removed. Thereby, as shown in Figure 3 , the semiconductor layer ACT including the first region R1 and the second region R2 can be provided.

[0097] In some embodiments, as shown in Figure 15 , if the etching process is performed (e.g., when the etching process is performed), the second region R2 and the third region R3 can be removed. According to some embodiments, as shown in Figure 4 , the semiconductor layer ACT including the first region R1 can be provided.

[0098] The characteristics of the semiconductor layer according to embodiments and comparative examples will now be described with reference to Figures 16 to 23 . Each of Figures 16 to 23 shows the characteristics of the semiconductor layer according to embodiments and comparative examples.

[0099] Figure 16 An image of the semiconductor layer manufactured according to the comparative example is shown. Since the semiconductor layer manufactured according to the comparative example includes protrusions, it was found that the surface roughness value was large, and a large number of protrusions were formed.

[0100] Figure 17An image of the semiconductor layer ACT manufactured according to the embodiment is shown. According to the embodiment, the protrusions formed by the laser beam irradiation process are substantially removed (or the formation of the protrusions is significantly reduced). For example, the substantially planarized semiconductor layer ACT can be provided by preventing or reducing over-etching of the polycrystalline semiconductor layer, and thereby selectively removing the protrusions (or reducing the formation of the protrusions).

[0101] Figure 18 An image of the protrusions of the semiconductor layer manufactured according to the comparative example is shown. The protrusions can have a height of about 1026 angstroms, and the recessed portions (e.g., depressions) can have a height of about 380 angstroms. Figure 18 An image in which the high and low portions of the semiconductor layer have a height difference of about 646 angstroms is shown. It is found that the upper surface of the semiconductor layer is not flat but uneven.

[0102] Figure 19 An image of the upper surface of the semiconductor layer ACT manufactured according to the embodiment is shown. With respect to the upper surface of the semiconductor layer ACT manufactured according to the embodiment, it is found that the high portion thereof has a thickness of about 504 angstroms, and the low portion thereof has a thickness of about 371 angstroms. For example, Figure 19 the height difference between the highest portion and the lowest portion in Figure 18 is 133 angstroms, which is significantly reduced compared to the comparative example of

[0103] Referring to Figures 20 to 23 , Figure 20 an injection of 10 KeV of argon gas is shown, Figure 21 an injection of 20 KeV of argon gas is shown, Figure 22 an injection of 30 KeV of argon gas is shown, Figure 23 an injection of 40 KeV of argon gas is shown.

[0104] Referring to Figure 20 , it is found that the argon ions are hardly doped into the semiconductor layer ACT and the buffer layer BF, and are doped only into the sacrificial layer SL. Referring to Figure 21 , it is found that, compared to Figure 20 , argon is also doped into the semiconductor layer ACT. By Figure 22 it is found that argon is not only doped into the sacrificial layer SL, but also into the semiconductor layer ACT, by Figure 23 it is found that argon is not only partially doped into the semiconductor layer ACT, but also partially doped into the buffer layer BF. For example, it is suitable or appropriate to inject a doping element of 20 KeV to 40 KeV.

[0105] A process of etching a polycrystalline silicon layer doped with argon will now be described with reference to Table 1. The acceleration voltage was 10 KeV and the doping amount was 1.0E 16 ions / cm 2Under the conditions specified in the embodiments, argon is implanted into polycrystalline silicon.

[0106] When the protrusions of the semiconductor layer comprising polysilicon are etched using a BOE solution similar to that used in the comparative example (e.g., when the protrusions of the semiconductor layer comprising polysilicon are etched using a BOE solution similar to that used in the comparative example), the etch rate of the sacrificial layer SL is 9.05 Å / s, and the etch rate of the semiconductor layer is approximately 1.66 Å / s. The etch ratio of the sacrificial layer SL to the semiconductor layer is found to be approximately 5.45.

[0107] The etching rate of the argon-doped polycrystalline silicon layer is known from the above embodiments. The etching rate of the sacrificial layer SL is approximately 12.54 Å / s, the etching rate of the semiconductor layer is approximately 4.31 Å / s, and the etching ratio between the sacrificial layer SL and the semiconductor layer is approximately 2.90. For example, it is known that as the etching rate of the argon-doped semiconductor layer increases, the etch selectivity ratio of the sacrificial layer SL / semiconductor layer decreases, and this is advantageous or beneficial for etching protrusions.

[0108] Table 1

[0109] Electronic devices may include display devices according to embodiments of the present disclosure. Electronic devices may be smartphones, televisions, monitors, tablet computers, electric vehicles, mobile phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), laptop computers, billboards, Internet of Things (IoT) devices, smartwatches, watch phones, or head-mounted displays (HMDs).

[0110] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include a display device, and may also include modules or devices having additional functions in addition to the display device.

[0111] Figure 24 This is a block diagram of an electronic device according to an embodiment. (Refer to...) Figure 24 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0112] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0113] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes an application program stored in the memory 13, a video data signal and / or an input control signal is transmitted to the display module 11, and the display module 11 can process the received signal to output video information through a display screen.

[0114] The power module 14 can include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device 10.

[0115] At least one of the components of the display module 11 can be included in the display device according to the above-described embodiments. In addition, some of the individual modules functionally included in a single module can be incorporated into the display device, while other individual modules can be provided separately from the display device. For example, the display device can include the display module 11, while the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 10 that are not part of the display device.

[0116] Figure 25 A schematic diagram of an electronic device according to various embodiments is shown.

[0117] Reference Figure 25 According to various electronic devices having a display device according to embodiments, not only image display electronic devices such as a smart phone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, a desktop monitor 10_1e, but also wearable electronic devices having a display module such as smart glasses 10_2a, a head-mounted display 10_2b, a smart watch 10_2c, and automotive electronic devices having a display module 10_3 such as a display module placed on a car dashboard, a center dashboard, a CID (center information display), an interior mirror display, etc. can be included.

[0118] According to the above-described embodiments, protrusions included by the polysilicon layer can be easily removed (or formation of the protrusions can be reduced). Since a semiconductor layer having a flat upper surface can be provided, the reliability of the transistor can be improved, and a stable display device can be provided. Although the subject matter of the present disclosure has been described in connection with what is presently considered to be the practical exemplary embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

[0119] Description of some symbols SUB: Substrate ACT: Semiconductor layer GE: gate electrode SE: source electrode DE: drain electrode R1: first region R2: second region R3: third region

Claims

1. A display device, the display device comprising: Base; A semiconductor layer is placed on the substrate. The gate electrode is stacked on a portion of the semiconductor layer; as well as The source and drain electrodes are electrically connected to another portion of the semiconductor layer. The semiconductor layer includes: a first region comprising polysilicon; and a second region comprising polysilicon and a first dopant element. The first region and the second region are disposed in the thickness direction of the substrate.

2. The display device according to claim 1, wherein: The first doping element includes carbon.

3. The display device according to claim 1, wherein: The surface roughness of the upper surface of the semiconductor layer is 2 nanometers to 5 nanometers.

4. The display device according to claim 1, wherein: The first region includes the first doped element.

5. The display device according to claim 4, wherein: The content of the first dopant element included in the first region is less than the content of the first dopant element included in the second region.

6. The display device according to claim 4, wherein: The semiconductor layer further includes a third region located on the second region, and The third region includes polycrystalline silicon and a second doped element.

7. The display device according to claim 6, wherein: The second doping element includes argon.

8. The display device according to claim 6, wherein: At least one of the first region and the second region further includes the second doping element.

9. The display device according to claim 8, wherein: The content of the second dopant element included in at least one of the first region and the second region is less than the content of the second dopant element included in the third region.

10. The display device according to claim 1, further comprising: The light-emitting element is electrically connected to the drain electrode.

11. A method for manufacturing a display device, the method comprising: An amorphous silicon layer is formed on the substrate; A polycrystalline silicon layer is formed by irradiating the amorphous silicon layer with a laser beam. A sacrificial layer is formed on the polycrystalline silicon layer; The first doping element is doped into the first doped region of the polycrystalline silicon layer, including the upper region; The second doping element is doped into the second doping region on the first doping region; as well as Etch a portion of the sacrificial layer and the polysilicon layer.

12. The method according to claim 11, wherein: The first doping element includes carbon.

13. The method according to claim 11, wherein: The second doping element includes argon.

14. The method of claim 11, wherein: In the step of forming the polycrystalline silicon layer by irradiating a laser beam The polycrystalline silicon layer includes protrusions.

15. The method of claim 14, wherein: The second dopant element is doped into the protrusion.

16. The method of claim 11, wherein: The sacrificial layer comprises silicon oxide.

17. The method of claim 11, wherein: The thickness of the sacrificial layer is 500 to 1000 angstroms.

18. The method according to claim 11, wherein: The etching rate of the polysilicon layer doped with the second dopant element is faster than that of the polysilicon layer doped with the first dopant element.

19. An electronic device, the electronic device including a display device, the display device comprising: Base; A semiconductor layer is placed on the substrate. The gate electrode is stacked on a portion of the semiconductor layer; as well as The source and drain electrodes are electrically connected to another portion of the semiconductor layer. The semiconductor layer includes: a first region comprising polycrystalline silicon; and The second region includes polycrystalline silicon and the first doped element, and The first region and the second region are disposed in the thickness direction of the substrate.

20. The electronic device according to claim 19, wherein, The electronic device is a smartphone, television, monitor, tablet computer, electric vehicle, mobile phone, tablet PC, mobile communication terminal, electronic notebook, e-book, portable multimedia player, navigation device, ultra-mobile PC, laptop computer, billboard, Internet of Things device, smartwatch, watch phone, or head-mounted display.

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