Display device and electronic device

Abstract

A display device and an electronic device are disclosed. The display device includes a display panel and a panel driver that drives the display panel. The panel driver receives a multi-frequency drive ("MFD") enable command from the host processor. In a first frame period, the panel driver receives, from the host processor, a boundary setting command indicating a boundary between a first panel region of the display panel and a second panel region of the display panel. In a second frame period following the first frame period, the panel driver receives input image data for the first panel region from the host processor, does not receive input image data for the second panel region from the host processor, drives the first panel region based on the input image data for the first panel region, and does not drive the second panel region.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, and more particularly to display devices that perform multi-frequency drive (“MFD”) and electronic devices including display devices. Background Technology

[0002] The reduction in power consumption can be beneficial for display devices used in portable devices such as smartphones and tablet computers. In display devices, power consumption can be reduced by using low-frequency driving technology that drives or refreshes the display panel at a frequency lower than the normal driving frequency. Summary of the Invention

[0003] In display devices employing low-frequency drive technology, when a still image is not displayed across the entire display panel, or when a still image is displayed only in a portion of the display panel, the entire display panel can be driven at the normal drive frequency. Therefore, in such cases, low-frequency drive can be omitted, and power consumption can be maintained without reducing power consumption.

[0004] Some embodiments provide a display device capable of driving a panel area at different frequencies in a mode in which input image data is not stored in a frame memory.

[0005] Some embodiments provide electronic devices capable of driving panel areas at different frequencies in modes in which input image data is not stored in a frame memory.

[0006] According to an embodiment, the display device includes a display panel and a panel driver for driving the display panel. In this embodiment, the panel driver receives a multi-frequency drive (“MFD”) enable command from a host processor. In this embodiment, during a first frame cycle, the panel driver receives a boundary setting command from the host processor indicating the boundary between a first panel area and a second panel area of ​​the display panel. In this embodiment, during a second frame cycle following the first frame cycle, the panel driver receives input image data for the first panel area from the host processor, does not receive input image data for the second panel area from the host processor, drives the first panel area based on the input image data for the first panel area, and does not drive the second panel area.

[0007] In one embodiment, during the second frame period, the panel driver may provide data voltage and scan signal to the first panel area to drive the first panel area, and may not provide data voltage and scan signal to the second panel area to not drive the second panel area.

[0008] In an embodiment, during the second frame cycle, the panel driver can drive the first panel area and the second panel area at different driving frequencies in a mode in which the input image data received from the host processor is not stored in the frame memory included in the display device.

[0009] In one embodiment, the first panel area may be an upper panel area positioned above a boundary indicated by a boundary setting command, and the second panel area may be a lower panel area positioned below the boundary. In this embodiment, during the second frame period, the panel driver may drive the upper panel area at a first driving frequency and drive the lower panel area at a second driving frequency lower than the first driving frequency.

[0010] In one embodiment, the panel driver may include an MFD enable register that stores the value of an MFD enable command. In this embodiment, the panel driver may generate an MFD enable signal based on the value stored in the MFD enable register.

[0011] In one embodiment, during the first portion of the effective period of the second frame period allocated to the first panel area, the panel driver may periodically receive horizontal synchronization data packets from the host processor. In another embodiment, during the second portion of the effective period of the second frame period allocated to the second panel area, the panel driver may not receive horizontal synchronization data packets from the host processor.

[0012] In one embodiment, during the second part of the effective period of the second frame cycle, the data channel between the host processor and the panel driver may have a low power state indicating that no data is being transmitted.

[0013] In one embodiment, the panel driver can compare first input image data received in a previous frame period with second input image data received in the current frame period, and can transmit a tearing effect signal to the host processor when the second input image data is different from the first input image data.

[0014] In one embodiment, the host processor may retransmit the second input image data to the panel driver in the next frame cycle in response to a tearing effect signal.

[0015] In an embodiment, the host processor may compare the number of first line data included in the first input image data with the number of second line data included in the second input image data, and may determine that the second input image data is different from the first input image data when the number of second line data is different from the number of first line data.

[0016] In an embodiment, the host processor may compare a first check value of the first input image data with a second check value of the second input image data when the number of second line data is equal to the number of first line data, and may determine that the second input image data is different from the first input image data when the second check value is different from the first check value.

[0017] According to an embodiment, the display device includes a display panel and a panel driver for driving the display panel. In this embodiment, the panel driver receives an MFD enable command from a host processor. In this embodiment, during a first frame cycle, the panel driver receives from the host processor a panel area update command indicating whether each of a plurality of panel areas is updated and at least one boundary setting command indicating at least one boundary between the plurality of panel areas. In this embodiment, during a second frame cycle following the first frame cycle, the panel driver receives from the host processor input image data for the panel area to be updated, specified by the panel area update command, among the plurality of panel areas, and drives the specified panel area to be updated based on the input image data.

[0018] In an embodiment, during the second frame period, the panel driver may not receive input image data from the host processor for the panel area specified by the panel area update command as not to be updated among the multiple panel areas, and may not drive the panel area specified as not to be updated.

[0019] In an embodiment, the number of bits in a panel area update command can be equal to the number of multiple panel areas.

[0020] In this embodiment, the number of bits in the panel area update command can be determined based on the number of panel areas into which the display panel is divided.

[0021] In one embodiment, the multiple panel areas may include a first panel area, a second panel area, and a third panel area. In this embodiment, the panel area update command may include a first bit indicating whether the first panel area is updated, a second bit indicating whether the second panel area is updated, and a third bit indicating whether the third panel area is updated.

[0022] In one embodiment, during the second frame cycle, the panel driver can drive multiple panel areas at different driving frequencies in a mode in which the input image data received from the host processor is not stored in the frame memory included in the display device.

[0023] In one embodiment, the panel driver can compare first input image data received in a previous frame period with second input image data received in the current frame period, and can transmit a tearing effect signal to the host processor when the second input image data is different from the first input image data.

[0024] In an embodiment, the panel driver may compare the first input image data with the second input image data based on a panel area update command, the number of line data included in the first input image data, the number of line data included in the second input image data, and the check values ​​of the first and second input image data.

[0025] According to an embodiment, the electronic device includes a host processor that provides input image data and a display device that displays an image based on the input image data. In this embodiment, the host processor transmits an MFD enable command to the display device. In this embodiment, during a first frame cycle, the host processor transmits a boundary setting command to the display device, indicating the boundary between a first panel area and a second panel area of ​​the display panel of the display device. In this embodiment, during a second frame cycle following the first frame cycle, the host processor transmits input image data for the first panel area to the display device but does not transmit input image data for the second panel area to the display device, and the display device drives the first panel area based on the input image data for the first panel area but does not drive the second panel area.

[0026] As described above, in the display device and electronic device according to the embodiments, the display device can receive MFD enable commands and boundary setting commands from the main processor, and can drive only a portion of the display panel by receiving input image data for only a portion of the display panel in subsequent frame cycles. Therefore, the display device can drive multiple panel areas at different driving frequencies in a mode in which the input image data is not stored in the frame memory (e.g., video mode). Attached Figure Description

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 This is a flowchart illustrating a method of operating the display device according to an embodiment.

[0030] Figure 3 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0031] Figure 4 This is a flowchart illustrating a method of operating the display device according to an embodiment.

[0032] Figure 5 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0033] Figure 6 This is a block diagram illustrating a display device according to an embodiment.

[0034] Figure 7 This is a flowchart illustrating a method of operating the display device according to an embodiment.

[0035] Figure 8This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0036] Figure 9 This is a flowchart illustrating a method of operating the display device according to an embodiment.

[0037] Figure 10 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0038] Figure 11 This is a block diagram illustrating a display device according to an embodiment.

[0039] Figure 12 This is a diagram illustrating an example of how a display panel is divided into multiple slices and how multiple slice update commands indicate whether the slices are being updated.

[0040] Figure 13 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0041] Figure 14 This is a block diagram illustrating an electronic device including a display device according to an embodiment. Detailed Implementation

[0042] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, similar reference numerals denote similar elements.

[0043] It will be understood that when an element is referred to as being "on" another element, that element can be directly on the other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediary element.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or section from another. Therefore, “first element,” “first component,” “first area,” “first layer,” or “first section” discussed below may be referred to as a second element, second component, second area, second layer, or second section without departing from the teachings herein.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the terms “a,” “an,” “the,” and “at least one” as used herein do not indicate a limitation of quantity and are intended to include both singular and plural forms. Thus, a reference to “the” element following a reference to “a” element in a claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprise” and / or “comprising” or “include” and / or “including” are used in this specification, they specify the presence of the stated features, areas, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the relative terms are intended to include different orientations of the device. For example, if a device in a figure is flipped, an element described as being “down” to other elements will subsequently be oriented “up” to other elements. Thus, the term “down” can include both “down” and “up” orientations depending on the specific orientation of the figure. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” other elements will subsequently be oriented “above” other elements. Thus, the term “below” or “under” can include both up and down orientations.

[0047] Taking into account the errors associated with measurements and a particular number of measurements (such as limitations of the measurement system), the terms “approximately” or “about” as used herein include the values ​​and mean within an acceptable range of deviation for a particular value as determined by a person of ordinary skill in the art. For example, “approximately” can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0051] refer to Figure 1 According to an embodiment, the display device 100 may include a display panel 110 comprising a plurality of pixels PX and a panel driver 120 for driving the display panel 110. In some embodiments, the panel driver 120 may include a data driver 130 for providing a data signal DS to the plurality of pixels PX, a scan driver 140 for providing a scan signal SS to the plurality of pixels PX, a transmit driver 150 for providing a transmit signal EM to the plurality of pixels PX, a frame memory 160, and a controller 170 for controlling the operation of the display device 100.

[0052] Display panel 110 may include data lines, scan lines, emission lines, and a plurality of pixels PX connected to the data lines, scan lines, and emission lines. In some embodiments, each pixel PX may include at least two transistors, at least one capacitor, and a light-emitting element, and display panel 110 may be a light-emitting display panel. In embodiments, for example, the light-emitting element may be an organic light-emitting diode (“OLED”), a nano-light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In other embodiments, display panel 110 may be a liquid crystal display (“LCD”) panel or any other suitable display panel.

[0053] Data driver 130 can generate a data signal DS based on a data control signal DCTRL received from controller 170 and output image data ODAT, and can provide the data signal DS to multiple pixels PX via data lines. The data control signal DCTRL may include a data enable signal DE indicating that the output image data ODAT is being transmitted. Additionally, in some embodiments, the data control signal DCTRL may include, but is not limited to, a horizontal start signal and a load signal. In some embodiments, data driver 130 can provide a data voltage VD corresponding to the output image data ODAT as the data signal DS to multiple pixels PX during a vertical active period, and can output a blanking voltage VB to the data lines during vertical blanking periods (e.g., vertical front porch period and vertical rear porch period). In some embodiments, data driver 130 and controller 170 can be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (“TED”). In other embodiments, data driver 130 and controller 170 can be implemented as separate integrated circuits.

[0054] The scan driver 140 can generate a scan signal SS based on a scan control signal SCTRL received from the controller 170, and can sequentially provide the scan signal SS to multiple pixels PX line by line via scan lines. The scan control signal SCTRL may include, but is not limited to, a scan start signal, a scan clock signal, etc. In some embodiments, the scan control signal SCTRL may also include an output enable signal OE for controlling the output of the scan signal SS. In embodiments, for example, the scan driver 140 may output the scan signal SS in response to an output enable signal OE with a high level, and may not output the scan signal SS in response to an output enable signal OE with a low level. In other embodiments, the output of the scan signal SS may be controlled by a scan clock signal. Furthermore, in some embodiments, the scan driver 140 may be integrated or formed in the display panel 110. In other embodiments, the scan driver 140 may be implemented using one or more integrated circuits.

[0055] The transmit driver 150 can generate a transmit signal EM based on a transmit control signal ECTRL received from the controller 170, and can sequentially provide the transmit signal EM to multiple pixels PX row by row via transmit lines. In some embodiments, the transmit control signal ECTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. In some embodiments, the transmit driver 150 may be integrated or formed in the display panel 110. In other embodiments, the transmit driver 150 may be implemented using one or more integrated circuits.

[0056] Controller 170 (e.g., a timing controller (“TCON”) may receive input image data IDAT, vertical sync data packet VSP, and horizontal sync data packet HSP from an external source (e.g., a host processor 200 (e.g., an application processor (“AP”), a graphics processing unit (“GPU”), or a graphics card)). Controller 170 may generate output image data ODAT provided to data driver 130 based on the input image data IDAT. Furthermore, in some embodiments, controller 170 may generate an internal vertical sync signal in response to the vertical sync data packet VSP, and may generate an internal horizontal sync signal in response to the horizontal sync data packet HSP. As described below, controller 170 of display device 100 according to an embodiment may also receive a multi-frequency drive (“MFD”) enable command MECMD and a boundary setting command BSCMD from host processor 200. In some embodiments, the input image data IDAT... AT, Vertical Synchronization Packet (VSP), Horizontal Synchronization Packet (HSP), MFD Enable Command (MECMD), and Boundary Setting Command (BSCMD) can be transmitted via the same data channel between the host processor 200 and the controller 170, but are not limited thereto. Furthermore, in some embodiments, the controller 170 may periodically receive an external synchronization signal ESYNC from the host processor 200 at each horizontal time, but is not limited thereto. Additionally, in some embodiments, the controller 170 may provide a tearing effect signal (TE) to the host processor 200. The controller 170 can control the data driver 130 by providing the data control signal DCTRL and the output image data ODAT to the data driver 130, control the scan driver 140 by providing the scan control signal SCTRL to the scan driver 140, and control the transmit driver 150 by providing the transmit control signal ECTRL to the transmit driver 150.

[0057] In the display device 100 according to an embodiment, in a first mode (e.g., command mode), the panel driver 120 can store the input image data IDAT received from the host processor 200 in the frame memory 160, and can drive the display panel 110 to display an image based on the input image data IDAT stored in the frame memory 160. Furthermore, in a second mode (e.g., video mode), the panel driver 120 can drive the display panel 110 to display an image based on the input image data IDAT received from the host processor 200 without storing the input image data IDAT received from the host processor 200 in the frame memory 160. Conventional display devices typically operate in the first mode (e.g., command mode) to perform MFD operations that drive the panel area at a different driving frequency. That is, in the second mode (e.g., video mode) where the input image data IDAT is not stored in the frame memory 160, conventional display devices may not perform MFD operations.

[0058] In the display device 100 according to the embodiment, not only in the first mode (e.g., command mode), but also in the second mode (e.g., video mode) in which the input image data IDAT received from the host processor 200 is not stored in the frame memory 160, the panel driver 120 can receive the MFD enable command MECMD and the boundary setting command BSCMD from the host processor 200, and can drive the first panel area PR1 and the second panel area PR2 of the display panel 110 at different driving frequencies based on the MFD enable command MECMD and the boundary setting command BSCMD.

[0059] In a second mode (e.g., video mode), panel driver 120 may receive an MFD enable command MECMD from host processor 200 indicating whether an MFD operation should be performed. In embodiments, for example, an MFD enable command MECMD with a first value may indicate the start of an MFD operation, and an MFD enable command MECMD with a second value may indicate the end of an MFD operation. In some embodiments, controller 170 of panel driver 120 may include an MFD enable register 180 storing the value of the MFD enable command MECMD. Controller 170 may generate an MFD enable signal based on the value stored in MFD enable register 180.

[0060] In this embodiment, during the first frame period after receiving the MFD enable command MECMD with a first value, the panel driver 120 may receive from the host processor 200 a boundary setting command BSCMD indicating the boundary BD between a first panel area PR1 and a second panel area PR2 of the display panel 110. The panel driver 120 may divide the display panel 110 into a first panel area PR1 and a second panel area PR2 with a boundary BD between them based on the boundary setting command BSCMD.

[0061] In the second frame period following the first frame period, panel driver 120 may receive input image data IDAT for the first panel area PR1 from host processor 200, but may not receive input image data IDAT for the second panel area PR2 from host processor 200. Furthermore, panel driver 120 may drive the first panel area PR1 based on the input image data IDAT for the first panel area PR1, but may not drive the second panel area PR2. That is, in the second frame period, to drive the first panel area PR1, data driver 130 of panel driver 120 may provide a data voltage VD to the first panel area PR1, and scan driver 140 of panel driver 120 may provide a scan signal SS to the first panel area PR1. However, in the second frame period, to not drive the second panel area PR2, data driver 130 of panel driver 120 may not provide a data voltage VD to the second panel area PR2, and scan driver 140 of panel driver 120 may not provide a scan signal SS to the second panel area PR2.

[0062] Therefore, the display device 100 according to the embodiment can drive the first panel area PR1 and the second panel area PR2 at different driving frequencies in a mode in which the input image data IDAT received from the host processor 200 is not stored in the frame memory 160. In some embodiments, the first panel area PR1 may be an upper panel area positioned above the boundary BD indicated by the boundary setting command BSCMD, and the second panel area PR2 may be a lower panel area positioned below the boundary BD. The panel driver 120 can drive the first panel area PR1 or the upper panel area at a first driving frequency, and can drive the second panel area PR2 or the lower panel area at a second driving frequency lower than the first driving frequency.

[0063] Figure 2 This is a flowchart illustrating a method of operating the display device according to an embodiment, and Figure 3 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0064] refer to Figure 1 and Figure 2 In this embodiment, the host processor 200 can transmit the MFD enable command MECMD to the display device 100, and the display device 100 can receive the MFD enable command MECMD from the host processor 200 (S310).

[0065] In an embodiment, for example, such as Figure 3As illustrated in the diagram, each frame period FP can include a vertical active period VAP in which the data voltage VD is provided to the display panel 110, a vertical rear corridor period VBP preceding the vertical active period VAP, and a vertical front corridor period VFP following the vertical active period VAP. Furthermore, at the beginning of each frame period FP, the panel driver 120 can receive a vertical synchronization data packet VSP as an interface signal IFS between the host processor 200 and the display device 100, and can generate an internal vertical synchronization signal IVSYNC in response to the vertical synchronization data packet VSP. Additionally, the panel driver 120 can receive a horizontal synchronization data packet HSP as an interface signal IFS at each horizontal time.

[0066] During the vertical active period VAP of the frame period FP preceding the start of MFD operation, panel driver 120 may receive input image data IDAT or frame data FDAT for the entire area of ​​display panel 110 from host processor 200, and may provide data voltage VD and scan signal SS to the entire area of ​​display panel 110 based on frame data FDAT to drive the entire area of ​​display panel 110. During the vertical front porch period VFP following the vertical active period VAP, panel driver 120 may receive an MFD enable command MECMD with a first value (e.g., a value of "1") indicating the start of MFD operation from host processor 200, and may store the first value of the MFD enable command MECMD in MFD enable register 180. In subsequent first frame period FP1, second frame period FP2, and third frame period FP3, panel driver 120 may generate an MFD enable signal MFD_EN with a high level based on the first value stored in MFD enable register 180, and may perform MFD operation.

[0067] In the first frame period FP1 after transmitting the MFD enable command MECMD with a first value, the host processor 200 can transmit the boundary setting command BSCMD indicating the boundary BD between the first panel area PR1 and the second panel area PR2 to the display device 100, and the display device 100 can receive the boundary setting command BSCMD from the host processor 200 (S320).

[0068] In an embodiment, for example, such as Figure 3As illustrated in the diagram, during the vertical active period (VAP) of the first frame period (FP1) after receiving the MFD enable command MECMD with a first value, panel driver 120 can receive frame data FDAT and drive the entire area of ​​display panel 110 based on the frame data FDAT. In an embodiment, for example, controller 170 can provide frame data FDAT as output image data ODAT to data driver 130, provide a data enable signal DE with a high level throughout the vertical active period (VAP), and data driver 130 can provide data voltage VD to the entire area of ​​display panel 110. Furthermore, controller 170 can provide an output enable signal OE with a high level to scan driver 140 throughout the vertical active period (VAP), and scan driver 140 can provide scan signal SS to the entire area of ​​display panel 110.

[0069] In some embodiments, the vertical front porch period VFP of the first frame period FP1 can be extended to a Δfront porch period ΔVFP corresponding to any given time. When the vertical front porch period VFP is extended by the Δfront porch period ΔVFP, the driving frequency of the display panel 110 can be reduced. Furthermore, in some embodiments, in the Δfront porch period ΔVFP, such as Figure 3 As illustrated in the diagram, the data channel between the host processor 200 and the display device 100 can be in a low-power state (LPS) indicating that no data is being transmitted. In an embodiment, for example, the data channel includes a positive data line and a negative data line, and both the positive and negative data lines can be fixed at a high voltage level in the low-power state (LPS), but are not limited thereto.

[0070] Furthermore, during the vertical front porch period VFP or the Δ front porch period ΔVFP of the first frame period FP1, the panel driver 120 may receive from the host processor 200 a boundary setting command BSCMD indicating the boundary BD between the first panel area PR1 and the second panel area PR2.

[0071] In the second frame period FP2 following the transmission boundary setting command BSCMD, the host processor 200 may transmit the input image data IDAT for the first panel area PR1 only to the display device 100, and may not transmit the input image data IDAT for the second panel area PR2 to the display device 100. The display device 100 may receive the input image data IDAT for the first panel area PR1 only from the host processor 200, and may not receive the input image data IDAT for the second panel area PR2 from the host processor 200 (S330). Furthermore, in the frame period, the display device 100 may drive only the first panel area PR1 based on the input image data IDAT (S340). That is, the display device 100 may drive the first panel area PR1 based on the input image data IDAT for the first panel area PR1, and may not drive the second panel area PR2.

[0072] In an embodiment, for example, such as Figure 3 As illustrated in the diagram, during the vertical active period VAP of the second frame period FP2 following the first frame period FP1 of the transmission boundary setting command BSCMD, panel driver 120 may receive input image data IDAT_PR1 for the first panel area PR1 only from host processor 200, and may drive the first panel area PR1 only based on the input image data IDAT_PR1. In an embodiment, for example, controller 170 may provide the input image data IDAT_PR1 for the first panel area PR1 as output image data ODAT to data driver 130, and may provide a data enable signal DE with a high level in the first portion of the vertical active period VAP allocated to the first panel area PR1. Data driver 130 may provide a data voltage VD to the first panel area PR1 based on the output image data ODAT. Furthermore, controller 170 may provide an output enable signal OE with a high level in the first portion of the vertical active period VAP allocated to the first panel area PR1 to scan driver 140, and scan driver 140 may provide a scan signal SS to the first panel area PR1. Furthermore, in the first part of the vertical active period VAP allocated to the first panel area PR1, the panel driver 120 can periodically receive horizontal synchronization packets HSP from the host processor 200 at each horizontal time.

[0073] However, during the vertical active period (VAP) of the second frame period FP2, panel driver 120 may not receive input image data IDAT for the second panel area PR2 from host processor 200, and may not drive the second panel area PR2. In an embodiment, for example, controller 170 may provide a data enable signal DE with a low level during the second portion of the vertical active period (VAP) allocated to the second panel area PR2, and data driver 130 may not provide data voltage VD to the second panel area PR2. Furthermore, controller 170 may provide an output enable signal OE with a low level to scan driver 140 during the second portion of the vertical active period (VAP) allocated to the second panel area PR2, and scan driver 140 may not provide scan signal SS to the second panel area PR2. Additionally, during the second portion of the vertical active period (VAP) allocated to the second panel area PR2, panel driver 120 may not receive horizontal synchronization data packets HSP from host processor 200. In some embodiments, during the second portion of the vertical active period VAP allocated to the second panel area PR2 and during the vertical front porch period VFP following the vertical active period VAP, the data channel between the host processor 200 and the panel driver 120 of the display device 100 may be in a low power state LPS indicating no data transmission.

[0074] Furthermore, in the third frame period FP3 following the second frame period FP2, similar to the second frame period FP2, the panel driver 120 can receive input image data IDAT_PR1 from the host processor 200 for the first panel area PR1 only, and can drive only the first panel area PR1. Therefore, the second panel area PR2 can be driven at a lower driving frequency DF_PR2 than the driving frequency DF_PR1 of the first panel area PR1. In an embodiment, for example, the first panel area PR1 can be driven at a driving frequency DF_PR1 of approximately 60 Hz in the first frame period FP1, and can be driven at a driving frequency DF_PR1 of approximately 120 Hz in each of the second frame period FP2 and the third frame period FP3. However, the second panel area PR2 can be driven at a driving frequency DF_PR2 of approximately 30 Hz in the first frame period FP1, the second frame period FP2, and the third frame period FP3.

[0075] In some embodiments, such as Figure 3 As illustrated in the diagram, during the third frame period FP3, while the panel driver 120 also receives a portion of the input image data IDAT for the second panel area PR2, IDAT_PR2_P, from the host processor 200, the panel driver 120 may also drive a portion of the second panel area PR2, but is not limited thereto.

[0076] Furthermore, during the vertical front porch period (VFP) of the third frame period (FP3), the panel driver 120 can receive an MFD enable command MECMD with a second value (e.g., a value of "0") indicating the end of MFD operation from the host processor 200, and can store the second value of the MFD enable command MECMD in the MFD enable register 180. In subsequent frame periods (FP), the panel driver 120 can generate an MFD enable signal MFD_EN with a low level based on the second value stored in the MFD enable register 180, and can drive the entire area of ​​the display panel 110.

[0077] As described above, the display device 100 according to the embodiment can receive an MFD enable command MECMD and a boundary setting command BSCMD from the host processor 200, and can drive only a portion of the display panel 110 based on the MFD enable command MECMD and the boundary setting command BSCMD. Therefore, the display device 100 can drive the first panel area PR1 and the second panel area PR2 at different drive frequencies DF_PR1 and DF_PR2, respectively, in a mode in which the input image data IDAT is not stored in the frame memory 160 (e.g., video mode).

[0078] Figure 4 This is a flowchart illustrating a method of operating the display device according to an embodiment, and Figure 5This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0079] In addition to the display device 100 providing the host processor 200 with the tearing effect signal TE for refreshing the display panel 110, Figure 4 The method can be with Figure 2 The methods are similar.

[0080] refer to Figure 1 and Figure 4 In this embodiment, the host processor 200 can transmit the MFD enable command MECMD and the boundary setting command BSCMD to the display device 100 (S310 and S320), and can transmit input image data IDAT for the first panel area PR1 only in subsequent frame cycles (S330). In this case, the display device 100 can drive only the first panel area PR1 in subsequent frame cycles (S340).

[0081] Furthermore, the panel driver 120 of the display device 100 can compare first input image data received in a previous frame period with second input image data received in the current frame period (S350 and S360). When the second input image data differs from the first input image data, the panel driver 120 can transmit a tearing effect signal TE to the host processor 200 (S370). In some embodiments, the panel driver 120 can compare the number of first line data included in the first input image data with the number of second line data included in the second input image data to compare the first input image data and the second input image data (S350). In this embodiment, when the number of second line data differs from the number of first line data, the panel driver 120 can determine that the second input image data is different from the first input image data. Furthermore, in some embodiments, when the number of second line data is equal to the number of first line data, the panel driver 120 can also compare a first check value of the first input image data with a second check value of the second input image data (S360). In embodiments, for example, each of the first check value and the second check value may be a cyclic redundancy check (“CRC”) value or a checksum value, but is not limited thereto. In this embodiment, when the second check value differs from the first check value, the panel driver 120 can determine that the second input image data is different from the first input image data. In the next frame cycle, the host processor 200 can retransmit the second input image data to the panel driver 120 in response to the tearing effect signal TE (S380), and the panel driver 120 can drive the display panel 110 based on the retransmitted second input image data (S390).

[0082] In an embodiment, for example, such as Figure 5As illustrated in the diagram, when an MFD enable command MECMD with a first value (e.g., a value of "1") is received in the first frame period FP1, the panel driver 120 can perform MFD operations in subsequent second frame periods FP2, third frame periods FP3, fourth frame periods FP4, fifth frame periods FP5, and sixth frame periods FP6. When frame data FDAT is received as input image data IDAT in the second frame period FP2, the panel driver 120 can drive the entire area of ​​the display panel 110 by providing a data voltage VD corresponding to the frame data FDAT to the display panel 110. Furthermore, the panel driver 120 can compare the frame data FDAT received in the first frame period FP1 with the frame data FDAT received in the second frame period FP2. In some embodiments, the panel driver 120 can compare the number of line data and the check value of the frame data FDAT in the first frame period FP1 with the number of line data and the check value of the frame data FDAT in the second frame period FP2, respectively. When the number of line data and the check value are the same, the panel driver 120 may not transmit the tearing effect signal TE to the host processor 200. When the first input image data IDAT1 is received in the third frame period FP3, the panel driver 120 can drive a portion of the display panel 110 by providing a data voltage VD corresponding to the first input image data IDAT1 to the display panel 110. Furthermore, the panel driver 120 can compare the frame data FDAT received in the second frame period FP2 with the first input image data IDAT1 received in the third frame period FP3. In an embodiment, for example, the number of line data and the check value in the second frame period FP2 can be compared with the number of line data and the check value in the third frame period FP3 respectively. When the number of line data included in the first input image data IDAT1 received in the third frame period FP3 is less than the number of line data included in the frame data FDAT received in the second frame period FP2, the panel driver 120 can transmit the tearing effect signal TE to the host processor 200.

[0083] In response to the tearing effect signal TE, in the fourth frame cycle FP4, the host processor 200 can retransmit the first input image data IDAT1 of the third frame cycle FP3 to the display device 100. The panel driver 120 can then drive a portion of the display panel 110 again based on the first input image data IDAT1. In this case, the step efficiency phenomenon where the display panel 110 does not have the desired brightness when the brightness changes between multiple frame cycles can be significantly reduced or effectively prevented. Furthermore, when the number of line data and the check value are the same in the third frame cycle FP3 and the fourth frame cycle FP4, the panel driver 120 may not transmit the tearing effect signal TE to the host processor 200.

[0084] Furthermore, when the second input image data IDAT2 is received in the fifth frame period FP5, the panel driver 120 can drive a portion of the display panel 110 by providing a data voltage VD corresponding to the second input image data IDAT2 to the display panel 110. Additionally, the panel driver 120 can compare the first input image data IDAT1 received in the fourth frame period FP4 with the second input image data IDAT2 received in the fifth frame period FP5. In an embodiment, for example, the number and check value of line data in the fourth frame period FP4 can be compared with the number and check value of line data in the fifth frame period FP5, respectively. When the number of line data in the fourth frame period FP4 and the fifth frame period FP5 are different from each other, or when the check values ​​in the fourth frame period FP4 and the fifth frame period FP5 are different from each other, the panel driver 120 can transmit a tearing effect signal TE to the host processor 200.

[0085] In response to the tearing effect signal TE, in the sixth frame cycle FP6, the host processor 200 can retransmit the second input image data IDAT2 from the fifth frame cycle FP5 to the display device 100. The panel driver 120 can then drive a portion of the display panel 110 again based on the second input image data IDAT2. In this case, step efficiency phenomena can be significantly reduced or effectively prevented. Furthermore, when the number of line data and the check value are the same in the fifth frame cycle FP5 and the sixth frame cycle FP6, the panel driver 120 may not transmit the tearing effect signal TE to the host processor 200. Moreover, when the panel driver 120 receives an MFD enable command MECMD with a second value (e.g., a value of "0") from the host processor 200 in the sixth frame cycle FP6, the panel driver 120 can drive the entire area of ​​the display panel 110 in the subsequent seventh frame cycle FP7.

[0086] Figure 6 This is a block diagram illustrating a display device according to an embodiment.

[0087] refer to Figure 6 The display device 400 according to an embodiment may include a display panel 410 and a panel driver 420 for driving the display panel 410. In some embodiments, the panel driver 420 may include a data driver 430, a scan driver 440, a transmit driver 450, a frame memory 460, and a controller 470. Besides the display panel 410 being divided into a first panel area PR1, a second panel area PR2, and a third panel area PR3, Figure 6 The display device 400 may have the same as Figure 1 The display device 100 has a similar configuration and similar operation.

[0088] In the display device 400 according to an embodiment, the panel driver 420 may receive an MFD enable command MECMD from the host processor 200 and perform MFD operations in response to the MFD enable command MECMD. Furthermore, during a first frame period, the panel driver 420 may receive from the host processor 200: a panel area update command PRUCMD indicating whether each of the first panel area PR1, the second panel area PR2, and the third panel area PR3 is updated; and a first boundary setting command BSCMD1 and a second boundary setting command BSCMD2 respectively indicating the first boundary BD1 and the second boundary BD2 between the first panel area PR1, the second panel area PR2, and the third panel area PR3. In some embodiments, the number of bits in the panel area update command PRUCMD may be substantially equal to the number of the plurality of panel areas. Furthermore, each bit of the panel area update command PRUCMD may indicate whether the corresponding panel area is updated. In embodiments, for example, when the display panel 410 is divided into a first panel area PR1, a second panel area PR2, and a third panel area PR3, the panel area update command PRUCMD may have a first bit indicating whether the first panel area PR1 is updated, a second bit indicating whether the second panel area PR2 is updated, and a third bit indicating whether the third panel area PR3 is updated. Furthermore, in some embodiments, the number of bits in the panel area update command PRUCMD may be determined based on the number of panel areas into which the display panel 410 is divided.

[0089] In the second frame period following the first frame period, the panel driver 420 may receive from the host processor 200 input image data IDAT for the panel areas specified (or indicated by) the panel area update command PRUCMD to be updated in the first panel area PR1, the second panel area PR2, and the third panel area PR3, and may drive only the panel areas specified to be updated based on the input image data IDAT. That is, in the second frame period, the panel driver 420 may not receive input image data IDAT from the host processor 200 for the panel areas not specified by the panel area update command PRUCMD to be not updated, and may not drive the panel areas specified not to be updated.

[0090] Therefore, the display device 400 according to the embodiment can drive the first panel area PR1, the second panel area PR2, and the third panel area PR3 at different driving frequencies not only in a first mode (e.g., command mode) in which the input image data IDAT received from the host processor 200 is stored in the frame memory 460, but also in a second mode (e.g., video mode) in which the input image data IDAT received from the host processor 200 is not stored in the frame memory 460.

[0091] Figure 7 This is a flowchart illustrating a method of operating the display device according to an embodiment, and Figure 8 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0092] refer to Figure 6 , Figure 7 and Figure 8 In an embodiment, the host processor 200 can transmit the MFD enable command MECMD to the display device 400, and the display device 400 can receive the MFD enable command MECMD from the host processor 200 (S510). In an embodiment, for example, during the vertical front porch period VFP of the frame period FP before the start of MFD operation, the panel driver 420 can receive the MFD enable command MECMD with a first value (e.g., a value of "1") indicating the start of MFD operation from the host processor 200, and can store the first value of the MFD enable command MECMD in the MFD enable register 480. In subsequent first frame periods FP1, second frame periods FP2, third frame periods FP3, fourth frame periods FP4, and fifth frame periods FP5, the panel driver 420 can generate an MFD enable signal MFD_EN with a high level based on the first value stored in the MFD enable register 480, and can perform the MFD operation. In addition, in some embodiments, the panel driver 420 may receive from the host processor 200 a panel area update command PRUCMD indicating all updated values ​​with “111” in the first panel area PR1, the second panel area PR2, and the third panel area PR3, but is not limited thereto.

[0093] Furthermore, in the first frame period FP1 following the transmission of the MFD enable command MECMD with a first value, the panel driver 420 can receive frame data FDAT from the host processor 200 for the entire area of ​​the display panel 410, and can drive the entire area of ​​the display panel 410. Additionally, in the first frame period FP1, the panel driver 420 can receive from the host processor 200 a panel area update command PRUCMD (S520) with a value of "001" indicating that the first panel area PR1 is updated and the second panel area PR2 and the third panel area PR3 are not updated. In this case, the panel driver 420 can also receive from the host processor 200 a first boundary setting command BSCMD1 (S520) indicating the first boundary BD1 between the first panel area PR1 to be updated and the second panel area PR2 to be not updated.

[0094] In the second frame period FP2 following the first frame period FP1, the panel driver 420 may receive from the host processor 200 input image data IDAT_PR1, which is used only for updating the first panel area PR1 specified by the panel area update command PRUCMD (S530). Based on the input image data IDAT_PR1, only the first panel area PR1 may be driven (S540), and the second panel area PR2 and the third panel area PR3 may not be driven. Furthermore, in the second frame period FP2, the panel driver 420 may receive from the host processor 200 a panel area update command PRUCMD with a value of "011" indicating that the first panel area PR1 and the second panel area PR2 are updated and the third panel area PR3 is not updated (S520). In this case, the panel driver 420 may also receive from the host processor 200 a second boundary setting command BSCMD2 indicating the second boundary BD2 between the second panel area PR2 specified for updating and the third panel area PR3 specified for not updating (S520).

[0095] In the third frame period FP3 following the second frame period FP2, the panel driver 420 may receive input image data IDAT_PR1 and input image data IDAT_PR2 from the host processor 200, which are used only for updating the first panel area PR1 and the second panel area PR2 specified by the panel area update command PRUCMD (S530). Based on the input image data IDAT_PR1 and input image data IDAT_PR2, the driver may drive only the first panel area PR1 and the second panel area PR2 (S540), and may not drive the third panel area PR3. In some embodiments, the vertical front porch period VFP of the third frame period FP3 may be extended to a Δfront porch period ΔVFP corresponding to any given time. Furthermore, in some embodiments, during the Δfront porch period ΔVFP, the data channel between the host processor 200 and the display device 400 may be in a low-power state LPS indicating that no data is being transmitted. Furthermore, in the third frame period FP3, the panel driver 420 may receive from the host processor 200 a panel area update command PRUCMD with a value of "101" indicating that the first panel area PR1 and the third panel area PR3 are updated and the second panel area PR2 is not updated (S520). In this case, the panel driver 420 may also receive from the host processor 200 a first boundary setting command BSCMD1 indicating the first boundary BD1 between the first panel area PR1 and the second panel area PR2 and a second boundary setting command BSCMD2 indicating the second boundary BD2 between the second panel area PR2 and the third panel area PR3 (S520).

[0096] In the fourth frame period FP4 following the third frame period FP3, the panel driver 420 may receive from the host processor 200 input image data IDAT_PR1 and input image data IDAT_PR3, which are used only for updating the first panel area PR1 and the third panel area PR3 as specified by the panel area update command PRUCMD (S530). Based on the input image data IDAT_PR1 and input image data IDAT_PR3, only the first panel area PR1 and the third panel area PR3 may be driven (S540), and the second panel area PR2 may not be driven. Furthermore, in the fourth frame period FP4, the panel driver 420 may receive from the host processor 200 a panel area update command PRUCMD with a value of "110" indicating that the second panel area PR2 and the third panel area PR3 are updated and the first panel area PR1 is not updated (S520). In this case, the panel driver 420 may also receive from the host processor 200 a first boundary setting command BSCMD1 indicating the first boundary BD1 between the first panel area PR1 and the second panel area PR2 (S520).

[0097] In the fifth frame period FP5 following the fourth frame period FP4, the panel driver 420 may receive input image data IDAT_PR2 and input image data IDAT_PR3 from the host processor 200, which are used only for updating the second panel area PR2 and the third panel area PR3 as specified by the panel area update command PRUCMD (S530). Based on the input image data IDAT_PR2 and input image data IDAT_PR3, the driver may drive only the second panel area PR2 and the third panel area PR3 (S540), and may not drive the first panel area PR1.

[0098] Therefore, the first panel area PR1, the second panel area PR2, and the third panel area PR3 can be driven at different driving frequencies DF_PR1, DF_PR2, and DF_DR3. In an embodiment, for example, the first panel area PR1 can be driven at a driving frequency of approximately 120 Hz DF_PR1 in each of the first frame period FP1 and the second frame period FP2, and at a driving frequency of approximately 60 Hz DF_PR1 in each of the third frame period FP3, the fourth frame period FP4, and the fifth frame period FP5. However, the second panel area PR2 can be driven at a driving frequency of approximately 60 Hz DF_PR2 in the first frame period FP1 and the second frame period FP2, at a driving frequency of approximately 40 Hz DF_PR2 in the third frame period FP3 and the fourth frame period FP4, and at a driving frequency of approximately 120 Hz DF_PR2 in the fifth frame period FP5. Furthermore, the third panel area PR3 can be driven at a drive frequency of approximately 30 Hz DF_PR3 in the first frame period FP1, the second frame period FP2 and the third frame period FP3, and can be driven at a drive frequency of approximately 120 Hz DF_PR3 in each of the fourth frame period FP4 and the fifth frame period FP5.

[0099] Furthermore, in the fifth frame period FP5, the panel driver 420 may receive from the host processor 200 an MFD enable command MECMD with a second value (e.g., a value of "0") indicating the end of MFD operation, and may store the second value of the MFD enable command MECMD in the MFD enable register 480. In subsequent frame periods FP, the panel driver 420 may generate an MFD enable signal MFD_EN with a low level based on the second value stored in the MFD enable register 480, and may drive the entire area of ​​the display panel 410.

[0100] As described above, the display device 400 according to the embodiment can receive the MFD enable command MECMD, the panel area update command PRUCMD, the first boundary setting command BSCMD1, and the second boundary setting command BSCMD2 from the host processor 200, and can drive the first panel area PR1, the second panel area PR2, and the third panel area PR3 at different driving frequencies DF_PR1, DF_PR2, and DF_PR3 respectively based on the MFD enable command MECMD, the panel area update command PRUCMD, the first boundary setting command BSCMD1, and the second boundary setting command BSCMD2.

[0101] Figure 9 This is a flowchart illustrating a method of operating the display device according to an embodiment, and Figure 10 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0102] In addition to the display device 400 providing the host processor 200 with the tearing effect signal TE for refreshing the display panel 410, Figure 9 The method can be with Figure 7 The methods are similar.

[0103] refer to Figure 6 and Figure 9 In this embodiment, the host processor 200 can transmit the MFD enable command MECMD, the panel area update command PRUCMD, and the first boundary setting command BSCMD1 and the second boundary setting command BSCMD2 to the display device 400 (S510 and S520), and can also transmit input image data IDAT only for the panel area to be updated specified by the panel area update command PRUCMD (S530). In this case, the display device 400 can drive only the panel area to be updated specified by the panel area update command PRUCMD based on the input image data IDAT (S540).

[0104] Furthermore, the panel driver 420 of the display device 400 can compare the first input image data received in the previous frame period with the second input image data received in the current frame period (S545, S550 and S560), and can transmit the tearing effect signal TE to the host processor 200 when the second input image data is different from the first input image data (S570). In some embodiments, to compare the first input image data with the second input image data, the panel driver 420 may compare the panel area updated in the previous frame period with the panel area updated in the current frame period (or the panel area update command PRUCMD) (S545), may compare the number of line data included in the first input image data and the number of line data included in the second input image data in the previous frame period with the number of line data included in the first input image data and the number of line data included in the second input image data in the current frame period respectively (S550), and may compare the check value (e.g., CRC value or checksum value) of the first input image data in the previous frame period with the check value of the first input image data and the check value of the second input image data in the current frame period respectively (S560). In the next frame period, the host processor 200 may retransmit the second input image data to the panel driver 420 in response to the tearing effect signal TE (S580), and the panel driver 420 may drive the display panel 410 based on the retransmitted second input image data (S590).

[0105] In an embodiment, for example, such as Figure 10As illustrated, when an MFD enable command MECMD with a first value (e.g., a value of "1") is received in the first frame period FP1, the panel driver 420 can perform MFD operations in subsequent second frame periods FP2, third frame periods FP3, fourth frame periods FP4, fifth frame periods FP5, and sixth frame periods FP6. If frame data FDAT for the first panel area PR1, second panel area PR2, and third panel area PR3 is received as input image data IDAT in the second frame period FP2, and first input image data IDAT1 for only the first panel area PR1 is received in the third frame period FP3, all of the first panel areas PR1, second panel area PR2, and third panel area PR3 can be updated in the second frame period FP2, but the first panel area PR1 can only be driven or updated in the third frame period FP3. Therefore, the panel driver 420 can transmit the tearing effect signal TE to the host processor 200. In response to the tearing effect signal TE, in the fourth frame period FP4, the host processor 200 can retransmit the first input image data IDAT1 of the third frame period FP3 to the display device 400. Panel driver 420 can re-drive the first panel area PR1 based on the first input image data IDAT1. In this case, the step efficiency phenomenon in which the display panel 410 does not have the desired brightness when the brightness changes between multiple frame cycles can be significantly reduced or effectively prevented. Furthermore, in the third frame cycle FP3 and the fourth frame cycle FP4, when the updated panel areas (i.e., the first panel area PR1) are the same, the number of line data is the same, and the check values ​​are the same, panel driver 420 may not transmit the tearing effect signal TE. Furthermore, if the first input image data IDAT1 for the first panel area PR1 is received in the fourth frame cycle FP4 and the second input image data IDAT2 for the first panel area PR1 and the third panel area PR3 is received in the fifth frame cycle FP5, panel driver 420 may transmit the tearing effect signal TE to host processor 200. In response to the tearing effect signal TE, host processor 200 may re-transmit the second input image data IDAT2 of the fifth frame cycle FP5 to display device 400 in the sixth frame cycle FP6. Panel driver 420 can drive the first panel area PR1 and the third panel area PR3 again based on the second input image data IDAT2. Furthermore, in the sixth frame cycle FP6, when panel driver 420 receives an MFD enable command MECMD with a second value (e.g., a value of "0") from host processor 200, panel driver 420 can drive the entire area of ​​display panel 410 in the subsequent seventh frame cycle FP7.

[0106] Figure 11 This is a block diagram illustrating a display device according to an embodiment. Figure 12This is a diagram illustrating an example of how a display panel is divided into multiple slices and how multiple slice update commands indicate whether these slices are being updated. Figure 13 This is a timing diagram used to describe an example of the operation of a display device according to an embodiment.

[0107] refer to Figure 11 , Figure 12 and Figure 13 According to an embodiment, the display device 600 may include a display panel 610 and a panel driver 620 for driving the display panel 610. In some embodiments, the panel driver 620 may include a data driver 630, a scan driver 640, a transmit driver 650, a frame memory 660, and a controller 670. Besides the display panel 610 being divided into a first slice SLICE1, a second slice SLICE2, ..., a forty-seventh slice SLICE47, and a forty-eighth slice SLICE48, and each of the first slice SLICE1, the second slice SLICE2, ..., the forty-seventh slice SLICE47, and the forty-eighth slice SLICE48 being selectively driven (or updated) in each frame cycle, Figure 11 The display device 600 may have the same as Figure 1 The display device 100 or Figure 6 The display device 400 has a similar configuration and similar operation.

[0108] In the display device 600 according to an embodiment, the panel driver 620 may receive an MFD enable command MECMD from the host processor 200 and perform an MFD operation in response to the MFD enable command MECMD. In an embodiment, for example, as Figure 13 As illustrated in the diagram, during the frame period FP preceding the start of MFD operation, the panel driver 620 receives an MFD enable command MECMD with a value of "1" from the host processor 200, indicating the start of MFD operation, and stores the value of the MFD enable command MECMD in the MFD enable register 680. In subsequent frame periods FP1, FP2, and FP3, the panel driver 620 generates a high-level MFD enable signal MFD_EN based on the value stored in the MFD enable register 680, and performs the MFD operation.

[0109] Furthermore, the panel driver 620 can receive a panel area number command PRNCMD from the host processor 200, indicating the number of panel areas into which the display panel 610 is divided. In embodiments, for example, a panel area number command PRNCMD with a value of 0 can indicate that the display panel 610 is not divided, a panel area number command PRNCMD with a value of 1 can indicate that the display panel 610 is divided into two panel areas, and a panel area number command PRNCMD with a value of 2 can indicate that the display panel 610 is divided into three panel areas, but is not limited thereto. Furthermore, in Figure 11 and Figure 12 In the example, when the panel driver 620 receives a panel area number command PRNCMD with a value of 2 from the host processor 200, the display panel 610 can be divided into a first panel area PR1, a second panel area PR2, and a third panel area PR3.

[0110] Additionally, the panel driver 620 may receive from the host processor 200 at least one boundary setting command BSCMD indicating a first boundary BD1 and a second boundary BD2 between the first panel area PR1, the second panel area PR2, and the third panel area PR3. In an embodiment, as... Figure 11 and Figure 12 As illustrated in the diagram, panel driver 620 can receive from host processor 200 a first boundary setting command BSCMD1 indicating a first boundary BD1 between a first panel area PR1 and a second panel area PR2, and a second boundary setting command BSCMD2 indicating a second boundary BD2 between the second panel area PR2 and a third panel area PR3. Furthermore, in embodiments, as... Figure 11 and Figure 12 As shown in the diagram, the display panel 610 can be divided into SLICE1 to SLICE48. The first panel area PR1 can be set by the first boundary setting command BSCMD1 to include SLICE1 to SLICE16. The second panel area PR2 can be set by the first boundary setting command BSCMD1 and the second boundary setting command BSCMD2 to include SLICE17 to SLICE32. The third panel area PR3 can be set by the second boundary setting command BSCMD2 to include SLICE33 to SLICE48, but is not limited thereto.

[0111] In the first frame period FP1, the panel driver 620 may receive from the host processor 200 a panel area update command PRUCMD indicating whether each of the first panel area PR1, the second panel area PR2, and the third panel area PR3 has been updated. In some embodiments, the number of bits in the panel area update command PRUCMD may be substantially equal to the number of the multiple panel areas, and each bit of the panel area update command PRUCMD may indicate whether the corresponding panel area has been updated. In an embodiment, for example, in the first frame period FP1, the panel area update command PRUCMD may have a first bit (e.g., the least significant bit) indicating that the first panel area PR1 has been updated, a second bit (e.g., the most significant bit) indicating that the second panel area PR2 has been updated, and a third bit (e.g., the most significant bit) indicating that the third panel area PR3 has been updated. Furthermore, in some embodiments, the number of bits in the panel area update command PRUCMD may be determined based on the number of multiple panel areas into which the display panel 610 is divided.

[0112] Furthermore, during the first frame period FP1, the panel driver 620 may receive from the host processor 200 a plurality of slice update commands SLUCMD indicating whether each of the first slice SLICE1, second slice SLICE2, ..., forty-seventh slice SLICE47 and forty-eighth slice SLICE48 in the first panel area PR1, second panel area PR2, and third panel area PR3 has been updated. In an embodiment, for example, each slice update command SLUCMD may have eight bits indicating whether eight slices have been updated, but is not limited thereto. In an embodiment, such as... Figure 12As illustrated in the diagram, the first slice update command SLUCMD1 with the value "11110000" indicates that slices SLICE1, SLICE2, SLICE3, and SLICE4 are not updated, while slices SLICE5, SLICE6, SLICE7, and SLICE8 are updated. Furthermore, the second slice update command SLUCMD2 with the value "00000000" indicates that slices SLICE9, SLICE10, SLICE11, SLICE12, SLICE13, SLICE14, SLICE15, and SLICE16 are not updated. Furthermore, the third slice update command SLUCMD3 with the value "11110000" indicates that slices 17, 18, 19, and 20 are not updated, while slices 21, 22, 23, and 24 are updated. Additionally, the fourth slice update command SLUCMD4 with the value "00000011" indicates that slices 25 and 26 are updated, while slices 27, 28, 29, 30, 31, and 32 are not updated. Furthermore, the fifth slice update command SLUCMD5 with a value of "00000000" can indicate that slices 33, 34, 35, 36, 37, 38, 39, and 40 are not updated. Additionally, the sixth slice update command SLUCMD6 with a value of "00111100" can indicate that slices 41, 42, 47, and 48 are not updated, while slices 43, 44, 45, and 46 are updated. That is, in the embodiment, as... Figure 12As illustrated in the diagram, the first slice update command SLUCMD1 to the sixth slice update command SLUCMD6 can instruct the first slice area USL1, including the fifth slice SLICE5 to the eighth slice SLICE8, the second slice area USL2, including the twenty-first slice SLICE21 to the twenty-sixth slice SLICE26, and the third slice area USL3, including the forty-third slice SLICE43 to the forty-sixth slice SLICE46, to be updated. In some embodiments, the panel area update command PRUCMD can have a higher priority than the slice update command SLUCMD. In an embodiment, for example, when the panel area update command PRUCMD indicates that the panel area should not be updated, the slice update command SLUCMD for slices within the panel area can be ignored, and the slices within the panel area can be left unupdated.

[0113] In the second frame period FP2 following the first frame period FP1, the panel driver 620 can receive from the host processor 200 input image data IDAT_USL1, input image data IDAT_USL2, and input image data IDAT_USL3 for the fifth SLICE5 to eighth SLICE8, the twenty-first SLICE21 to twenty-sixth SLICE26, and the forty-third SLICE43 to forty-sixth SLICE46 specified by the panel area update command PRUCMD and the first SLICE update command SLUCMD1 to the sixth SLUCMD6 for the first SLICE1 to forty-eighth SLICE48. Furthermore, it can drive the fifth SLICE5 to eighth SLICE8, the twenty-first SLICE21 to twenty-sixth SLICE26, and the forty-third SLICE43 to forty-sixth SLICE46 based on the input image data IDAT_USL1, input image data IDAT_USL2, and input image data IDAT_USL3. In an embodiment, for example, the input image data IDAT_USL1 received in the first frame period FP1... Figure 12In the case of the first slice update command SLUCMD1 to the sixth slice update command SLUCMD6 illustrated in the middle, during the second frame period FP2, the panel driver 620 can receive input image data IDAT_USL1 for the first slice area USL1 including the fifth slice SLICE5 to the eighth slice SLICE8, input image data IDAT_USL2 for the second slice area USL2 including the twenty-first slice SLICE21 to the twenty-sixth slice SLICE26, and input image data IDAT_USL3 for the third slice area USL3 including the forty-third slice SLICE43 to the forty-sixth slice SLICE46. Furthermore, in the second frame period FP2, the panel driver 620 can drive the fifth SLICE5 to the eighth SLICE8 based on the input image data IDAT_USL1 for the first SLICE area USL1, drive the twenty-first SLICE21 to the twenty-sixth SLICE26 based on the input image data IDAT_USL2 for the second SLICE area USL2, drive the forty-third SLICE43 to the forty-sixth SLICE46 based on the input image data IDAT_USL3 for the third SLICE area USL3, and may not drive the first SLICE1 to the fourth SLICE4, the ninth SLICE9 to the twentieth SLICE20, the twenty-seventh SLICE27 to the forty-second SLICE42, and the forty-seventh SLICE47 and the forty-eighth SLICE48. That is, in the second frame period FP2, the panel driver 620 can only drive the fifth slice SLICE5 to the eighth slice SLICE8, the twenty-first slice SLICE21 to the twenty-sixth slice SLICE26, and the forty-third slice SLICE43 to the forty-sixth slice SLICE46, which are specified to be updated by the panel area update command PRUCMD and the first slice update command SLUCMD1 to the sixth slice update command SLUCMD6. It can not receive the first slice SLICE46, which is specified not to be updated by the panel area update command PRUCMD and the first slice update command SLUCMD1 to the sixth slice update command SLUCMD6. The input image data IDAT of slices E1 to 4, slices 9 to 20, slices 27 to 42, slices 47 and 48 can be driven without updating the first slice to fourth slice, slice 9 to 20, slice 27 to 42, slice 47 and 48.

[0114] In the second frame period FP2, the panel driver 620 may receive from the host processor 200 a panel area update command PRUCMD with a value of "110" indicating that the first panel area PR1 is not updated and the second panel area PR2 and the third panel area PR3 are updated. Furthermore, in some embodiments, the panel driver 620 may receive a slice reset command SLRCMD from the host processor 200 instead of the first slice update commands SLUCMD1 through SLUCMD6. The slice reset command SLRCMD may indicate that slices SLICE17 through SLICE48, included in the second panel area PR2 and the third panel area PR3 specified to be updated by the panel area update command PRUCMD, are updated. Therefore, in the third frame period FP3 following the second frame period FP2, the panel driver 620 can receive input image data IDAT_PR2 and input image data IDAT_PR3 from the host processor 200 for updating the second panel area PR2 and the third panel area PR3, respectively, as specified by the panel area update command PRUCMD. Based on the input image data IDAT_PR2 and input image data IDAT_PR3, the driver can drive slices 17 to 48, which are included in the second panel area PR2 and the third panel area PR3. Furthermore, in the third frame period FP3, the panel driver 620 may not receive input image data IDAT for the first panel area PR1, and may not drive slices 1 to 16, which are included in the first panel area PR1.

[0115] Therefore, the display device 600 according to the embodiment can drive the first slice SLICE1 to the forty-eighth slice SLICE48 at different driving frequencies not only in a first mode (e.g., command mode) in which the input image data IDAT received from the host processor 200 is stored in the frame memory 660, but also in a second mode (e.g., video mode) in which the input image data IDAT received from the host processor 200 is not stored in the frame memory 660.

[0116] Figure 14 This is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0117] refer to Figure 14 Embodiments of electronic device 1100 may include a host processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electrical devices, etc.

[0118] The host processor 1110 can perform various computing functions or tasks. The host processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. The host processor 1110 can be connected to other components via address buses, control buses, data buses, etc. Furthermore, in some embodiments, the host processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0119] The memory device 1120 may store data for the operation of the electronic device 1100. In embodiments, for example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device.

[0120] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0121] Display device 1160 may receive MFD enable commands, boundary setting commands, and / or panel area update commands from host processor 1110, and may drive only a portion of the display panel by receiving input image data for only a portion of the display panel in subsequent frame cycles. Therefore, display device 1160 may drive the panel area at different drive frequencies in modes in which the input image data is not stored in the frame memory (e.g., video mode). In this embodiment, display device 1160 may correspond to display device 100, display device 400, and display device 600 mentioned above.

[0122] The embodiments of the present invention described above can be applied to any electronic device 1100 including display device 1160, such as mobile phones, smartphones, virtual reality (“VR”) devices, televisions (“TV”) (e.g., digital televisions, three-dimensional (“3D”) televisions, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0123] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the principles of the invention to those skilled in the art.

[0124] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope or spirit of the invention as defined by the appended claims.

Claims

1. A display device, comprising: Display panel; as well as A panel driver that drives the display panel. The panel driver receives a multi-frequency drive enable command from the host processor. During the first frame cycle, the panel driver receives from the host processor a boundary setting command indicating the boundary between the first panel area and the second panel area of ​​the display panel. In the second frame period following the first frame period, the panel driver receives input image data for the first panel area from the host processor, but does not receive input image data for the second panel area from the host processor. It drives the first panel area based on the input image data for the first panel area, but does not drive the second panel area.

2. The display device according to claim 1, wherein, During the second frame period, the panel driver provides data voltage and scan signal to the first panel area to drive the first panel area, and does not provide the data voltage and scan signal to the second panel area to not drive the second panel area.

3. The display device according to claim 1, wherein, During the second frame cycle, the panel driver drives the first panel area and the second panel area at different driving frequencies in a mode in which the input image data received from the host processor is not stored in the frame memory included in the display device.

4. The display device according to claim 1, wherein, The first panel area is an upper panel area positioned above the boundary indicated by the boundary setting command, and the second panel area is a lower panel area positioned below the boundary. During the second frame period, the panel driver drives the upper panel area at a first driving frequency and drives the lower panel area at a second driving frequency lower than the first driving frequency.

5. The display device according to claim 1, wherein, The panel driver includes: A multi-frequency drive enable register stores the value of the multi-frequency drive enable command, and The panel driver generates a multi-frequency drive enable signal based on the value stored in the multi-frequency drive enable register.

6. The display device according to claim 1, wherein, During the first portion of the effective period of the second frame period allocated to the first panel area, the panel driver periodically receives horizontal synchronization packets from the host processor, and Specifically, during the second portion of the effective period of the second frame period allocated to the second panel area, the panel driver does not receive the horizontal synchronization data packet from the host processor.

7. The display device according to claim 6, wherein, During the second portion of the effective period of the second frame cycle, the data channel between the host processor and the panel driver is in a low-power state indicating that no data is being transmitted.

8. The display device according to claim 1, wherein, The panel driver compares the first input image data received in the previous frame period with the second input image data received in the current frame period, and transmits the tearing effect signal to the host processor when the second input image data is different from the first input image data.

9. A display device, comprising: Display panel; as well as A panel driver that drives the display panel. The panel driver receives a multi-frequency drive enable command from the host processor. In the first frame period, the panel driver receives from the host processor a panel area update command indicating whether each of the plurality of panel areas is updated, and at least one boundary setting command indicating at least one boundary between the plurality of panel areas. In the second frame period following the first frame period, the panel driver receives input image data from the host processor for the panel area to be updated specified by the panel area update command among the plurality of panel areas, and drives the specified panel area to be updated based on the input image data.

10. An electronic device comprising: A host processor that provides input image data; as well as A display device that displays an image based on the input image data. The host processor transmits the multi-frequency drive enable command to the display device. Specifically, during the first frame cycle, the host processor transmits a boundary setting command, indicating the boundary between the first panel area and the second panel area of ​​the display panel of the display device, to the display device. In the second frame period following the first frame period, the host processor transmits the input image data for the first panel area to the display device but does not transmit the input image data for the second panel area to the display device, and the display device drives the first panel area based on the input image data for the first panel area but does not drive the second panel area.

Images