Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a display panel; a gate driver; a data driver; an emission driver; a drive controller; and a viewing angle controller for providing a first viewing angle signal and a second viewing angle signal for the display panel, in which display image data is alternately displayed in the display panel at different viewing angles through the first light emitting circuit and the second light emitting circuit in response to the first viewing angle signal and the second viewing angle signal, and the viewing angle of the second light-emitting circuit is narrower than that of the first light-emitting circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present inventive concept relate to a display apparatus, an electronic apparatus in which the display apparatus is applied, and a method of operating the display apparatus. More particularly, embodiments of the present inventive concept relate to a display apparatus, an electronic apparatus, and a method of operating the display apparatus that reduce a useless space and power consumption of the display apparatus. BACKGROUND

[0002] The display apparatus can include a display panel, a gate driver, a data driver, an emission driver, and a driving controller. The display panel includes a plurality of gate lines, a plurality of emission lines, a plurality of data lines, and a plurality of pixels. The gate driver provides a gate signal to the plurality of gate lines. The data driver provides a data voltage to the plurality of data lines. The emission driver provides an emission signal to the plurality of emission lines. The driving controller controls the gate driver, the data driver, and the emission driver.

[0003] To provide a narrow viewing angle mode, each of the plurality of pixels can include a first light emitting element, a second light emitting element having a narrower viewing angle than the first light emitting element, a first viewing angle control transistor connected to the first light emitting element, and a second viewing angle control transistor connected to the second light emitting element. In many cases, additional scan drivers are needed in the display apparatus to generate and control various viewing angle signals. The additional scan drivers can require extra space and higher power consumption. SUMMARY

[0004] Example embodiments provide a display apparatus, an electronic apparatus in which the display apparatus is applied, and a method of operating the display apparatus.

[0005] According to an embodiment, a display apparatus includes a display panel including a plurality of pixels; a gate driver configured to generate gate signals to provide the gate signals for the plurality of pixels; a data driver configured to generate data voltages to provide the data voltages for the plurality of pixels; an emission driver configured to generate emission signals to provide the emission signals for the plurality of pixels; a driving controller configured to generate display image data based on input image data; and a viewing angle controller configured to generate first and second viewing angle signals to provide the first and second viewing angle signals for the plurality of pixels, wherein the display image data is alternately displayed in the display panel at different viewing angles in response to the first and second viewing angle signals, wherein each of the plurality of pixels includes a first light emitting circuit including a first light emitting element and a first viewing angle control transistor, wherein the first viewing angle control transistor is turned on to transmit a driving current to the first light emitting element in response to the first viewing angle signal, and a second light emitting circuit including a second light emitting element and a second viewing angle control transistor, wherein the second viewing angle control transistor is turned on to transmit the driving current to the second light emitting element in response to the second viewing angle signal, and wherein a viewing angle of the second light emitting circuit is narrower than a viewing angle of the first light emitting circuit.

[0006] Each of the plurality of pixels is configured to receive the first and second viewing angle signals through first and second viewing angle signal lines, respectively.

[0007] Each of the plurality of pixels includes a compensation circuit, and the compensation circuit includes a data write transistor configured to receive the data voltage, a driving transistor configured to generate the driving current corresponding to the data voltage, and an emission transistor configured to transmit the driving current to the first and second light emitting circuits in response to the emission signal, wherein the compensation circuit is configured to compensate for a threshold voltage of the driving transistor.

[0008] A gate electrode of the first viewing angle control transistor is connected to the first viewing angle signal line, a source electrode of the first viewing angle control transistor is connected to the compensation circuit, and a drain electrode of the first viewing angle control transistor is connected to an anode electrode of the first light emitting element, and a gate electrode of the second viewing angle control transistor is connected to the second viewing angle signal line, a source electrode of the second viewing angle control transistor is connected to the compensation circuit, and a drain electrode of the second viewing angle control transistor is connected to an anode electrode of the second light emitting element.

[0009] A gate electrode of the emission transistor receives the emission signal, a source electrode of the emission transistor is connected to a drain electrode of the driving transistor, and a drain electrode of the emission transistor is connected to a source electrode of the first viewing angle control transistor, and a source electrode of the second viewing angle control transistor is connected to a drain electrode of the emission transistor.

[0010] In odd frames, the first view signal has an active level and the second view signal has a disabled level, wherein the odd frames are odd numbered frames among a series of frames, and in even frames, the first view signal has a disabled level and the second view signal has an active level, wherein the even frames are even numbered frames among the series of frames.

[0011] In odd frames, the first view signal has a logic low level and the second view signal has a logic high level, and in even frames, the first view signal has a logic high level and the second view signal has a logic low level.

[0012] In odd frames, the first view signal has an active level and the second view signal has an active level, wherein the odd frames are odd numbered frames among a series of frames, and in even frames, the first view signal has a disabled level and the second view signal has an active level, wherein the even frames are even numbered frames among the series of frames.

[0013] In odd frames, the first view signal has a logic low level and the second view signal has a logic low level, and in even frames, the first view signal has a logic high level and the second view signal has a logic low level.

[0014] The view angle controller is embedded in one of the gate driver, the data driver, the emission driver, and the driving controller.

[0015] According to an embodiment, a display apparatus includes a display panel including a plurality of pixels, a gate driver configured to generate gate signals to provide the gate signals for the plurality of pixels, a data driver configured to generate data voltages to provide the data voltages for the plurality of pixels, an emission driver configured to generate emission signals to provide the emission signals for the plurality of pixels, a driving controller configured to generate display image data based on input image data, and a view angle controller configured to generate a first view signal and a second view signal to provide the first view signal and the second view signal for the plurality of pixels, wherein the display image data is alternately displayed in different view angles in the display panel in response to the first view signal and the second view signal, wherein each of the plurality of pixels includes a first light emitting circuit including a first light emitting element and a first view angle control transistor, wherein the first view angle control transistor is turned on to transmit a driving current to the first light emitting element in response to the first view signal, and a second light emitting circuit including a second light emitting element and a second view angle control transistor, wherein the second view angle control transistor is turned on to transmit the driving current to the second light emitting element in response to the second view signal, wherein a view angle of the second light emitting circuit is narrower than a view angle of the first light emitting circuit, and wherein the display apparatus is configured to operate in one of a regular mode and a narrow view angle mode, wherein the view angle in the narrow view angle mode is narrower than the view angle in the regular mode.

[0016] In the normal mode, the first view signal has an active level and the second view signal has a disable level in the odd frames and the even frames, wherein the odd frames are odd numbered frames among a series of frames and the even frames are even numbered frames among the series of frames, and in the narrow view mode, the first view signal has an active level and the second view signal has a disable level in the odd frames and the first view signal has a disable level and the second view signal has an active level in the even frames.

[0017] In the normal mode, the first view signal has a logic low level and the second view signal has a logic high level in the odd frames and the even frames, and in the narrow view mode, the first view signal has a logic low level and the second view signal has a logic high level in the odd frames and the first view signal has a logic high level and the second view signal has a logic low level in the even frames.

[0018] In the normal mode, the first view signal has an active level and the second view signal has a disable level in the odd frames and the even frames, wherein the odd frames are odd numbered frames among a series of frames and the even frames are even numbered frames among the series of frames, and in the narrow view mode, the first view signal has an active level and the second view signal has an active level in the odd frames and the first view signal has a disable level and the second view signal has an active level in the even frames.

[0019] In the normal mode, the first view signal has a logic low level in the even frames and the odd frames, and the second view signal has a logic high level in the even frames and the odd frames, and in the narrow view mode, the first view signal has a logic low level and the second view signal has a logic low level in the odd frames, and the first view signal has a logic high level and the second view signal has a logic low level in the even frames.

[0020] Each of the plurality of pixels is configured to receive the first view signal and the second view signal through the first view signal line and the second view signal line, respectively.

[0021] Each of the plurality of pixels includes a compensation circuit, and the compensation circuit includes a data write transistor configured to receive a data voltage, a driving transistor configured to generate a driving current corresponding to the data voltage, and an emission transistor configured to transfer the driving current to the first light emitting circuit and the second light emitting circuit in response to an emission signal, and wherein the compensation circuit is configured to compensate for a threshold voltage of the driving transistor.

[0022] A gate electrode of the first view control transistor is connected to a first view signal line, a source electrode of the first view control transistor is connected to the compensation circuit, and a drain electrode of the first view control transistor is connected to an anode electrode of the first light emitting element, and a gate electrode of the second view control transistor is connected to a second view signal line, a source electrode of the second view control transistor is connected to the compensation circuit, and a drain electrode of the second view control transistor is connected to an anode electrode of the second light emitting element.

[0023] According to embodiments, an electronic device includes a processor configured to output an input control signal and input image data, and a display device configured to display an image based on the input image data, the display device including a display panel including a plurality of pixels, a gate driver configured to generate gate signals to provide the gate signals for the plurality of pixels, a data driver configured to generate data voltages to provide the data voltages for the plurality of pixels, an emission driver configured to generate emission signals to provide the emission signals for the plurality of pixels, a driving controller configured to generate display image data based on the input control signal and the input image data, and a view controller configured to generate a first view signal and a second view signal to provide the first view signal and the second view signal for the plurality of pixels, wherein the display image data is alternately displayed in the display panel at different view angles in response to the first view signal and the second view signal, wherein each of the plurality of pixels includes a first light emitting circuit including a first light emitting element and a first view control transistor, wherein the first view control transistor is turned on to transmit a driving current to the first light emitting element in response to the first view signal, and a second light emitting circuit including a second light emitting element and a second view control transistor, wherein the second view control transistor is turned on to transmit a driving current to the second light emitting element in response to the second view signal, and wherein a view angle of the second light emitting circuit is narrower than a view angle of the first light emitting circuit.

[0024] The electronic device further includes an input / output (I / O) device configured to sense a user input via a touch or a cursor selection of an icon presented in the display panel, wherein the processor is caused to execute one of a first view mode and a second view mode of the display device upon receiving the user input. The display panel includes a regular view angle area and a narrow view angle area, and when the processor is caused to execute the first view mode, a view angle of the regular view angle area and a view angle of the narrow view angle area are substantially the same, and when the processor is caused to execute the second view mode, the view angle of the narrow view angle area is narrower than the view angle of the regular view angle area. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and other aspects, features, and advantages of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a block diagram illustrating a display device according to an embodiment of the idea of the present application;

[0027] Figure 2 is a block diagram illustrating Figure 1 a connection relationship between a plurality of pixels included in a display panel and a viewing angle controller;

[0028] Figure 3 is a circuit diagram illustrating a pixel according to an embodiment of the idea of the present application;

[0029] Figure 4 is a timing chart illustrating an operation of the pixel of Figure 3 according to an embodiment of the idea of the present application;

[0030] Figure 5 is a circuit diagram illustrating an operation of the pixel of Figure 3 in a first frame and a third frame of the timing chart of Figure 4 ;

[0031] Figure 6 is a circuit diagram illustrating an operation of the pixel of Figure 3 in a second frame and a fourth frame of the timing chart of Figure 4 ;

[0032] Figure 7 is a timing chart illustrating an operation of the pixel of Figure 3 according to an embodiment of the idea of the present application;

[0033] Figure 8 is a circuit diagram illustrating an operation of the pixel of Figure 3 in a first frame and a third frame of the timing chart of Figure 7 ;

[0034] Figure 9 is a circuit diagram illustrating an operation of the pixel of Figure 3 in a second frame and a fourth frame of the timing chart of Figure 7 ;

[0035] Figure 10 is a block diagram illustrating a display device according to an embodiment of the idea of the present application;

[0036] Figure 11 is a block diagram illustrating a display device according to an embodiment of the idea of the present application;

[0037] Figure 12 is a block diagram illustrating a display device according to an embodiment of the idea of the present application;

[0038] Figure 13 is a block diagram illustrating a display device according to an embodiment of the idea of the present application;

[0039] Figure 14is a flowchart illustrating a driving mode of a display apparatus according to an embodiment of the inventive concept;

[0040] Figure 15 is a flowchart illustrating a driving mode of a display apparatus according to an embodiment of the inventive concept;

[0041] Figure 16 is a flowchart illustrating a method of operating a display apparatus according to an embodiment of the inventive concept;

[0042] Figure 17 is a block diagram of an electronic apparatus according to an embodiment of the inventive concept; and

[0043] Figure 18 is a diagram of a smart phone illustrating an example of an electronic apparatus according to Figure 17 DETAILED DESCRIPTION

[0044] Hereinafter, a display apparatus according to an embodiment will be described in greater detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like components.

[0045] The display apparatus displays display image data (or image data) in a display panel at different viewing angles. The display apparatus can provide two viewing angle modes, one of which is a regular viewing angle mode and the other of which is a narrow viewing angle mode. Herein, the regular viewing angle mode is also referred to as a regular mode. A viewing angle controller of the display apparatus generates a regular viewing angle signal and a narrow viewing angle signal. First and second light emitting circuits of the display apparatus alternately display the image data in the display panel in different time frames in response to the regular viewing angle signal and the narrow viewing angle signal. The viewing angle of the second light emitting circuit is narrower than that of the first light emitting circuit. Since the first and second light emitting circuits share a common circuit, it is possible to reduce the dead space and power consumption of the display apparatus.

[0046] Figure 1 is a block diagram of a display apparatus 1 according to an embodiment of the inventive concept.

[0047] Referring to Figure 1 , the display apparatus 1 includes a display panel 100, a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, an emission driver 600, and a viewing angle controller 700.

[0048] The display panel 100 has a display area in which an image is displayed and a peripheral area adjacent to the display area.

[0049] ​The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, a first view angle signal line VSL1, a second view angle signal line VSL2, and a plurality of pixels PX. The plurality of pixels PX are electrically connected to the gate lines GL, the data lines DL, the emission lines EL, the first view angle signal line VSL1, and the second view angle signal line VSL2. The gate lines GL can extend in a first direction D1, the data lines DL can extend in a second direction D2 perpendicular to the first direction D1, and the emission lines EL can extend in the first direction D1. The first view angle signal line VSL1 and the second view angle signal line VSL2 can extend in the first direction D1.

[0050] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG can include red image data, green image data, and blue image data. Depending on the application of the display device 1, the input image data IMG can also include white image data, magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can also include a vertical synchronization signal and a horizontal synchronization signal.

[0051] The drive controller 200 generates first control signals CONT1, second control signals CONT2, third control signals CONT3, fourth control signals CONT4, and data signals DATA based on the input image data IMG and the input control signals CONT. The data signals DATA can include display image data.

[0052] The drive controller 200 generates the first control signals CONT1 for controlling the operation of the gate driver 300 based on the input control signals CONT, and provides the first control signals CONT1 to the gate driver 300. The first control signals CONT1 can include a vertical start signal and a gate clock signal.

[0053] The drive controller 200 generates the second control signals CONT2 for controlling the operation of the data driver 500 based on the input control signals CONT, and provides the second control signals CONT2 to the data driver 500. The second control signals CONT2 can include a horizontal start signal and a load signal.

[0054] The drive controller 200 generates the data signals DATA based on the input image data IMG, and provides the data signals DATA to the data driver 500.

[0055] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and provides the third control signal CONT3 to the gamma reference voltage generator 400.

[0056] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and provides the fourth control signal CONT4 to the emission driver 600.

[0057] The gate driver 300 can generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 can provide the gate signal to the gate line GL. The gate signal can include an initialization signal, a compensation signal, a data write signal, and a bias signal.

[0058] According to an embodiment, the gate driver 300 can be integrated in the peripheral area of the display panel 100. Alternatively, the gate driver 300 can be mounted on the peripheral area of the display panel 100.

[0059] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can provide a reference value for determining a value of the data signal DATA.

[0060] The gamma reference voltage generator 400 can be embedded in the driving controller 200 or embedded in the data driver 500.

[0061] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 provides the data voltage to the data line DL.

[0062] The data driver 500 can be integrated in the peripheral area of the display panel 100. Alternatively, the data driver 500 can be mounted on the peripheral area of the display panel 100.

[0063] Although the driving controller 200, the data driver 500, and the gamma reference voltage generator 400 are described as being integrated in the display panel 100, the driving controller 200, the data driver 500, and the gamma reference voltage generator 400 can be mounted on the peripheral area of the display panel 100. Figure 1The driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrated in a circuit block. A driving module in which the driving controller 200 and the data driver 500 are integrated in a circuit block can be referred to as a timing controller embedded data driver (TED).

[0064] The emission driver 600 can generate an emission signal to drive the emission line EL in response to a fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EL.

[0065] According to an embodiment, the emission driver 600 can be integrated in a peripheral area of the display panel 100. Alternatively, the emission driver 600 can be mounted on a peripheral area of the display panel 100.

[0066] The viewing angle controller 700 can provide a first viewing angle signal and a second viewing angle signal, and the viewing angle controller 700 can control a viewing angle of the display panel 100 with the first viewing angle signal and the second viewing angle signal.

[0067] According to an embodiment, the viewing angle controller 700 can provide a first viewing angle signal VS1 (see Figure 3 ) and a second viewing angle signal VS2 (see Figure 3 ) for the pixels PX through first viewing angle signal lines VSL1 and second viewing angle signal lines VSL2. The first viewing angle signal lines VSL1 and the second viewing angle signal lines VSL2 can extend in a first direction D1. The first viewing angle signal lines VSL1 can provide the first viewing angle signal VS1 for the pixels PX along the first direction D1, and the second viewing angle signal lines VSL2 can provide the second viewing angle signal VS2 for the pixels PX along the first direction D1. The viewing angle controller 700 can provide the first viewing angle signal VS1 for controlling a viewing angle of the display panel 100 for the pixels PX through the first viewing angle signal lines VSL1, and the viewing angle controller 700 can provide the second viewing angle signal VS2 for controlling a viewing angle of the display panel 100 for the pixels PX through the second viewing angle signal lines VSL2.

[0068] The viewing angle controller 700 can receive a viewing angle control signal. The viewing angle controller 700 can output the first viewing angle signal VS1 and the second viewing angle signal VS2 in response to the viewing angle control signal.

[0069] Although the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 are shown as separate circuit blocks, some of the circuit blocks can be integrated in a circuit block (or integrated as one circuit block). For example, the driving controller 200 and the data driver 500 can be integrated in a circuit block. The driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrated in a circuit block. A driving module in which the driving controller 200 and the data driver 500 are integrated in a circuit block can be referred to as a timing controller embedded data driver (TED). Figure 1The gate driver 300 is disposed at a first side of the display panel 100 and the emission driver 600 is disposed at a second side of the display panel 100 opposite the first side, but the inventive concept can not be limited thereto. Both the gate driver 300 and the emission driver 600 can be disposed at the first side of the display panel 100. Alternatively, both the gate driver 300 and the emission driver 600 can be disposed at the second side of the display panel 100. Further, the gate driver 300 and the emission driver 600 can be integrated in a circuit block.

[0070] Figure 2 is a block diagram illustrating Figure 1 a connection relationship between a plurality of pixels PX included in the display panel 100 and the viewing angle controller 700.

[0071] Referring to Figure 1 and Figure 2 , the display panel 100 can include a plurality of pixels PX. The plurality of pixels PX can be connected to a first viewing angle signal line VSL1 and a second viewing angle signal line VSL2.

[0072] The first viewing angle signal line VSL1 and the second viewing angle signal line VSL2 can extend in a first direction D1. The first viewing angle signal line VSL1 can be connected to the pixels PX along the first direction D1, and the second viewing angle signal line VSL2 can be connected to the pixels PX along the first direction D1.

[0073] The viewing angle controller 700 can provide a first viewing angle signal VS1 (see Figure 3 ) to the pixels PX through the first viewing angle signal line VSL1, and the viewing angle controller 700 can provide a second viewing angle signal VS2 (see Figure 3 ) to the pixels PX through the second viewing angle signal line VSL2.

[0074] The first viewing angle signal VS1 and the second viewing angle signal VS2 can be signals commonly applied to the plurality of pixels PX, and the first viewing angle signal VS1 and the second viewing angle signal VS2 can be simultaneously provided to the plurality of pixels PX. The first viewing angle signal VS1 and the second viewing angle signal VS2 can control a viewing angle of the display panel 100.

[0075] The viewing angle controller 700 provides the first viewing angle signal VS1 and the second viewing angle signal VS2 to the pixels PX through the first viewing angle signal line VSL1 and the second viewing angle signal line VSL2, respectively. Since an additional scan driver for generating and outputting the first viewing angle signal VS1 and the second viewing angle signal VS2 is not necessary, it is possible to reduce a dead space and power consumption of the display device 1 while maintaining a resolution of the display device 1.

[0076] Figure 3is a circuit diagram showing a pixel PX according to an embodiment of the inventive concept.

[0077] Referring to Figure 3 , the pixel PX can include a first light emitting circuit EC1, a second light emitting circuit EC2, and a compensation circuit CC. The first light emitting circuit EC1 and the second light emitting circuit EC2 can be connected to the compensation circuit CC.

[0078] The compensation circuit CC can include a first capacitor C1, a second capacitor C2, and a first to sixth transistor T1 to T6.

[0079] A first electrode of the first capacitor C1 can be connected to a second node N2, and a second electrode of the first capacitor C1 can be connected to a first node N1.

[0080] A first electrode of the second capacitor C2 can receive a first power supply voltage ELVDD, and a second electrode of the second capacitor C2 can be connected to the second node N2.

[0081] A gate electrode of the first transistor T1 can be connected to the first node N1, a source electrode of the first transistor T1 can receive the first power supply voltage ELVDD, and a drain electrode of the first transistor T1 can be connected to a third node N3. The gate electrode of the first transistor T1 can be coupled to a data line DL (see Figure 1 ) and generate a driving current corresponding to a data voltage VDATA. The first transistor T1 can be referred to as a driving transistor.

[0082] A gate electrode of the second transistor T2 can receive a data write signal GW[n], a source electrode of the second transistor T2 can receive the data voltage VDATA, and a drain electrode of the second transistor T2 can be connected to the second node N2. The second transistor T2 can be referred to as a data write transistor.

[0083] A gate electrode of the third transistor T3 can receive a compensation signal GC[n], a source electrode of the third transistor T3 can be connected to the second node N2, and a drain electrode of the third transistor T3 can receive a reference voltage VREF.

[0084] A gate electrode of the fourth transistor T4 can receive an initialization signal GI[n], a source electrode of the fourth transistor T4 can be connected to the first node N1, and a drain electrode of the fourth transistor T4 can receive an initialization voltage VINIT.

[0085] A gate electrode of the fifth transistor T5 can receive the compensation signal GC[n], a source electrode of the fifth transistor T5 can be connected to the first node N1, and a drain electrode of the fifth transistor T5 can be connected to the third node N3.

[0086] The gate electrode of the sixth transistor T6 can receive the emission signal EM[n], the source electrode of the sixth transistor T6 can be connected to the third node N3, and the drain electrode of the sixth transistor T6 can be connected to the fourth node N4. The sixth transistor T6 can transmit the drive current to the first light emitting circuit EC1 and / or the second light emitting circuit EC2 in response to the emission signal EM[n]. The sixth transistor T6 can be referred to as an emission transistor.

[0087] Since the first transistor T1 can be subjected to deterioration in an application field, the threshold voltage of the first transistor T1 can be shifted. The compensation circuit CC can compensate for the shift of the threshold voltage of the first transistor T1.

[0088] The first light emitting circuit EC1 can include the first light emitting element EL1, a seventh transistor T7, and a ninth transistor T9.

[0089] The anode electrode of the first light emitting element EL1 can be connected to the seventh transistor T7 and the ninth transistor T9, and the cathode electrode of the first light emitting element EL1 can receive the second power supply voltage ELVSS.

[0090] The gate electrode of the seventh transistor T7 can receive the first view angle signal VS1, the source electrode of the seventh transistor T7 can be connected to the fourth node N4, and the drain electrode of the seventh transistor T7 can be connected to the anode electrode of the first light emitting element EL1. The seventh transistor T7 can be referred to as a first view angle control transistor.

[0091] The gate electrode of the ninth transistor T9 can receive the bias signal GB[n], the source electrode of the ninth transistor T9 can be connected to the anode electrode of the first light emitting element EL1, and the drain electrode of the ninth transistor T9 can receive the anode initialization voltage VAIN T.

[0092] When the first view angle signal VS1 has an active level (e.g., a logic low level), the seventh transistor T7 can be turned on to transmit the drive current generated by the first transistor T1 to the first light emitting element EL1. When the drive current is transmitted to the first light emitting element EL1, the first light emitting element EL1 can turn on to emit light at a level corresponding to the brightness of the drive current.

[0093] The second light emitting circuit EC2 can include a second light emitting element EL2, an eighth transistor T8, and a tenth transistor T10. The viewing angle of the second light emitting circuit EC2 can be narrower than the viewing angle of the first light emitting circuit EC1. More specifically, the viewing angle of a display image displayed by the second light emitting circuit EC2 can be narrower than the viewing angle of a display image displayed by the first light emitting circuit EC1. For example, a first display image displayed by the first light emitting circuit EC1 in the first light emitting region can not be affected by the viewing angle, while a second display image displayed by the second light emitting circuit EC2 in the second light emitting region can be observed within a limited viewing angle of the second display image.

[0094] The anode electrode of the second light emitting element EL2 can be connected to the eighth transistor T8 and the tenth transistor T10, and the cathode electrode of the second light emitting element EL2 can receive the second power supply voltage ELVSS.

[0095] The second light emitting element EL2 can be smaller in size than the first light emitting element EL1, but the inventive concept can not be limited thereto.

[0096] The gate electrode of the eighth transistor T8 can receive the second viewing angle signal VS2, the source electrode of the eighth transistor T8 can be connected to the fourth node N4, and the drain electrode of the eighth transistor T8 can be connected to the anode electrode of the second light emitting element EL2. The eighth transistor T8 can be referred to as a second viewing angle control transistor.

[0097] The gate electrode of the tenth transistor T10 can receive the bias signal GB[n], the source electrode of the tenth transistor T10 can be connected to the anode electrode of the second light emitting element EL2, and the drain electrode of the tenth transistor T10 can receive the anode initialization voltage VAINT.

[0098] When the second viewing angle signal VS2 has an active level (e.g., a logic low level), the eighth transistor T8 can be turned on to transmit the driving current generated by the first transistor T1 to the second light emitting element EL2. When the driving current is transmitted to the second light emitting element EL2, the second light emitting element EL2 can turn on to emit light at a level of brightness corresponding to the driving current.

[0099] Although the first transistor T1 to the tenth transistor T10 are implemented with PMOS (P-channel metal-oxide-semiconductor) transistors in Figure 3 , other types of transistors can be used for the implementation. For example, each of the first transistor T1 to the tenth transistor T10 can be implemented with an NMOS (N-channel metal-oxide-semiconductor) transistor.

[0100] Although the first transistor T1 to the tenth transistor T10 are implemented with PMOS (P-channel metal-oxide-semiconductor) transistors in Figure 3Each of the second to fifth transistors T2 to T5 is implemented with a single transistor, but the inventive concept can not be limited thereto. For example, each of the second to fifth transistors T2 to T5 can be implemented with two or more transistors connected in series to reduce a leakage current while the transistors are turned off.

[0101] Since the first and second light emitting circuits EC1 and EC2 share the compensation circuit CC, the pixels PX can be effectively laid out, and the resolution of the display device 1 (see Figure 1 ) can be improved. Due to the effective layout of the pixels, the dead space and power consumption of the display device 1 can be reduced. In a display panel, the term "dead space" (also referred to as a bezel) refers to an outer edge area of a display that does not display an image. This area does not emit light and typically contains electronics and circuitry necessary for the display to operate.

[0102] Figure 4 is a timing chart illustrating operations of the pixel PX according to an embodiment of the inventive concept. Figure 3 Figure 5 is a circuit diagram illustrating operations of the pixel PX of Figure 3 in the first frame FP1 and the third frame FP3 of the timing chart of Figure 4 Figure 6 is a circuit diagram illustrating operations of the pixel PX of Figure 3 in the second frame FP2 and the fourth frame FP4 of the timing chart of Figure 4

[0103] Referring to Figure 1 , Figure 3 and Figure 4 , the display panel 100 can include a regular area and a narrow viewing angle area. The display panel 100 can display odd-numbered frames and even-numbered frames alternately in the regular area of the display panel 100 and the narrow viewing angle area of the display panel 100.

[0104] According to an embodiment, in an odd-numbered frame, the first viewing angle signal VS1 can have an active level and the second viewing angle signal VS2 can have a disabled level, where the odd-numbered frame is a frame having an odd number among a series of frames. Respectively, the active level can be a logic low level and the disabled level can be a logic high level. The odd-numbered frame can be the first frame FP1 or the third frame FP3. The data driver 500 can provide a regular image data voltage as a data voltage for the regular area of the display panel 100 and can not provide a data voltage for the narrow viewing angle area of the display panel 100. Alternatively, the data driver 500 can output a regular image data voltage as a data voltage for the regular area of the display panel 100 and output a black image data voltage as a data voltage for the narrow viewing angle area of the display panel 100. ​​​

[0105] In an even frame, the first view signal VS1 can have a disable level and the second view signal VS2 can have an active level. The even frame is an even numbered frame among a series of frames. The active level can be a logic low level and the disable level can be a logic high level. The even frame can be the second frame FP2 or the fourth frame FP4. The data driver 500 can not provide data voltages for the regular area of the display panel 100 and provide the narrow view image data voltages as the data voltages for the narrow view area of the display panel 100. Alternatively, the data driver 500 can provide black image data voltages as the data voltages for the regular area of the display panel 100 and provide the narrow view image data voltages as the data voltages for the narrow view area of the display panel 100.

[0106] Referring to Figure 3 to Figure 5 In an odd frame, the first view signal VS1 can have an active level and the seventh transistor T7 can be turned on. In the odd frame, the second view signal VS2 can have a disable level and the eighth transistor T8 can be turned off. The active level can be a logic low level and the disable level can be a logic high level. The odd frame can be the first frame FP1 or the third frame FP3. The driving current generated by the first transistor T1 can be transmitted to the first light emitting circuit EC1 and can not be transmitted to the second light emitting circuit EC2. The first light emitting element EL1 of the first light emitting circuit EC1 can be turned on by the driving current to emit light, while the second light emitting element EL2 of the second light emitting circuit EC2 can remain off. A regular image can be displayed in the regular area of the display panel 100 and no image can be displayed in the narrow view area of the display panel 100. Alternatively, a regular image can be displayed in the regular area of the display panel 100 and a black image can be displayed in the narrow view area of the display panel 100.

[0107] Referring to Figure 3 , Figure 4 and Figure 6In the even frame, the first view signal VS1 can have a disable level and the seventh transistor T7 can be turned off. In the even frame, the second view signal VS2 can have an active level and the eighth transistor T8 can be turned on. The active level can be a logic low level and the disable level can be a logic high level. The even frame can be the second frame FP2 or the fourth frame FP4. The drive current generated by the first transistor T1 can be transmitted to the second light emitting circuit EC2 and can not be transmitted to the first light emitting circuit ECl. The second light emitting element EL2 of the second light emitting circuit EC2 can be turned on by the drive current to emit light, while the first light emitting element ELL of the first light emitting circuit ECl can remain off. The viewing angle of the display image displayed with the second light emitting element EL2 can be narrower than the viewing angle of the display image displayed with the first light emitting element ELL. The regular image can not be displayed in the regular area of the display panel 100 and the narrow viewing angle image can be displayed in the narrow viewing angle area of the display panel 100. Alternatively, the black image can be displayed in the regular area of the display panel 100 and the narrow viewing angle image can be displayed in the narrow viewing angle area of the display panel 100.

[0108] Because the first light emitting circuit ECl and the second light emitting circuit EC2 are activated alternately, the total exposure time for the narrow viewing angle area can be reduced. More specifically, because the first light emitting circuit ECl is activated in the odd frame and is disabled in the even frame, and the second light emitting circuit EC2 is disabled in the odd frame and is activated in the even frame, the total exposure time for the narrow viewing angle area can be reduced to half.

[0109] The view controller 700 (see Figure 1 ) provides the first view signal VS1 and the second view signal VS2 to the pixel PX through the first view signal line VSL1 and the second view signal line VSL2. An additional scan driver for generating and outputting the first view signal VS1 and the second view signal VS2 can not be necessary. Thus, the dead space and the power consumption of the display device 1 can be reduced while the resolution of the display device 1 can be improved.

[0110] Figure 7 is a timing chart illustrating the operation of the pixel PX of Figure 3 according to an embodiment of the inventive concept. Figure 8 is a circuit diagram illustrating the operation of the pixel PX of Figure 3 in the first frame FP1 and the third frame FP3 of the timing chart of Figure 7 . Figure 9 is a circuit diagram illustrating the operation of the pixel PX of Figure 3 in the second frame FP2 and the fourth frame FP4 of the timing chart of Figure 7 .

[0111] Referring to Figure 1 ,Figure 3 and Figure 7 The display panel 100 can alternately display odd frames and even frames in the normal area of the display panel 100 and the narrow viewing angle area of the display panel 100.

[0112] In the odd frame, the first viewing angle signal VS1 can have an active level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level. The odd frame can be the first frame FP1 or the third frame FP3. The data driver 500 can output the normal image data voltage as the data voltage for the normal area and can not provide the data voltage for the narrow viewing angle area. Alternatively, the data driver 500 can provide the normal image data voltage as the data voltage for the normal area and provide the black image data voltage as the data voltage for the narrow viewing angle area.

[0113] In the even frame, the first viewing angle signal VS1 can have a disable level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level and the disable level can be a logic high level. The even frame can be the second frame FP2 or the fourth frame FP4. The data driver 500 can not provide the data voltage for the normal area and can provide the narrow viewing angle image data voltage as the data voltage for the narrow viewing angle area. Alternatively, the data driver 500 can provide the black image data voltage as the data voltage for the normal area and provide the narrow viewing angle image data voltage as the data voltage for the narrow viewing angle area.

[0114] Referring to Figure 3 , Figure 7 and Figure 8 In the odd frame, both the first viewing angle signal VS1 and the second viewing angle signal VS2 can have an active level, and the seventh transistor T7 and the eighth transistor T8 can be turned on, where the active level can be a logic low level and the odd frame can be the first frame FP1 or the third frame FP3. The driving current generated by the first transistor T1 can be transmitted to both the first light emitting circuit EC1 and the second light emitting circuit EC2. Both the first light emitting element EL1 of the first light emitting circuit EC1 and the second light emitting element EL2 of the second light emitting circuit EC2 can be turned on by the driving current to emit light. A normal image can be displayed in the normal area of the display panel 100, and a black image can be output in the narrow viewing angle area of the display panel 100.

[0115] Because both the first light emitting element EL1 and the second light emitting element EL2 are turned on based on the normal image data voltage to emit light for the normal area, the brightness level of the normal area can be higher than the brightness level of the normal area when only the first light emitting element EL1 is turned on to emit light.

[0116] Referring toFigure 3 , Figure 7 and Figure 9 In even-numbered frames, the first viewing angle signal VS1 can have a disabled level and the seventh transistor T7 can be turned off, where the disabled level is a logic high level, and the even-numbered frames can be the second frame FP2 or the fourth frame FP4. The second viewing angle signal VS2 can have an active level and the eighth transistor T8 can be turned on. The drive current generated by the first transistor T1 can be transmitted to the second light-emitting circuit EC2 or not to the first light-emitting circuit EC1. The second light-emitting element EL2 of the second light-emitting circuit EC2 can be turned on by the drive current to emit light, while the first light-emitting element EL1 of the first light-emitting circuit EC1 can remain off. The viewing angle of the image displayed through the second light-emitting element EL2 can be narrower than the viewing angle of the image displayed through the first light-emitting element EL1. In even-numbered frames, a regular image can not be displayed in the regular area of ​​the display panel 100, and a narrow-viewing-angle image can be displayed in the narrow-viewing-angle area of ​​the display panel 100. Alternatively, a black image can be displayed in the regular area of ​​the display panel 100, and a narrow-viewing-angle image can be displayed in the narrow-viewing-angle area of ​​the display panel 100.

[0117] Because both the first light-emitting circuit EC1 and the second light-emitting circuit EC2 are activated in odd-numbered frames, and the first light-emitting circuit EC1 is disabled in even-numbered frames while the second light-emitting circuit EC2 is activated in even-numbered frames, the total exposure time in the narrow field of view area can be reduced.

[0118] The viewing angle controller 700 provides the first viewing angle signal VS1 and the second viewing angle signal VS2 to the pixel PX via the first viewing angle signal line VSL1 and the second viewing angle signal line VSL2. An additional scan driver for generating and outputting the first viewing angle signal VS1 and the second viewing angle signal VS2 is not required. Therefore, unnecessary space and power consumption in the display device 1 can be reduced, while the resolution of the display device 1 can be improved.

[0119] Figure 10 This is a block diagram illustrating a display device 1a according to an embodiment of the concept of the present invention.

[0120] In addition to the view controller 700a being included in the drive controller 200a, the display device 1a and the reference Figure 1 The display device 1 described in the embodiment is substantially the same.

[0121] The view controller 700a can be embedded in the drive controller 200a. The drive controller 200a can provide a first view signal VS1 (see...) for pixel PX. Figure 3 ) and second-view signal VS2 (see Figure 3The data driver 500a can provide the first view angle signal VS1 and the second view angle signal VS2 to the plurality of pixels PX through the first view angle signal line VSL1 and the second view angle signal line VSL2 to control the view angle of the display panel 100.

[0122] The data driver 500a can provide the first view angle signal VS1 and the second view angle signal VS2 to the plurality of pixels PX through the first view angle signal line VSL1 and the second view angle signal line VSL2 to control the view angle of the display panel 100.

[0123] An additional scan driver for generating and outputting the first view angle signal VS1 and the second view angle signal VS2 can not be necessary. Accordingly, it is possible to reduce the useless space and power consumption of the display apparatus 1a while it is possible to improve the resolution of the display apparatus 1a.

[0124] Figure 11 is a block diagram illustrating a display apparatus 1b according to an embodiment of the inventive concept.

[0125] The display apparatus 1b is substantially the same as the display apparatus 1 described with reference to the embodiment explained above except that the view angle controller 700b is embedded in the data driver 500b. Figure 1

[0126] The data driver 500b can provide the first view angle signal VS1 (see Figure 3 ) and the second view angle signal VS2 (see Figure 3 ) to the plurality of pixels PX through the first view angle signal line VSL1 and the second view angle signal line VSL2 to control the view angle of the display panel 100.

[0127] An additional scan driver for generating and outputting the first view angle signal VS1 and the second view angle signal VS2 can not be necessary. Accordingly, it is possible to reduce the useless space and power consumption of the display apparatus 1b while it is possible to improve the resolution of the display apparatus 1b.

[0128] Figure 12 is a block diagram illustrating a display apparatus 1c according to an embodiment of the inventive concept.

[0129] The display apparatus 1c is substantially the same as the display apparatus 1 described with reference to the embodiment explained above except that the view angle controller 700c is embedded in the gate driver 300c. Figure 1

[0130] The gate driver 300c can provide the first view angle signal VS1 (see Figure 3 ) and the second view angle signal VS2 (see Figure 3 ) to the plurality of pixels PX through the first view angle signal line VSL1 and the second view angle signal line VSL2 to control the view angle of the display panel 100.

[0131] ​​The additional scan driver for generating and outputting the first view angle signal VS1 and the second view angle signal VS2 can not be necessary. Thus, the dead space and power consumption of the display apparatus 1c can be reduced, while the resolution of the display apparatus 1c can be improved.

[0132] Figure 13 is a block diagram illustrating a display apparatus 1d according to an embodiment of the inventive concept.

[0133] The display apparatus 1d is substantially the same as the display apparatus 1 described with reference to Figure 1 the above-described embodiment, except that the view angle controller 700d is embedded in the emission driver 600d.

[0134] The emission driver 600d can provide the first view angle signal VS1 (see Figure 3 ) and the second view angle signal VS2 (see Figure 3 ) to the pixel PX through the first view angle signal line VSL1 and the second view angle signal line VSL2 to control the view angle of the display panel 100.

[0135] The additional scan driver for generating and outputting the first view angle signal VS1 and the second view angle signal VS2 can not be necessary. Thus, the dead space and power consumption of the display apparatus 1d can be reduced, while the resolution of the display apparatus 1d can be improved.

[0136] Figure 14 is a flowchart illustrating a driving mode of the display apparatus 1 (see Figure 1 ) according to an embodiment of the inventive concept.

[0137] Referring to Figure 1 , Figure 3 and Figure 14 , the display apparatus 1 can operate in one of a normal mode and a narrow view angle mode.

[0138] In the normal mode, the first view angle signal VS1 can have an active level and the second view angle signal VS2 can have a disable level regardless of the frame sequence. For example, in odd and even frames of the normal mode, the first view angle signal VS1 can have an active level, and in odd and even frames of the normal mode, the second view angle signal VS2 can have a disable level. The active level can be a logic low level and the disable level is a logic high level.

[0139] In the normal mode, the seventh transistor T7 can be turned on, and the eighth transistor T8 can be turned off. Thus, the first light emitting circuit EC1 can be activated and the first light emitting element EL1 can turn on to emit light, and the second light emitting circuit EC2 can be disabled and the second light emitting element EL2 can remain off.

[0140] Since the first light emitting element EL1 is turned on and the second light emitting element EL2 is turned off in the normal mode, the display panel 100 can have only the normal area in the normal mode.

[0141] In the odd frame of the narrow viewing angle mode, the first viewing angle signal VS1 can have an active level and the second viewing angle signal VS2 can have a disable level, where the active level can be a logic low level and the disable level is a logic high level. The seventh transistor T7 can be turned on by the first viewing angle signal VS1 and the eighth transistor T8 can be turned off by the second viewing angle signal VS2. Therefore, the driving current generated by the first transistor T1 can be transmitted to the first light emitting circuit EC1 and can not be transmitted to the second light emitting circuit EC2. The first light emitting element EL1 of the first light emitting circuit EC1 can be turned on by the driving current to emit light, while the second light emitting element EL2 of the second light emitting circuit EC2 can remain off, and a normal image can be displayed in the normal area of the display panel 100 and a narrow viewing angle image can not be displayed in the narrow viewing angle area. Alternatively, a normal image can be displayed in the normal area of the display panel 100 and a black image can be displayed in the narrow viewing angle area.

[0142] In the even frame of the narrow viewing angle mode, the first viewing angle signal VS1 can have a disable level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level and the disable level is a logic high level. The seventh transistor T7 can be turned off by the first viewing angle signal VS1 and the eighth transistor T8 can be turned on by the second viewing angle signal VS2. Therefore, the driving current generated by the first transistor T1 can be transmitted to the second light emitting circuit EC2 and can not be transmitted to the first light emitting circuit EC1. The second light emitting element EL2 of the second light emitting circuit EC2 can be turned on by the driving current to emit light, while the first light emitting element EL1 of the first light emitting circuit EC1 can remain off. A normal image can not be displayed in the normal area of the display panel 100 and a narrow viewing angle image can be displayed in the narrow viewing angle area. Alternatively, a black image can be displayed in the normal area of the display panel 100 and a narrow viewing angle image can be displayed in the narrow viewing angle area.

[0143] Since the first light emitting circuit EC1 and the second light emitting circuit EC2 are activated alternately, the total exposure time of the narrow viewing angle area can be reduced.

[0144] Figure 15 is a flowchart showing a driving mode of the display apparatus 1 according to an embodiment of the present inventive concept.

[0145] The driving mode of the display device 1 according to the present embodiment is substantially the same as that described with reference to Figure 14 The driving mode of the display device 1 described is substantially the same.

[0146] In the odd frame of the narrow viewing angle mode, both the first viewing angle signal VS1 and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level. The seventh transistor T7 and the eighth transistor T8 can be turned on by the first viewing angle signal VS1 and the second viewing angle signal VS2. Thus, the driving current generated by the first transistor T1 can be divided and transmitted to the first light emitting circuit EC1 and the second light emitting circuit EC2. Both the first light emitting element EL1 and the second light emitting element EL2 can be turned on to emit light based on the divided driving current.

[0147] The first light emitting element EL1 and the second light emitting element EL2 can be turned on to emit light based on the regular image data voltage for the regular area. When the first light emitting element EL1 and the second light emitting element EL2 are turned on, the brightness level of the regular area can be higher compared to the brightness level of the regular area when only the first light emitting element EL1 is turned on to emit light.

[0148] In the even frame of the narrow viewing angle mode, the first light emitting circuit EC1 is disabled, and the second light emitting circuit EC2 is activated. The viewing angle of the narrow viewing angle area can be narrower than that of the regular area. Thus, the total exposure time of the narrow viewing angle area can be reduced.

[0149] Figure 16 is a flowchart showing a method of operating the display device 1 (see Figure 1 ) according to an embodiment of the inventive concept.

[0150] With reference to Figure 1 to Figure 3 and Figure 14 to Figure 16 , the method of operating the display device 1 can include selecting one of a regular mode and a narrow viewing angle mode having a narrower viewing angle than that of the regular mode as a driving mode (operation S100), providing a first viewing angle signal VS1 and a second viewing angle signal VS2 for a plurality of pixels PX according to the driving mode (operation S200), and providing a gate signal, a data voltage, and an emission signal for the plurality of pixels PX (operation S300).

[0151] For selecting one of the regular mode and the narrow viewing angle mode as the driving mode (operation S100), the viewing angle controller 700 can generate the first viewing angle signal VS1 and the second viewing angle signal VS2 based on the selected driving mode.

[0152] According to an embodiment, in the normal mode, the first view signal VS1 can have an active level and the second view signal VS2 can have a disable level regardless of the frame sequence, where the active level can be a logic low level and the disable level is a logic high level.

[0153] In the odd frame of the narrow view mode, the first view signal VS1 can have an active level and the second view signal VS2 can have a disable level. In the even frame of the narrow view mode, the first view signal VS1 can have a disable level and the second view signal VS2 can have an active level. The active level can be a logic low level and the disable level is a logic high level.

[0154] For providing the first view signal VS1 and the second view signal VS2 to the plurality of pixels PX according to the driving mode (operation S200), the view controller 700 can provide the first view signal VS1 and the second view signal VS2 to the pixel PX through the first view signal line VSL1 and the second view signal line VSL2. The seventh transistor T7 of the pixel PX can be turned on and / or turned off based on the logic level of the first view signal VS1. The eighth transistor T8 of the pixel PX can be turned on and / or turned off based on the logic level of the second view signal VS2.

[0155] According to an embodiment, in the normal mode, the first view signal VS1 can have an active level and the second view signal VS2 can have a disable level regardless of the frame sequence. Accordingly, the seventh transistor T7 can be turned on and the eighth transistor T8 can be turned off. The first light emitting circuit EC1 can be activated, and the first light emitting element EL1 can be turned on to emit light. The second light emitting circuit EC2 can be disabled, and the second light emitting element EL2 can remain turned off.

[0156] In the odd frame of the narrow view mode, the first view signal VS1 can have an active level and the second view signal VS2 can have a disable level, where the active level can be a logic low level and the disable level is a logic high level. The seventh transistor T7 can be turned on by the first view signal VS1, and the eighth transistor T8 can be turned off by the second view signal VS2. Accordingly, the driving current generated by the first transistor T1 can be transmitted to the first light emitting circuit EC1 and can not be transmitted to the second light emitting circuit EC2. The first light emitting element EL1 of the first light emitting circuit EC1 can be turned on to emit light by the driving current, and the second light emitting element EL2 of the second light emitting circuit EC2 can remain turned off.

[0157] In the even frame of the narrow viewing angle mode, the first viewing angle signal VS1 can have a disable level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level and the disable level is a logic high level. The seventh transistor T7 can be turned off by the first viewing angle signal VS1, and the eighth transistor T8 can be turned on by the second viewing angle signal VS2. Thus, the driving current generated by the first transistor T1 can be transmitted to the second light emitting circuit EC2 and can not be transmitted to the first light emitting circuit EC1. The second light emitting element EL2 of the second light emitting circuit EC2 can be turned on by the driving current to emit light, while the first light emitting element EL1 of the first light emitting circuit EC1 can remain off.

[0158] In the odd frame of the narrow viewing angle mode, the first viewing angle signal VS1 can have an active level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level. The seventh transistor T7 can be turned on by the first viewing angle signal VS1 and the eighth transistor T8 can be turned on by the second viewing angle signal VS2. Thus, the driving current generated by the first transistor T1 can be transmitted to both the first light emitting circuit EC1 and the second light emitting circuit EC2. The first light emitting element EL1 of the first light emitting circuit EC1 and the second light emitting element EL2 of the second light emitting circuit EC2 can be turned on to emit light.

[0159] The first light emitting element EL1 and the second light emitting element EL2 can be turned on to emit light based on the regular image data voltage for the regular region. Because both the first light emitting element EL1 and the second light emitting element EL2 can be turned on, the luminance level of the display device 1 in the regular region can be higher compared to the luminance level of the display device 1 in the regular region when only the first light emitting element EL1 is turned on to emit light.

[0160] In the even frame of the narrow viewing angle mode, the first viewing angle signal VS1 can have a disable level and the second viewing angle signal VS2 can have an active level, where the active level can be a logic low level and the disable level can be a logic high level. The seventh transistor T7 can be turned off by the first viewing angle signal VS1, and the eighth transistor T8 can be turned on by the second viewing angle signal VS2. Thus, the driving current generated by the first transistor T1 can be transmitted to the second light emitting circuit EC2 and can not be transmitted to the first light emitting circuit EC1. The second light emitting element EL2 of the second light emitting circuit EC2 can be turned on by the driving current to emit light, while the first light emitting element EL1 of the first light emitting circuit EC1 can remain off.

[0161] The gate driver 300 can provide the gate signal to the display panel 100, the data driver 500 can provide the data voltage VDATA to the display panel 100, and the emission driver 600 can provide the emission signal to the display panel 100 according to the driving mode, in order to provide the gate signal, the data voltage, and the emission signal for the plurality of pixels PX (operation S300).

[0162] Because the levels of the first view angle signal VS1 and the second view angle signal VS2 are controlled in the narrow view angle mode, the view angle of the display device 1 in the narrow view angle region can be narrower than the view angle of the display device 1 in the regular region. Accordingly, the total exposure time of the narrow view angle region can be reduced.

[0163] The view angle controller 700 provides the first view angle signal VS1 and the second view angle signal VS2 to the plurality of pixels PX through the first view angle signal line VSL1 and the second view angle signal line VSL2. An additional scan driver for generating and outputting the first view angle signal VS1 and the second view angle signal VS2 can not be necessary. Accordingly, the useless space and the power consumption of the display device 1 can be reduced, while the resolution of the display device 1 can be improved.

[0164] Figure 17 is a block diagram illustrating an electronic device 1000 according to an embodiment of the idea of the present invention. Figure 18 is a diagram of a smart phone, which is an example of the electronic device 1000. Figure 17

[0165] Referring to Figure 17 and Figure 18 , the electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 can be the display device 1 of Figure 1 . In addition, the electronic device 1000 can further include a port for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices.

[0166] The input / output (I / O) device 1040 can sense a user input via a touch or a cursor selection of an icon presented in a display panel, in which the processor is caused to perform one of a regular view angle mode and a narrow view angle mode of the display device upon receiving the user input.

[0167] ​The display panel of the display device 1060 can include a regular viewing angle area and a narrow viewing angle area, and when the processor 1010 is caused to execute a first viewing angle mode (i.e., a regular viewing angle mode), a viewing angle of the regular viewing angle area and a viewing angle of the narrow viewing angle area are substantially the same, and when the processor 1010 is caused to execute a second viewing angle mode (i.e., a narrow viewing angle mode), the viewing angle of the narrow viewing angle area is narrower than the viewing angle of the regular viewing angle area.

[0168] The input / output (I / O) device 1040 can be a touch screen embedded in the display panel, and the touch screen can include a touch sensor for sensing a touch or tap by a user.

[0169] As shown in FIG. 1A, Figure 18 The electronic device 1000 can be a smart phone, as shown in FIG. 1A. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be a television, a monitor, a cellular phone, a video phone, a smart pad, a smart watch, a tablet personal computer (PC), a car navigation system, a laptop computer, and a head-mounted display (HMD) device.

[0170] The processor 1010 can implement various computing functions. The processor 1010 can be a microprocessor, a central processing unit (CPU), and an application processor (AP). The processor 1010 can be coupled to other components via an address bus, a control bus, and a data bus. The processor 1010 can be coupled to an extension bus, such as a peripheral component interconnect (PCI) bus.

[0171] The processor 1010 can provide input image data IMG (see FIG. 1B) and an input control signal CONT (see FIG. 1C) to the driving controller 200. Figure 1 Figure 1 Figure 1

[0172] The memory device 1020 can store data for operating the electronic device 1000. For example, the memory device 1020 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0173] ​​​The storage 1030 can include a solid state drive (SSD) device, a hard disk drive (HDD) device, and a read-only compact disc memory (CD-ROM) device.

[0174] The I / O device 1040 can include an input device such as a keyboard, a keypad, a mouse device, a touchpad, and a touch screen, and an output device such as a printer and a speaker. The I / O device 1040 can include the display device 1060.

[0175] The power supply 1050 can supply power used to operate the electronic device 1000.

[0176] The display device 1060 can be connected to other components through a bus or other communication links.

[0177] The inventive concept can be applied to any display device and any electronic device including a display device. For example, the inventive concept can be applied to a television (TV), a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal computer (PC), a home appliance, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, and a navigation device.

[0178] The foregoing is a summary of the inventive concept and should not be construed as limiting the inventive concept. Although several embodiments of the inventive concept have been described, it will be readily apparent to those skilled in the art that many modifications can be made within the novel teachings and advantages of the inventive concept. Accordingly, the modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structure described herein as performing the recited function and not only structural equivalents but also equivalent structures. It will be appreciated that the specification is intended to be construed as not limited to the particular embodiments disclosed in the specification and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims and their equivalents, and the equivalents are included within the inventive concept.

Claims

1. A display device, wherein, The display device includes: a display panel including a plurality of pixels; a gate driver configured to generate gate signals to provide the gate signals for the plurality of pixels; a data driver configured to generate data voltages to provide the data voltages for the plurality of pixels; an emission driver configured to generate emission signals to provide the emission signals for the plurality of pixels; a driving controller configured to generate display image data based on input image data; and a viewing angle controller configured to generate first and second viewing angle signals to provide the first and second viewing angle signals for the plurality of pixels, wherein the display image data is alternately displayed in the display panel at different viewing angles in response to the first and second viewing angle signals, wherein each of the plurality of pixels includes: a first light emitting circuit including a first light emitting element and a first viewing angle control transistor, wherein the first viewing angle control transistor is turned on in response to the first viewing angle signal to transmit a driving current to the first light emitting element; and a second light emitting circuit including a second light emitting element and a second viewing angle control transistor, wherein the second viewing angle control transistor is turned on in response to the second viewing angle signal to transmit a driving current to the second light emitting element, and wherein a viewing angle of the second light emitting circuit is narrower than a viewing angle of the first light emitting circuit.

2. The display device according to claim 1, wherein Each of the plurality of pixels is configured to receive the first and second viewing angle signals through first and second viewing angle signal lines, respectively.

3. The display device according to claim 2, wherein Each of the plurality of pixels includes a compensation circuit, and the compensation circuit includes: a data write transistor configured to receive the data voltage; a driving transistor configured to generate a driving current corresponding to the data voltage; and an emission transistor configured to transmit the driving current to the first and second light emitting circuits in response to the emission signal, wherein the compensation circuit is configured to compensate for a threshold voltage of the driving transistor.

4. The display device according to claim 3, wherein a gate electrode of the first viewing angle control transistor is connected to the first viewing angle signal line, a source electrode of the first viewing angle control transistor is connected to the compensation circuit, and a drain electrode of the first viewing angle control transistor is connected to an anode electrode of the first light emitting element, and a gate electrode of the second viewing angle control transistor is connected to the second viewing angle signal line, a source electrode of the second viewing angle control transistor is connected to the compensation circuit, and a drain electrode of the second viewing angle control transistor is connected to an anode electrode of the second light emitting element.

5. The display device of claim 4, wherein, a gate electrode of the emission transistor receives the emission signal, a source electrode of the emission transistor is connected to a drain electrode of the driving transistor, and a drain electrode of the emission transistor is connected to the source electrode of the first viewing angle control transistor, and the source electrode of the second viewing angle control transistor is connected to the drain electrode of the emission transistor.

6. The display device according to claim 1, wherein In odd frames, the first view signal has an active level and the second view signal has a disabled level, wherein the odd frames are odd-numbered frames among a series of frames, and in even frames, the first view signal has a disabled level and the second view signal has an active level, wherein the even frames are even-numbered frames among the series of frames.

7. The display device of claim 6, wherein, In the odd frames, the first view signal has a logic low level and the second view signal has a logic high level, and in the even frames, the first view signal has a logic high level and the second view signal has the logic low level.

8. The display device according to claim 1, wherein In odd frames, the first view signal has an active level and the second view signal has an active level, wherein the odd frames are odd-numbered frames among a series of frames, and in even frames, the first view signal has a disabled level and the second view signal has the active level, wherein the even frames are even-numbered frames among the series of frames.

9. The display device of claim 8, wherein, In the odd frames, the first view signal has a logic low level and the second view signal has a logic low level, and in the even frames, the first view signal has a logic high level and the second view signal has the logic low level.

10. The display device according to claim 1, wherein The view angle controller is embedded in one of the gate driver, the data driver, the emission driver, and the driving controller.

11. A display device, wherein, The display device includes: a display panel including a plurality of pixels; a gate driver configured to generate a gate signal to provide the gate signal for the plurality of pixels; a data driver configured to generate a data voltage to provide the data voltage for the plurality of pixels; an emission driver configured to generate an emission signal to provide the emission signal for the plurality of pixels; a driving controller configured to generate display image data based on input image data; and a view angle controller configured to generate a first view signal and a second view signal to provide the first view signal and the second view signal for the plurality of pixels, wherein the display image data is alternately displayed in different view angles in the display panel in response to the first view signal and the second view signal, wherein each of the plurality of pixels includes: a first light emitting circuit including a first light emitting element and a first view angle control transistor, wherein the first view angle control transistor is turned on to transmit a driving current to the first light emitting element in response to the first view signal; and a second light emitting circuit including a second light emitting element and a second view angle control transistor, wherein the second view angle control transistor is turned on to transmit a driving current to the second light emitting element in response to the second view signal, wherein a view angle of the second light emitting circuit is narrower than a view angle of the first light emitting circuit, and wherein the display device is configured to operate in one of a regular mode and a narrow view angle mode, wherein a view angle in the narrow view angle mode is narrower than a view angle in the regular mode.

12. The display device of claim 11, wherein, In the normal mode, in odd frames and even frames, the first view signal has an active level and the second view signal has a disable level, wherein the odd frames are odd numbered frames among a series of frames and the even frames are even numbered frames among the series of frames, and in the narrow view mode, in the odd frames, the first view signal has the active level and the second view signal has the disable level, and in the even frames, the first view signal has a disable level and the second view signal has the active level.

13. The display device of claim 12, wherein, In the normal mode, in the odd frames and the even frames, the first view signal has a logic low level and the second view signal has a logic high level, and in the narrow view mode, in the odd frames, the first view signal has the logic low level and the second view signal has a logic low level, and in the even frames, the first view signal has a logic high level and the second view signal has the logic low level.

14. The display device of claim 11, wherein, In the normal mode, in odd frames and even frames, the first view signal has an active level and the second view signal has a disable level, wherein the odd frames are odd numbered frames among a series of frames and the even frames are even numbered frames among the series of frames, and in the narrow view mode, in the odd frames, the first view signal has the active level and the second view signal has an active level, and in the even frames, the first view signal has a disable level and the second view signal has the active level.

15. The display device of claim 14, wherein, In the normal mode, in the even frames and the odd frames, the first view signal has a logic low level, and in the even frames and the odd frames, the second view signal has a logic high level, and in the narrow view mode, in the odd frames, the first view signal has the logic low level and the second view signal has a logic low level, and in the even frames, the first view signal has a logic high level and the second view signal has the logic low level.

16. The display device of claim 11, wherein, Each of the plurality of pixels is configured to receive the first view signal and the second view signal through a first view signal line and a second view signal line, respectively.

17. The display device of claim 16, wherein, Each of the plurality of pixels includes a compensation circuit, and the compensation circuit includes: a data write transistor configured to receive the data voltage; a drive transistor configured to generate a drive current corresponding to the data voltage; and an emission transistor configured to transmit the drive current to the first light emitting circuit and the second light emitting circuit in response to the emission signal, and wherein the compensation circuit is configured to compensate for a threshold voltage of the drive transistor.

18. The display device of claim 17, wherein, A gate electrode of the first view control transistor is connected to the first view signal line, a source electrode of the first view control transistor is connected to the compensation circuit, and a drain electrode of the first view control transistor is connected to an anode electrode of the first light emitting element, and a gate electrode of the second view control transistor is connected to the second view signal line, a source electrode of the second view control transistor is connected to the compensation circuit, and a drain electrode of the second view control transistor is connected to an anode electrode of the second light emitting element.

19. An electronic device, wherein, The electronic device includes: a processor configured to output an input control signal and input image data; and a display device configured to display an image based on the input image data, the display device including: a display panel including a plurality of pixels; a gate driver configured to generate a gate signal to supply the gate signal for the plurality of pixels; a data driver configured to generate a data voltage to supply the data voltage for the plurality of pixels; an emission driver configured to generate an emission signal to supply the emission signal for the plurality of pixels; a driving controller configured to generate display image data based on the input control signal and the input image data; and a view controller configured to generate a first view signal and a second view signal to supply the first view signal and the second view signal for the plurality of pixels, wherein the display image data is alternately displayed in the display panel at different view angles in response to the first view signal and the second view signal, wherein each of the plurality of pixels includes: a first light emitting circuit including a first light emitting element and a first view control transistor, wherein the first view control transistor is turned on to transmit a driving current to the first light emitting element in response to the first view signal; and a second light emitting circuit including a second light emitting element and a second view control transistor, wherein the second view control transistor is turned on to transmit a driving current to the second light emitting element in response to the second view signal, and wherein a view angle of the second light emitting circuit is narrower than a view angle of the first light emitting circuit. 20.The electronic device of claim 19, wherein, The electronic device further includes an input / output device configured to sense a user input via a touch or a cursor selection of an icon presented in the display panel, wherein the processor is caused to execute one of a first view mode and a second view mode of the display device upon receiving the user input, wherein the display panel includes a regular view angle area and a narrow view angle area, and when the processor is caused to execute the first view mode, a view angle of the regular view angle area and a view angle of the narrow view angle area are the same, and when the processor is caused to execute the second view mode, the view angle of the narrow view angle area is narrower than the view angle of the regular view angle area.

Images