Display device and electronic terminal

Abstract

The invention provides a display device and an electronic terminal. A pixel of the display device comprises a light-emitting device and a pixel driving circuit, the pixel driving circuit comprises a first transistor, a third transistor and a second capacitor, the first transistor is an oxide semiconductor thin film transistor, one of a source electrode and a drain electrode of the third transistor is electrically connected with one of a source electrode and a drain electrode of the first transistor, and the second capacitor is electrically connected with the first transistor. The other one of the source electrode and the drain electrode of the third transistor is electrically connected with the grid electrode of the first transistor, one pole plate of the second capacitor is electrically connected with the grid electrode of the third transistor, and the other pole plate of the second capacitor is electrically connected with the grid electrode of the first transistor. The coupling effect of the grid electrode of the third transistor on the grid electrode of the first transistor is enhanced through the second capacitor, the leakage current when the third transistor is closed is reduced, and the technical problem that the pixel driving circuit with the driving transistor being an oxide semiconductor thin film transistor causes the phenomenon of negative and positive screens of the display device is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and an electronic terminal. BACKGROUND

[0002] In a pixel driving circuit of an organic light-emitting diode (OLED) display panel, in the case that a first transistor as a driving transistor is an oxide semiconductor thin film transistor, the organic light-emitting diode display panel is prone to a positive and negative screen phenomenon, as shown in FIG. 1, that is, the organic light-emitting diode display panel will appear a color uneven phenomenon of bright area Z1 and dark area Z2 when displaying the same gray scale (for example, 0 gray scale), which seriously affects the display quality. Figure 1

[0003] Therefore, it is necessary to provide a new technical scheme to solve the above technical problems. SUMMARY

[0004] The embodiment of the present application aims to provide a display device and an electronic terminal, and aims to solve the technical problem of the positive and negative screen phenomenon of the display device in which the driving transistor of the pixel driving circuit is an oxide semiconductor thin film transistor.

[0005] The embodiment of the present application provides a display device, which comprises a display panel, the display panel comprises a plurality of pixels, the pixel comprises a light-emitting device and a pixel driving circuit, the pixel driving circuit comprises a first transistor, a third transistor and a second capacitor, the first transistor is an oxide semiconductor thin film transistor, one of the source and the drain of the third transistor is electrically connected with one of the source and the drain of the first transistor, the other of the source and the drain of the third transistor is electrically connected with the gate of the first transistor, one of the two polar plates of the second capacitor is electrically connected with the gate of the third transistor, and the other of the two polar plates of the second capacitor is electrically connected with the gate of the first transistor.

[0006] In the above display device, the pixel driving circuit further comprises a metal member; one of the two polar plates of the second capacitor comprises the gate of the third transistor, and the other of the two polar plates of the second capacitor comprises the metal member; and the metal member and the gate of the third transistor at least partially overlap in the visual angle of viewing the display panel from above.

[0007] In the above display device, the gate of the third transistor comprises a first gate and / or a second gate; one of the two polar plates of the second capacitor comprises the first gate and / or the second gate; and the metal member and the first gate and / or the second gate at least partially overlap in the visual angle of viewing the display panel from above.

[0008] ​In the display device, in a view angle of viewing the display panel from above, a size of the metal member in a second direction is greater than any one of a width of the scan signal line corresponding to the first gate electrode, and a width of the scan signal line corresponding to the second gate electrode; the second direction is a width direction of the scan signal line corresponding to the first gate electrode and / or the second gate electrode.

[0009] In the display device, in a view angle of viewing the display panel from above, the metal member does not overlap with one of the source electrode and the drain electrode of the first transistor.

[0010] In the display device, one of the source electrode and the drain electrode of the first transistor includes a first trace and a second trace; in a view angle of viewing the display panel from above, the first trace is parallel to a first direction, and the second trace is perpendicular to the first direction; a distance between the second trace and the metal member is greater than a distance between the first trace and the metal member; the first direction is a length direction of the scan signal line corresponding to the gate electrode of the third transistor.

[0011] In the display device, in a view angle of viewing the display panel from above, an edge of the metal member close to the second trace is parallel to a part of the edge of the second trace, and an edge of the metal member close to the first trace is parallel to a part of the edge of the first trace.

[0012] In the display device, the display panel includes a substrate and a plurality of film layers disposed on the substrate; at least one of the plurality of film layers includes one of the source electrode and the drain electrode of the third transistor; the metal member is located in the same film layer as the one of the source electrode and the drain electrode of the third transistor.

[0013] In the display device, in a view angle of viewing the display panel from above, a size of the metal member in a first direction is greater than a width of the scan signal line corresponding to the gate electrode of the third transistor; the first direction is a length direction of the scan signal line corresponding to the gate electrode of the third transistor.

[0014] In the display device, the pixel driving circuit further comprises a second transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor; one of the source and the drain of the second transistor is electrically connected with the second scan signal input end, and the other of the source and the drain of the second transistor is electrically connected with the other of the source and the drain of the first transistor; the gate of the fourth transistor is electrically connected with the second light-emitting control signal input end or the third light-emitting control signal input end, and one of the source and the drain of the fourth transistor is electrically connected with the first reset signal input end; the gate of the fifth transistor is electrically connected with the first light-emitting control signal input end, one of the source and the drain of the fifth transistor is electrically connected with the first power signal input end, and the other of the source and the drain of the fifth transistor is electrically connected with one of the source and the drain of the first transistor and / or one of the source and the drain of the third transistor; the gate of the sixth transistor is electrically connected with the second light-emitting control signal input end, one of the source and the drain of the sixth transistor is electrically connected with the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected with the other of the source and the drain of the fourth transistor; one of the plates of the first capacitor is electrically connected with the other of the source and the drain of the fourth transistor, and the other plate of the first capacitor is electrically connected with a line between the other of the source and the drain of the third transistor and the gate of the first transistor; one of the plates of the second capacitor is electrically connected with the gate of the third transistor, and the other plate of the second capacitor is electrically connected with a line between the other of the source and the drain of the third transistor and the gate of the first transistor.

[0015] The embodiment of the present application further provides an electronic terminal, which comprises the display device.

[0016] The display device provided by the present application effectively solves the technical problem of the display device in which the driving transistor of the pixel driving circuit is an oxide semiconductor thin film transistor, and the display device has the phenomenon of positive and negative screens.

[0017] Specifically, during the operation of the pixel driving circuit, when the level of the first scan signal input end is switched from high to low, the third transistor is switched from an open state to a closed state. In the prior art, the potential change of the first scan signal input end will produce uneven coupling effects on the gate of the first transistor and one of the source and the drain of the first transistor, and the coupling effect on one of the source and the drain of the first transistor is greater, resulting in that the potential drop of one of the source and the drain of the first transistor is greater than the potential drop of the gate of the first transistor, thereby generating a potential difference between the gate of the first transistor and one of the source and the drain of the first transistor, so that the current flows from the gate of the first transistor to one of the source and the drain of the first transistor, forming a leakage current.

[0018] The second capacitor is directly connected between the gate of the third transistor (the first scan signal input end) and the gate of the first transistor, and when the potential of the first scan signal input end changes, the second capacitor can more effectively transmit the potential change of the first scan signal input end to the gate of the first transistor, thereby enhancing the coupling effect of the first scan signal input end on the gate of the first transistor. The enhanced coupling effect enables the potential of the gate of the first transistor to more closely follow the potential change of the first scan signal input end, and when the potential of the first scan signal input end decreases, the potential of the gate of the first transistor also decreases accordingly, thereby reducing the potential difference between the gate of the first transistor and one of the source and the drain of the first transistor.

[0019] By reducing the above-mentioned potential difference, the second capacitor effectively suppresses the flow of current from the gate of the first transistor to one of the source and the drain of the first transistor, and significantly reduces the leakage current when the third transistor is closed. The reduction of the leakage current directly improves the electrical uniformity of the pixel driving circuit, and when the threshold voltage of the third transistor deviates, the second capacitor can effectively suppress the leakage current phenomenon aggravated by the threshold voltage deviation, thereby preventing the display panel from appearing the color unevenness of bright and dark areas, and significantly improving the positive and negative screen problem. In addition, the setting of the second capacitor also improves the anti-leakage light capability of the display panel when displaying a 0 gray scale picture, enhances the stability and consistency of the display device when displaying in low gray scale, and improves the overall display quality. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram of the traditional display device appearing the positive and negative screen phenomenon.

[0021] Figure 2 is a circuit diagram of a pixel of the display device provided by the embodiment of the present application.

[0022] Figure 3 is Figure 2Waveform diagrams of the first light-emitting control signal input end to the third light-emitting control signal input end and the first scan signal input end and the second scan signal input end of the pixel shown.

[0023] Figure 4 is a cross-sectional view of a display panel of a display device provided by an embodiment of the present application.

[0024] Figure 5 is a design layout of a pixel driving circuit of a display device provided by an embodiment of the present application.

[0025] Figure 6 is a schematic diagram of a comparison between a technical solution of the present application and a traditional technical solution in terms of the influence of threshold voltage shift of a third transistor on current. DETAILED DESCRIPTION

[0026] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish different technical features. The term "multiple" and similar terms mean two or more, unless otherwise explicitly limited.

[0028] Embodiments of the present application can be combined with each other.

[0029] In an organic light-emitting diode display panel, the generation of the positive and negative screen phenomenon is related to the electrical non-uniformity of the third transistor in the pixel driving circuit of the organic light-emitting diode display panel. During the operation of the pixel driving circuit, at the moment when the third transistor switches from the on state to the off state, that is, at the moment when the level of the first scan signal input end switches from the high level to the low level, the potential of the first scan signal input end will have a coupling effect on the potentials of the second node and the first node in the circuit, and the coupling effect on the potential of the second node is greater than that on the potential of the first node. This non-uniform coupling effect will cause the potential of the second node to decrease more than the potential of the first node, thereby generating a potential difference between the first node and the second node, causing the current to flow from the first node to the second node.

[0030] When the third transistor is off, due to the influence of the above-mentioned coupling effect, a leakage current will be generated in the pixel driving circuit, causing the potential of the first node to decrease. When the threshold voltage of the third transistor shifts, this leakage current phenomenon will cause the color and brightness non-uniformity phenomenon of the organic light-emitting diode display panel to deteriorate further, thereby seriously affecting the display quality and user experience of the organic light-emitting diode display panel.

[0031] To solve the above technical problems, embodiments of the present application provide a display device, which comprises a display panel, and is applied to the field of organic light-emitting diode display technology, and is used to solve the technical problem of the phenomenon of positive and negative screens in the display device in which the driving transistor (first transistor T1) of the pixel driving circuit is an oxide semiconductor thin film transistor.

[0032] The display device provided by the embodiments of the present application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of the present application take the OLED display device as an example for illustration.

[0033] The display device provided by the embodiments of the present application comprises a display panel, a timing controller, and a source driving circuit. The display panel comprises a plurality of pixels, each of which comprises a light-emitting device EL and a pixel driving circuit. Figure 2 As shown in the figure, the pixel driving circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor Cst, and a second capacitor Cboost.

[0034] The gate of the first transistor T1 is electrically connected with a line in which the first node Q is located, one of the source and the drain of the first transistor T1 is electrically connected with a line in which the second node A is located, and the other of the source and the drain of the first transistor T1 is electrically connected with a line in which the third node B is located, that is, the first node Q is one node in the line in which the gate of the first transistor T1 is located, the second node A is one node in the line in which one of the source and the drain of the first transistor T1 is located, and the third node B is one node in the line in which the other of the source and the drain of the first transistor T1 is located. The gate of the second transistor T2 is electrically connected with the second scan signal input terminal Scan2, the gate of the second transistor T2 and the second scan signal input terminal Scan2 are part of a corresponding scan signal line, one of the source and the drain of the second transistor T2 is electrically connected with the data signal input terminal Data, the data signal input terminal Data is part of a corresponding data signal line, and the other of the source and the drain of the second transistor T2 is electrically connected with the other of the source and the drain of the first transistor T1 (the line in which the third node B is located). The gate of the third transistor T3 is electrically connected with the first scan signal input terminal Scan1, the gate of the third transistor T3 and the first scan signal input terminal Scan1 are part of a corresponding scan signal line, one of the source and the drain of the third transistor T3 is electrically connected with one of the source and the drain of the first transistor T1 (the line in which the second node A is located), and the other of the source and the drain of the third transistor T3 is electrically connected with the gate of the first transistor T1 (the line in which the first node Q is located). The gate of the fourth transistor T4 is electrically connected with the second light-emitting control signal input terminal EM2 or the third light-emitting control signal input terminal EM3, one of the source and the drain of the fourth transistor T4 is electrically connected with the first reset signal input terminal VI-ano, and the other of the source and the drain of the fourth transistor T4 is electrically connected with a line in which the fourth node C is located, the fourth node C being one node in a line in which the other of the source and the drain of the sixth transistor T6 is located. One plate of the first capacitor Cst is electrically connected with the other of the source and the drain of the fourth transistor T4 (the line in which the fourth node C is located), and the other plate of the first capacitor Cst is electrically connected with a line between the other of the source and the drain of the third transistor T3 and the gate of the first transistor T1 (the line in which the first node Q is located). The gate of the fifth transistor T5 is electrically connected with the first light-emitting control signal input terminal EM1, one of the source and the drain of the fifth transistor T5 is electrically connected with the first power signal input terminal VDD, and the other of the source and the drain of the fifth transistor T5 is electrically connected with one of the source and the drain of the first transistor T1 (the line in which the second node A is located).The gate of the sixth transistor T6 is electrically connected with a second light-emitting control signal input terminal EM2, one of the source and the drain of the sixth transistor T6 is electrically connected with the other of the source and the drain of the first transistor T1 (a line where the third node B is located), and the other of the source and the drain of the sixth transistor T6 is electrically connected with an anode of the light-emitting device EL (a line where the fourth node C is located).

[0035] The light-emitting device EL is an organic light-emitting diode device, and the light-emitting device EL is electrically connected with the pixel driving circuit. Specifically, the anode of the light-emitting device EL is electrically connected with the line where the fourth node C is located, and the cathode of the light-emitting device EL is electrically connected with the second power signal input terminal VSS.

[0036] The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type thin film transistors, and the fifth transistor T5 and the sixth transistor T6 are both P-type thin film transistors. The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are oxide semiconductor thin film transistors, and the fifth transistor T5 and the sixth transistor T6 are polycrystalline silicon thin film transistors.

[0037] The line where the first node Q is located includes a line between the gate of the first transistor T1 and the other of the source and the drain of the third transistor T3, the line where the second node A is located includes a line between the one of the source and the drain of the first transistor T1 and the other of the source and the drain of the fifth transistor T5. The line where the third node B is located includes a line between the other of the source and the drain of the first transistor T1 and the one of the source and the drain of the sixth transistor T6, and the line where the fourth node C is located includes a line between the other of the source and the drain of the fourth transistor T4 and the other of the source and the drain of the sixth transistor T6.

[0038] One plate of the second capacitor Cboost is electrically connected with the gate of the third transistor T3 (the first scan signal input end Scan1), the gate of the third transistor T3 is a part of the scan signal line corresponding to the first scan signal input end Scan1, and the other plate of the second capacitor Cboost is electrically connected with the line between the other one of the source and the drain of the third transistor T3 and the gate of the first transistor T1 (the line where the first node Q is located). The second capacitor Cboost is used to increase the coupling capacitance between the first scan signal input end Scan1 and the line where the first node Q is located. When the third transistor T3 is switched from the open state to the closed state, the level of the first scan signal input end Scan1 is switched from the high level to the low level, and the potential change of the first scan signal input end Scan1 produces a coupling effect on the potential of the line where the first node Q is located, so that the potential of the line where the first node Q is located decreases accordingly with the decrease of the potential of the first scan signal input end Scan1, the potential difference between the line where the first node Q is located and the line where the second node A is located is reduced, the flow of current from the line where the first node Q is located to the line where the second node A is located is inhibited, the leakage current when the third transistor T3 is closed is reduced, and the color unevenness caused by the threshold voltage shift of the third transistor T3 is improved.

[0039] As shown in Figure 5 The pixel driving circuit further includes a metal member M, one plate of the second capacitor Cboost includes the gate of the third transistor T3, and the other plate of the second capacitor Cboost includes the metal member M. In the perspective of viewing the display panel from above, the metal member M at least partially overlaps the gate of the third transistor T3. The gate of the third transistor T3 includes the first gate and / or the second gate, one plate of the second capacitor Cboost includes the first gate and / or the second gate, and the other plate of the second capacitor Cboost includes the metal member M. In the perspective of viewing the display panel from above, the metal member M at least partially overlaps the gate of the third transistor T3, the first gate overlaps the second gate, and the metal member M at least partially overlaps the first gate and / or the second gate.

[0040] In the perspective of viewing the display panel from above, the size W1 of the metal member M in the second direction is greater than any one of the width of the scan signal line corresponding to the first gate and the width of the scan signal line corresponding to the second gate, and the second direction is the width direction of the scan signal line corresponding to the first gate and / or the second gate, that is, the direction perpendicular to the length direction of the scan signal line corresponding to the first scan signal input end Scan1.

[0041] In a top-down view of the display panel, the metal member M does not overlap with one of the source and the drain of the first transistor (a line where the second node A is located).

[0042] One of the source and the drain of the first transistor T1 (a line where the second node A is located) includes a first trace L1 and a second trace L2. In a top-down view of the display panel, the first trace L1 is parallel to the first direction, and the second trace L2 is perpendicular to the first direction, i.e., the first trace L1 is perpendicular to the second trace L2, and the first trace L1 is parallel to the length direction of the scan signal line corresponding to the first scan signal input end Scan1. The distance G2 between the second trace L2 and the metal member M is greater than the distance G1 between the first trace L1 and the metal member M. The first direction is the length direction of the scan signal line corresponding to the gate of the third transistor T3.

[0043] In a top-down view of the display panel, the edge E2 of the metal member M close to the second trace L2 is parallel to a part of the edge of the second trace L2, and the edge E1 of the metal member M close to the first trace L1 is parallel to a part of the edge of the first trace L1.

[0044] In a top-down view of the display panel, the dimension W2 of the metal member M in the first direction is greater than the width W3 of the scan signal line.

[0045] The display panel includes a display area AA and a peripheral area PA. The display area AA is provided with a plurality of pixels arranged in an array, and the peripheral area PA is located at the periphery of the display area AA. The display panel further includes a plurality of gate lines, a plurality of data lines, a plurality of light-emitting control signal lines, at least one light-emitting control circuit, and at least one gate drive circuit. The plurality of gate lines and the plurality of light-emitting control signal lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along the second direction and are arranged along the first direction. The first direction is perpendicular to the second direction. The light-emitting control circuit is in the peripheral area PA and is electrically connected to the plurality of light-emitting control signal lines. The gate drive circuit is provided in the peripheral area PA and is electrically connected to the plurality of gate lines.

[0046] The source drive circuit is electrically connected to the plurality of data lines through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit.

[0047] As Figure 4As shown, the display panel includes a substrate PI and a plurality of film layers disposed on the substrate PI, the plurality of film layers including a barrier layer MB, a buffer layer BUF, a first semiconductor layer POLY, a first gate insulating layer GI1, a first gate electrode layer GE1, a second gate insulating layer GI2, a second gate electrode layer GE2, a first interlayer insulating layer ILD1, a second semiconductor layer IGZO, a third gate insulating layer GI3, a third gate electrode layer GE3, a fourth gate insulating layer GI4, a fourth gate electrode layer GE4, a second interlayer insulating layer ILD2, a first source-drain electrode layer SD1, a passivation layer PV, a first planarization layer PLN1, a second source-drain electrode layer SD2, a second planarization layer PLN2, a third source-drain electrode layer SD3, a third planarization layer PLN3, an anode layer ANO, a pixel definition layer PDL, and a support PS.

[0048] The barrier layer MB is disposed on the substrate PI, the buffer layer BUF is disposed on the barrier layer MB, the first semiconductor layer POLY is disposed on the buffer layer BUF, the first gate insulating layer GI1 is disposed on the buffer layer BUF and the first semiconductor layer POLY, the first gate electrode layer GE1 is disposed on the first gate insulating layer GI1, the second gate insulating layer GI2 is disposed on the first gate insulating layer GI1 and the first gate electrode layer GE1, the second gate electrode layer GE2 is disposed on the second gate insulating layer GI2, the first interlayer insulating layer ILD1 is disposed on the second gate insulating layer GI2 and the second gate electrode layer GE2, the second semiconductor layer IGZO is disposed on the first interlayer insulating layer ILD1, the third gate insulating layer GI3 is disposed on the first interlayer insulating layer ILD1 and the second semiconductor layer IGZO, the third gate electrode layer GE3 is disposed on the third gate insulating layer GI3, the fourth gate insulating layer GI4 is disposed on the third gate insulating layer GI3 and the third gate electrode layer GE3, the fourth gate electrode layer GE4 is disposed on the fourth gate insulating layer GI4, the second interlayer insulating layer ILD2 is disposed on the fourth gate insulating layer GI4 and the fourth gate electrode layer GE4, the first source-drain layer SD1 is disposed on the second interlayer insulating layer ILD2, the passivation layer PV is disposed on the second interlayer insulating layer ILD2 and the first source-drain layer SD1, the first planarization layer PLN1 is disposed on the passivation layer PV, the second source-drain layer SD2 is disposed on the first planarization layer PLN1, the second planarization layer PLN2 is disposed on the first planarization layer PLN1 and the second source-drain layer SD2, the third source-drain layer SD3 is disposed on the second planarization layer PLN2, the third planarization layer PLN3 is disposed on the second planarization layer PLN2 and the third source-drain layer SD3, the anode layer ANO is disposed on the third planarization layer PLN3, the pixel definition layer PDL is disposed on the third planarization layer PLN3 and the anode layer ANO, the pixel definition layer PDL is provided with an opening, the opening is provided with a light-emitting layer and a cathode layer, the light-emitting layer is disposed on the anode layer ANO, the cathode layer is disposed on the light-emitting layer, and the support PS is disposed on the pixel definition layer PDL.

[0049] At least one of the plurality of film layers includes one of a source and a drain of a third transistor. The metal member M is located in any one of the first source-drain layer SD1, the second source-drain layer SD2, and the third source-drain layer SD3, and the metal member M is located in the same film layer as one of the source and the drain of the third transistor T3. A dielectric layer between the metal member M and a gate of the third transistor T3 forms a dielectric of a second capacitor Cboost.

[0050] The display panel includes a display area AA in which a plurality of pixels are arranged, and a peripheral area PA in which a gate drive circuit is arranged. The transistor of the gate drive circuit is a first type transistor, and the first type transistor includes a first semiconductor layer POLY which is a first semiconductor portion located in the peripheral area PA, a first gate layer GE1 which is a first gate located in the peripheral area PA, and a first source-drain layer SD1 which is a first source and a first drain located in the peripheral area PA. The pixel includes a first type transistor and a second type transistor, the first type transistor being a polycrystalline silicon thin film transistor, and the second type transistor being a metal oxide thin film transistor. The first type transistor of the pixel includes a first semiconductor layer POLY which is a first semiconductor portion located in the display area AA, a first gate layer GE1 which is a first gate located in the display area AA, and a first source-drain layer SD1 which is a first source and a first drain located in the display area AA. The second type transistor of the pixel includes a second semiconductor layer IGZO which is a second semiconductor portion located in the display area AA, a second gate layer GE2 which is a second gate located in the display area AA, a third gate layer GE3 which is a third gate located in the display area AA, a fourth gate layer GE4 which is a fourth gate located in the display area AA, and a first source-drain layer SD1 which is a first source and a first drain located in the display area AA.

[0051] The first source and a non-channel portion of the second semiconductor portion IGZO and the second gate layer GE2 which is a second gate located in the display area AA are electrically connected, a portion of the second source-drain layer SD2 located in the display area AA is electrically connected to the first drain, a portion of the third source-drain layer SD3 located in the display area AA is electrically connected to a portion of the second source-drain layer SD2 located in the display area AA, and the anode layer ANO is electrically connected to a portion of the third source-drain layer SD3 located in the display area AA.

[0052] As Figure 3As shown, the working process of the pixel driving circuit includes multiple timing stages, and the first light-emitting control signal input end EM1, the second light-emitting control signal input end EM2, the third light-emitting control signal input end EM3, the first scan signal input end Scan1 and the second scan signal input end Scan2 switch high and low levels according to preset timing. In the first stage S1, the first light-emitting control signal input end EM1 is at low level, the second light-emitting control signal input end EM2 is at low level, the third light-emitting control signal input end EM3 is at low level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level. In the second stage S2, the first light-emitting control signal input end EM1 is at low level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at low level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level. In the third stage S3, the first light-emitting control signal input end EM1 is at low level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at low level, the first scan signal input end Scan1 is at high level, and the second scan signal input end Scan2 is at low level. In the fourth stage S4, the first light-emitting control signal input end EM1 is at low level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at high level, and the second scan signal input end Scan2 is at low level. In the fifth stage S5, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at high level, and the second scan signal input end Scan2 is at low level. In the sixth stage S6, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at high level, and the second scan signal input end Scan2 is at high level. In the seventh stage S7, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at high level, and the second scan signal input end Scan2 is at low level. In the eighth stage S8, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at high level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level.In the ninth stage S9, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at low level, the third light-emitting control signal input end EM3 is at high level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level. In the tenth stage S10, the first light-emitting control signal input end EM1 is at high level, the second light-emitting control signal input end EM2 is at low level, the third light-emitting control signal input end EM3 is at low level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level. In the eleventh stage S11, the first light-emitting control signal input end EM1 is at low level, the second light-emitting control signal input end EM2 is at low level, the third light-emitting control signal input end EM3 is at low level, the first scan signal input end Scan1 is at low level, and the second scan signal input end Scan2 is at low level.

[0053] To verify the technical effect of the present application, the current changes of the traditional technical solution and the technical solution of the present application under the threshold voltage shift of the third transistor T3 are compared and tested. The test results are shown in Figure 6

[0054] In the test, the horizontal axis represents the threshold voltage shift of the third transistor T3, and the unit is volt, and the test range is-1V to 1V. The vertical axis represents the current change percentage, and the range is-30% to 30%. The technical solution of the present application sets the second capacitor Cboost between the first scan signal input end Scan1 and the gate of the first transistor T1 (the line where the first node Q is located). The traditional technical solution does not set the second capacitor Cboost.

[0055] The test results show that when the threshold voltage of the third transistor T3 occurs positive shift, the current change amplitude of the traditional technical solution is obviously greater than that of the technical solution of the present application. When the threshold voltage of the third transistor T3 shifts by 1V, the current change of the traditional technical solution reaches about 30%, while the current change of the technical solution of the present application is only about 18%. When the threshold voltage of the third transistor T3 occurs negative shift, it is also observed that the current change amplitude of the traditional technical solution is greater than that of the technical solution of the present application. When the threshold voltage of the third transistor T3 shifts by-1V, the current change of the traditional technical solution reaches about-23%, while the current change of the technical solution of the present application is only about-15%.

[0056] ​The test data verify that the application effectively reduces the influence of the threshold voltage offset of the third transistor T3 on the current, reduces the leakage current when the third transistor T3 is turned off, and thus improves the color and brightness unevenness of the display panel by adding the second capacitor Cboost between the first scan signal input end Scan1 and the gate of the first transistor T1 (the line where the first node Q is located).

[0057] Embodiments of the application also provide an electronic terminal comprising the display device described above. The electronic terminal includes electronic devices such as mobile phones, tablets, notebooks, smart watches, vehicle-mounted displays, etc. The display device serves as a display module of the electronic terminal to display image information for the user.

[0058] The embodiments of the application are described in detail above, and the content of the specification should not be understood as limiting the protection scope of the application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes a plurality of pixels. Each pixel includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a first transistor, a third transistor, and a second capacitor. The first transistor is an oxide semiconductor thin-film transistor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the first transistor, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor. One plate of the second capacitor is electrically connected to the gate of the third transistor, and the other plate of the second capacitor is electrically connected to the gate of the first transistor.

2. The display device according to claim 1, characterized in that, The pixel driving circuit also includes metal components; One plate of the second capacitor includes the gate of the third transistor, and the other plate of the second capacitor includes the metal component; From a top-down view of the display panel, the metal component at least partially overlaps with the gate of the third transistor.

3. The display device according to claim 2, characterized in that, The gate of the third transistor includes a first gate and / or a second gate; One plate of the second capacitor includes the first gate and / or the second gate; From a top-down view of the display panel, the metal component at least partially overlaps with the first gate and / or the second gate.

4. The display device according to claim 3, characterized in that, From a top-down view of the display panel, the size of the metal component in the second direction is greater than either the width of the scan signal line corresponding to the first gate or the width of the scan signal line corresponding to the second gate. Wherein, the second direction is the width direction of the scan signal line corresponding to the first gate and / or the second gate.

5. The display device according to claim 2, characterized in that, From a top-down view of the display panel, the metal component does not overlap with either the source or drain of the first transistor.

6. The display device according to claim 2, characterized in that, One of the source and drain of the first transistor includes a first trace and a second trace; From a top-down view of the display panel, the first trace is parallel to the first direction, the second trace is perpendicular to the first direction, and the distance between the second trace and the metal component is greater than the distance between the first trace and the metal component. Wherein, the first direction is the length direction of the scan signal line corresponding to the gate of the third transistor.

7. The display device according to claim 6, characterized in that, From a top-down view of the display panel, the edge of the metal component near the second trace is parallel to a portion of the edge of the second trace, and the edge of the metal component near the first trace is parallel to a portion of the edge of the first trace.

8. The display device according to claim 2, characterized in that, The display panel includes a substrate and a plurality of film layers disposed on the substrate, wherein at least one of the plurality of film layers includes one of the source and drain of the third transistor; The metal component is located in the same film layer as one of the source and drain electrodes of the third transistor.

9. The display device according to claim 2, characterized in that, From a top-down view of the display panel, the size of the metal component in the first direction is larger than the width of the scan signal line corresponding to the gate of the third transistor; Wherein, the first direction is the length direction of the scan signal line corresponding to the gate of the third transistor.

10. The display device according to claim 1, characterized in that, The pixel driving circuit also includes a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; The gate of the second transistor is electrically connected to the second scan signal input terminal, one of the source and drain of the second transistor is electrically connected to the data signal input terminal, and the other of the source and drain of the second transistor is electrically connected to the other of the source and drain of the first transistor. The gate of the fourth transistor is electrically connected to either the second light-emitting control signal input terminal or the third light-emitting control signal input terminal, and one of the source and drain of the fourth transistor is electrically connected to the first reset signal input terminal. The gate of the fifth transistor is electrically connected to the first light-emitting control signal input terminal, one of the source and drain of the fifth transistor is electrically connected to the first power supply signal input terminal, and the other of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the first transistor and / or one of the source and drain of the third transistor. The gate of the sixth transistor is electrically connected to the second light-emitting control signal input terminal, one of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the fourth transistor. One plate of the first capacitor is electrically connected to the other of the source and drain of the fourth transistor, and the other plate of the first capacitor is electrically connected to the line between the other of the source and drain of the third transistor and the gate of the first transistor. One plate of the second capacitor is electrically connected to the gate of the third transistor, and the other plate of the second capacitor is electrically connected to the line between the source and drain of the third transistor and the gate of the first transistor.

11. An electronic terminal, characterized in that, The electronic terminal includes a display device as described in any one of claims 1 to 10.

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