Scanning driving circuit, display device and electronic equipment

Abstract

The invention discloses a scanning driving circuit, a display device and electronic equipment, and belongs to the technical field of display. The scanning driving circuit comprises a plurality of cascaded scanning driving units. Each scanning driving unit comprises an input module, a pull-down module and an output module. The pull-down module comprises a first transistor, a second transistor and a potential coupling component; the input module is used for outputting a circuit input signal to the pull-up node, and the circuit input signal is used for adjusting a potential signal of the pull-up node; the potential coupling component is used for receiving a first clock signal and outputting a control signal to the control end of the first transistor, and the level of the control signal and the level of the first clock signal change synchronously; the first transistor is used for adjusting a potential signal of the pull-down node under the control of a control signal; the second transistor is used for adjusting the potential signal of the pull-down node under the control of the potential signal of the pull-up node; and the output module is used for outputting a driving signal under the control of the potential signal of the pull-up node and the potential signal of the pull-down node.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a scanning driving circuit, a display device, and an electronic device. Background Technology

[0002] With the rapid development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been widely used in the high-end display field due to its advantages such as self-illumination, high contrast and fast response.

[0003] In AMOLED display driving systems, the scan circuit (SCAN) is a crucial component, directly impacting key performance indicators such as refresh rate, power consumption, and bezel width of the display panel. The scan circuit comprises multiple scan drive units. Each scan drive unit provides scan signals to different pixel rows to drive pixel emission. Current scan drive units typically use an 8T2C circuit structure, consisting of eight transistors and two capacitors. In particular, the pull-down module of the scan drive unit usually requires at least four transistors to support its functionality. Clearly, the large number of transistors results in a larger circuit area for the scan drive circuit, thus requiring more wiring space for the display panel and resulting in a wider bezel. Summary of the Invention

[0004] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Embodiments of this application provide a scan driving circuit, a display device, and an electronic device to solve the problem of excessively large circuit area in current scan driving circuits. The technical solution is as follows: This application provides a scan driving circuit, including multiple cascaded scan driving units. Each scan driving unit includes an input module, a pull-down module, and an output module. The pull-down module includes a first transistor, a second transistor, and a potential coupling component. The input module is connected to the output module, the first transistor is connected to the potential coupling component and the output module, and the second transistor is connected to the pull-up node and the pull-down node. The pull-up node is the electrical connection point between the input module and the output module, and the pull-down node is the electrical connection point between the pull-down module and the output module. The input module is used to output the circuit input signal to the pull-up node, and the circuit input signal is used to adjust the potential signal of the pull-up node; the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor, and the level of the control signal changes synchronously with the level of the first clock signal; the first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal, and the second transistor is used to adjust the potential signal of the pull-up node under the control of the potential signal of the pull-up node; the output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node.

[0005] In this embodiment, the scanning drive unit of the scanning drive circuit includes an input module, a pull-down module, and an output module. The input module is used to input signals to the pull-up node output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. In the pull-down module, a potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor. The level of the control signal changes synchronously with the level of the first clock signal. The first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal; the second transistor is used to adjust the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node. Since the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies, the circuit area of ​​the scanning drive unit provided by this application is relatively narrow, thereby effectively reducing the circuit area of ​​the scanning drive circuit, reducing the wiring space required for the scanning drive circuit, adapting to the narrow bezel design of the display device, effectively improving the screen-to-body ratio of the display device, and enhancing the user viewing experience. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a scanning drive circuit provided by related technologies; Figure 2 This is a timing diagram of a scan drive circuit provided by related technologies; Figure 3 This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application; Figure 4 This is a partial structural schematic diagram of a scanning drive circuit provided in an embodiment of this application; Figure 5 This is a complete structural schematic diagram of a scanning drive circuit provided in an embodiment of this application; Figure 6 This is a timing diagram of a scan driving circuit provided in an embodiment of this application; Figure 7This is a schematic diagram of the cascaded relationship of a scanning drive circuit provided in an embodiment of this application; Figure 8 This is a timing diagram illustrating the cascaded relationship of a scanning drive circuit provided in an embodiment of this application. Detailed Implementation

[0007] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0008] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0009] The scanning drive circuit, display device, and electronic device provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0010] With the rapid development of display technology, AMOLED display technology has been widely used in the high-end display field due to its advantages such as self-emissiveness, high contrast, and fast response.

[0011] In AMOLED display driving systems, the SCAN circuit is a crucial component, its performance directly impacting key indicators such as the display panel's refresh rate, power consumption, and bezel width. The scan driving circuit comprises multiple scan driving units. Each unit provides scan signals to different pixel rows to drive pixel emission. Current scan driving units typically use an 8T2C circuit structure, consisting of eight transistors and two capacitors. In particular, the pull-down module of the scan driving unit usually requires at least four transistors to support its functionality. Clearly, the large number of transistors results in a larger circuit area for the scan driving circuit, thus requiring more wiring space for the display panel and leading to a wider bezel.

[0012] Please refer to Figure 1 The diagram illustrates a structural schematic of a scanning drive circuit provided by related technologies. For example... Figure 1As shown, the scan drive circuit has an 8T2C structure, which includes eight transistors and two capacitors. Specifically, the scan drive circuit includes an input module 11, a pull-down module 12, and an output module 13.

[0013] Input module 11 includes: eighth transistor T8; pull-down module 12 includes: ninth transistor T9, tenth transistor T10, eleventh transistor T11 and twelfth transistor T12; output module 13 includes: thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, first capacitor C1 and second capacitor C2.

[0014] The control terminal of the eighth transistor T8 receives the first clock signal SCK1, its input terminal receives the circuit input signal SIN, and its output terminal is connected to the pull-up node PU. The control terminal of the ninth transistor T9 receives the second clock signal SCK2, its input terminal is connected to the second node B, and its output terminal is connected to the pull-up node PU. The control terminal of the tenth transistor T10 is connected to the pull-down node PD, its input terminal receives the first level signal VGH, and its output terminal is connected to the second node B. The control terminal of the eleventh transistor T11 is connected to the pull-up node PU, its input terminal receives the first clock signal SCK1, and its output terminal is connected to the pull-down node PD. The control terminal of the twelfth transistor T12 receives the first clock signal SCK1, its input terminal receives the second level signal VGL, and its output terminal is connected to the pull-down node PD. The control terminal of the thirteenth transistor T13 is connected to the pull-down node PD. The input terminal of the thirteenth transistor T13 receives the first level signal VGH, and its output terminal outputs the drive signal SN_OUT. The control terminal of the fourteenth transistor T14 is connected to the first node A. The input terminal of the fourteenth transistor T14 receives the second clock signal SCK2, and its output terminal outputs the drive signal SN_OUT. The control terminal of the fifteenth transistor T15 receives the second level signal VGL. The input terminal of the fifteenth transistor T15 is connected to the pull-up level PU, and its output terminal is connected to the first node A. A first capacitor C1 is positioned between the control terminal and the input terminal of the thirteenth transistor T13. A second capacitor C2 is positioned between the control terminal and the output terminal of the fourteenth transistor T14.

[0015] Specifically, the pull-up node PU is the electrical connection point of the output terminal of the eighth transistor T8, the output terminal of the ninth transistor T9, the control terminal of the eleventh transistor T11, and the input terminal of the fifteenth transistor T15. The pull-down node PD is the electrical connection point of the control terminal of the tenth transistor T10, the output terminal of the eleventh transistor T11, the output terminal of the twelfth transistor T12, and the control terminal of the thirteenth transistor T13. The first node A is the electrical connection point of the control terminal of the fourteenth transistor T14, the output terminal of the fifteenth transistor T15, and one end of the first capacitor C1. The second node B is the electrical connection point of the input terminal of the ninth transistor T9 and the output terminal of the tenth transistor T10.

[0016] Figure 1 The transistors in the scan drive circuit shown can be either N-channel metal-oxide-semiconductor (NMOS) or P-channel metal-oxide-semiconductor (PMOS). In an NMOS, the control terminal is the gate, the input terminal is the drain, and the output terminal is the source. In a PMOS, the control terminal is the gate, the input terminal is the source, and the output terminal is the drain. The following embodiment illustrates the case where transistors 8 through 15 in the scan drive circuit are all PMOS. For a PMOS, it turns on when it receives a low-level control signal at the gate (i.e., the control terminal) and turns off when it receives a high-level control signal at the gate. Specifically, the control terminal of the eighth transistor T8 turns on when it receives a low-level first clock signal SCK1 and turns off when it receives a high-level first clock signal SCK1. The voltage of the first level signal VGH is greater than the voltage of the second level signal VGL. Therefore, the first level signal VGH is considered to be a high level signal, and the second level signal VGL is considered to be a low level signal.

[0017] like Figure 2 As shown, the operation of the 8T2C scan drive circuit includes: output sustain phase t1, output sustain phase t2, low-level write phase t3, low-level output phase t4, discharge phase t5, output sustain phase t6, and alternating discharge phase t5 and output sustain phase t6. The specific operation process of each time period is as follows: During the output sustain phase t1, the circuit input signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level.

[0018] The eighth transistor T8 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-up node PU is adjusted to the high-level circuit input signal SIN, so that the eleventh transistor T11 is turned off. The twelfth transistor T12 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-down node PD is adjusted to the second-level signal VGL, so that the tenth transistor T10 and the thirteenth transistor T13 are turned on. Furthermore, the potential signal of the second node B and the drive signal SN_OUT are both adjusted to the first-level signal VGH. The fifteenth transistor T15 is turned on under the control of the second-level signal VGL, and the potential signal of the first node A is adjusted to the potential signal of the pull-up node PU, so that the fourteenth transistor T14 is turned off. The ninth transistor T9 is turned off under the control of the second clock signal SCK2.

[0019] During the output sustain phase t2, the circuit input signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level.

[0020] The eighth transistor T8 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-up node PU maintains the high-level circuit input signal SIN for the time period t1, so that the eleventh transistor T11 remains off. The twelfth transistor T12 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-down node PD maintains the second-level signal VGL for the time period t1, so that the tenth transistor T10 and the thirteenth transistor T13 remain on. Furthermore, the potential signal of the second node B and the drive signal SN_OUT both maintain the first-level signal VGH for the time period t1. The fifteenth transistor T15 is turned on under the control of the second-level signal VGL. The potential signal of the first node A is adjusted to the potential signal of the pull-up node PU, so that the fourteenth transistor T14 is turned off. The ninth transistor T9 is turned on under the control of the second clock signal SCK2. The potential signal of the pull-up node PU is adjusted to the potential signal of the second node B.

[0021] During the low-level write phase t3, the circuit input signal SIN is a low-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal.

[0022] The eighth transistor T8 is turned on under the control of the first clock signal SCK1. The potential signal of the pull-up node PU is adjusted to the low-level circuit input signal SIN, so that the eleventh transistor T11 is turned off. The potential signal of the pull-down node PD is maintained at the second-level signal VGL for the time period t2, so that the twelfth transistor T12 is turned off. The tenth transistor T10 and the thirteenth transistor T13 are turned on. Consequently, the potential signal of the second node B and the drive signal SN_OUT are both adjusted to the first-level signal VGH. The fifteenth transistor T15 is turned on under the control of the second-level signal VGL. The potential signal of the first node A is adjusted to the potential signal of the pull-up node PU, so that the fourteenth transistor T14 is turned on. The ninth transistor T9 is turned off under the control of the second clock signal SCK2.

[0023] During the low-level output sustaining phase t4, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal.

[0024] The eighth transistor T8 is turned off under the control of the first clock signal SCK1, and the potential signal of the pull-up node PU maintains the low level of the circuit input signal SIN during the time period t3. The twelfth transistor T12 is turned off under the control of the first clock signal SCK1. The eleventh transistor T11 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-down node PD is adjusted to the high level of the first clock signal SCK1, so that the tenth transistor T10 and the thirteenth transistor T13 are turned off. During the time period t3, the voltage difference across the second capacitor C2 is V. C2 =V B -V SN_OUT =V GL -V th -V GH When the second clock signal SCK2 transitions from a high level to a low level, the fourteenth transistor T14 turns on, causing the drive signal SN_OUT to transition from a high level to a low level along with the second clock signal SCK2. Correspondingly, the voltage of the potential signal at the first node A changes with the voltage of the drive signal SN_OUT. At this time, the voltage V of the potential signal at the first node A... A It satisfies V A =V SN_OUT +V C2 =V GL +V GL -V th -V GH =2*V GL -V th -V GH The fourteenth transistor T14 at voltage V AThe transistor is turned on under the control of the second clock signal SCK2. At this time, the fifteenth transistor T15 is turned off under the control of the second level VGL. The ninth transistor T9 is turned on under the control of the second clock signal SCK2, and the potential signal of the pull-up node PU is adjusted to the potential signal of the second node B.

[0025] During the discharge phase t5, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal.

[0026] The eighth transistor T8 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-up node PU is adjusted to the high-level circuit input signal SIN, so that the eleventh transistor T11 is turned off. The twelfth transistor T12 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-down node PD is adjusted to the second-level signal VGL, so that the tenth transistor T10 and the thirteenth transistor T13 are turned on. Furthermore, the potential signal of the second node B and the drive signal SN_OUT are both adjusted to the first-level signal VGH. The fifteenth transistor T15 is turned on under the control of the second-level signal VGL, and the potential signal of the first node A is adjusted to the potential signal of the pull-up node PU, so that the fourteenth transistor T14 is turned off. The ninth transistor T9 is turned off under the control of the second clock signal SCK2.

[0027] During the output sustaining phase t6, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal.

[0028] The eighth transistor T8 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-up node PU maintains the high-level circuit input signal SIN during the t5 time period, so that the eleventh transistor T11 remains off. The twelfth transistor T12 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-down node PD maintains the second-level signal VGL during the t5 time period, so that the tenth transistor T10 and the thirteenth transistor T13 remain on. Consequently, the potential signal of the second node B and the drive signal SN_OUT both maintain the first-level signal VGH during the t5 time period. The fifteenth transistor T15 is turned on under the control of the second-level signal VGL. The potential signal of the first node A is adjusted to the potential signal of the pull-up node PU, so that the fourteenth transistor T14 is turned off. The ninth transistor T9 is turned on under the control of the second clock signal SCK2. The potential signal of the pull-up node PU is adjusted to the potential signal of the second node B.

[0029] After time period t6 ends, the scan drive circuit alternates between discharge phase t5 and output maintenance phase t6 to obtain the complete drive signal of the scan drive circuit.

[0030] Obviously, Figure 2 The scan drive unit shown has a large number of transistors in its pull-down module 12, resulting in a complex circuit structure and high wiring density, making it difficult to meet the narrow bezel design requirements of current electronic devices. Furthermore, since the control terminal of the twelfth transistor T12 is fixedly connected to the second clock signal SCK2, the rate of change of the target voltage between the control terminal and the input terminal of the twelfth transistor T12 is determined by the level transition speed of the second clock signal SCK2. Therefore, the pull-down speed at which the potential signal of the pull-down node transitions from a high-level signal to a low-level signal is limited by the rate of change of the target voltage of the twelfth transistor T12. The pull-down speed of the potential signal of the pull-down node directly affects the conduction speed of the tenth transistor T10 and the thirteenth transistor T13, thus affecting the transition time of the drive signal of the scan drive unit. Therefore, if the level transition speed of the second clock signal SCK2 is slow, the pull-down speed of the pull-down node will be slow, resulting in a longer transition time of the drive signal of the scan drive circuit, affecting signal stability.

[0031] This application provides a scan driving circuit to address the aforementioned problems to some extent. The scan driving circuit includes multiple cascaded scan driving units. Please refer to... Figure 3 This illustrates a schematic diagram of the structure of a scanning driving unit provided in an embodiment of this application. Figure 3 As shown, the scan driving unit includes: an input module 01, a pull-down module 02, and an output module 03. The pull-down module 02 includes: a first transistor T1, a second transistor T2, and a potential coupling component 04.

[0032] Input module 01 is connected to output module 03. First transistor T1 is connected to potential coupling component 04 and output module 03, and second transistor T2 is connected to pull-up node PU and pull-down node PD. Pull-up node PU is the electrical connection point between input module 01 and output module 03, and pull-down node PD is the electrical connection point between pull-down module 02 and output module 03.

[0033] Input module 01 is used to input signals to the pull-up node PU output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. Potential coupling component 04 is used to receive the first clock signal SCK1 and output a control signal to the control terminal of the first transistor T1. The level of the control signal changes synchronously with the level of the first clock signal SCK1. The first transistor T1 is used to adjust the potential signal of the pull-down node PD under the control of the control signal. The second transistor T2 is used to adjust the potential signal of the pull-down node PD under the control of the potential signal of the pull-up node PU. Output module 03 is used to output the drive signal SN_OUT under the control of the potential signals of the pull-up node PU and the pull-down node PD.

[0034] In the embodiments of this application, the effective level refers to the level of the control signal that controls the transistor to turn on; the invalid level refers to the level of the control signal that controls the transistor to turn off.

[0035] The level of the first clock signal SCK1 can be either active or inactive. In input module 01, input module 01 can receive the circuit input signal SIN and, under the control of the active first clock signal SCK1, adjust the potential signal of the pull-up node PU to match the circuit input signal SIN; under the control of the inactive first clock signal SCK1, it will not adjust the potential signal of the pull-up node PU based on the circuit input signal SIN, thus maintaining the potential signal of the pull-up node PU. Clearly, the potential signal of the pull-up node PU is related to the circuit input signal SIN. The circuit input signal SIN can be either an active or inactive circuit input signal. Correspondingly, the potential signal of the pull-up node PU can be either an active or inactive circuit input signal.

[0036] In pull-down module 02, the control terminal of the first transistor T1 is connected to the potential coupling component 04. The input terminal of the first transistor T1 is used to receive the first clock signal SCK1, and the output terminal of the first transistor T1 is connected to the pull-down node PD. The control terminal of the second transistor T2 is connected to the pull-up node PU. The input terminal of the second transistor T2 is used to receive the first clock signal SCK1, and the output terminal of the second transistor T2 is connected to the pull-down node PD.

[0037] The potential coupling component 04 can be used to receive the first clock signal SCK1 and control the level of the control signal of the first transistor T1 to follow the level change of the first clock signal SCK1. That is, when the level of the first clock signal SCK1 is active, the potential coupling component 04 controls the level of the control signal of the first transistor T1 to be active, so that the first transistor T1 is turned on under the control of the active level control signal, adjusting the potential signal of the pull-down node PD to the active level of the first clock signal SCK1. When the level of the first clock signal SCK1 is inactive, the potential coupling component 04 controls the level of the control signal of the first transistor T1 to be inactive, so that the first transistor T1 is turned off under the control of the inactive level control signal, and will not adjust the potential signal of the pull-down node PD based on the first clock signal SCK1 received at the input terminal.

[0038] The second transistor T2 is used to adjust the potential signal of the pull-down node PD under the control of the potential signal of the pull-up node PU. Specifically, when the potential signal of the pull-up node PU is an active circuit input signal, the second transistor T2 is turned on to adjust the potential signal of the pull-down node PD to the first clock signal SCK1; when the potential signal of the pull-up node PU is an inactive circuit input signal, the second transistor T2 is turned off and will not adjust the potential signal of the pull-down node PD based on the first clock signal SCK1 received at the input terminal. Obviously, the potential signal of the pull-down node PD is either the active first clock signal SCK1 or the inactive first clock signal SCK1.

[0039] Clearly, the potential signal of the pull-down node PD is jointly controlled by the second transistor T2 and the potential coupling component 04. On one hand, the second transistor T2 is used to adjust the potential signal of the pull-down node PD under the control of the potential signal of the pull-up node PU. On the other hand, the potential coupling component 04 is used to control the first transistor T1 to adjust the potential signal of the pull-down node PD. Therefore, by having the input stages of the first transistor T1 and the second transistor T2 both connected to the first clock signal SCK1, the two-way adjustment process of the potential signal of the pull-down node PD can be effectively ensured to be synchronized. This ensures that if either transistor T1 or T2 fails, the other transistor can still maintain the effective adjustment of the potential signal of the pull-down node PD, thus ensuring the stability of the adjustment of the potential signal of the pull-down node PD and thereby ensuring the operational stability of the scan drive circuit. In addition, by adjusting the potential signal of the pull-down node PD through two channels, the potential settling time of the potential signal of the pull-down node PD can be effectively shortened, the signal adjustment time can be shortened, and the operational stability of the circuit can be further guaranteed.

[0040] In output module 03, output module 03 is used to receive the first level signal VGH, the potential signal of pull-up node PU, and the potential signal of pull-down node PD, so as to adjust the drive signal SN_OUT to the second clock signal SCK2 output under the control of the potential signals of pull-up node PU and pull-down node PD, or adjust the drive signal SN_OUT to the first level signal VGH output. Optionally, output module 03 is used to adjust the drive signal SN_OUT to the second clock signal SCK2 output when the potential signal of pull-up node PU is an effective circuit input signal; and to adjust the drive signal SN_OUT to the first level signal VGH output when the potential signal of pull-up node PU is an effective first clock signal SCK1.

[0041] In summary, the scanning drive circuit provided in this application includes an input module, a pull-down module, and an output module. The input module inputs a signal to the output circuit of the pull-up node, and the circuit input signal is used to adjust the potential signal of the pull-up node. In the pull-down module, the potential coupling component receives a first clock signal and outputs a control signal to the control terminal of the first transistor. The level of the control signal changes synchronously with the level of the first clock signal. The first transistor adjusts the potential signal of the pull-down node under the control of the control signal. The second transistor adjusts the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module outputs a drive signal under the control of the potential signals of the pull-up node and the pull-down node. Since the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies, the circuit area of ​​the scanning drive unit provided in this application is relatively narrow, thereby effectively reducing the circuit area of ​​the scanning drive circuit, reducing the wiring space required for the scanning drive circuit, and adapting to the narrow bezel design of the display device.

[0042] In this embodiment, the pull-down module 02 includes a first transistor T1, a second transistor T2, and a potential coupling component 04. The potential coupling component 04 is used to receive a first clock signal SCK1 and control the level of the control signal of the first transistor T1 to follow the level change of the first clock signal SCK1.

[0043] Optionally, such as Figure 4 As shown, the potential coupling component 04 includes: a third transistor T3 and a first potential adjustment device 041.

[0044] The control terminal of the third transistor T3 is used to receive the second clock signal SCK2, the input terminal of the third transistor T3 is used to receive the first level signal VGH, and the output terminal of the third transistor T3 is connected to the control terminal of the first transistor T1. The first potential adjustment device 041 is disposed between the control terminal of the first transistor T1 and the input terminal of the first transistor T2.

[0045] Specifically, when the level of the first clock signal SCK1 is at the first level (i.e., invalid level), the third transistor T3, under the control of the second clock signal SCK2, adjusts the control signal received by the control terminal of the first transistor T1 to the first level signal VGH. When the level of the first clock signal SCK1 changes from the first level to the second level (i.e., active level), the first potential adjustment device 041 adjusts the control signal of the first transistor T1 from the first level signal VGH to the second level control signal.

[0046] In an optional embodiment, the level of the first level signal VGH is an active level. The level of the second level signal VGH is an inactive level. The level of the second clock signal SCK2 can be either an active or inactive level. Furthermore, the first clock signal SCK1 and the second clock signal SCK2 are out of phase but have the same frequency. The third transistor T3 is used to output the first level signal VGH to the control terminal of the first transistor T1 under the control of the active level second clock signal SCK2; and to stop outputting the first level signal VGH to the control terminal of the first transistor T1 under the control of the inactive level second clock signal SCK2.

[0047] When the level of the first clock signal SCK1 is at the first level, the level of the second clock signal SCK2 is at the active level. The first transistor T1 is turned off under the control of the first clock signal SCK1 at the first level, and the first potential adjustment device 041 receives the first clock signal SCK1 at the first level.

[0048] The third transistor T3 is turned on under the control of the second clock signal SCK2 to adjust the control signal received at the control terminal of the first transistor T1 to the first level signal VGH. At this time, the signal at the control terminal of the first transistor T1 is the first level signal VGH, and the level of the first level signal VGH is the same as the level of the first clock signal SCK1.

[0049] When the level of the first clock signal SCK1 is at the second level, the level of the second clock signal SCK2 is at an invalid level. The third transistor T3 is turned off under the control of the invalid second clock signal SCK2, ceasing to output the second clock signal SCK2 to the control terminal of the first transistor T1. The first potential adjustment device 041 receives the first clock signal SCK1 at the second level and adjusts the level of the control signal at the control terminal of the first transistor T1 to the second level. At this time, the first transistor T1 is turned on under the control of the first clock signal SCK1 at the second level, adjusting the potential signal of the pull-down node PD to the first clock signal SCK1 at the second level.

[0050] In some embodiments, the first potential adjustment device 041 is used to control the level of the control signal of the first transistor T1 to follow the level change of the first clock signal SCK1 according to the target voltage difference, so that the voltage of the control signal of the first transistor T1 and the voltage of the first clock signal SCK1 maintain the target voltage difference.

[0051] Specifically, when the level of the first clock signal SCK1 is at the first level and the level of the second clock signal SCK2 is at the active level, the signal at the control terminal of the first transistor T1 is the first level signal VGH, and the level of the first level signal VGH is the same as the level of the first clock signal SCK1. The target voltage difference is the voltage difference between the first level signal VGH and the first clock signal SCK1 at the first level.

[0052] When the first clock signal SCK1 transitions from an invalid level to an active level, and the second clock signal SCK2 transitions from an active level to an invalid level, the control signal of the first transistor T1 is the first-level signal VGH, while the signal received by the first potential adjustment device 041 is the active first clock signal SCK1. The voltage difference between the two is greater than the target voltage difference. The first potential adjustment device 041 is used to pull down the voltage of the control signal of the first transistor T1 so that the voltage of the control signal is the sum of the voltage of the active first clock signal SCK1 and the target voltage difference. Therefore, the level of the control signal of the first transistor T1 flips from the first level to the second level.

[0053] In this embodiment, the first potential adjustment device 041 can control the level of the control signal of the first transistor T1 to follow the level change of the first clock signal SCK1 according to the target voltage difference. The speed at which the first potential adjustment device 041 flips the control signal level of the first transistor T1 according to the target voltage difference is faster than the signal level flipping speed. Therefore, the pull-down speed of the potential signal of the pull-down node can be effectively improved. As can be seen from the foregoing analysis, the transition duration of the drive signal of the scan drive unit is positively correlated with the pull-down speed of the pull-down node. Therefore, improving the pull-down speed of the potential signal of the pull-down node can effectively shorten the transition duration of the drive signal of the scan drive unit, improve the stability of the drive signal of the scan drive unit, and improve the performance of the scan drive circuit.

[0054] In an alternative case, such as Figure 5 As shown, the first potential adjustment device 041 is capacitor C1. The first plate of capacitor C1 is connected to the input terminal of the first transistor T1 to receive the first clock signal SCK1; the second plate of capacitor C1 is connected to the intersection of the control terminal of the first transistor T1 and the output terminal of the third transistor T3. Capacitor C1 can maintain a constant voltage difference between the first and second plates. Therefore, capacitor C1 can be used to adjust the voltage of the control signal of the first transistor T1 according to the target voltage difference and the voltage of the first clock signal SCK1, so that the level of the control signal of the first transistor T1 follows the level change of the first clock signal SCK1.

[0055] The target voltage difference is the voltage difference between the first level signal VGH and the first clock signal SCK1, which is at the first level. When the level of the first clock signal SCK1 is the first level and the level of the second clock signal SCK2 is the active level, the signal at the control terminal of the first transistor T1 is the first level signal VGH, and the voltage of the second plate of capacitor C1 is the voltage of the first level signal VGH. The first plate of capacitor C1 receives the first clock signal SCK1 at the first level, and its voltage is the voltage of the first clock signal SCK1 at the first level. At this time, the voltage difference between the first and second plates of capacitor C1 is the target voltage difference, and the level of the control signal of the first transistor T1 is the same as the level of the first clock signal SCK1.

[0056] When the first clock signal SCK1 transitions from an invalid level to an active level, and the second clock signal SCK2 transitions from an active level to an invalid level, the control signal for the first transistor T1 is the first level signal VGH, and the voltage of the second plate of capacitor C1 is maintained at the voltage of the first level signal VGH.

[0057] The voltage of the first plate of capacitor C1 changes as it receives the first clock signal SCK1 at the second level. This voltage change causes capacitor C1 to adjust the voltage of its second plate, maintaining the target voltage difference between the two plates. As the voltage at the control terminal of the first transistor T1 changes, the level of its control signal follows the level of the first clock signal SCK1, switching from the first level to the second level. Since the speed at which the capacitor adjusts its plate voltage is faster than the speed at which the signal level changes, the pull-down speed of the potential signal of the pull-down node can be effectively improved. As the previous analysis shows, the transition time of the drive signal of the scan drive unit is positively correlated with the pull-down speed of the pull-down node. Therefore, improving the pull-down speed of the potential signal of the pull-down node can effectively shorten the transition time of the drive signal of the scan drive unit, improve the stability of the drive signal of the scan drive unit, and enhance the performance of the scan drive circuit.

[0058] In another alternative embodiment, the first potential adjustment device 041 may include a dedicated level shifter IC 041. The dedicated level shifter IC 041 is connected to both the input terminal and the control terminal of the first transistor T1, and is used to adjust the control terminal voltage of the first transistor T1 based on the voltage of the signal received at the input terminal of the first transistor T1 and the target voltage difference, so that the input terminal voltage and the control terminal voltage of the first transistor T1 are maintained at the target voltage difference. Similarly, as described above.

[0059] When the level of the first clock signal SCK1 is the first level and the level of the second clock signal SCK2 is the active level, the signal at the control terminal of the first transistor T1 is the first level signal VGH, the signal at the input terminal of the first transistor T1 is the first level first clock signal SCK1, and the voltage difference between the two is the target voltage difference.

[0060] When the first clock signal SCK1 transitions from an invalid level to an active level, and the second clock signal SCK2 transitions from an active level to an invalid level, the control signal for the first transistor T1 is the first level signal VGH, and its voltage is maintained at the voltage of the first level signal VGH.

[0061] The input terminal of the first transistor T1 receives the first clock signal SCK1, which is at the second level, causing a change in the input voltage. The dedicated level shift chip 041 adjusts the control terminal voltage of the first transistor T1 according to the input voltage of the first transistor T1, so that the level of the control signal of the first transistor T1 follows the level change of the first clock signal SCK1, flipping from the first level to the second level.

[0062] In this embodiment, the input module 01 is used to adjust the potential signal of the pull-up node PU. The pull-up node PU is the electrical connection point between the input module 01 and the output module 03.

[0063] Optional, such as Figure 5 As shown, input module 01 includes a fourth transistor T4. The control terminal of the fourth transistor T4 receives a first clock signal SCK1, the input terminal receives a circuit input signal SIN, and the output terminal is connected to the pull-up node PU. The fourth transistor T4 is used to adjust the potential signal of the pull-up node PU under the control of the first clock signal SCK1. Specifically, optionally, the fourth transistor T4 adjusts the potential signal of the pull-up node PU to the circuit input signal SIN under the control of the active level of the first clock signal SCK1; under the control of the inactive level of the first clock signal SCK1, it does not adjust the potential signal of the pull-up node PU based on the circuit input signal SIN, thus maintaining the potential signal of the pull-up node PU.

[0064] In this embodiment of the application, the output module 03 is used to output the drive signal SN_OUT under the control of the potential signal of the pull-up node PU and the potential signal of the pull-down node PD.

[0065] Alternatively, please continue to refer to Figure 5 The output module 03 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second potential adjustment device 031, and a third potential adjustment device 032.

[0066] The fifth transistor T5 has a control terminal that receives the second-level signal VGL. Its input terminal is connected to the pull-up node PU, and its output terminal is connected to the control terminal of the seventh transistor T7. Under the combined control of the second-level signal VGL and the potential signal of the pull-up node PU, the fifth transistor T5 adjusts the control terminal of the seventh transistor T7 to the potential signal of the pull-up node PU. When the voltage difference between the second-level signal SCK2 and the potential signal of the pull-up node PU is less than the voltage threshold of the fifth transistor T5, the fifth transistor T5 is in the on state; when the voltage difference is greater than the voltage threshold of the pull-up node PU, the fifth transistor T5 is in the off state. Furthermore, the fifth transistor T5 can adjust the control signal of the seventh transistor T7 to the potential signal of the pull-up node PU, enabling real-time adjustment of the control signal of the seventh transistor T7 and the potential signal of the pull-up node PU, while effectively blocking the reverse propagation of the low-potential control signal of the seventh transistor T7 to the potential signal of the pull-up node PU. Due to the physical characteristics of transistors, the input voltage of the fifth transistor T5 is always greater than the output voltage of the fifth transistor T5. Therefore, the voltage of the potential signal of the pull-up node PU is always greater than the voltage of the gate signal of the seventh transistor T7.

[0067] The control terminal of the sixth transistor T6 is connected to the pull-down node PU. The input terminal of the sixth transistor T6 is used to receive the first level signal VGH, and the output terminal of the sixth transistor T6 is connected to the drive signal SN_OUT. The sixth transistor T6 is used to adjust and output the drive signal SN_OUT under the control of the potential signal of the pull-down node PD.

[0068] The control terminal of the seventh transistor T7 is connected to the output stage of the fifth transistor T5. The input terminal of the seventh transistor T6 is used to receive the second clock signal SCK2, and the output terminal of the seventh transistor T6 is connected to the drive signal SN_OUT. The seventh transistor T7 is used to adjust and output the drive signal SN_OUT under the control of the output terminal of the fifth transistor T5.

[0069] The second potential adjustment device 031 is disposed between the control terminal and the output terminal of the seventh transistor T7. The second potential adjustment device 031 is used to control the level of the drive signal SN_OUT to follow the level change of the potential signal of the first node C, so as to accelerate the change process of the drive signal SN_OUT, improve the output stability of the drive signal SN_OUT, and ensure the stable operation of the circuit.

[0070] The third potential adjustment device 032 is disposed between the control terminal and the input terminal of the sixth transistor T6. The third potential adjustment device 032 is used to maintain the differential voltage between the control terminal and the input terminal of the sixth transistor T6 at a set differential voltage, to ensure the control stability of the sixth transistor T6, and to ensure that the sixth transistor T6 can adjust and output the drive signal SN_OUT in a timely manner, thus maintaining circuit stability. Optionally, as follows... Figure 5 As shown, the second potential adjustment device 031 can be capacitor C2, and the third potential adjustment device 032 can be capacitor C3. Of course, in some embodiments, the second potential adjustment device 031 can be a dedicated level shifting chip, and the third potential adjustment device 032 can be a dedicated level shifting chip.

[0071] In this embodiment, the first transistor T1 to the seventh transistor T8 in the scan driving circuit can be either an NMOS transistor or a PMOS transistor. In an NMOS transistor, the control terminal is the gate, the input terminal is the drain, and the output terminal is the source. In a PMOS transistor, the control terminal is the gate, the input terminal is the source, and the output terminal is the drain. The following embodiments use PMOS transistors as examples where the first transistor T1 to the seventh transistor T7 in the scan driving circuit are all PMOS transistors to describe the operation of the scan driving unit provided in this embodiment. It should be noted that the voltage of the first level signal VGH is greater than the voltage of the second level signal VGL. Therefore, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal.

[0072] like Figure 6 As shown, the working process of the scan driving unit provided in this application embodiment includes: output sustain phase t1, output sustain phase t2, low-level write phase t3, low-level output phase t4, discharge phase t5, and output sustain phase t6. The specific working process of each time period is as follows: During the output sustain phase t1, the circuit input signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level.

[0073] The fourth transistor T4 is turned on under the control of the first clock signal SCK1, and the potential signal of the pull-up node PU is adjusted to the high-level circuit input signal SIN, so that the second transistor T2 is turned off. The fifth transistor T5 is turned on under the control of the second-level signal VGL. The potential signal of the first node C is adjusted to the potential signal of the pull-up node PU, so that the seventh transistor T7 is turned off. The third transistor T3 is turned off under the control of the second clock signal SCK2. When the first clock signal SCK1 changes from a high-level signal to a low-level signal, the potential signal of the second node D changes accordingly with the first clock signal SCK1. At this time, the potential signal of the second node D is a low-level signal, so that the first transistor T1 is turned on, the potential signal of the pull-down node PD is adjusted to the low-level first clock signal SCK1, and then the sixth transistor T6 is turned on, and the drive signal SN_OUT is adjusted to the first-level signal VGH.

[0074] During the output sustaining phase t2, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal.

[0075] The fourth transistor T4 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-up node PU maintains the high level of the circuit input signal SIN for the time period t1, so that the second transistor T2 remains off. The fifth transistor T5 is turned on under the control of the second level signal VGL. The potential signal of the first node C maintains the potential signal of the pull-up node PU for the time period t1, so that the seventh transistor T7 remains off. The third transistor T3 is turned on under the control of the second clock signal SCK2. The potential signal of the second node D is adjusted to the first level signal VGH, and the first transistor T1 is turned off under the control of the potential signal of the second node D. The potential signal of the pull-down node PD maintains the low level of the first clock signal SCK1 for the time period t1. The sixth transistor T6 is turned on, and the drive signal SN_OUT maintains the first level signal VGH for the time period t1.

[0076] During the low-level write phase t3, the circuit input signal SIN is a low-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal.

[0077] The fourth transistor T4 is turned on under the control of the first clock signal SCK1. The potential signal of the pull-up node PU is adjusted to the low-level circuit input signal SIN, so that the second transistor T2 is turned off. The potential signal of the pull-down node PD maintains the low level of the first clock signal SCK1 for the time period t2. Consequently, the sixth transistor T6 is turned on, and the drive signal SN_OUT maintains the first level signal VGH for the time period t2. The fifth transistor T5 is turned on under the control of the second level point VGL. The potential signal of the first node C maintains the potential signal of the pull-up node PU for the time period t2, so that the seventh transistor T7 remains off. The third transistor T3 is turned off under the control of the second clock signal SCK2, and the first transistor T1 is turned on under the control of the first clock signal SCK1.

[0078] During the low-level output phase t4, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal.

[0079] The fourth transistor T4 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-up node PU maintains the low level of the circuit input signal SIN during the t3 time period, so that the second transistor T2 is turned on. The potential signal of the pull-down node PD is adjusted to the high level of the first clock signal SCK1, and then the sixth transistor T6 is turned off. Because the second capacitor C2 has a voltage holding function at the first node C, that is, during the t3 stage, the voltage difference across the second capacitor C2 is V. C2 =V B -V SN_OUT =V GL -V th -V GH When the second clock signal SCK2 transitions from a high level to a low level, the seventh transistor T7 turns on, causing the drive signal SN_OUT to transition from a high level to a low level along with the second clock signal SCK2. Correspondingly, the voltage of the potential signal at the first node C changes with the voltage of the drive signal SN_OUT. At this time, the voltage V of the potential signal at the first node C... C It satisfies V C =V SN_OUT +V C2 =V GL +V GL -V th -V GH =2*V GL -V th -V GH The seventh transistor at voltage V CThe third transistor T3 is turned on under the control of the second clock signal SCK2, and the potential signal of the second node D is adjusted to the first level signal VGH, so that the first transistor T1 is turned off.

[0080] During the discharge phase t5, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal.

[0081] The fourth transistor T4 is turned on under the control of the first clock signal SCK1. The potential signal of the pull-up node PD is adjusted to the high-level circuit input signal SIN, so that the second transistor T2 is turned off. The potential signal of the pull-down node PD maintains the high level of the first clock signal SCK1 for the time period t4. The fifth transistor T5 is turned on under the control of the second level signal VGL. The potential signal of the first node C is adjusted to the potential signal of the pull-up node PD, so that the seventh transistor T7 is turned off. The third transistor T3 is turned off under the control of the second clock signal SCK2. When the first clock signal SCK1 changes from a high level signal to a low level signal, the potential signal of the second node D changes accordingly with the first clock signal SCK1. At this time, the potential signal of the second node D is a low level signal, so that the first transistor T1 is turned on. The potential signal of the pull-down node PD is adjusted to the first clock signal SCK1, so that the sixth transistor T6 is turned on. The drive signal SN_OUT is adjusted to the first level signal VGH.

[0082] During the output sustaining phase t6, the circuit input signal SIN is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal.

[0083] The fourth transistor T4 is turned off under the control of the first clock signal SCK1. The potential signal of the pull-up node PU is maintained at a high level for the time period t5, so that the second transistor T2 remains off. The potential signal of the pull-down node PD is maintained at a low level for the time period t5, which is the first clock signal SCK1. Consequently, the sixth transistor T6 is turned on, and the drive signal SN_OUT is adjusted to the first level signal VGH. The fifth transistor T5 is turned on under the control of the second level signal VGL. The potential signal of the first node C is maintained at the potential signal of the pull-up node PD for the time period t5, and the seventh transistor T7 remains off. The third transistor T3 is turned on under the control of the second clock signal SCK2. The potential signal of the second node D is adjusted to the first level signal VGH, so that the first transistor T1 is turned off.

[0084] After time period t6 ends, the scan drive circuit alternates between discharge phase t5 and output maintenance phase t6 to obtain the complete drive signal of the scan drive circuit.

[0085] In the scanning drive circuit provided in this application embodiment, the scanning drive unit includes an input module, a pull-down module, and an output module. The input module is used to input signals to the pull-up node output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. In the pull-down module, the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor. The level of the control signal changes synchronously with the level of the first clock signal. The first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal. The second transistor is used to adjust the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node. Since the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies, the circuit area of ​​the scanning drive unit provided in this application is relatively narrow, thereby effectively reducing the circuit area of ​​the scanning drive circuit, reducing the wiring space required for the scanning drive circuit, and adapting to the narrow bezel design of the display device.

[0086] In some embodiments of this application, the scan driving circuit includes two stacked device layers. A first potential adjustment device C1 is disposed on one device layer, and a first transistor T1, a second transistor T2, and a third transistor T3 are disposed on the other device layer.

[0087] Optionally, in Figure 5 In the scan drive unit shown, the first potential adjustment device C1, the second potential adjustment device C2, and the third first potential adjustment device C3 can be disposed on one device layer; the first transistor T1 to the seventh transistor T7 can be disposed on another device layer simultaneously. For example, the first potential adjustment device C1 and the first transistor T1 are stacked. The first potential adjustment device C1 is connected to the control terminal and input terminal of the first transistor T1 through a via. The second potential adjustment device C2 and the seventh transistor T7 are stacked. The second potential adjustment device C2 is connected to the control terminal and output terminal of the seventh transistor T7 through a via. The third potential adjustment device C3 and the sixth transistor T6 are stacked. The third potential adjustment device C3 is connected to the control terminal and output terminal of the sixth transistor T6 through a via.

[0088] In current planar integrated circuit design, potential adjustment devices and transistor devices need to be arranged on the same chip surface, creating a space competition problem in this two-dimensional planar structure. Potential adjustment devices, needing sufficient plate area to achieve the required physical values, often occupy a large chip area; while transistor devices also need sufficient channel length and electrode spacing to maintain normal operating characteristics. This space competition makes it difficult to effectively compress the overall circuit module size, failing to meet the stringent requirements of modern display devices for narrow bezel designs in driving circuits.

[0089] In current planar integrated circuit design, circuit devices are typically arranged on the same device layer. However, due to the need for safe spacing between devices to prevent coupling and signal interference, the circuit area tends to be large, making it difficult to effectively compress the circuit size and meet the narrow bezel design requirements of current display devices. In this embodiment, by stacking circuit devices, the potential adjustment devices (including the first potential adjustment device C1, the second potential adjustment device C2, and the third potential adjustment device C3) and transistors can be located on different device layers. This effectively utilizes three-dimensional space, significantly reducing the circuit area and wiring space without affecting device performance, thus better adapting to the narrow bezel design of display devices.

[0090] Optional, Figure 7 This is a schematic diagram illustrating the cascaded relationship of a scanning drive circuit provided in an embodiment of this application. For example... Figure 7 As shown, the scan drive circuit includes multiple cascaded scan drive units. In the scan drive circuit, each scan drive unit receives the circuit input signal SIN, the first clock signal SCK1, and the second clock signal SCK2 to obtain the drive signal SN_OUT. Specifically, the circuit input signal SIN received by the first-stage scan drive unit is the data circuit input signal DSIN of the scan drive circuit. For all scan drive units other than the first-stage scan drive unit, the circuit input signal SIN received is the drive signal SN_OUT of the preceding scan drive unit.

[0091] For example, please continue to refer to Figure 7The scan drive circuit includes at least six cascaded scan drive units Scan1-Scan6. The signal input terminal Psin of the first-stage scan drive unit Scan1 receives the data circuit input signal DSIN. The signal output terminal OUT of the first-stage scan drive unit Scan1 is connected to the signal input terminal Psin of the second-stage scan drive unit Scan2, and is used to transmit the drive signal SN_OUT1 to the second-stage scan drive unit Scan2. The signal output terminal OUT of the second-stage scan drive unit Scan2 is connected to the signal input terminal Psin of the third-stage scan drive unit Scan3, and is used to transmit the drive signal SN_OUT2 to the second-stage scan drive unit Scan3. The signal output terminal OUT of the third-stage scan drive unit Scan3 is connected to the signal input terminal Psin of the fourth-stage scan drive unit Scan4, and is used to transmit the drive signal SN_OUT3 to the fourth-stage scan drive unit Scan4. And so on, with the signal output terminal OUT of the fifth-stage scan drive unit Scan5 connected to the signal input terminal Psin of the sixth-stage scan drive unit Scan6, and so on, to transmit the drive signal SN_OUT5 to the sixth-stage scan drive unit Scan6. Furthermore, the first clock signal terminal Psck1 and the second clock signal terminal Psck2 of each scanning drive unit are used to receive the first clock signal SCK1 and the second clock signal SCK2, respectively.

[0092] The signal input terminal Psin of the scan drive unit is connected to the input terminal of the fourth transistor T4 in the scan drive unit, providing the circuit input signal SIN. The first clock signal terminal Psck1 of the scan drive unit is connected to the input terminals of the first transistor T1, the second transistor T2, and the control terminal of the fourth transistor T4, providing the first clock signal SCK1. The second clock signal terminal Psck2 of the scan drive unit is connected to the control terminal of the seventh transistor T7 in the scan drive unit, providing the second clock signal SCK2.

[0093] Please refer to Figure 8 It shows a timing diagram of a scan driving circuit provided in an embodiment of this application, such as... Figure 8 As shown, this circuit operates under the control of the first clock signal SCK1, the second clock signal SCK2, and the data circuit input signal DSIN to cascade and generate 2400 drive signals SN_OUT1 to SN_OUT2400. The first clock signal SCK1 and the second clock signal SCK2 have the same frequency but opposite phase, and their period is Sin_t0. Starting from the second time period t1, the multi-stage scan drive unit sequentially outputs drive signals with valid levels.

[0094] In the scanning drive circuit provided in this application embodiment, the scanning drive unit includes an input module, a pull-down module, and an output module. The input module is used to input signals to the pull-up node output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. In the pull-down module, the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor. The level of the control signal changes synchronously with the level of the first clock signal. The first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal; the second transistor is used to adjust the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node. Since the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies, the circuit area of ​​the scanning drive unit provided in this application is relatively narrow, thereby effectively reducing the circuit area of ​​the scanning drive circuit, reducing the wiring space required for the scanning drive circuit, and adapting to the narrow bezel design of the display device.

[0095] This application also provides a display device including the scanning drive circuit provided in this application embodiment. In the display device provided in this application embodiment, the scanning drive unit of the scanning drive circuit includes an input module, a pull-down module, and an output module. The input module is used to input signals to the pull-up node output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. In the pull-down module, the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor, the level of the control signal changing synchronously with the level of the first clock signal. The first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal. The second transistor is used to adjust the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node. Note that the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies. Therefore, the scanning drive unit provided by the technical solution of this application has a relatively narrow circuit area, which effectively reduces the circuit area of ​​the scanning drive circuit, thereby reducing the wiring space required for the scanning drive circuit, adapting to the narrow bezel design of the display device, effectively improving the screen ratio of the display device, and enhancing the user's viewing experience.

[0096] This application also provides an electronic device, which may include the scanning drive circuit or display device provided in this application. For example, the electronic device may be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It may also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application does not specifically limit the scope of the electronic device.

[0097] In the electronic device provided in this application embodiment, the scanning driving unit of the scanning driving circuit includes an input module, a pull-down module, and an output module. The input module is used to input signals to the pull-up node output circuit, and the circuit input signals are used to adjust the potential signal of the pull-up node. In the pull-down module, the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor. The level of the control signal changes synchronously with the level of the first clock signal. The first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal. The second transistor is used to adjust the potential signal of the pull-down node under the control of the potential signal of the pull-up node. The output module is used to output a driving signal under the control of the potential signals of the pull-up node and the pull-down node. Since the number of transistors included in the pull-down module in this application is less than the number of transistors included in the pull-down module in related technologies, the circuit area of ​​the scanning driving unit provided in this application is relatively narrow, thereby effectively reducing the circuit area of ​​the scanning driving circuit, reducing the wiring space required for the scanning driving circuit, adapting to the narrow bezel design of the display device, effectively improving the screen-to-body ratio of the display device, and enhancing the user viewing experience.

[0098] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0100] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A scanning drive circuit, characterized in that, The system includes multiple cascaded scan driving units, each of which includes an input module, a pull-down module, and an output module. The pull-down module includes a first transistor, a second transistor, and a potential coupling component. The input module is connected to the output module, the first transistor is connected to the potential coupling component and the output module, and the second transistor is connected to the pull-up node and the pull-down node. The pull-up node is the electrical connection point between the input module and the output module, and the pull-down node is the electrical connection point between the pull-down module and the output module. The input module is used to input a signal to the pull-up node output circuit, and the circuit input signal is used to adjust the potential signal of the pull-up node; the potential coupling component is used to receive a first clock signal and output a control signal to the control terminal of the first transistor, and the level of the control signal changes synchronously with the level of the first clock signal; the first transistor is used to adjust the potential signal of the pull-down node under the control of the control signal; the second transistor is used to adjust the potential signal of the pull-up node under the control of the potential signal of the pull-up node; the output module is used to output a drive signal under the control of the potential signals of the pull-up node and the pull-down node.

2. The scanning drive circuit according to claim 1, characterized in that, The potential coupling component includes: a third transistor and a first potential adjustment device; The control terminal of the third transistor is used to receive the second clock signal, the input terminal of the third transistor is used to receive the first level signal, and the output terminal of the third transistor is connected to the control terminal of the first transistor. The first potential adjustment device is disposed between the control terminal and the input terminal of the first transistor; When the level of the first clock signal is at the first level, the third transistor, under the control of the second clock signal, adjusts the control signal received by the control terminal of the first transistor to the first level signal; when the level of the first clock signal changes from the first level to the second level, the first potential adjustment device adjusts the control signal of the first transistor from the first level signal to the second level control signal.

3. The scanning drive circuit according to claim 2, characterized in that, The first potential adjustment device is a capacitor.

4. The scanning drive circuit according to claim 2, characterized in that, The scanning drive circuit includes two stacked device layers, with the first potential adjustment device disposed on one device layer and the first transistor, the second transistor, and the third transistor disposed on the other device layer.

5. The scanning drive circuit according to any one of claims 1 to 4, characterized in that, The drop-down module includes: The control terminal of the first transistor is connected to the potential coupling component, the input terminal of the first transistor is used to receive the first clock signal, and the output terminal of the first transistor is connected to the pull-down node. The control terminal of the second transistor is connected to the pull-up node, the input terminal of the second transistor is used to receive the first clock signal, and the output terminal of the second transistor is connected to the pull-down node.

6. The scanning drive circuit according to claim 1, characterized in that, The input module includes: a fourth transistor; The control terminal of the fourth transistor is used to receive the first clock signal, the input terminal of the fourth transistor is used to receive the circuit input signal, and the output terminal of the fourth transistor is connected to the pull-up node; the fourth transistor is used to adjust the potential signal of the pull-up node to the circuit input signal under the control of the first clock signal.

7. The scanning drive circuit according to claim 1, characterized in that, The output module includes: a fifth transistor, a sixth transistor, a seventh transistor, a second potential adjustment device, and a third potential adjustment device; The input terminal of the fifth transistor is connected to the pull-up node, and the output terminal of the fifth transistor is connected to the control terminal of the seventh transistor. The control terminal of the fifth transistor is used to receive the second level signal. The control terminal of the sixth transistor is connected to the pull-down node, the input terminal of the sixth transistor is used to receive the first level signal, the output terminal of the sixth transistor is connected to the output terminal of the seventh transistor and is used to output the drive signal, the control terminal of the seventh transistor is connected to the output terminal of the fifth transistor, and the input terminal of the seventh transistor is used to receive the second clock signal; The second potential adjustment device is disposed between the control terminal and the output terminal of the seventh transistor; the third potential adjustment device is disposed between the control terminal and the input terminal of the sixth transistor.

8. The scanning drive circuit according to any one of claims 1 to 7, characterized in that, The first clock signal and the second clock signal have opposite phases but the same frequency.

9. A display device, characterized in that, Includes the scanning drive circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, It includes the scanning driving circuit according to any one of claims 1 to 8, or the display device according to claim 9.

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