Interface multiplexing circuit and dynamic random access memory

Abstract

This application discloses an interface multiplexing circuit and a dynamic random access memory (DRAM). The interface multiplexing circuit includes an interface module, an information bus, and a processing module. The interface module acquires external instructions, which include instruction information and operation information. The information bus is connected to the interface module and transmits the instruction information and operation information. The processing module is connected to the information bus and performs corresponding operations based on the instruction information and operation information. The types of external instructions include configuration instructions and test instructions. Test instructions and configuration instructions use the same instruction format and reuse the information bus. Furthermore, the truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction. Through this method, the interface multiplexing circuit of this application allows configuration instructions and test instructions to reuse the same circuit and information bus, thereby saving circuit area and power consumption.

Description

Technical Field

[0001] This application relates to the field of memory technology, specifically to an interface multiplexing circuit and a dynamic random access memory. Background Technology

[0002] In the field of dynamic random access memory (DRAM) technology, taking Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM, DDR SDRAM) as an example, the Joint Electron Device Engineering Council (JEDEC) standard clearly defines the form and requirements of its configuration instructions, but does not specifically specify test instructions, which are usually determined by the manufacturers themselves. However, in the mass production testing phase of DRAM, it is necessary to rely on test instructions to implement a series of special functions that are only used in the testing process and are not accessible to users, such as parallel testing or voltage regulation. Since test instructions and configuration instructions usually differ, they often lack compatibility and reusability. Therefore, in existing technical solutions, the two instruction sets operate independently, and the information generated has no shared channel, resulting in a significant increase in circuit area overhead. Summary of the Invention

[0003] To address the aforementioned problems, this application proposes an interface multiplexing circuit and a dynamic random access memory (DRAM), aiming to solve these problems.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an interface multiplexing circuit, which includes an interface module, an information bus, and a processing module. The interface module is used to acquire external instructions, wherein the external instructions include instruction information and operation information; the information bus is connected to the interface module and is used to transmit instruction information and operation information; the processing module is connected to the information bus and is used to perform corresponding operations based on the instruction information and operation information; wherein the types of external instructions include configuration instructions and test instructions, the test instructions and configuration instructions adopt the same instruction format and reuse the information bus, and the truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction.

[0005] The processing module includes a configuration module and a testing module. The information bus is connected to the configuration module, and the testing module is connected to the configuration module.

[0006] The configuration module is used to parse instruction information to identify the type of external instruction and perform corresponding operations according to the type of external instruction; in response to the external instruction being a configuration instruction, the configuration module updates the configuration information based on the operation information.

[0007] Specifically, if the external command is a test command and a test enable signal is received, the configuration module sends operation information to the test module so that the test module can update the test information based on the operation information; if the external command is a test command but a test enable signal is not received, the configuration module prohibits sending operation information to the test module.

[0008] The interface multiplexing circuit also includes a test enable control module, which is connected to the configuration module and is used to determine whether the test enable signal is enabled based on the configuration information.

[0009] The interface multiplexing circuit also includes a data acquisition circuit, which is connected between the interface module and the information bus to collect and store instruction information and operation information. The instruction information of the test instruction and the instruction information of the configuration instruction are stored in the same location in the data acquisition circuit; the operation information of the test instruction and the operation information of the configuration instruction are also stored in the same location in the data acquisition circuit.

[0010] The operation information for configuration and test instructions further includes the mode register address and mode register value.

[0011] The information bus includes an instruction address information bus and an instruction data information bus; the instruction address information bus is used to transmit the mode register address of configuration instructions or test instructions, and the instruction data information bus is used to transmit the mode register value of configuration instructions or test instructions.

[0012] The truth values ​​corresponding to the instruction information of the test instruction include a first truth value and a second truth value. The number of bits in the first truth value and the second truth value is the same as the number of bits in the truth value corresponding to the instruction information of the configuration instruction. The first truth value and the second truth value are configured to be different from the truth values ​​corresponding to the instruction information of each configuration instruction. The first truth value and the second truth value are also configured to be different.

[0013] The interface module is included in the double data rate synchronous dynamic random access memory interface, and / or the interface module is included in the dynamic random access memory interface, the dynamic random access memory interface further includes a data interface for receiving and / or sending data from the outside, and the data interface is independent of the interface module.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a dynamic random access memory, which includes the interface multiplexing circuit of any one of the above.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the interface multiplexing circuit of this application includes an interface module, an information bus, and a processing module. The interface module is used to acquire external instructions, which include instruction information and operation information. The information bus is connected to the interface module and is used to transmit the instruction information and operation information. The processing module is connected to the information bus and is used to perform corresponding operations based on the instruction information and operation information. The types of external instructions include configuration instructions and test instructions. Test instructions and configuration instructions use the same instruction format and reuse the information bus. Furthermore, the truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction. Through the above method, the interface multiplexing circuit of this application allows configuration instructions and test instructions to reuse the same circuit and information bus, thereby saving circuit area and power consumption. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0017] Figure 1 This is a schematic diagram of the structure of the first embodiment of the interface multiplexing circuit provided in this application;

[0018] Figure 2 This is a schematic diagram of the structure of the second embodiment of the interface multiplexing circuit provided in this application;

[0019] Figure 3 This is a schematic diagram of the structure of the third embodiment of the interface multiplexing circuit provided in this application;

[0020] Figure 4 This is a schematic diagram of the fourth embodiment of the interface multiplexing circuit provided in this application;

[0021] Figure 5 This is a schematic diagram of an embodiment of the configuration instructions provided in this application;

[0022] Figure 6 This is a schematic diagram of an embodiment of the test instructions provided in this application;

[0023] Figure 7 This is a schematic diagram of an embodiment of the truth table corresponding to the instruction information of the configuration instructions for the low-power double data rate fourth-generation synchronous dynamic random access memory provided in this application.

[0024] Figure 8 This is a schematic diagram of the structure of an embodiment of the dynamic random access memory provided in this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0026] In the field of dynamic random access memory (DRAM) technology, taking Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM, DDR SDRAM) as an example, the Joint Electron Device Engineering Council (JEDEC) standard clearly defines the form and requirements of its configuration instructions, but does not specifically specify test instructions, which are usually determined by the manufacturers themselves. However, in the mass production testing phase of DRAM, it is necessary to rely on test instructions to implement a series of special functions that are only used in the testing process and are not accessible to users, such as parallel testing or voltage regulation. Since test instructions and configuration instructions usually differ, they often lack compatibility and reusability. Therefore, in existing technical solutions, the two instruction sets operate independently, and the information generated has no shared channel, resulting in a significant increase in circuit area overhead.

[0027] To address the aforementioned issues, this application first proposes an interface multiplexing circuit, please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the interface multiplexing circuit provided in this application. Figure 1 As shown, the interface multiplexing circuit 100 of this embodiment includes an interface module 10, an information bus 20, and a processing module 30. The interface module 10 is used to acquire external instructions, wherein the external instructions include instruction information and operation information. The information bus 20 is connected to the interface module 10 and is used to transmit instruction information and operation information. The processing module 30 is connected to the information bus 20 and is used to perform corresponding operations based on the instruction information and operation information. The types of external instructions include configuration instructions and test instructions. The test instructions and configuration instructions adopt the same instruction format and reuse the information bus 20. The truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction.

[0028] In this embodiment, the interface module 10 is included in the dynamic random access memory interface; that is, the interface multiplexing circuit 100 of this embodiment can be applied to dynamic random access memory. Taking double data rate synchronous dynamic random access memory (DDR SDRAM) as an example, the truth values ​​corresponding to its configuration instructions have been clearly defined. For example, the Move Register to Special Register (MRS) instruction has been clearly defined. However, test instructions have not been defined or standardized. For example, the Design For Test (DFT) instruction has not been defined or standardized. Therefore, in order to multiplex the information bus 20 for test instructions and configuration instructions, in this embodiment, it is necessary to set the test instructions and configuration instructions to the same instruction format and multiplex the information bus 20. In addition, in order to distinguish between test instructions and configuration instructions, it is also necessary to configure the truth value corresponding to the instruction information of the test instructions to be different from the truth value corresponding to the instruction information of each configuration instruction. That is, by adjusting part of the bits of the truth value corresponding to the instruction information of the test instructions, it is ensured that the truth value corresponding to the instruction information of the test instructions does not conflict with the truth value of the existing configuration instructions. Setting the truth value corresponding to the instruction information of the test instruction to be completely different from the truth value corresponding to the instruction information of all configuration instructions can avoid conflicts between the test instructions and configuration instructions and ensure the accuracy of instruction execution.

[0029] Among them, the test instructions mentioned above (such as DFT instructions) are external instructions used to modify the internal test signals of the chip. Test instructions include, but are not limited to, parallel test instructions, internal voltage adjustment instructions, current adjustment instructions, and chip power consumption control instructions.

[0030] Unlike existing technologies, the interface multiplexing circuit 100 of this application includes an interface module 10, an information bus 20, and a processing module 30. The interface module 10 is used to acquire external instructions, which include instruction information and operation information. The information bus 20 is connected to the interface module 10 and is used to transmit instruction information and operation information. The processing module 30 is connected to the information bus 20 and is used to perform corresponding operations based on the instruction information and operation information. The types of external instructions include configuration instructions and test instructions. Test instructions and configuration instructions use the same instruction format and reuse the information bus 20. The truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction. In this way, the interface multiplexing circuit 100 of this application can reuse the same circuit and information bus for configuration instructions and test instructions, thereby saving circuit area and power consumption.

[0031] Furthermore, since both test instructions and configuration instructions are generated from the same module and processed through the same path and circuitry, the matching between the mode register address and the mode register value in the operation information of the information bus 20 is good, and the timing difference will be very small.

[0032] Optionally, based on the above embodiments, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the interface multiplexing circuit provided in this application. Figure 2 As shown, the processing module 30 in this embodiment includes a configuration module 31 and a test module 32. The information bus 20 is connected to the configuration module 31, and the test module 32 is connected to the configuration module 31.

[0033] In this embodiment, the processing module 30 includes a configuration module 31 and a testing module 32. The configuration module 31 receives and processes instruction information and operation information from the information bus 20, and the testing module 32 obtains the operation information corresponding to the test instruction through its connection with the configuration module 31. In this embodiment, connecting the testing module 32 and the configuration module 31 on the same line allows them to share the information bus 20, enabling the configuration module 31 and the testing module 32 to interact through the same set of physical lines.

[0034] That is, in this embodiment, through the collaborative design of the configuration module 31 and the test module 32, the configuration instructions and test instructions can share the same set of information buses 20, which effectively reduces the number of signal lines inside the memory and reduces the circuit area occupied.

[0035] Optionally, based on all the above embodiments, in this embodiment, as follows: Figure 2 As shown, the configuration module 31 is used to parse instruction information to identify the type of external instruction and perform corresponding operations according to the type of external instruction; in response to the external instruction being a configuration instruction, the configuration module 31 updates the configuration information based on the operation information.

[0036] That is, in this embodiment, when the information bus 20 sends an external instruction to the configuration module 31, the configuration module 31 can only update the configuration information if the external instruction is a configuration instruction. When the information bus 20 sends a test instruction to the configuration module 31, the configuration module 31 will not perform a configuration information update operation.

[0037] Optionally, based on all the above embodiments, in this embodiment, in response to an external instruction being a test instruction and a test enable signal being received, the configuration module 31 sends operation information to the test module so that the test module 32 updates the test information based on the operation information; in response to an external instruction being a test instruction but no test enable signal being received, the configuration module 31 prohibits sending operation information to the test module 32.

[0038] In this embodiment, when the instruction type sent from the information bus 20 to the configuration module 31 is a test instruction, the configuration module 31 will only send the operation information corresponding to the test instruction to the test module 32 after receiving the test enable signal. At this time, the test module 32 will update the test information based on the operation information corresponding to the test instruction. That is, in this embodiment, the operation information corresponding to the test instruction will only cause the test module 32 to update the test information when the test enable signal is enabled. Furthermore, in this embodiment, the test enable signal is only used during dynamic random access memory testing and is not made available to the user.

[0039] In this embodiment, by setting a test enable signal, when the user uses configuration commands, the test module 32 will not work due to the operation information corresponding to the configuration commands, thereby helping to reduce power consumption in normal use scenarios.

[0040] Optionally, based on all the above embodiments, please refer to Figure 3 , Figure 3 This is a schematic diagram of the third embodiment of the interface multiplexing circuit provided in this application. Figure 3 As shown, the interface multiplexing circuit 100 in this embodiment also includes a test enable control module 40, which is connected to the configuration module 31 and is used to determine whether the test enable signal is enabled based on the configuration information.

[0041] As mentioned earlier, to reduce power consumption in normal user scenarios, the configuration module 31 only sends the operation information corresponding to the test instruction to the test module 32 when it receives a test enable signal and the type of the external instruction is a test instruction, so that the test module 32 can update the test information. Therefore, a test enable control module 40 is added in this embodiment. The test enable control module 40 in this embodiment is connected to the configuration module 31 and can decide whether to send a test enable signal to the configuration module 31 based on a certain configuration information updated by the configuration module 31. That is, the test enable control module 40 can determine whether to output a test enable signal to the configuration module 31 by analyzing a specific flag bit in the configuration information.

[0042] In this way, the interface multiplexing circuit 100 of this embodiment can avoid unnecessary circuit operation in normal working mode, thereby reducing overall power consumption. When the test enable signal is not activated, the test module 32 and the connection bus between the test module 32 and the configuration module 31 are inactive, thereby reducing the overall power consumption of the circuit.

[0043] Optionally, based on all the above embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the fourth embodiment of the interface multiplexing circuit provided in this application. Figure 4 As shown, the interface multiplexing circuit 100 in this embodiment also includes a data acquisition circuit 50. The data acquisition circuit 50 is connected between the interface module 10 and the information bus 20 and is used to acquire and store instruction information and operation information. The instruction information of the test instruction and the instruction information of the configuration instruction are stored in the same location in the data acquisition circuit 50. The operation information of the test instruction and the operation information of the configuration instruction are also stored in the same location in the data acquisition circuit 50.

[0044] In this embodiment, the data acquisition circuit 50 is connected to the interface module 10 and the information bus 20, and is used to acquire and save instruction information and operation information. The data acquisition circuit 50 can be implemented through a combination of storage units and control logic, such as using register groups or buffers to store data, and managing the triggering and synchronization of data acquisition through a timing control module. In this embodiment, the data acquisition circuit 50 can be integrated inside the interface module 10, or it can interact directly with the information bus 20 as an independent module. When the interface module 10 receives a test instruction or configuration instruction, the data acquisition circuit 50 can temporarily store the instruction information and operation information corresponding to the test instruction or configuration instruction, and then transmit them to the processing module 30.

[0045] Furthermore, to improve the efficiency of subsequent data transmission, in this embodiment, the instruction information of the test instruction and the instruction information of the configuration instruction are stored in the same location in the data acquisition circuit 50, and the operation information of the test instruction and the operation information of the configuration instruction are also stored in the same location in the data acquisition circuit 50. That is, regardless of the type of external instruction, its corresponding instruction information is stored in a fixed storage location in the data acquisition circuit 50, and its corresponding operation information is stored in another fixed storage location in the data acquisition circuit 50.

[0046] In this embodiment, configuration instructions and test instructions can also share the same set of data acquisition circuits 50 through the above method, thereby reducing the circuit area occupied.

[0047] Optionally, such as Figure 4 As shown, in this embodiment, the operation information for the configuration and test instructions includes the mode register address (i.e., Figures 5-7 The MA in the truth table corresponding to the instruction information and the Operation Value (also known as the Mode Register Value) are... Figures 5-7The information bus 20 in this embodiment includes an instruction address information bus 21 and an instruction data information bus 22; the instruction address information bus 21 is used to transmit the mode register address of the configuration instruction or test instruction, and the instruction data information bus 22 is used to transmit the mode register value of the configuration instruction or test instruction.

[0048] In this embodiment, the information bus 20 can be divided into an instruction address information bus 21 and an instruction data information bus 22. The instruction address information bus 21 is responsible for transmitting the mode register address in the configuration instruction or test instruction, so that the configuration module 31 connected to it can perform addressing operations based on the mode register address. The instruction data information bus 22 is responsible for transmitting the mode register value in the configuration instruction or test instruction, so that the subsequent configuration module 31 or test module 32 can perform corresponding information updates based on the mode register value.

[0049] In addition, such as Figure 4 As shown, in this embodiment, the data acquisition circuit 50 also needs to send instruction information to the configuration module 31 so that the configuration module 31 can parse the instruction information to identify the type of external instruction and perform corresponding operations according to the type of external instruction.

[0050] By separating the transmission paths of the mode register address and the mode register value, this embodiment can ensure the accuracy and stability of instruction execution.

[0051] Optionally, based on all the above embodiments, in this embodiment, the truth value corresponding to the instruction information of the test instruction includes a first truth value and a second truth value. The number of bits of the first truth value and the second truth value is the same as the number of bits of the truth value corresponding to the instruction information of the configuration instruction. The first truth value and the second truth value are configured to be different from the truth value corresponding to the instruction information of each configuration instruction. The first truth value and the second truth value are also configured to be different.

[0052] In this embodiment, please refer to Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the configuration instructions provided in this application. In this embodiment, taking Low Power Double Data Rate 4th Generation (LPDDR4) Synchronous Dynamic Random Access Memory (SDRAM) as an example, according to the definition of its corresponding JDEDC, the information obtained from the configuration instructions corresponding to the write operation is as follows: Figure 5As shown, in this embodiment, the configuration instruction (SDRAM Command) is a "Mode Register Write" instruction, and the "Mode Register Write" instruction includes Mode Register Write-1 and Mode Register Write-2.

[0053] In Mode Register Write-1, when the chip select signal (CS) is high (i.e., "H"), CA0 to CA4 provide the first instruction information for the "Mode Register Write" operation, and CA5 provides the mode register value OP from the operation information. <7> When the chip select signal (CS) is low (i.e., "L"), CA0 to CA5 provide the mode register address MA<5:0> from the operation information of the "Mode Register Write" instruction. In Mode Register Write-2, when the chip select signal (CS) is high (i.e., "H"), CA0 to CA4 provide the second instruction information of the "Mode Register Write" instruction, and CA5 provides the mode register value OP from the operation information. <6> When the chip select signal (CS) is low (i.e., "L"), CA0 to CA5 provide the mode register values ​​OP<5:0> from the operation information. Based on the above, it can be seen that the "ModeRegister Write" instruction provides a total of 14 bits of operation information, including OP<7:0> and MA<5:0>. Figure 5 It can be seen that in order to distinguish between Mode RegisterWrite-1 and Mode Register Write-2 in the "Mode Register Write" instruction, there is a difference in CA4 in the first instruction information of Mode Register Write-1 and the second instruction information of Mode Register Write-2.

[0054] In this embodiment, if the test instruction wants to reuse the information bus 20 of the configuration instruction, the test instruction can only provide a maximum of 14 bits of operation information. At the same time, the test instruction and the configuration instruction need to use the same instruction format to ensure that the data acquisition circuit 50 can also be reused.

[0055] Please see Figure 6 and Figure 7 , Figure 6This is a schematic diagram of an embodiment of the test instructions provided in this application; Figure 7 This is a schematic diagram of an embodiment of the truth table corresponding to the configuration instructions of the low-power double data rate fourth-generation synchronous dynamic random access memory provided in this application.

[0056] like Figure 6 As shown, the test instruction (DFT instruction) takes Test mode Write as an example. Test mode Write uses the same format as the configuration instruction, including Test mode Write-1 and Test mode Write-2. In Test mode Write-1, when the chip select signal (CS) is high (i.e., "H"), the "*" provided by CA0 to CA4 represents the first truth value corresponding to the first instruction information of Test mode Write-1, and CA5 provides the operation information corresponding to Test mode Write. When the chip select signal (CS) is low (i.e., "L"), CA0 to CA5 provide the operation information corresponding to Test mode Write. In Test mode Write-2, when the chip select signal (CS) is high (i.e., "H"), the "*" provided by CA0 to CA4 represents the second truth value corresponding to the second instruction information of Test mode Write-2, and CA5 provides the operation information corresponding to Test mode Write. When the chip select signal (CS) is low (i.e., "L"), CA0 to CA5 provide the operation information corresponding to Test mode Write. Therefore, the test instruction provides a maximum of 14 bits of operation information.

[0057] Furthermore, in order to enable the test instructions to reuse the information bus 20 of the configuration instructions and the data acquisition circuit 50, such as Figure 6 As shown, the number of bits for the first and second truth values ​​of the test instruction needs to be configured to be the same as the number of bits for the truth value corresponding to the instruction information of the configuration instruction, and the first and second truth values ​​need to be configured to be the same as... Figure 7 The truth values ​​corresponding to the instruction information of each configuration instruction shown are different. In order to distinguish between Test mode Write-1 and Test mode Write-2, the first truth value and the second truth value also need to be configured to be different. However, the specific values ​​of the first truth value and the second truth value are determined by the design and only need to meet the above conditions. There are no restrictions here.

[0058] Through the above method, this embodiment can make the instruction formats of test instructions and configuration instructions completely consistent and independent of each other. Thus, test instructions and configuration instructions can reuse the same data acquisition circuit 50 and information bus 20.

[0059] In this embodiment, by setting a test instruction truth value that differs from the configuration instruction truth value, it can be ensured that the two instructions will not conflict when multiplexed on the information bus 20, thereby achieving transmission channel sharing. This design eliminates the need for separate routing for the test instruction, effectively reducing chip wiring complexity and circuit area. Furthermore, since the test instruction truth value is different from the configuration instruction, it avoids accidental triggering of the test function in normal operating mode, improving system stability. At this time, configuring the first and second truth values ​​to be different also enhances the accuracy of the test instruction in obtaining the corresponding operation information, thereby improving the efficiency of the test instruction.

[0060] Optionally, based on all the above embodiments, in this embodiment, the interface module 10 described above is included in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) interface. Furthermore, in this embodiment, the interface module 10 is included in a Dynamic Random Access Memory (DRAM) interface. The interface module 10 may be a Command / Address (CA) interface of the DRAM interface. The DRAM interface may also include a data interface for receiving and / or sending data from the outside (e.g., a bidirectional data transfer interface of the DDR interface), and the data interface is independent of the interface module 10.

[0061] In this embodiment, the instruction address interface and data interface of the dynamic random access memory interface are configured to be independent of each other. Specifically, the interface multiplexing circuit 100 involved in this embodiment only multiplexes the information bus 20 corresponding to the instruction address interface.

[0062] Optionally, please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of an embodiment of the dynamic random access memory provided in this application. Figure 8 As shown, the dynamic random access memory 200 of this embodiment includes the interface multiplexing circuit 100 of any of the above embodiments.

[0063] In this embodiment, the dynamic random access memory 200 includes, but is not limited to, low-power double data rate synchronous dynamic random access memory.

[0064] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An interface multiplexing circuit, characterized in that, The interface multiplexing circuit includes: An interface module is used to acquire external instructions, wherein the external instructions include instruction information and operation information; An information bus is connected to the interface module, and the information bus is used to transmit the instruction information and the operation information. A processing module, connected to the information bus, is used to perform corresponding operations based on the instruction information and the operation information; The external instructions include configuration instructions and test instructions. The test instructions and configuration instructions use the same instruction format and reuse the information bus. The truth value corresponding to the instruction information of the test instructions is configured to be different from the truth value corresponding to the instruction information of each configuration instruction. The truth value corresponding to the instruction information of the test instruction includes a first truth value and a second truth value. The number of bits in the first truth value and the second truth value is the same as the number of bits in the truth value corresponding to the instruction information of the configuration instruction. The first truth value and the second truth value are configured to be different from the truth value corresponding to the instruction information of each configuration instruction. The first truth value and the second truth value are also configured to be different.

2. The interface multiplexing circuit according to claim 1, characterized in that, The processing module includes a configuration module and a testing module. The information bus is connected to the configuration module, and the testing module is connected to the configuration module.

3. The interface multiplexing circuit according to claim 2, characterized in that, The configuration module is used to parse the instruction information to identify the type of the external instruction, and perform corresponding operations according to the type of the external instruction; in response to the external instruction being the configuration instruction, the configuration module updates the configuration information based on the operation information.

4. The interface multiplexing circuit according to claim 3, characterized in that, In response to the external instruction being the test instruction and a test enable signal being received, the configuration module sends the operation information to the test module so that the test module updates the test information based on the operation information; in response to the external instruction being the test instruction but no test enable signal being received, the configuration module prohibits sending the operation information to the test module.

5. The interface multiplexing circuit according to claim 4, characterized in that, The interface multiplexing circuit further includes a test enable control module, which is connected to the configuration module and is used to determine whether the test enable signal is enabled based on the configuration information.

6. The interface multiplexing circuit according to claim 1, characterized in that, The interface multiplexing circuit further includes a data acquisition circuit, which is connected between the interface module and the information bus, and is used to acquire and store the instruction information and the operation information; wherein, the instruction information of the test instruction and the instruction information of the configuration instruction are stored in the same location in the data acquisition circuit; the operation information of the test instruction and the operation information of the configuration instruction are also stored in the same location in the data acquisition circuit.

7. The interface multiplexing circuit according to claim 1, characterized in that, The operation information of the configuration instruction and the test instruction further includes the mode register address and the mode register value.

8. The interface multiplexing circuit according to claim 7, characterized in that, The information bus includes an instruction address information bus and an instruction data information bus; the instruction address information bus is used to transmit the mode register address of the configuration instruction or the test instruction, and the instruction data information bus is used to transmit the mode register value of the configuration instruction or the test instruction.

9. The interface multiplexing circuit according to claim 1, characterized in that, The interface module is contained in the Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) interface, or, The interface module is included in the dynamic random access memory interface, which further includes a data interface for receiving and / or sending data from the outside, and the data interface is independent of the interface module.

10. A dynamic random access memory, characterized in that, Includes the interface multiplexing circuit described in any one of claims 1-9.

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