High-frequency power amplifier and production process of high-frequency power amplifier

Abstract

The invention relates to the technical field of amplifiers, in particular to a high-frequency power amplifier and a production process of the high-frequency power amplifier. Comprising a heat sink material, an insulating layer, a lead frame, a passive device, a sealing cover and a chip, the heat sink material is made of CPC, CMC, CWC or C diamond materials, the insulating layer is made of ceramic materials, the lead frame is made of kovar alloy, and the sealing cover is made of metal or ceramic materials; at least one layer between the heat sink material and the insulating layer, between the insulating layer and the lead frame, and between the lead frame and the sealing cover is bonded through B-order glue or epoxy resin glue. The problem of material thermal expansion mismatch caused by high-temperature welding can be solved, and the process complexity and cost are reduced.

Description

Technical Field

[0001] This invention relates to the field of amplifier technology, specifically to a high-frequency power amplifier and its manufacturing process. Background Technology

[0002] In the field of high-frequency power amplifier devices, existing technologies generally employ a full-welding process for packaging. This involves welding the chip to the heat sink material, and also welding the heat sink material to the insulating layer, the insulating layer to the lead frame, and the lead frame to the cap. This full-welding process presents a major problem that urgently needs to be addressed: multi-layer high-temperature welding can lead to microcracks or even warping due to the mismatch in thermal expansion coefficients between materials such as ceramics and heat sink metals, resulting in packaging failure. During high-temperature welding, the stringent surface treatment requirements and extremely high temperature control standards not only result in insufficient process redundancy and low yield rates but also significantly increase production costs. Furthermore, the multi-level interconnection structure of the chip, capacitors, and lead frame increases contact resistance, causing unintended heat generation and severely impacting the device's operating condition and lifespan.

[0003] Based on the above problems, there is an urgent need for a high-frequency power amplifier device packaging technology solution that can solve the material thermal expansion mismatch problem caused by high-temperature welding, reduce process complexity and cost, and improve product reliability. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a high-frequency power amplifier, comprising a heat sink material, an insulating layer, a lead frame, passive components, a cover, and a chip. The heat sink material is made of CPC, CMC, CWC, or C-diamond; the insulating layer is made of ceramic; the lead frame is made of Kovar alloy; and the cover is made of metal or ceramic. At least one layer is bonded between the heat sink material and the insulating layer, between the insulating layer and the lead frame, and between the lead frame and the cover using B-grade adhesive or epoxy resin. The chip is made of silicon, gallium nitride, or gallium arsenide and is connected to the heat sink material via sintered silver or nano-silver paste containing metallic components. It is also bonded to the lead frame via metal wire bonding or connected to the lead frame via passive components. The adhesive forms a flexible connection interface in the encapsulation structure to achieve efficient heat conduction and reduce structural stress caused by temperature differences.

[0005] Preferably, the thermal conductivity λ of the heat sink material is not less than 150 W / (m·K), and the rate of change of the coefficient of thermal expansion α1 within the temperature range of 25℃ to 150℃ does not exceed 5%; the absolute value of the difference between the coefficient of thermal expansion α2 of the insulating layer and the coefficient of thermal expansion α1 of the heat sink material is not greater than 3 × 10⁻⁶. -6 / ℃, and the absolute value of the difference between the coefficient of thermal expansion α3 of the lead frame and the coefficient of thermal expansion is no greater than 2×10. -6 / ℃.

[0006] Preferably, the elastic modulus E of the cured adhesive is in the range of 1 GPa to 5 GPa, the thermal conductivity λg is 0.5 W / (m·K) to 2.5 W / (m·K), the adhesive layer thickness t_g is controlled between 50 μm and 150 μm, and the curing shrinkage rate does not exceed 1.5%; the contact thermal resistance Rth between the chip and the heat sink material is not greater than 0.5 °C / W, the metal wire bonding length L does not exceed 4.5 mm, and the metal wire diameter d is 25 μm to 50 μm.

[0007] According to claim 3, the high-frequency power amplifier is characterized in that the passive component is a capacitor, which is integrated into the lead frame by surface mount technology, and its equivalent series resistance ESR is not greater than 50mΩ and its equivalent series inductance ESL is not greater than 1nH; the packaging structure adopts a gradient material combination and layered curing process, and the material of each layer is offset by the elastic buffer of the adhesive layer to offset the mechanical deformation caused by temperature changes, so as to ensure structural stability.

[0008] Preferably, the thermal conductivity η of the encapsulation structure is calculated using the following formula: ; Where Q is the actual thermal conductivity, Q0 is the theoretical thermal conductivity, λg is the thermal conductivity of the adhesive, A is the thermal conductivity contact area, h is the heat dissipation coefficient of the packaging structure, ΔT is the temperature difference between the heat sink material and the environment, Rc is the contact thermal resistance between the chip and the heat sink material, Rint is the interface thermal resistance between the insulating layer and the lead frame, and Rg is the thermal resistance of the adhesive layer.

[0009] Preferably, the contact resistance Rc between the chip and the lead frame or passive component is calculated using the following formula: ; Where ρ is the resistivity of the metal wire material, F is the bonding pressure, r is the radius of the metal wire, E' is the comprehensive elastic modulus, ρc is the surface resistivity of the contact interface, t is the oxide layer thickness, and Ac is the actual contact area.

[0010] Preferably, the thermal stress σ of the packaging structure under temperature cycling conditions is calculated using the following formula: ; Where E1 is the elastic modulus of the heat sink material, E2 is the elastic modulus of the insulating layer material, α1 is the thermal expansion coefficient of the heat sink material, α2 is the thermal expansion coefficient of the insulating layer material, ΔT is the temperature change, and ν is the Poisson's ratio of the material.

[0011] A manufacturing process for a high-frequency power amplifier, applied to any of the high-frequency power amplifiers described above, comprising: Heat sink materials, insulation layers, lead frames, passive components, and caps are selected, and the surfaces of each component are subjected to plasma cleaning treatment. Apply B-grade adhesive or epoxy resin to the interface between the heat sink material and the insulation layer, or between the insulation layer and the lead frame, or between the lead frame and the cap, with the adhesive layer thickness controlled between 50μm and 150μm. The chip is sintered onto the heat sink material using sintered silver or nano silver paste, with the sintering temperature controlled between 200°C and 300°C and the sintering pressure less than or equal to 5MPa. Thermo-ultrasonic bonding process is used to connect metal wires to lead frames or passive components, with bonding temperature of 150℃ to 250℃, bonding pressure of 50g to 200g, and ultrasonic power of 5W to 30W. A layered curing process is carried out, with the curing temperature increasing from 80℃ to 150℃ at a rate of 2℃ / min to 5℃ / min, and then held at that temperature for 2 to 4 hours to ensure that the thermal expansion characteristics of each layer of material are compatible.

[0012] In a further preferred embodiment, in the layered curing process, the temperature is maintained at 80℃ to 120℃ for 1 to 2 hours, and then the temperature is raised to 150℃ and maintained for 1 to 2 hours; the interfacial thermal resistance Rint between the heat sink material and the insulating layer is controlled at 0.2℃ / W to 0.4℃ / W through material gradient matching, and the interfacial thermal resistance between the insulating layer and the lead frame is controlled at 0.3℃ / W to 0.5℃ / W through adhesive layer thickness optimization.

[0013] More preferably, the arc height after wire bonding is controlled at 1.2 to 1.5 times the height of the lead frame, and the bonding point offset does not exceed 50% of the wire diameter; in the temperature cycling test from -40℃ to 125℃, the thermal stress σ of the package structure does not exceed 30% of the material yield strength, the thermal resistance increase does not exceed 15% after 1000 cycles, and the contact resistance increase does not exceed 10%.

[0014] Technical effects: This invention replaces some high-temperature welding processes with adhesive bonding, creating a flexible connection interface. This solves the problems of cracking, warping, and packaging failure caused by mismatched thermal expansion coefficients of materials due to high-temperature welding in existing technologies. Simultaneously, it reduces process complexity and cost, and improves yield. The chip and heat sink material are still connected by metal, ensuring effective heat dissipation. This solution uses the elastic buffer of the adhesive to reduce structural stress caused by temperature differences, improving the mechanical stability of the packaging structure and the long-term reliability of the product. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a high-frequency power amplifier and a block diagram of the high-frequency power amplifier of this application; Figure 2 This is a flowchart of the high-frequency power amplifier and the high-frequency power amplifier of this application. Detailed Implementation

[0017] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0018] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, operations, elements, components and / or collections thereof.

[0019] Please see Figure 1 and Figure 2 In the existing technology, high-frequency power amplifiers adopt a full welding process, which has problems such as high requirements for multi-layer welding process, low yield rate, large contact resistance and serious heat generation in multi-level interconnection structure, cracks caused by thermal expansion coefficient mismatch due to high temperature welding, packaging failure, and high cost of gold and tin welding. Based on this, this embodiment provides a high-frequency power amplifier, including a heat sink material, an insulating layer, a lead frame, a cover, and a chip. The heat sink material is made of CPC, CMC, CWC, or C diamond; the insulating layer is made of ceramic; the lead frame is made of Kovar alloy; the passive components are ceramic capacitors; and the cover is made of metal or ceramic. At least one layer between the heat sink material and the insulating layer, between the insulating layer and the lead frame, and between the lead frame and the cover is bonded by B-grade adhesive or epoxy resin. The chip is made of silicon, gallium nitride, or gallium arsenide and is connected to the heat sink material by sintered silver or nano-silver paste containing metal components, and is bonded to the lead frame by metal wire bonding or connected to the lead frame via passive components. The adhesive forms a flexible connection interface in the encapsulation structure to achieve efficient heat conduction and reduce structural stress caused by temperature differences.

[0020] This solution reduces process complexity and the extremely high requirements for temperature control by replacing part of the high-temperature welding process with adhesive. It also reduces the strict surface treatment control issues caused by multi-layer welding, and improves redundancy and yield. By constructing a flexible connection interface, it ensures efficient heat conduction and significantly reduces structural stress caused by temperature differences. It avoids problems such as microcracks and warping packaging failures caused by the mismatch of thermal expansion coefficients of ceramic / heat sink metals due to high-temperature welding. The chip and heat sink material are still connected by metal, which ensures heat dissipation and reduces raw material and equipment costs compared to gold-tin welding.

[0021] In existing technologies, high-temperature welding can cause a mismatch in the thermal expansion coefficients of ceramic and heat sink metal, resulting in microcracks and even warping and packaging failure, which affects product reliability and service life.

[0022] Based on this, the thermal conductivity λ of the heat sink material is not less than 150 W / (m·K), and the rate of change of the coefficient of thermal expansion α1 within the temperature range of 25℃ to 150℃ does not exceed 5%; the absolute value of the difference between the coefficient of thermal expansion α2 of the insulating layer and the coefficient of thermal expansion α1 of the heat sink material is not greater than 3 × 10⁻⁶. -6 / ℃, and the absolute value of the difference between the coefficient of thermal expansion α3 of the lead frame and the coefficient of thermal expansion is no greater than 2×10. -6 / ℃.

[0023] This solution achieves mutual adaptation of the thermal expansion characteristics of each layer of materials in the packaging structure by limiting the rate of change of the thermal conductivity and coefficient of thermal expansion of the heat sink material, and controlling the difference in the coefficients of thermal expansion between the insulating layer, the heat sink material, and the lead frame. High thermal conductivity ensures effective heat conduction, while precise matching of the coefficients of thermal expansion reduces material deformation differences caused by temperature changes. Utilizing the synergistic properties of the materials themselves further reduces mechanical deformation caused by temperature changes, ensuring the stability of the overall structure and effectively avoiding problems such as cracking and warping due to thermal expansion mismatch, thus improving the long-term reliability of the product.

[0024] In existing technologies, the performance of adhesives after curing is unstable, which affects the thermal conduction and mechanical stability of the packaging structure. The contact thermal resistance between the chip and the heat sink material is large, and unreasonable metal wire bonding parameters lead to increased contact resistance and severe heat generation, affecting the device's operating status and lifespan.

[0025] Based on this, the elastic modulus E of the cured adhesive is in the range of 1 GPa to 5 GPa, the thermal conductivity λg is 0.5 W / (m·K) to 2.5 W / (m·K), the adhesive layer thickness t_g is controlled between 50 μm and 150 μm, and the curing shrinkage rate does not exceed 1.5%; the contact thermal resistance Rth between the chip and the heat sink material is not greater than 0.5 °C / W, the metal wire bonding length L does not exceed 4.5 mm, and the metal wire diameter d is 25 μm to 50 μm.

[0026] This solution precisely controls the elastic modulus, thermal conductivity, thickness, and curing shrinkage of the adhesive after curing. This allows the adhesive layer to act as a good elastic buffer within the encapsulation structure, offsetting mechanical deformation caused by temperature changes, while also ensuring efficient heat conduction. Reduced contact thermal resistance decreases heat transfer losses between the chip and the heat sink material. Optimization of the wire bonding length and diameter shortens the current conduction path, reduces contact resistance, and minimizes unplanned heat generation, thereby ensuring stable overall device operation and extending device lifespan.

[0027] In existing technologies, the multi-level interconnection structure of chips / capacitors / lead frames increases contact resistance, leading to unplanned heating, affecting the overall working condition and lifespan, and causing severe electromagnetic interference in high-frequency applications.

[0028] Based on this, the passive component is a capacitor, which is integrated into the lead frame through surface mount technology. Its equivalent series resistance (ESR) is no greater than 50mΩ and its equivalent series inductance (ESL) is no greater than 1nH. The packaging structure adopts a gradient material combination and a layered curing process. Each layer of material is offset by the elastic buffer of the adhesive layer to counteract the mechanical deformation caused by temperature changes, ensuring structural stability.

[0029] This solution integrates passive component capacitors into the leadframe using a surface mount process, limiting their equivalent series resistance and inductance. This shortens the connection path between the chip and the leadframe, reduces contact resistance, and decreases heat generation. Simultaneously, the low equivalent series inductance effectively reduces electromagnetic interference in high-frequency applications. The use of gradient material combinations and layered curing processes further adapts the thermal expansion characteristics of each layer to each other. The elastic buffering effect of the adhesive layers more effectively offsets mechanical deformation caused by temperature changes, further ensuring the stability of the package structure and improving the reliability and stability of the product in high-frequency operating environments. Existing technologies cannot accurately assess the thermal conductivity of packaging structures, making it difficult to optimize thermal conduction paths, resulting in poor heat dissipation and affecting device performance and lifespan.

[0030] Based on this, the thermal conductivity η of the encapsulation structure is calculated using the following formula: ; Where Q is the actual thermal conductivity, Q0 is the theoretical thermal conductivity, λg is the thermal conductivity of the adhesive, A is the thermal conductivity contact area, h is the heat dissipation coefficient of the packaging structure, ΔT is the temperature difference between the heat sink material and the environment, Rc is the contact thermal resistance between the chip and the heat sink material, Rint is the interface thermal resistance between the insulating layer and the lead frame, and Rg is the thermal resistance of the adhesive layer.

[0031] This formula is used to calculate the thermal conductivity efficiency of a high-frequency power amplifier package structure. It quantifies the heat dissipation capability of the package structure by comparing the actual thermal conductivity to the theoretical thermal conductivity. Thermal conductivity efficiency is a key indicator of whether a package structure can effectively dissipate the heat generated by the chip, directly affecting the device's operating temperature and performance stability.

[0032] η (thermal conductivity efficiency): This represents the ratio of the actual thermal conductivity Q of the package structure to the theoretical thermal conductivity Q0, reflecting the package structure's ability to conduct heat. A higher η value indicates more efficient heat conduction and better heat dissipation of the device.

[0033] Q Actual thermal conductivity: refers to the heat conducted from the chip to the environment through heat sink materials, insulating layers, and other components in the actual package structure. It is affected by various factors, such as the thermal conductivity of the materials, contact area, and thermal resistance.

[0034] Q0 theoretical thermal conductivity: This is the amount of heat that the encapsulation structure should be able to conduct under ideal conditions, without considering any thermal resistance loss. It serves as a benchmark for comparison with actual thermal conductivity, thus determining the thermal conductivity efficiency.

[0035] λg, the thermal conductivity of the adhesive: As a material that replaces part of the soldering process in the encapsulation structure, the thermal conductivity of the adhesive directly affects heat conduction. The larger λg is, the stronger the adhesive's ability to conduct heat, which helps to improve the overall heat conduction efficiency. In this formula, λg is multiplied by the heat conduction contact area A, reflecting the role of the adhesive in the heat conduction path.

[0036] A. Thermal conductivity contact area: The larger the thermal conductivity contact area, the wider the heat conduction path, and the more heat is conducted. Increasing the contact area can improve thermal conductivity efficiency, but in actual packaging, limitations such as structural dimensions need to be considered.

[0037] h represents the thermal conductivity of a package structure, indicating its ability to exchange heat with the environment. A larger h value indicates a faster rate of heat dissipation from the package structure to the environment, which helps reduce device temperature. It is influenced by factors such as the shape and surface treatment of the package structure.

[0038] ΔT: Temperature difference between the heat sink material and the environment: The temperature difference between the heat sink material and the environment is the driving force for heat conduction. The greater the temperature difference, the stronger the tendency for heat conduction. However, an excessively large temperature difference may lead to increased thermal stress, affecting the stability of the packaging structure.

[0039] Rc (Reduced Contact Resistance): The contact thermal resistance between the chip and the heat sink material hinders heat conduction. The larger the Rc, the more heat is lost at the contact interface, and the lower the heat conduction efficiency. Rc can be reduced by optimizing the connection process between the chip and the heat sink material, such as using sintered silver or nano-silver paste containing metallic components.

[0040] Rint (Rear Intensity) is a key factor affecting thermal conductivity. By using a gradient material combination and a layered curing process to match the thermal expansion characteristics of the insulation layer and the lead frame, rint can be reduced.

[0041] Thermal resistance of the Rg adhesive layer: The thermal resistance of the adhesive layer is related to factors such as the thermal conductivity and thickness of the adhesive. Adhesive layer thickness t g By controlling the Rg within a suitable range of 50μm to 150μm, a reasonable level can be maintained, thus not significantly affecting the heat transfer efficiency. (In the formula...) This reflects the relationship between the thermal resistance of the chip and the heat sink material and the thermal resistance of the interface between the insulating layer and the lead frame, relative to the thermal resistance of the adhesive layer. The larger the value, the greater the impact of the thermal resistance of the former two on the heat conduction efficiency.

[0042] This formula provides a quantitative evaluation method for the thermal conductivity efficiency of packaging structures. By clearly defining each parameter, it enables accurate analysis of factors affecting thermal conductivity efficiency. Parameters such as adhesive thermal conductivity, thermal conductivity contact area, and packaging structure heat dissipation coefficient can be optimized in a targeted manner to reduce contact thermal resistance and interface thermal resistance, thereby improving the thermal conductivity efficiency of the packaging structure, optimizing heat dissipation paths, ensuring efficient heat conduction, reducing device temperature, and improving device performance and lifespan. This provides a scientific theoretical basis for the design and optimization of packaging structures.

[0043] Existing technologies cannot accurately calculate the contact resistance between the chip and the lead frame or passive components, making it difficult to optimize connection parameters. This results in high contact resistance, severe heat generation, and affects the device's operating status.

[0044] Based on this, the contact resistance Rc between the chip and the lead frame or passive component is calculated using the following formula: Where ρ is the resistivity of the metal wire material, F is the bonding pressure, r is the radius of the metal wire, E' is the comprehensive elastic modulus, ρc is the surface resistivity of the contact interface, t is the oxide layer thickness, and Ac is the actual contact area.

[0045] This formula is used to calculate the contact resistance between the chip and the lead frame or passive components. Contact resistance is a crucial factor affecting the conductivity and heat generation of a device. Accurately calculating contact resistance helps optimize connection processes and parameters, reduce resistance, decrease heat generation, and improve device stability and lifespan.

[0046] Rc contact resistance: refers to the resistance generated by the conductive contact between the chip and the lead frame or passive component. The smaller Rc is, the less energy is lost when current flows, the less heat is generated in the device, and the more stable the operation.

[0047] ρ (Resistivity of Metal Wire Material): As a conductor connecting chips to lead frames or passive components, the resistivity of the metal wire directly determines the resistance. The smaller the ρ, the better the conductivity of the metal wire and the lower the contact resistance. When selecting metal wire materials, materials with low resistivity, such as gold and silver, should be given priority.

[0048] Bonding pressure (F): Bonding pressure is a crucial parameter in thermo-ultrasonic bonding processes. Appropriate bonding pressure ensures tight contact between the metal wire and the chip or leadframe surface, reducing gaps at the contact interface and thus lowering contact resistance. However, excessive pressure may damage the chip or metal wire, while insufficient pressure results in weak contact and increased resistance.

[0049] The radius of the metal wire affects the contact area and mechanical strength. A larger radius results in a larger contact area and lower contact resistance, but it also increases the cost and manufacturing complexity of the metal wire. A balance needs to be struck between contact resistance, cost, and manufacturing process, aiming to control the metal wire diameter d within the range of 25μm to 50μm.

[0050] E' Composite Elastic Modulus: The composite elastic modulus reflects the elastic properties of the metal wire and the contact material. It is related to the material's elastic modulus and Poisson's ratio. The larger the composite elastic modulus, the smaller the deformation of the material under bonding stress, the higher the stability of the contact interface, and the more stable the contact resistance.

[0051] This section illustrates the influence of the resistivity of the wire material, bonding pressure, wire radius, and combined elastic modulus on the contact resistance. When the bonding pressure F increases, the wire radius r increases, or the combined elastic modulus E' decreases, the denominator increases, the value of this section decreases, and the contact resistance Rc decreases.

[0052] ρc, the surface resistivity of the contact interface, affects the contact resistance. A higher surface resistivity ρc indicates poorer conductivity and higher contact resistance. Cleaning the contact surface, such as with plasma cleaning, can reduce surface resistivity and thus contact resistance.

[0053] Oxide layer thickness (t): The oxide layer on the contact interface increases resistance. The thicker the oxide layer (t), the greater the contact resistance. In the bonding process, oxide layer formation should be minimized, such as by controlling the oxygen content of the bonding environment and shortening the bonding time.

[0054] Actual contact area (AC): The actual contact area refers to the area where the metal wire actually contacts the surface of the chip or lead frame, not the geometric contact area. A larger actual contact area results in lower contact resistance. By optimizing bonding process parameters, such as bonding temperature, pressure, and ultrasonic power, the actual contact area can be increased, and the contact resistance reduced.

[0055] This section reflects the influence of the surface resistivity of the contact interface, the oxide layer thickness, and the actual contact area on the contact resistance. When the surface resistivity ρc of the contact interface decreases, the oxide layer thickness t decreases, or the actual contact area Ac increases, the value of this section decreases, and the contact resistance Rc decreases.

[0056] This formula clarifies the relationship between contact resistance and parameters such as the resistivity of the metal wire material, bonding pressure, metal wire radius, overall elastic modulus, surface resistivity of the contact interface, oxide layer thickness, and actual contact area, providing a method for accurately calculating contact resistance. Through this formula, the influence of each parameter on contact resistance can be clearly understood, allowing for targeted optimization of process parameters such as bonding pressure and metal wire radius, selection of appropriate metal wire materials, reduction of surface resistivity and oxide layer thickness at the contact interface, increase of actual contact area, reduction of contact resistance, reduction of heat generation, and ensuring stable device operation. This provides important theoretical guidance for the connection design and process optimization of chips and leadframes or passive components.

[0057] Existing technologies cannot accurately calculate the thermal stress of the packaging structure under temperature cycling conditions, making it difficult to assess structural stability and thus failing to effectively solve the problems of cracks and warping caused by thermal stress.

[0058] Based on this, the thermal stress σ of the encapsulation structure under temperature cycling conditions is calculated using the following formula: ; Where E1 is the elastic modulus of the heat sink material, E2 is the elastic modulus of the insulating layer material, α1 is the thermal expansion coefficient of the heat sink material, α2 is the thermal expansion coefficient of the insulating layer material, ΔT is the temperature change, and ν is the Poisson's ratio of the material.

[0059] This formula is used to calculate the thermal stress of a high-frequency power amplifier package structure under temperature cycling conditions. Thermal stress is the stress generated when the thermal expansion coefficients of the materials in each layer of the package structure change with temperature. Accurate calculation of thermal stress helps to assess the mechanical stability of the package structure, avoid problems such as cracks and warping caused by excessive thermal stress, and improve product reliability and service life.

[0060] σ thermal stress: This represents the stress generated by the packaging structure due to thermal expansion mismatch during temperature cycling. The larger the σ value, the greater the mechanical stress on the packaging structure, and the more prone it is to failure phenomena such as cracking and warping.

[0061] E1, the elastic modulus of a heat sink material, is an indicator that measures a material's ability to resist elastic deformation. The larger the elastic modulus E1 of a heat sink material, the smaller the deformation of the material under the same thermal stress. However, it will also generate a larger reaction force on other materials, increasing the thermal stress.

[0062] E2 Elastic Modulus of Insulation Layer Material: The elastic modulus E2 of the insulation layer material also affects the magnitude of thermal stress. The relative magnitudes of E2 and E1 determine the distribution of thermal stress between the heat sink material and the insulation layer.

[0063] α1, the coefficient of thermal expansion of a heat sink material: The coefficient of thermal expansion α1 of a heat sink material indicates the degree of expansion or contraction when the temperature changes. The larger α1 is, the greater the deformation of the heat sink material when the temperature changes.

[0064] The difference between the thermal expansion coefficients α2 and α1 of the insulation layer material is the fundamental cause of thermal stress. When the difference between α1 and α2 is large, temperature changes will cause a large difference in deformation between the heat sink material and the insulation layer, thus generating thermal stress.

[0065] Temperature change ΔT: The temperature change ΔT is the driving force for thermal stress. The larger the ΔT, the greater the difference in deformation between the heat sink material and the insulation layer, and the greater the thermal stress. In temperature cycling tests, a temperature range of -40℃ to 125℃ will generate significant thermal stress, requiring material selection and process design to reduce thermal stress.

[0066] This section contains the main formulas for calculating thermal stress, reflecting the influence of the difference in elastic modulus and thermal expansion coefficient between the heat sink material and the insulation layer, as well as the amount of temperature change, on thermal stress. As E1 and E2 increase... When the value of this part increases or ΔT increases, the thermal stress σ increases. This can be mitigated by selecting heat sink materials and insulation layers with similar coefficients of thermal expansion, such as ensuring the absolute value of the difference between α1 and α2 is no greater than 3 × 10⁻⁶. -6 / ℃ can reduce thermal stress.

[0067] ν Poisson's ratio: Poisson's ratio is the ratio of transverse strain to longitudinal strain in a material. It reflects the transverse deformation characteristics of a material under stress. In the formula, Poisson's ratio is a correction factor used to account for the deformation of materials under three-dimensional stress. Different materials have different Poisson's ratios; generally, the Poisson's ratio for metals is between 0.25 and 0.35, while that for ceramics is between 0.1 and 0.2. Considering the influence of Poisson's ratio makes the calculation of thermal stress more accurate. This formula shows that thermal stress is directly proportional to the difference in elastic modulus and coefficient of thermal expansion between the heat sink material and the insulating layer, and to the amount of temperature change, and inversely proportional to the material's Poisson's ratio. Therefore, in packaging structure design, materials with similar coefficients of thermal expansion should be selected as much as possible to reduce temperature changes, or thermal stress should be reduced through process design, such as using flexible connection interfaces and gradient material combinations, to ensure the mechanical stability of the packaging structure under extreme temperature cycling conditions.

[0068] This formula establishes a mathematical relationship between the thermal stress of the packaging structure and the elastic modulus, coefficient of thermal expansion, temperature change, and Poisson's ratio of the heat sink and insulating materials. It can accurately calculate the thermal stress borne by the packaging structure under temperature cycling conditions. This formula allows for the analysis of the impact of different material combinations and temperature changes on thermal stress, enabling the selection of appropriate materials and structural optimization during the design phase. This reduces thermal stress, improves the mechanical stability of the packaging structure under extreme temperature cycling conditions, effectively avoids cracks and warping caused by thermal stress, and enhances product reliability and lifespan. It provides crucial theoretical support for the thermal stress-resistant design of packaging structures.

[0069] Existing technologies involve complex manufacturing processes with extremely high requirements for surface treatment and temperature control, resulting in low yield rates, high packaging costs, and an inability to effectively solve problems such as thermal expansion mismatch and high contact resistance.

[0070] Based on this, the manufacturing process of the high-frequency power amplifier includes the following steps: selecting heat sink material, insulating layer, lead frame, and cap, and performing plasma cleaning treatment on the surface of each component; applying B-grade adhesive or epoxy resin adhesive to the interface between the heat sink material and the insulating layer, or between the insulating layer and the lead frame, or between the lead frame and the cap, with the adhesive layer thickness controlled between 50μm and 150μm; sintering the chip to the heat sink material using sintered silver or nano-silver paste, with the sintering temperature controlled between 200℃ and 300℃ and the sintering pressure less than or equal to 5MPa; using thermo-ultrasonic bonding technology to connect the chip to the lead frame or passive components with metal wires, with a bonding temperature of 150℃ to 250℃, a bonding pressure of 50g to 200g, and an ultrasonic power of 5W to 30W; performing a layered curing process, with the curing temperature increasing from 80℃ to 150℃ at a rate of 2℃ / min to 5℃ / min, and holding for 2h to 4h to adapt the thermal expansion characteristics of each layer of material.

[0071] This manufacturing process enhances the cleanliness and activity of component surfaces through plasma cleaning, ensuring excellent adhesion between the adhesive and the component surfaces. Precise control of the adhesive layer thickness guarantees its elastic cushioning and thermal conductivity. Optimized chip sintering temperature and pressure settings ensure a strong bond between the chip and the heat sink material while avoiding the negative impact of high temperatures on material properties. Optimized thermo-ultrasonic bonding process parameters reduce contact resistance in wire bonding. The layered curing process, through gradual temperature increases, ensures that the thermal expansion characteristics of each layer are compatible, reducing internal stress during curing and lowering the risk of cracks and warping due to thermal expansion mismatch. Overall, the process reduces the stringent requirements for temperature control, simplifies process complexity, improves yield, and lowers packaging costs, while effectively solving problems such as thermal expansion mismatch and high contact resistance, ensuring product performance and reliability.

[0072] The existing layered curing process parameters are unreasonable, resulting in poor matching of the thermal expansion characteristics of each layer material, high interfacial thermal resistance, and affecting the stability of the encapsulation structure and thermal conduction efficiency.

[0073] Based on this, in the layered curing process, the temperature is maintained at 80℃ to 120℃ for 1 to 2 hours, and then the temperature is raised to 150℃ and maintained for 1 to 2 hours; the interfacial thermal resistance Rint between the heat sink material and the insulating layer is controlled at 0.2℃ / W to 0.4℃ / W through material gradient matching, and the interfacial thermal resistance between the insulating layer and the lead frame is controlled at 0.3℃ / W to 0.5℃ / W through adhesive layer thickness optimization.

[0074] This solution incorporates a heat preservation step between 80°C and 120°C in the layered curing process, allowing the adhesive to partially cure at a lower temperature. This reduces stress accumulation during subsequent temperature increases. A subsequent heat preservation step at 150°C ensures complete adhesive curing and further optimizes the thermal expansion characteristics of each layer. Precise control of the thermal resistance at the interfaces between the heat sink material and the insulation layer, and between the insulation layer and the lead frame, through material gradient matching and adhesive layer thickness optimization, reduces thermal resistance along the heat conduction path and improves heat transfer efficiency. This process optimization further enhances the stability of the encapsulation structure, reduces problems caused by thermal expansion mismatch, ensures efficient heat transfer, and improves product performance and reliability.

[0075] In the existing technology, unreasonable wire bonding parameters lead to bonding point offset and improper arc height, which affects contact resistance and device performance. The packaging structure experiences high thermal stress during temperature cycling tests, resulting in a large increase in thermal resistance and contact resistance, and low reliability.

[0076] Based on this, the arc height after the metal wire bonding is controlled at 1.2 to 1.5 times the height of the lead frame, and the bonding point offset does not exceed 50% of the metal wire diameter; in the temperature cycling test from -40℃ to 125℃, the thermal stress σ of the package structure does not exceed 30% of the material yield strength, the thermal resistance increase does not exceed 15% after 1000 cycles, and the contact resistance increase does not exceed 10%.

[0077] This solution ensures the quality of wire bonding by strictly controlling the wire bonding arc height and bonding point offset, reducing the risk of poor contact and wire breakage, lowering contact resistance, and guaranteeing stable electrical performance of the device. The limited increase in thermal stress, thermal resistance, and contact resistance during temperature cycling tests verifies the stability and reliability of the package structure under extreme temperature environments. Thermal stress does not exceed 30% of the material's yield strength, preventing plastic deformation or fracture due to excessive thermal stress. The small increase in thermal resistance and contact resistance after 1000 cycles indicates that the heat dissipation and conductivity of the package structure remain stable during long-term use, effectively improving product lifespan and reliability, and meeting the application requirements of high-reliability industrial and automotive power devices.

[0078] Unless otherwise specified, the equipment components involved in the above embodiments are all conventional equipment components, and the connection methods and control methods involved are all conventional connection methods and control methods unless otherwise specified.

[0079] The present invention has been described in detail above with reference to the embodiments. However, those skilled in the art will understand that, without departing from the spirit of the present invention, various specific parameters in the above embodiments can be changed to form multiple specific embodiments, all of which are common variations of the present invention, and will not be described in detail here.

Claims

1. A high-frequency power amplifier, characterized in that, The package includes a heat sink material, an insulating layer, a lead frame, passive components, a cap, and a chip. The heat sink material is made of CPC, CMC, CWC, or C-diamond. The insulating layer is made of ceramic. The lead frame is made of Kovar alloy. The passive components are ceramic capacitors. The cap is made of metal or ceramic. At least one layer between the heat sink material and the insulating layer, between the insulating layer and the lead frame, and between the lead frame and the cap is bonded using B-grade adhesive or epoxy resin. The chip is made of silicon, gallium nitride, or gallium arsenide and is connected to the heat sink material using sintered silver or nano-silver paste containing metal components. It is also bonded to the lead frame via metal wire bonding or connected to the lead frame via passive components. The adhesive forms a flexible connection interface in the package structure to achieve efficient heat conduction and reduce structural stress caused by temperature differences.

2. The high-frequency power amplifier according to claim 1, characterized in that, The thermal conductivity λ of the heat sink material is not less than 150 W / (m·K), and the rate of change of the coefficient of thermal expansion α1 within the temperature range of 25℃ to 150℃ does not exceed 5%; the absolute value of the difference between the coefficient of thermal expansion α2 of the insulating layer and the coefficient of thermal expansion α1 of the heat sink material is not greater than 3 × 10⁻⁶. -6 / ℃, and the absolute value of the difference between the coefficient of thermal expansion α3 of the lead frame and the coefficient of thermal expansion is no greater than 2×10. -6 / ℃.

3. The high-frequency power amplifier according to claim 1 or 2, characterized in that, The elastic modulus E of the cured adhesive is in the range of 1 GPa to 5 GPa, the thermal conductivity λg is 0.5 W / (m·K) to 2.5 W / (m·K), the adhesive layer thickness t_g is controlled between 50 μm and 150 μm, and the curing shrinkage rate does not exceed 1.5%; the contact thermal resistance Rth between the chip and the heat sink material is not greater than 0.5℃ / W, the metal wire bonding length L does not exceed 4.5 mm, and the metal wire diameter d is 25 μm to 50 μm.

4. The high-frequency power amplifier according to claim 3, characterized in that, The passive component is a capacitor, which is integrated into the lead frame through surface mount technology. Its equivalent series resistance (ESR) is no greater than 50mΩ and its equivalent series inductance (ESL) is no greater than 1nH. The packaging structure adopts a gradient material combination and a layered curing process. Each layer of material is offset by the elastic buffer of the adhesive layer to counteract the mechanical deformation caused by temperature changes, ensuring structural stability.

5. The high-frequency power amplifier according to claim 4, characterized in that, The thermal conductivity η of the encapsulation structure is calculated using the following formula: ； Where Q is the actual thermal conductivity, Q0 is the theoretical thermal conductivity, λg is the thermal conductivity of the adhesive, A is the thermal conductivity contact area, h is the heat dissipation coefficient of the packaging structure, ΔT is the temperature difference between the heat sink material and the environment, Rc is the contact thermal resistance between the chip and the heat sink material, Rint is the interface thermal resistance between the insulating layer and the lead frame, and Rg is the thermal resistance of the adhesive layer.

6. The high-frequency power amplifier according to claim 5, characterized in that, The contact resistance Rc between the chip and the lead frame or passive component is calculated using the following formula: ； Where ρ is the resistivity of the metal wire material, F is the bonding pressure, r is the radius of the metal wire, E' is the comprehensive elastic modulus, ρc is the surface resistivity of the contact interface, t is the oxide layer thickness, and Ac is the actual contact area.

7. The high-frequency power amplifier according to claim 6, characterized in that, The thermal stress σ of the encapsulation structure under temperature cycling conditions is calculated using the following formula: ； Where E1 is the elastic modulus of the heat sink material, E2 is the elastic modulus of the insulating layer material, α1 is the thermal expansion coefficient of the heat sink material, α2 is the thermal expansion coefficient of the insulating layer material, ΔT is the temperature change, and ν is the Poisson's ratio of the material.

8. A manufacturing process for a high-frequency power amplifier, applied to the high-frequency power amplifier as described in any one of claims 1-7, characterized in that, include: Heat sink materials, insulation layers, lead frames, and caps are selected, and the surfaces of each component are subjected to plasma cleaning treatment. Apply B-grade adhesive or epoxy resin to the interface between the heat sink material and the insulation layer, or between the insulation layer and the lead frame, or between the lead frame and the cap, with the adhesive layer thickness controlled between 50μm and 150μm. The chip is sintered onto the heat sink material using sintered silver or nano silver paste, with the sintering temperature controlled between 200°C and 300°C and the sintering pressure less than or equal to 5MPa. Thermo-ultrasonic bonding process is used to connect metal wires to lead frames or passive components, with bonding temperature of 150℃ to 250℃, bonding pressure of 50g to 200g, and ultrasonic power of 5W to 30W. A layered curing process is carried out, with the curing temperature increasing from 80℃ to 150℃ at a rate of 2℃ / min to 5℃ / min, and then held at that temperature for 2 to 4 hours to ensure that the thermal expansion characteristics of each layer of material are compatible.

9. The production process according to claim 8, characterized in that, In the layered curing process, the temperature is maintained at 80℃ to 120℃ for 1 to 2 hours, and then raised to 150℃ and maintained for 1 to 2 hours. The interfacial thermal resistance Rint between the heat sink material and the insulation layer is controlled at 0.2℃ / W to 0.4℃ / W through material gradient matching, and the interfacial thermal resistance between the insulation layer and the lead frame is controlled at 0.3℃ / W to 0.5℃ / W through adhesive layer thickness optimization.

10. The production process according to claim 9, characterized in that, The arc height after wire bonding is controlled to be 1.2 to 1.5 times the height of the lead frame, and the bonding point offset does not exceed 50% of the wire diameter; in the temperature cycling test from -40℃ to 125℃, the thermal stress σ of the package structure does not exceed 30% of the material yield strength, the thermal resistance increase does not exceed 15% after 1000 cycles, and the contact resistance increase does not exceed 10%.

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