Voltage regulation control method and system for power regulator

Abstract

The invention discloses a voltage regulation control method and system for an electric power regulator, and belongs to the technical field of voltage regulation, and the method specifically comprises the steps: collecting parameters of a power grid side and a load side, including current and voltage, building an operation model of the electric power regulator based on parameter identification, and according to the operation model and a target output voltage, calculating the voltage of the electric power regulator. The method comprises the following steps: calculating to obtain a reference voltage sequence in combination with electric energy quality and efficiency constraints, monitoring the states of a power grid and a load in real time, projecting the reference voltage sequence to a safe operation envelope when voltage fluctuation or abnormity is detected, performing hierarchical derating control, generating a regulation signal of the power regulator based on the corrected reference voltage sequence, and outputting the regulation signal of the power regulator. The operation model of the power regulator is calibrated through real-time feedback; the power quality and efficiency can be considered under the normal working condition, stable voltage control can be kept during power grid fluctuation, frequency deviation or load sudden change, and resource waste caused by single shutdown or extensive derating is avoided.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of voltage regulation, and particularly relates to a voltage regulation control method and system for a power regulator. BACKGROUND

[0002] As a core device of power conversion and voltage regulation, the power regulator is widely used in industrial power supply, smart grid, rail transit, new energy grid connection and precision electronic equipment power supply fields. Its main function is to regulate and stabilize the voltage between the power grid and the load to meet the demand of industrial equipment, precision instruments, data centers and new energy grid connection systems for power quality. The existing power regulator mainly uses power devices such as thyristor, IGBT or MOSFET to realize voltage regulation through phase control, pulse width modulation or tap switching.

[0003] Traditional power regulators usually rely on thyristor rectification, phase shift control or pulse width modulation technology to realize voltage regulation by changing the conduction angle, duty cycle or tap position. However, with the increasing complexity of power systems and the diversity of loads, the existing voltage regulation methods have the following problems: the uncertainty and complexity of the power grid environment make it difficult to cope with abnormal conditions and the regulation and control ability is insufficient. SUMMARY

[0004] In view of the deficiencies of the prior art, the application provides a voltage regulation control method and system for a power regulator, which realizes multi-dimensional constraint management, abnormal condition projection and hierarchical de-rating control, and has a new type of voltage regulation control method with self-learning and self-calibration capability to improve the adaptability and stability of the power regulator in dynamic environment.

[0005] To achieve the above purpose, the application provides the following technical solutions: A voltage regulation control method for a power regulator, comprising: Collecting parameters of the power grid side and the load side, including current and voltage, and establishing an operation model of the power regulator based on parameter identification; According to the operation model and the target output voltage, the reference voltage sequence is calculated in combination with power quality and efficiency constraints; Real-time monitoring of the power grid and load state, when voltage fluctuation or abnormality is detected, the reference voltage sequence is projected to the safe operation envelope, and hierarchical de-rating control is performed; Based on the corrected reference voltage sequence, the power regulator control signal is generated, and the operation model of the power regulator is calibrated through real-time feedback.

[0006] Specifically, the collection of parameters of the power grid side and the load side, including current and voltage, and the establishment of the operation model of the power regulator based on parameter identification, comprises: Setting a reference phase at the grid side and triggering the first sampling period, the voltage and current signals are divided into original data frames; Introducing a timing disturbance in the original data frames, and synchronously collecting the multi-dimensional operating quantities of the grid and the load within multiple sampling periods to form a sequence data set with disturbance markers; Segmenting and cross-screening the sequence data set, and removing fragments that do not meet the timing consistency to obtain candidate data for identification; Based on the candidate data, a multi-dimensional parameter mapping relationship is established, and the grid equivalent parameters and the load equivalent parameters are projected to a unified power regulator operating model through progressive iteration.

[0007] Specifically, according to the operating model and the target output voltage, the reference voltage sequence is calculated by combining power quality and efficiency constraints, including: In the prediction time window, the state quantity of the operating model and the target output voltage are obtained, the power quality and efficiency constraints are analyzed, and they are divided into time domain, frequency domain and energy three types of constraints, and the corresponding weight scheduling table and scene label are generated; According to the operating model and the weight scheduling table, a discrete reference trajectory set is constructed, the voltage amplitude and phase sequence in each discrete reference trajectory are obtained, and a modulation space index is established based on the voltage amplitude and phase sequence; Based on the modulation space index, the discrete reference trajectory is subjected to constraint consistency test, and the constraint inconsistent fragments are subjected to segment clipping and fragment replacement to obtain a feasible solution set, and the constraint consistency test includes time domain boundary, frequency band occupation, energy balance and sparsity constraint; Based on the scene label, the feasible solution set is sorted and selected according to the preset priority, and all solutions are quantized, amplitude limited and zero-crossing aligned under the modulation clock to obtain the reference voltage sequence.

[0008] Specifically, the constraint consistency test of the discrete reference trajectory based on the modulation space index, the constraint inconsistent fragments are subjected to segment clipping and fragment replacement to obtain a feasible solution set, including: The discrete reference trajectory is subjected to segmentation processing in the preset test window, and the time tag, frequency spectrum fingerprint and modulation space index are written for each segment to form a test segment sequence; The test segment sequence is subjected to sequential test, and the segments that do not meet the preset constraints are marked to generate a time domain inconsistency list; The segments in the test segment sequence that meet the preset constraints are subjected to joint test of frequency band occupation and energy balance, the segments that conflict with the disabled frequency band table or the energy quota table are added to the time domain inconsistency list, and a clipping instruction is generated for each conflict; The sparsity of the segment without conflict after joint verification is determined, the boundary of the dense area and the sparse area is located, the segment falling into the forbidden area is added to the inconsistency list, and the replacement instruction and the splicing anchor point are generated; According to the cutting instruction and the replacement instruction, the inconsistent segment is segmented and cut at the splicing anchor point thereof, and the replacement segment is selected from the preset candidate segment library according to the modulation space index to complete the splicing check, and a feasible solution set satisfying the time domain boundary, frequency band occupation, energy balance and sparsity constraint is output.

[0009] Specifically, the feasible solution set is sorted and selected according to a preset priority based on the scene label, and all solutions are quantized, amplitude-limited and zero-crossing aligned under the modulation space index to obtain a reference voltage sequence, including: The sorting rule is set for each feasible solution in the feasible solution set based on the scene label, and a priority sequence is formed; At the modulation clock trigger point, the solution with the highest priority in the priority sequence is selected as the main solution; The discrete reference trajectory of the main solution is quantized in amplitude and phase under the modulation clock to obtain a preliminary quantized trajectory of the main solution; The preliminary quantized trajectory of the main solution is compared point by point with the amplitude limit constraint and the energy boundary, and the segment that does not meet the condition is marked and the standby candidate solution is called for local replacement to generate a modified trajectory; Alignment anchors are set in the zero-crossing interval of the modified trajectory, and the sampling points in the neighborhood of the alignment anchors are shifted and spliced to check, and finally a continuous reference voltage sequence satisfying the constraint condition is output.

[0010] Specifically, the power grid and load state are monitored in real time, and when voltage fluctuation or abnormality is detected, the reference voltage sequence is projected into a safe operation envelope, and hierarchical de-rating control is performed, including: Under the synchronous reference, the state quantities of the power grid side and the load side are collected to generate a continuous state vector stream, and a scene label and an event counter are written for each sampling period; A preset abnormal mode library is used to compare the state vector stream in a sliding window, output abnormal event records according to the abnormal mode library, and generate abnormal event levels according to the influence domain and duration of the abnormal event records; A safe operation envelope is constructed based on the operation model of the power regulator and the preset constraint, the safe operation envelope is discretized into a multi-level boundary set, and priority rules and start-stop conditions are configured for each level of boundary; In the projection window corresponding to the event level, the reference voltage sequence is sequentially compressed in amplitude, rearranged in phase and remapped in frequency band according to the priority rules, and segment replacement is completed at the zero-crossing anchor point to obtain a limited voltage sequence; Determine a derating level according to the limited voltage sequence and the multi-level boundary set, generate a level transition table and a holding time, and update the output control quantity according to the level transition table under a modulated clock.

[0011] Specifically, the amplitude compression, phase rearrangement and band remapping of the reference voltage sequence are sequentially performed according to the priority rules in the projection window corresponding to the event level, and the segment replacement is completed at the zero-crossing anchor point to obtain the limited voltage sequence, including: Receive the projection instruction triggered by the abnormal event level, and select the boundary layer corresponding to the level in the multi-level boundary set in the safe operation envelope; Compress the amplitude interval of the reference voltage sequence in the boundary layer in segments, and write the compressed segments into a mark table; Rearrange the phase order of adjacent segments according to the mark table so as to conform to the phase sequence rules of the boundary layer; Perform band remapping on the rearranged segments to map them to the frequency interval of the boundary layer, and generate splicing anchor points; Splice and check the segments after band remapping with the unmodified segments at the splicing anchor points to obtain a continuous limited voltage sequence.

[0012] Specifically, determine a derating level according to the limited voltage sequence and the multi-level boundary set, generate a level transition table and a holding time, and update the output control quantity according to the transition table under a modulated clock, including: Compare the limited voltage sequence with the multi-level boundary set in segments to generate a boundary hit mark, a determination table of a duration period and a segment position, and determine a candidate derating level set based on the determination table; According to the candidate derating level set and the abnormal event level, select the current derating level and determine its adjacent level to obtain a level relationship set containing entry conditions and release conditions; Build a level transition table on the level relationship set, and configure a holding time for each transition path; Periodically evaluate the current level according to the level transition table and the holding time under a modulated clock, perform level switching at a zero-crossing anchor point when the entry condition is met, and maintain the existing level and update the timing state when the condition is not met; Write the level change result and the timing state back to the event counter and the safe operation envelope, and select the corresponding output control quantity according to the current level.

[0013] A voltage regulation control system for a power regulator is used to implement the voltage regulation control method for the power regulator, and includes a model establishment module, a voltage sequence calculation module, a voltage regulation control module and a feedback adjustment module. The model establishing module is used for collecting parameters of the power grid side and the load side, including current and voltage, and establishing an operation model of the power regulator based on the parameters; The voltage sequence calculating module is used for calculating a reference voltage sequence according to the operation model and a target output voltage, in combination with power quality and efficiency constraints; The voltage regulating control module is used for monitoring the power grid and the load state in real time, projecting the reference voltage sequence to a safe operation envelope when voltage fluctuation or abnormality is detected, and performing hierarchical de-rating control; The feedback adjusting module generates a power regulator regulating signal based on the corrected reference voltage sequence, and calibrates the operation model of the power regulator through real-time feedback.

[0014] Specifically, the voltage regulating control module comprises an abnormal event level generating unit, a limited voltage sequence calculating unit and a voltage regulating control unit. The abnormal event level generating unit is used for collecting state quantities of the power grid side and the load side, analyzing output abnormal event records, and generating an abnormal event level according to the influence domain and duration of the abnormal event records. The limited voltage sequence calculating unit is used for performing amplitude compression, phase rearrangement and frequency band remapping on the reference voltage sequence in turn according to the priority rules in the projection window corresponding to the event level, and completing segment replacement at the zero-crossing anchor point to obtain a limited voltage sequence. The voltage regulating control unit is used for determining a de-rating level, generating a level transition table and a retention time, and updating output control quantities according to the level transition table under a modulation clock.

[0015] Compared with the prior art, the present application has the following advantages: The present application proposes a voltage regulating control method and system for a power regulator, which establishes an online operation model of the power grid and the load, obtains a reference voltage sequence in combination with a target voltage and multi-dimensional constraint conditions, projects the sequence to a safe operation envelope when an abnormality is detected, forms a closed-loop control in cooperation with a hierarchical de-rating and self-calibration mechanism, and realizes dynamic, layered and progressive regulation of voltage. The method can take into account power quality and efficiency under normal working conditions, and can also maintain stable voltage control when the power grid fluctuates, the frequency deviates or the load suddenly changes, thereby avoiding resource waste caused by single shutdown or extensive de-rating. At the same time, the method has continuous online learning and self-adaptive ability, so that the power regulator can maintain long-term reliable operation in complex working conditions, and improves the regulation level and the stability of voltage regulating control. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A voltage regulating control method flowchart for a power regulator is provided in the present application. Figure 2A voltage regulation control system architecture for a power regulator is provided. DETAILED DESCRIPTION

[0017] The present application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the present application, but in no way limit the present application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made. These are all within the scope of protection of the present application.

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0019] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict, and are all within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. In addition, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0020] Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used in the present application are only for the purpose of describing the specific embodiments of the present application, and are not used to limit the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items.

[0021] Embodiment 1 Please refer to Figure 1 An embodiment provided by the present application: a method comprising the following specific steps: Step S1: Collecting parameters of the power grid side and the load side, including current and voltage, and establishing an operation model of the power regulator based on parameter identification.

[0022] The specific steps of step S1 are: Step S101: Setting a reference phase at the power grid side and triggering a first sampling period, and dividing the voltage and current signals into original data frames.

[0023] In the embodiment, zero-crossing detection and phase tracking are performed on the grid-side voltage signal to determine the reference phase point of the grid fundamental wave. Through the reference point, the initial triggering time can be locked in the sampling clock, ensuring that the collection of voltage and current signals is carried out under unified phase conditions, and avoiding sampling errors caused by phase drift. The establishment of the original data frame is not only a simple signal segmentation, but also provides a standardized reference in time and phase for subsequent parameter identification and model construction. By marking the phase zero point at the beginning of each data frame, the timing correspondence between subsequent current, voltage and power information is ensured. Further, a redundant sampling or sliding sampling strategy is introduced when dividing the original data frame, so that there is partial overlap between adjacent data frames. This strategy can enhance the data robustness in the presence of noise interference or grid fluctuations, and ensure the continuity and stability of the reference phase determination in actual operation.

[0024] Step S102: Introduce timing disturbance in the original data frame, and synchronously collect multi-dimensional operating quantities of the grid and the load in multiple sampling periods to form a sequence data set with disturbance labels.

[0025] In the embodiment, a small periodic offset or randomized disturbance is applied to the reference clock within a preset sampling period, so that the sampling points of each data frame show a controllable slight displacement on the time axis. At the same time of introducing the timing disturbance, the voltage, current and related state quantities on the grid side and the load side are synchronously collected in multiple sampling periods. Since the disturbance label is recorded in each data frame, a sequence data set with disturbance labels is formed.

[0026] Step S103: Segment and compare the sequence data set, and cross-screen to remove segments that do not meet the timing consistency to obtain candidate data for identification.

[0027] In the embodiment, the sequence data set is segmented according to the timing disturbance label and the sampling window, so that each segment of data has clear start and end markers and phase correspondence. Then, the adjacent segments are compared to detect whether their timestamps, phase points and disturbance offsets remain consistent. If some segments cause phase drift or time misalignment due to sampling loss, noise interference or abnormal disturbance labels, they are determined as segments that do not meet the timing consistency and are removed. After the above processing, the obtained candidate data has structured timing integrity and mutual correlation.

[0028] Step S104: Establish a multi-dimensional parameter mapping relationship based on the candidate data, and project the grid equivalent parameters and the load equivalent parameters to the unified power regulator operation model through progressive iteration.

[0029] In this embodiment, the voltage, current, phase and disturbance label contained in the candidate data are classified, and a multi-dimensional coordinate system is established according to the time sequence and the disturbance condition. In the coordinate system, the data points of different segments are mapped into corresponding parameter trajectories, which can depict the response characteristics of the power grid side and the load side under different disturbance conditions. Through the mapping relationship, the distribution areas of the power grid equivalent parameters and the load equivalent parameters can be intuitively distinguished in space. It should be noted that the multi-dimensional mapping relationship is not established at one time, but gradually converges through progressive iteration. Specifically, the power grid equivalent parameters and the load equivalent parameters are roughly estimated under the initial conditions, and are projected into the power grid subspace and the load subspace of the operation model respectively. In each iteration, the parameter mapping relationship is updated using new candidate data, and the boundaries and overlapping areas of the two types of parameters are corrected. After multiple rounds of progressive iteration, the projections of the power grid and load parameters gradually approach the stable solution, and finally a consistent parameter set can be formed in the unified power regulator operation model.

[0030] Step S2: According to the operation model and the target output voltage, the reference voltage sequence is calculated by combining the power quality and efficiency constraints.

[0031] The specific steps of step S2 are: Step S201: Obtain the state quantity of the operation model and the target output voltage in the prediction time domain window, analyze the power quality and efficiency constraints, divide them into time domain, frequency domain and energy constraints, and generate corresponding weight scheduling table and scene label.

[0032] In this embodiment, the operation model is called in the preset prediction time domain, and multi-dimensional state quantities including voltage amplitude, current phase, power factor, switching time sequence, etc. are extracted, and the target output voltage is introduced as a reference benchmark at the same time. Then, the constraints related to power quality and efficiency are analyzed, and classified according to their action mechanisms. Specifically, the time domain constraints include voltage waveform shift, zero-crossing point position and transient change rate restrictions; the frequency domain constraints cover harmonic amplitude distribution, bandwidth occupation and frequency band interference exclusion conditions; the energy constraints involve active and reactive power quotas, loss boundaries and energy transmission efficiency indicators; after completing the constraint classification, weights are assigned to different time domain, frequency domain and energy constraints, and written into the weight scheduling table. At the same time, scene labels are generated according to the power grid operation condition, load type and disturbance level, so that each type of constraint can be dynamically called in a specific scene.

[0033] Step S202: According to the operation model and the weight scheduling table, a discrete reference trajectory set is constructed, the voltage amplitude and phase sequence in each discrete reference trajectory are obtained, and a modulation space index is established based on the voltage amplitude and phase sequence.

[0034] In the present embodiment, the weight schedule table obtained in step S201 is imported in the running model, and target parameter intervals are dynamically allocated according to different constraint priorities, for example, a tolerance is set for transient voltage deviation on the time domain side, an amplitude limiting is set for specific harmonic components on the frequency domain side, and power factor and loss intervals are limited on the energy side, and then in the prediction time domain window, a plurality of reference trajectories satisfying the constraints are generated by means of point-by-point iteration and multi-scenario switching, and these trajectories are stored in the form of discretization as a set; when constructing the discrete reference trajectory set, each trajectory is disassembled into two core parts of a voltage amplitude sequence and a phase sequence, the voltage amplitude sequence reflects the voltage level at each sampling time, and the phase sequence describes the offset relationship with the grid fundamental reference; a modulation space index is established based on the voltage amplitude and phase sequence, and the specific method is to map the amplitude and phase sequence to a discrete modulation space, and assign a unique index identifier to each trajectory.

[0035] Step S203: constraint consistency test is performed on the discrete reference trajectory based on the modulation space index, and inconsistent constraint segments are segmented and replaced to obtain a feasible solution set, and the constraint consistency test includes time domain boundary, frequency band occupation, energy balance and sparsity constraint.

[0036] The specific steps of step S203 are as follows: Step S2031: The discrete reference trajectory is segmented in a preset test window, and a time stamp, a spectrum fingerprint and a modulation space index are written for each segment to form a test segment sequence.

[0037] In the present embodiment, the discrete reference trajectory is segmented according to time step and zero-crossing position in a preset test window, so that each segment of the trajectory contains independent amplitude sequence and phase sequence, and can be uniquely located on the time axis; each segment needs to write a time stamp, a spectrum fingerprint and a modulation space index, the time stamp is used to accurately identify the start and end positions of the segment in the overall trajectory, the spectrum fingerprint records the frequency domain attribute of the segment by extracting the main frequency band characteristics, and the modulation space index is used as an identifier for cross-segment calling and comparison; after the above processing, the test segment sequence formed is a set of ordered segment sequences that can be independently called.

[0038] Step S2032: sequentially test the test segment sequence, mark the segments that do not satisfy the preset constraints, and generate a time domain inconsistency list.

[0039] In the embodiment, the test segment sequence is unfolded in time sequence, and the start and end time, phase continuity and sampling step of the segment are compared point by point in the preset test window. When the time span of the segment does not match the set sampling window, or the start and end points of the segment cannot be aligned with the adjacent segment at the zero-crossing position, it is determined that the segment has time domain inconsistency, and is marked. The sequential test is not limited to the direct comparison of adjacent segments, but also includes the continuity analysis of the entire segment sequence. All segments that do not meet the preset constraints are recorded in the time domain inconsistency list.

[0040] Step S2033: The segments in the test segment sequence that meet the preset constraints are subjected to joint test of frequency band occupation and energy balance. The segments that conflict with the disabled frequency band table or the energy quota table are added to the time domain inconsistency list, and a pruning instruction is generated for each conflict.

[0041] In the embodiment, the test segment sequence is subjected to spectral decomposition, the main frequency components of the segment in the target bandwidth range are extracted, and are compared with the disabled frequency band table. When there is an energy distribution falling into the disabled frequency band in the segment, the segment is determined to conflict with the frequency band constraint. In terms of energy balance, the active and inactive components of the segment are accumulated, and are checked with the upper and lower limit intervals defined by the energy quota table. If it exceeds the quota boundary, it is determined to be energy unbalanced. All conflicting segments are added to the time domain inconsistency list, and a corresponding pruning instruction is generated for each conflict. The pruning instruction records the segment interval to be deleted or replaced, the associated spectral features and the energy constraint reference value.

[0042] Step S2034: The segments that do not conflict after joint test are subjected to sparsity determination, the boundaries of the switch dense area and the sparse area are located, the segments falling into the forbidden area are added to the inconsistency list, and a replacement instruction and a splicing anchor point are generated.

[0043] In the embodiment, Step S2035: According to the pruning instruction and the replacement instruction, the inconsistent segments are segmented and pruned at the splicing anchor points, and the replacement segments are selected from the preset candidate segment library according to the modulation space index to complete the splicing check. A feasible solution set that meets the time domain boundary, frequency band occupation, energy balance and sparsity constraints is output.

[0044] In the embodiment, the modulation space index recorded in the segment is unfolded into a switch time sequence, and the time interval distribution between adjacent switch events is calculated within a preset observation window. If the interval distribution of the segment is lower than a sparsity threshold for a long time, the segment is marked as a switch dense area; if the interval distribution of the segment is higher than the threshold for a long time, the segment is marked as a sparse area. The switch dense area and the sparse area both belong to the forbidden area category in the operation constraint of the power regulator. The dense area may cause excessive resource occupation of the segment in the high frequency band, and the sparse area may cause control response lag. When it is determined that the whole or part of a segment falls into the forbidden area, the segment is directly added to the inconsistency list, and a replacement instruction is generated at the start and end positions of the segment. The inconsistency list obtained finally contains not only the conflict segments in the time domain, the frequency domain and the energy dimension, but also the unqualified parts under the switch sparsity constraint.

[0045] Step S204: based on the scene label, the feasible solution set is sorted and selected according to a preset priority, and all solutions are quantized, amplitude-limited and zero-crossing aligned under the modulation clock to obtain a reference voltage sequence.

[0046] The specific steps of step S204 are as follows: Step S2041: based on the scene label, a sorting rule is set for each feasible solution in the feasible solution set, and a priority sequence is formed.

[0047] In the embodiment, each feasible solution is classified and identified according to the scene label generated in the early stage, for example, normal working condition, voltage fluctuation working condition, load mutation working condition and frequency deviation working condition. Each scene label corresponds to a set of constraint weights. When a feasible solution is classified into a certain scene category, the internal parameters of the feasible solution need to be reordered according to the constraint priority in the scene. The setting of the sorting rule does not only depend on a single index, but also comprehensively weights the time domain constraint, the frequency domain constraint and the energy constraint according to the scene weight. Through multi-dimensional weighting, each feasible solution will obtain a comprehensive priority value in its corresponding scene. All feasible solutions will form an ordered priority sequence according to the comprehensive priority values.

[0048] Step S2042: at the trigger point of the modulation clock, the solution with the highest priority in the priority sequence is selected as the main solution.

[0049] In the embodiment, the modulation clock usually operates at a fixed sampling frequency, and each trigger point corresponds to a new modulation period. In each period, the main solution selected by the priority sorting mechanism is the solution that best meets the requirements of the current working condition.

[0050] Step S2043: the discrete reference trajectory of the main solution is subjected to amplitude and phase quantization processing under the modulation clock to obtain a preliminary quantized trajectory of the main solution.

[0051] In the embodiment, at each sampling point of the modulation clock, the voltage amplitude and phase of the main solution are intercepted and rounded to a preset quantization step, so that the amplitude is mapped to a limited level set and the phase is mapped to a discrete angle set; the amplitude quantization result of each sampling period needs to be compared with the result of the adjacent period, if the deviation exceeds the threshold, the phase quantization result is fine-tuned to compensate, so as to maintain the overall smoothness of the track, at the same time, the quantization of the frequency component also needs to keep consistent with the modulation space index, to ensure that the track can match the pre-set constraint framework in both amplitude and phase dimensions; the final preliminary quantization track is completely synchronized with the modulation clock in time sequence, and is represented as a set of limited discrete point columns in data structure.

[0052] Step S2044: Point-by-point comparison of the preliminary quantization track of the main solution with the amplitude constraint and energy boundary, marking the unqualified segments and calling the backup candidate solution for local replacement to generate a modified track.

[0053] In the embodiment, the voltage amplitude and phase are compared point by point at the sampling points of the modulation clock, to check whether they fall within the interval specified by the amplitude constraint, and to check whether the contribution of each sampling point in the cumulative energy curve exceeds the energy boundary, if a segment appears to be out of limit in amplitude or energy allocation, the segment is immediately marked and the triggered constraint type and position index are recorded; the marked unqualified segment is not discarded directly, but is replaced locally by calling the backup candidate solution, which is provided by the suboptimal solution set reserved in the previous step S2042, each candidate solution has compatibility with the main solution in time sequence and scene label, in the local replacement process, first, the segment corresponding to the backup candidate solution is mapped to the same interval of the current modulation clock, and the boundary is interpolated and smoothed to ensure seamless connection with the front and rear parts of the original track; the modified track retains the basic structure of the main solution as a whole, while realizing compliance adjustment of the amplitude constraint and energy boundary in the local part.

[0054] Step S2045: Setting alignment anchor points in the zero-crossing interval of the modified track, and fine moving and splicing the sampling points in the neighborhood of the alignment anchor points, finally outputting a continuous and constraint-condition-satisfied reference voltage sequence.

[0055] In the embodiment, the zero-crossing interval of the voltage waveform is positioned in the modified trajectory, and an alignment anchor point is set at the symmetrical position of the interval, which is used as a connection reference point to ensure the phase continuity of the front and rear segments at the voltage zero-crossing, avoiding the occurrence of faults or distortion in the trajectory when switching; after the anchor point is determined, the sampling points in its neighborhood need to be moved slightly, which means that the adjacent sampling points are adjusted slightly on the time axis under the premise of ensuring that the amplitude and phase do not break through the amplitude constraint and energy boundary, so that the connection between the segments is smoother; then, the sampling points after the slight movement are spliced with the front and rear segments, and consistency checking is performed on the spliced part, including amplitude continuity checking, phase monotonicity checking and frequency band integrity checking; finally, the output reference voltage sequence is continuous globally and smooth locally, and meets the multi-dimensional constraint conditions set before.

[0056] Step S3: Real-time monitoring of the power grid and load state, when voltage fluctuation or abnormality is detected, projecting the reference voltage sequence to the safe operation envelope and performing hierarchical de-rating control.

[0057] The specific steps of step S3 are: Step S301: Collecting the state variables of the power grid side and the load side under the synchronous reference, generating a continuous state vector stream, and writing a scene label and an event counter for each sampling period.

[0058] In the embodiment, the sampling clock is corrected using the phase-locked reference signal, so that all sampling points take the zero-crossing or specific phase point of the power grid fundamental as a reference; then, the voltage, current and frequency offset of the power grid side are collected simultaneously in each sampling period, and the voltage, current and power factor of the load side are synchronously obtained; after obtaining the above sampling data, a continuous state vector stream is generated by sequential splicing. Each state vector contains multi-dimensional data of the power grid side and the load side; while generating the state vector, a scene label is attached to each sampling period, and the final state vector stream is not only continuous and consistent in time, but also has rich labels and event markers in semantics.

[0059] Step S302: Preparing an abnormal mode library, comparing the state vector stream with a sliding window, outputting abnormal event records according to the abnormal mode library, and generating abnormal event levels according to the influence domain and duration of the abnormal event records.

[0060] In the embodiment, the feature templates of multiple typical operation abnormalities, such as voltage sag, voltage surge, frequency offset, harmonic distortion, load mutation, etc., are preset in the abnormal mode library, and the corresponding time-domain waveform features, frequency-domain component distribution and energy mutation threshold are extracted for each type of abnormality. In the operation process, the state vector flow is unfolded in the form of a sliding window, each window covers several consecutive sampling periods, and the multi-dimensional state data in the window is matched and compared with the abnormal mode library in turn. If the matching result exceeds the set similarity threshold, it is determined that there is a corresponding abnormality in the window, and an abnormal event record is generated at the output end. All abnormal events are summarized in the form of records, and are divided into different abnormal levels according to the influence domain and duration, for example, transient disturbance can be judged as low level, and long-term global fluctuation is promoted to high level, and finally the abnormal event level is obtained.

[0061] Step S303: constructing a safe operation envelope based on the operation model of the power regulator and the preset constraints, discretizing the safe operation envelope into a multi-level boundary set, and configuring priority rules and start-stop conditions for each level of boundary.

[0062] In the embodiment, the grid equivalent parameters and load equivalent parameters identified in the early stage are introduced into the operation model of the power regulator, and the operation space is analyzed in combination with the constraints such as power quality, efficiency limit and device working range. In the analysis process, the allowed ranges of voltage amplitude, phase, frequency band occupation and energy quota under different working conditions are calculated respectively, and these ranges are projected as a multi-dimensional envelope interval. The envelope interval defines the safe boundary that the regulator must follow when the grid is disturbed or the load is mutated. The envelope interval is not a single boundary, but is discretized into a multi-level boundary set. For example, the first level boundary can correspond to the limit under slight fluctuation condition, the second level boundary corresponds to the contraction range under moderate disturbance condition, and the higher level corresponds to the limit operation under serious fault condition. Each level includes specific amplitude upper limit, phase offset tolerance and energy constraint boundary, forming a hierarchical progressive protection framework.

[0063] Further, while constructing the multi-level boundary set, priority rules and start-stop conditions are configured for each level. The priority rules are used to determine the order of boundary calling when multiple constraints are triggered at the same time, and the start-stop conditions specify the criteria for entering and exiting the boundary, for example, using abnormal level, event duration or energy cumulative deviation as the trigger basis.

[0064] Step S304: in the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement and frequency band remapping according to the priority rules, and the segment replacement is completed at the zero-crossing anchor point to obtain the limited voltage sequence.

[0065] The specific steps of step S304 are: Step S3041: receiving the projection instruction triggered by the abnormal event level, and selecting the boundary layer corresponding to the level in the multi-level boundary set in the safe operation envelope.

[0066] In this embodiment, the abnormal event level generated by the previous step S302 is parsed as a projection instruction carrying parameters such as abnormal type, impact domain and duration. After receiving the projection instruction, the control logic performs matching search in the multi-level boundary set of the safe operation envelope. Since the multi-level boundary set has previously defined the boundary layer corresponding to different abnormal levels, it can quickly locate the level corresponding to the current abnormality and determine the voltage amplitude limit, phase tolerance range and energy distribution boundary covered by the level.

[0067] Step S3042: segmentally compressing the amplitude interval of the reference voltage sequence in the boundary layer, and writing the compressed segment into the mark table.

[0068] Step S3043: rearranging the phase order of adjacent segments according to the mark table to make it comply with the phase sequence rule of the boundary layer.

[0069] In this embodiment, the mark table records the phase start point, end point and adjacent relationship of each segment before correction, and also gives the reference phase order under the boundary layer requirement. After searching the mark table, the control logic first identifies whether there is reverse order, jump or discontinuity in the phase connection between adjacent segments, and lists the parts that do not comply with the boundary layer rule in the rearrangement list. Then, by adjusting the arrangement order of the segments in the time axis, the phase evolution direction is kept consistent with the boundary layer rule, avoiding phase misalignment when crossing segments. In the rearrangement process, not only the simple front and rear position exchange of the segments is performed, but also the phase continuity condition is constrained. Finally, the trajectory formed strictly complies with the boundary layer rule in phase evolution, and realizes smooth connection between adjacent segments.

[0070] Step S3044: performing frequency band remapping on the rearranged segments, mapping them to the frequency interval of the boundary layer, and generating splicing anchor points.

[0071] In the embodiment, the rearranged track segment is subjected to spectral analysis to extract its main frequency components and harmonic distribution, and compared with the target frequency interval defined by the boundary layer. When it is found that some frequency components in the segment exceed the allowed range, the control logic will redistribute these components to the effective frequency band defined by the boundary layer by adjusting the sampling point interval or phase step. The frequency band remapping is not only a single frequency translation, but also a multidimensional adjustment combining the segment characteristics and the boundary layer rules. For example, when the high-order harmonic energy in the segment is too high, it can be weakened and dispersed to the adjacent frequency band through remapping. When the low-frequency component is insufficient, the gap is filled through frequency domain compensation, so that the overall frequency spectrum of the segment is closer to the template requirements of the target boundary layer. The remapped segment generates a splicing anchor point at the boundary. The splicing anchor point is used to identify the docking position of different segments in the time and frequency dimensions, to ensure that the amplitude, phase and spectrum can be connected smoothly in the subsequent splicing process.

[0072] Step S3045: Splicing and checking the remapped segment and the unmodified segment at the splicing anchor point to obtain a continuous limited voltage sequence.

[0073] In the embodiment, the pre-generated splicing anchor point is called at the segment boundary position. The anchor point contains time markers, phase alignment information and amplitude reference values. The control logic compares the remapped segment and the unmodified segment point by point at the anchor point, and checks the differences in amplitude, phase and sampling interval. When the difference exceeds the set threshold, the adjustment is made through interpolation correction or micro-shift. The splicing and checking is not only limited to the direct comparison of the boundary points, but also includes the continuity check of the adjacent interval. The final limited voltage sequence exhibits a continuous waveform on the time axis and maintains consistent distribution characteristics in the frequency domain, and meets the boundary conditions of the safe operating envelope.

[0074] Step S305: Determining the derating level according to the limited voltage sequence and the multi-level boundary set, generating the level transition table and the retention time, and updating the output control quantity according to the level transition table under the modulation clock.

[0075] The specific steps of step S305 are: Step S3051: Comparing the limited voltage sequence and the multi-level boundary set segment by segment to generate a determination table of boundary hit markers, duration periods and segment positions, and determining a candidate derating level set based on the determination table.

[0076] In the embodiment, Step S3052: Selecting the current derating level and determining its adjacent level according to the candidate derating level set and the abnormal event level to obtain a level relationship set containing entry conditions and release conditions.

[0077] In the embodiment, the limited voltage sequence is divided according to the modulation period, and each division segment retains key information such as amplitude, phase and energy component. Then, a multi-level boundary set is called to check whether the amplitude of each segment reaches the boundary threshold, whether the phase shift exceeds the tolerance range, and whether the energy quota breaks the limited interval. When any segment is detected to reach or exceed the boundary condition, a boundary hit marker is generated at the segment; the hit marker is not isolated, but is counted in combination with the continuous period and the segment position. The continuous period is used to determine whether a certain boundary trigger is a short-term disturbance or a long-term anomaly, and the segment position identifies the timing distribution of the trigger point in the entire sequence. Based on the determination table, a candidate derating level set can be determined, which usually contains multiple level intervals corresponding to different boundary levels and trigger strengths.

[0078] Step S3053: constructing a level transition table on the level relationship set, and configuring a holding time for each transition path.

[0079] In the embodiment, the hierarchical order and mutual adjacency relationship between each candidate level in the level relationship set are explicitly defined, such as the one-way promotion or two-way rollback path between the low level, the medium level and the high level. Then, on this basis, transition paths are generated one by one, and each path is attached with entry conditions and exit conditions, so that the switching between different levels has logical coherence rather than random jumping. A holding time is configured for each transition path. The holding time is used to specify that after the level transition is completed, at least a certain period of time must be maintained before switching again.

[0080] Step S3054: periodically evaluating the current level under the modulation clock according to the level transition table and the holding time, performing level switching at the zero-crossing anchor point when the entry condition is met, and maintaining the existing level and updating the timing state when the condition is not met.

[0081] In the embodiment, in each modulation clock period, the state of the current level is determined to check whether the entry condition specified by the transition table is met, including the number of boundary hits, the continuous period and the energy deviation. When the condition is met, the control logic will perform level switching at the zero-crossing anchor point, ensuring that the switching process is aligned with the zero-crossing point, thereby avoiding the mutation of the voltage sequence in amplitude and phase. If the evaluation result shows that the condition is not met, the current level remains unchanged, and the timing state is updated to the next period until the transition condition is met. The final control effect is that under the accurate driving of the modulation clock, the switching of the derating level is consistent with the zero-crossing point, the level stability is guaranteed, and the trajectory continuity is also maintained.

[0082] Step S3055: writing the level change result and the timing state back to the event counter and the safe operation envelope, and selecting the corresponding output control quantity according to the current level.

[0083] In the embodiment, when the period evaluation is completed under the modulation clock, if a level switching occurs, first, a new level mark and a corresponding holding timing state are written back to the event counter for recording the number of times, the duration and the triggered boundary layer information of the switching, and the level information is synchronously written into the safe operating envelope, so that the envelope can dynamically adjust its constraint conditions based on the latest level in the subsequent period, realizing the bidirectional consistency of the operating boundary and the derating level; after the write-back operation is completed, the corresponding output control quantity must be selected according to the current level. The output control quantity is usually preset as a voltage amplitude template, a phase modulation template or an energy distribution template under different levels. By matching the corresponding relationship between the current level and the template library, the control instruction conforming to the level constraint can be quickly extracted and loaded and executed in the next period of the modulation clock. If the current level remains unchanged, the output control quantity directly uses the existing template, and only the timing state is updated to record the continuation of the current period; the finally output control quantity strictly corresponds to the current level, and the event counter and the safe operating envelope both save the latest level state.

[0084] Step S4: generating a power regulator control signal based on the corrected reference voltage sequence, and calibrating the operation model of the power regulator through real-time feedback.

[0085] Embodiment 2 Please refer to Figure 2 Another embodiment provided by the application: a voltage regulation control system for a power regulator, comprising: a model establishment module, a voltage sequence calculation module, a voltage regulation control module and a feedback adjustment module; The model establishment module is used for collecting parameters of the grid side and the load side, including current and voltage, and establishing an operation model of the power regulator based on parameter identification; The voltage sequence calculation module is used for calculating a reference voltage sequence according to the operation model and a target output voltage, in combination with power quality and efficiency constraints; The voltage regulation control module is used for real-time monitoring of the grid and load state, and when voltage fluctuation or abnormality is detected, projecting the reference voltage sequence to a safe operating envelope and performing hierarchical derating control; The feedback adjustment module generates a power regulator control signal based on the corrected reference voltage sequence, and calibrates the operation model of the power regulator through real-time feedback.

[0086] The voltage regulation control module comprises: an abnormal event level generation unit, a restricted voltage sequence calculation unit and a voltage regulation control unit; The abnormal event level generation unit is used for collecting state quantities of the grid side and the load side, analyzing output abnormal event records, and generating abnormal event levels according to the abnormal event record influence domain and duration. The limited voltage sequence calculation unit is configured to sequentially perform amplitude compression, phase rearrangement, and frequency band remapping on the reference voltage sequence according to the priority rule in a projection window corresponding to the event level, and complete segment replacement at a zero-crossing anchor point to obtain a limited voltage sequence. The voltage regulation control unit is configured to determine a derating level, generate a level transition table and a holding time, and update an output control quantity according to the level transition table under a modulation clock.

[0087] In addition, the part of the above technical solution in the embodiments of the present application that is consistent with the implementation principle of the corresponding technical solution in the prior art is not described in detail to avoid excessive description.

[0088] The specific embodiments described above are further detailed to explain the purposes, technical solutions, and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A voltage regulation control method for a power regulator, applied to a power regulator containing controllable rectifier / inverter or solid-state switching devices, characterized in that, include: Collect parameters from the grid side and the load side, including current and voltage, and establish an operating model for the power regulator based on parameter identification; Based on the aforementioned operating model and target output voltage, and combined with power quality and efficiency constraints, a reference voltage sequence is calculated. The system monitors the power grid and load status in real time. When voltage fluctuations or anomalies are detected, the reference voltage sequence is projected onto the safe operation envelope, and graded derating control is performed. The power regulator control signal is generated based on the corrected reference voltage sequence, and the operation model of the power regulator is calibrated through real-time feedback.

2. The voltage regulation control method for a power regulator as described in claim 1, characterized in that, The process involves collecting parameters from both the grid and load sides, including current and voltage, and establishing an operating model for the power regulator based on these parameters. Set the reference phase on the grid side and trigger the first sampling cycle, dividing the voltage and current signals into raw data frames; A temporal perturbation is introduced into the original data frame, and multi-dimensional operating quantities of the power grid and load are collected synchronously in multiple sampling periods to form a sequence dataset with perturbation tags; The sequence dataset is segmented and cross-filtered to remove segments that do not meet the temporal consistency requirement, thereby obtaining candidate data for identification. Based on the candidate data, a multidimensional parameter mapping relationship is established, and the equivalent parameters of the power grid and the equivalent parameters of the load are projected onto the unified operating model of the power regulator through a progressive iterative method.

3. The voltage regulation control method for a power regulator as described in claim 2, characterized in that, Based on the aforementioned operating model and target output voltage, and considering power quality and efficiency constraints, a reference voltage sequence is calculated, including: Within the prediction time domain window, the state variables and target output voltage of the running model are obtained, the power quality and efficiency constraints are analyzed, and they are divided into three types of constraints: time domain, frequency domain and energy domain. Corresponding weight scheduling tables and scene labels are generated. Based on the aforementioned operating model and weight scheduling table, a set of discrete reference trajectories is constructed. At the same time, the voltage amplitude and phase sequence in each discrete reference trajectory are obtained, and a modulation space index is established based on the voltage amplitude and phase sequence. Based on the modulation space index, the discrete reference trajectory is subjected to constraint consistency check, and the inconsistent constraint segments are segmented, pruned and replaced to obtain a feasible solution set. The constraint consistency check includes time domain boundary, frequency band occupancy, energy balance and sparsity constraints. Based on scene labels, feasible solutions are sorted and selected according to preset priorities. Then, under the modulation clock, all solutions are quantized, limited, and zero-crossing aligned to obtain a reference voltage sequence.

4. The voltage regulation control method for a power regulator as described in claim 3, characterized in that, The constraint consistency check of the discrete reference trajectory based on the modulation spatial index is performed, and the segments with inconsistent constraints are segmented, pruned, and replaced to obtain a feasible solution set, including: Within a preset inspection window, the discrete reference trajectory is fragmented, and time stamps, spectral fingerprints, and modulation spatial indexes are written for each fragment to form an inspection fragment sequence. The sequence of test segments is sequentially tested, segments that do not meet preset constraints are marked, and a list of temporal inconsistencies is generated. For segments in the test segment sequence that meet the preset constraints, a joint test of frequency band occupancy and energy balance is performed. Segments that conflict with the prohibited frequency band table or energy quota table are added to the time domain inconsistency list, and a pruning instruction is generated for each conflict. For segments that do not conflict after joint inspection, sparsity is determined, the boundary between dense and sparse areas of switches is located, segments that fall into the restricted area are added to the inconsistency list, and replacement instructions and splicing anchors are generated. According to the trimming and replacement instructions, inconsistent segments are trimmed at their splicing anchor points, and replacement segments are selected from the preset candidate segment library according to the modulation space index to complete the splicing verification, and a set of feasible solutions that meet the constraints of time domain boundary, frequency band occupancy, energy balance and sparsity is output.

5. The voltage regulation control method for a power regulator as described in claim 4, characterized in that, The feasible solution set is sorted and selected according to a preset priority based on scene labels, and all solutions are quantized, limited, and zero-crossing aligned under the modulation space index to obtain a reference voltage sequence, including: Based on scene labels, sorting rules are set for each feasible solution in the feasible solution set, and a priority sequence is formed; At the modulation clock trigger point, the solution with the highest priority is selected as the master solution from the priority sequence; The discrete reference trajectory of the master solution is subjected to amplitude and phase quantization processing under a modulation clock to obtain the preliminary quantized trajectory of the master solution; The preliminary quantized trajectory of the master solution is compared point by point with the amplitude constraint and energy boundary. Segments that do not meet the conditions are marked and local replacements are performed by calling backup candidate solutions to generate a corrected trajectory. Alignment anchors are set in the zero-crossing interval of the corrected trajectory, and the sampling points in the neighborhood of the alignment anchors are slightly shifted and spliced ​​for verification. Finally, a continuous reference voltage sequence that meets the constraint conditions is output.

6. The voltage regulation control method for a power regulator as described in claim 5, characterized in that, The real-time monitoring of the power grid and load status, when detecting voltage fluctuations or anomalies, projects the reference voltage sequence onto the safe operating envelope and performs graded derating control, including: Under the synchronous reference, the state variables of the power grid side and the load side are collected to generate a continuous state vector stream, and a scene label and event counter are written for each sampling period. A preset abnormal pattern library is used to perform sliding window comparison on the state vector stream, output abnormal event records according to the abnormal pattern library, and generate abnormal event levels according to the influence domain and duration of the abnormal event records. A safe operation envelope is constructed based on the operation model and preset constraints of the power regulator. The safe operation envelope is discretized into a multi-level boundary set, and priority rules and start / stop conditions are configured for each level of boundary. Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero crossover anchor point to obtain the restricted voltage sequence. The derating level is determined based on the restricted voltage sequence and the multi-level boundary set, a level transition table and a hold duration are generated, and the output control quantity is updated according to the level transition table under the modulation clock.

7. The voltage regulation control method for a power regulator as described in claim 6, characterized in that, Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero-crossing anchor point to obtain a restricted voltage sequence, including: Receive projection instructions triggered by the abnormal event level, and select the boundary layer corresponding to that level in the multi-level boundary set in the safe operation envelope; Within the boundary layer, the amplitude range of the reference voltage sequence is compressed segment by segment, and the compressed segments are written into a tag table; The phase order of adjacent segments is rearranged according to the label table to conform to the phase sequence rules of the boundary layer; The rearranged segments are remapped to the frequency range of the boundary layer, and splicing anchor points are generated. At the splicing anchor point, the frequency band remapped segment is spliced ​​and verified with the unmodified segment to obtain a continuous restricted voltage sequence.

8. The voltage regulation control method for a power regulator as described in claim 7, characterized in that, Based on the constrained voltage sequence and multi-level boundary set, the derating level is determined, a level transition table and hold duration are generated, and the output control quantity is updated according to the transition table under the modulation clock, including: The restricted voltage sequence is compared segment by segment with the multi-level boundary set to generate a judgment table of boundary hit mark, duration period and segment position, and the candidate derating level set is determined based on the judgment table. Based on the candidate reduction level set and the abnormal event level, the current reduction level is selected and its adjacent levels are determined, resulting in a level relationship set that includes entry conditions and removal conditions; Construct a hierarchy transition table on the set of hierarchy relationships and configure the retention time for each transition path; Under the modulation clock, the current level is periodically evaluated according to the level transition table and the holding time. If the entry condition is met, the level switch is performed at the zero crossover anchor point. If the condition is not met, the existing level is maintained and the timing state is updated. Write the level change result and timing status back to the event counter and safe operation envelope, and select the corresponding output control quantity according to the current level.

9. A voltage regulation control system for a power regulator, used to implement the voltage regulation control method for a power regulator according to any one of claims 1-8, characterized in that, include: The module includes a model building module, a voltage sequence calculation module, a voltage regulation control module, and a feedback adjustment module. The model building module is used to collect parameters from the grid side and the load side, including current and voltage, and to build an operating model of the power regulator based on parameter identification. The voltage sequence calculation module is used to calculate a reference voltage sequence based on the operating model and the target output voltage, combined with power quality and efficiency constraints. The voltage regulation control module is used to monitor the power grid and load status in real time. When voltage fluctuations or abnormalities are detected, the reference voltage sequence is projected onto the safe operation envelope and graded derating control is performed. The feedback adjustment module generates a power regulator control signal based on the corrected reference voltage sequence and calibrates the power regulator's operating model through real-time feedback.

10. A voltage regulation control system for a power regulator as described in claim 9, characterized in that, The voltage regulation control module includes: an abnormal event level generation unit, a limited voltage sequence calculation unit, and a voltage regulation control unit; The abnormal event level generation unit is used to collect the state variables of the power grid side and the load side, analyze and output abnormal event records, and generate abnormal event levels according to the impact domain and duration of the abnormal event records. The restricted voltage sequence calculation unit is used to perform amplitude compression, phase rearrangement and frequency band remapping on the reference voltage sequence in sequence according to the priority rules within the projection window corresponding to the event level, and to complete the segment replacement at the zero crossover anchor point to obtain the restricted voltage sequence. The voltage regulation control unit is used to determine the derating level, generate a level transition table and a hold duration, and update the output control quantity according to the level transition table under the modulation clock.

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