A multi-stage voltage delay driving circuit, PCB board and chip

Abstract

The application relates to the field of electronic technology and discloses a multistage voltage delay driving circuit, a PCB (Printed Circuit Board) and a chip, which comprise an external parameter input module, a time information reading module and a driving voltage adjusting module; the external parameter input module can receive time configuration parameters and voltage reference parameters; the time information reading module converts the time configuration parameters into digital time instructions to ensure the timing accuracy of driving adjustment; and the driving voltage adjusting module outputs gate driving voltages suitable for the switching characteristics of IGBTs in stages according to the digital time instructions and the voltage reference parameters; the multistage voltage delay driving circuit of the application effectively balances the switching efficiency and working safety of IGBTs through the dynamic stage-by-stage adjusting mode, significantly improves the practicability and reliability of the driving circuit, and further guarantees the stable operation of the entire power system.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a multi-level voltage delay drive circuit, PCB board, and chip. Background Technology

[0002] With the development of power electronics technology, the IGBT driver circuit, as a key unit connecting the control signal and the IGBT device, needs to realize the basic function of converting the low-voltage PWM signal into a drive voltage to control the IGBT switch.

[0003] However, existing driver ICs generally adopt a fixed drive voltage design, and the drive signal directly controls the IGBT to turn on and off. It is impossible to dynamically adjust the voltage according to different stages of IGBT switching, making it difficult to balance the switching efficiency and operational safety of the IGBT. This may cause overshoot risk due to fixed high voltage, or increase switching losses due to fixed low voltage, affecting the reliability of the IGBT and the entire power system. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to solve at least one of the technical problems mentioned above.

[0005] The solution to the technical problem of this invention is:

[0006] A first aspect of the present invention provides a multi-stage voltage delay drive circuit, comprising:

[0007] The system comprises an external parameter input module, a time information reading module, and a drive voltage adjustment module. The external parameter input module is electrically connected to both the time information reading module and the drive voltage adjustment module, and the time information reading module is electrically connected to the drive voltage adjustment module. The external parameter input module receives time configuration parameters and voltage reference parameters. The time information reading module converts the time configuration parameters into digital time commands. The drive voltage adjustment module outputs a gate drive voltage adapted to the IGBT switching characteristics in stages according to the digital time commands and the voltage reference parameters.

[0008] The beneficial effects of the first aspect of the present invention are as follows: First, the external parameter input module can receive time configuration parameters and voltage reference parameters, providing a customized basis for control of different switching stages; second, the time information reading module converts the time configuration parameters into digital time commands, ensuring the timing accuracy of drive adjustment; finally, the drive voltage adjustment module outputs gate drive voltages adapted to the IGBT switching characteristics in stages according to the digital time commands and voltage reference parameters, outputting high voltages in stages where faster switching is needed to reduce losses, and outputting matching voltages in stages where spikes need to be avoided; the multi-stage voltage delay drive circuit of the present invention effectively balances the switching efficiency and operational safety of the IGBT through this dynamic staged adjustment method, significantly improving the practicality and reliability of the drive circuit, thereby ensuring the stable operation of the entire power system.

[0009] As some sub-solutions of the above technical solution, the external parameter input module includes a first high-level port TON1H, a first low-level port TON1L, a second high-level port TON2H, a second low-level port TON2L, a first high-level port TOFF1H, a first low-level port TOFF1L, a second high-level port TOFF2H, a second low-level port TOFF2L, a reference voltage port VONREF, and a reference voltage port VOFFREF; the first high-level port TON1H... ON1H, the first low-level on port TON1L, the second high-level on port TON2H, the second low-level on port TON2L, the first high-level off port TOFF1H, the first low-level off port TOFF1L, the second high-level off port TOFF2H, and the second low-level off port TOFF2L are all electrically connected to the time information reading module; the on reference voltage port VONREF and the off reference voltage port VOFFREF are electrically connected to the drive voltage adjustment module.

[0010] As some sub-solutions of the above technical solution, the time information reading module includes a channel selection module, a conversion module, a data processing module, and a data storage module electrically connected in sequence; the data storage module is electrically connected to the drive voltage adjustment module; the channel selection module is electrically connected to the first high-level on port TON1H, the first low-level on port TON1L, the second high-level on port TON2H, the second low-level on port TON2L, the first high-level off port TOFF1H, the first low-level off port TOFF1L, the second high-level off port TOFF2H, and the second low-level off port TOFF2L, respectively; the channel selection module is used to select data in time sequence. The first high-order port TON1H, the first low-order port TON1L, the second high-order port TON2H, the second low-order port TON2L, the first high-order port TOFF1H, the first low-order port TOFF1L, the second high-order port TOFF2H, and the second low-order port TOFF are sequentially turned on to transmit the time configuration parameters provided by each port to the conversion module. The conversion module is used to convert the time configuration parameters into digital signals. The data processing module is used to perform a summation operation between the high and low orders of the digital signals to generate delay data. The data storage module is used to temporarily store the delay data and output it to the drive voltage adjustment module.

[0011] As some sub-solutions of the above technical solution, the drive voltage adjustment module includes an on-phase timing circuit, an off-phase timing circuit, an on-phase voltage switching circuit, and an off-phase voltage switching circuit; the on-phase timing circuit and the on-phase reference voltage port VONREF are electrically connected to the on-phase voltage switching circuit; the off-phase timing circuit and the off-phase reference voltage port VOFFREF are electrically connected to the off-phase voltage switching circuit; the on-phase timing circuit and the off-phase timing circuit are used to read the delay data and generate corresponding timing trigger signals; the on-phase voltage switching circuit and the off-phase voltage switching circuit are used to output gate drive voltage according to the timing trigger signals.

[0012] As some sub-solutions of the above technical solution, the turn-on stage timing circuit includes a detection trigger EF0, a first eight-bit timer, a first selector array, a first eight-bit adder EF10, a first AND gate G1, a second AND gate G2, a first OR gate, and a first storage trigger EF9.

[0013] The positive output terminal of the detection trigger EF0 is connected to the reset terminal of the first eight-bit timer and the clock terminal of the first storage trigger EF9, respectively; the first eight-bit timer includes a first trigger EF1, a second trigger EF2, a third trigger EF3, a fourth trigger EF4, a fifth trigger EF5, a sixth trigger EF6, a seventh trigger EF7, and an eighth trigger EF8 connected in series; the first selector array includes eight first selectors; the control terminals of the eight first selectors are electrically connected to the data storage module and the output terminal of the first eight-bit adder EF10, respectively; the data input terminals of the eight first selectors are connected to the first trigger EF1, the second trigger EF2, the third trigger EF3, the fourth trigger EF4, and the eighth trigger EF8, respectively. The fifth flip-flop EF5, the sixth flip-flop EF6, the seventh flip-flop EF7, and the eighth flip-flop EF8 are electrically connected; the data output terminals of the eight first selectors are connected to the input terminals of the first AND gate G1 and the second AND gate G2; the input terminal of the first eight-bit adder EF10 is connected to the data storage module; the output terminal of the first AND gate G1 is connected to the input terminal of the first storage flip-flop EF9, and the output terminal of the first storage flip-flop EF9 is connected to the turn-on voltage switching circuit; the output terminal of the second AND gate G2 is connected to the second input terminal of the first OR gate and the turn-on voltage switching circuit; the first input terminal of the first OR gate is connected to an external reference clock signal, and the output terminal of the first OR gate is connected to the clock terminal of the first eight-bit timer.

[0014] As some sub-solutions of the above technical solution, the shutdown phase timing circuit includes a second eight-bit timer, a second selector array, a second eight-bit adder EF19, a third AND gate G3, a fourth AND gate G4, a second OR gate, and a second storage flip-flop EF20; the inverting output terminal of the detection flip-flop EF0 is connected to the reset terminal of the second eight-bit timer and the clock terminal of the second storage flip-flop EF20 respectively; the second eight-bit timer includes an eleventh flip-flop EF11, a twelfth flip-flop EF12, a thirteenth flip-flop EF13, a fourteenth flip-flop EF14, a fifteenth flip-flop EF15, a sixteenth flip-flop EF16, a seventeenth flip-flop EF17, and an eighteenth flip-flop EF18 connected in series; the second selector array includes eight second selectors; the control terminals of the eight second selectors are electrically connected to the data storage module and the output terminal of the second eight-bit adder EF19 respectively; the data input terminals of the eight second selectors are respectively connected to the second eight-bit adder EF19. The eleventh flip-flop EF11, the twelfth flip-flop EF12, the thirteenth flip-flop EF13, the fourteenth flip-flop EF14, the fifteenth flip-flop EF15, the sixteenth flip-flop EF16, the seventeenth flip-flop EF17, and the eighteenth flip-flop EF18 are electrically connected; the data output terminals of the eight second selectors are connected to the input terminals of the third AND gate G3 and the fourth AND gate G4; the input terminal of the second eight-bit adder EF19 is connected to the data storage module; the output terminal of the third AND gate G3 is connected to the input terminal of the second storage flip-flop EF20, and the output terminal of the second storage flip-flop EF20 is connected to the turn-on voltage switching circuit; the output terminal of the fourth AND gate G4 is connected to the second input terminal of the second OR gate and the turn-on voltage switching circuit; the first input terminal of the second OR gate is connected to the reference clock signal, and the output terminal of the second OR gate is connected to the clock terminal of the second eight-bit timer.

[0015] As some sub-solutions of the above technical solution, the turn-on voltage switching circuit includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5, a sixth transmission gate TG6, a seventh transmission gate TG7, a power supply voltage terminal VCC, and a first drive output terminal G; the power supply voltage terminal VCC is connected to the input terminals of the first transmission gate TG1 and the second transmission gate TG2; the turn-on reference voltage port VONREF is connected to the input terminal of the third transmission gate TG3; the output terminal of the second AND gate G2 is connected to the control terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3; the output terminal of the first storage trigger EF9 is connected to the first... The control terminals of the four transmission gates TG4 and TG5 are connected; the output terminal of the detection trigger EF0 is connected to the control terminals of the sixth transmission gate TG6 and TG7; the output terminal of the first transmission gate TG1 is connected to the input terminal of the fourth transmission gate TG4; the output terminals of the second transmission gate TG2 and TG3 are connected to the input terminal of the fifth transmission gate TG5; the output terminals of the fourth transmission gate TG4 and TG5 are connected to the input terminal of the sixth transmission gate TG6; the input terminal of the seventh transmission gate TG7 is grounded; and the output terminals of the sixth transmission gate TG6 and TG7 are connected to the first drive output terminal G.

[0016] As some sub-solutions of the above technical solution, the shutdown voltage switching circuit includes an eighth transmission gate TG8, a ninth transmission gate TG9, a tenth transmission gate TG10, an eleventh transmission gate TG11, a twelfth transmission gate TG12, a thirteenth transmission gate TG13, a fourteenth transmission gate TG14, and a second drive output terminal E; the power supply voltage terminal VCC is connected to the input terminals of the eighth transmission gate TG8 and the ninth transmission gate TG9; the shutdown reference voltage port VOFFREF is connected to the input terminal of the tenth transmission gate TG10; the output terminal of the fourth AND gate G4 is connected to the control terminals of the eighth transmission gate TG8, the ninth transmission gate TG9, and the tenth transmission gate TG10; the output terminal of the second storage trigger EF20 is connected to the eleventh transmission gate TG11... The control terminal is connected to the control terminal of the fifth transmission gate TG5; the output terminal of the detection trigger EF0 is connected to the control terminal of the thirteenth transmission gate TG13 and the control terminal of the fourteenth transmission gate TG14; the output terminal of the eighth transmission gate TG8 is connected to the input terminal of the eleventh transmission gate TG11; the output terminals of the ninth transmission gate TG9 and the tenth transmission gate TG10 are connected to the input terminal of the twelfth transmission gate TG12; the output terminals of the eleventh transmission gate TG11 and the twelfth transmission gate TG12 are connected to the input terminal of the thirteenth transmission gate TG13; the input terminal of the fourteenth transmission gate TG14 is grounded; and the output terminals of the thirteenth transmission gate TG13 and the fourteenth transmission gate TG14 are connected to the second drive output terminal E.

[0017] A second aspect of the present invention provides a PCB board on which a multi-stage voltage delay drive circuit as described above is printed.

[0018] The PCB board according to the second aspect of the present invention, having included the multi-stage voltage delay drive circuit of the above-described technical solution, also has corresponding beneficial effects.

[0019] A third aspect of the present invention provides a chip, wherein the chip employs a multi-stage voltage delay drive circuit as described above to achieve operation control.

[0020] The chip according to the third aspect embodiment of the present invention, since it includes the multi-stage voltage delay drive circuit of the above-described technical solution, also has corresponding beneficial effects. Attached Figure Description

[0021] Figure 1 This is a circuit block diagram of the multi-stage voltage delay drive circuit provided by the present invention;

[0022] Figure 2 This is a circuit diagram of the turn-on timing circuit of the present invention;

[0023] Figure 3 This is a circuit diagram of the turn-off phase timing circuit of the present invention;

[0024] Figure 4 This is a circuit diagram of the switching circuit for the turn-on voltage of the present invention;

[0025] Figure 5 This is a circuit diagram of the shutdown voltage switching circuit of the present invention;

[0026] Figure 6 This is a schematic diagram of the chip provided in an embodiment of the present invention;

[0027] The reference numerals in the attached diagram are: 1-External parameter input module, 2-Time information reading module, 3-Drive voltage adjustment module. Detailed Implementation

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments have been briefly explained above. Obviously, the described drawings are only a part of the embodiments of the present invention, and not all of them. Those skilled in the art can obtain other design schemes and drawings based on these drawings without creative effort.

[0029] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages mentioned herein do not simply refer to direct connection of components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0030] Reference Figures 1 to 5 The embodiments of the present invention are described below;

[0031] A first aspect of the present invention provides a multi-stage voltage delay drive circuit, comprising:

[0032] The system comprises an external parameter input module 1, a time information reading module 2, and a drive voltage adjustment module 3. The external parameter input module 1 is electrically connected to both the time information reading module 2 and the drive voltage adjustment module 3, and the time information reading module 2 is electrically connected to the drive voltage adjustment module 3. The external parameter input module 1 receives time configuration parameters and voltage reference parameters. The time information reading module 2 converts the time configuration parameters into digital time commands. The drive voltage adjustment module 3 outputs a gate drive voltage adapted to the IGBT switching characteristics in stages according to the digital time commands and the voltage reference parameters.

[0033] In this embodiment, firstly, the external parameter input module 1 can receive time configuration parameters and voltage reference parameters, providing a customized basis for control at different switching stages; secondly, the time information reading module 2 converts the time configuration parameters into digital time commands to ensure the timing accuracy of drive adjustment; finally, the drive voltage adjustment module 3 outputs gate drive voltages adapted to the IGBT switching characteristics in stages according to the digital time commands and voltage reference parameters, outputting high voltages in stages where faster switching is needed to reduce losses, and outputting matching voltages in stages where spikes need to be avoided; the multi-stage voltage delay drive circuit of this invention effectively balances the switching efficiency and operational safety of the IGBT through this dynamic staged adjustment method, significantly improving the practicality and reliability of the drive circuit, thereby ensuring the stable operation of the entire power system.

[0034] Specifically, the external parameter input module 1 includes a first high-level port TON1H, a first low-level port TON1L, a second high-level port TON2H, a second low-level port TON2L, a first high-level port TOFF1H, a first low-level port TOFF1L, a second high-level port TOFF2H, a second low-level port TOFF2L, an on-reference voltage port VONREF, and a off-reference voltage port VOFFREF. The first high-level port TON1H, the first low-level port TON1L, the second high-level port TON2H, the second low-level port TON2L, the first high-level port TOFF1H, the first low-level port TOFF1L, the second high-level port TOFF2H, and the second low-level port TOFF2L are all electrically connected to the time information reading module 2. The on-reference voltage port VONREF and the off-reference voltage port VOFFREF are electrically connected to the drive voltage adjustment module 3.

[0035] In this embodiment, the first high-level turn-on port TON1H, the first low-level turn-on port TON1L, the second high-level turn-on port TON2H, the second low-level turn-on port TON2L, the first high-level turn-off port TOFF1H, the first low-level turn-off port TOFF1L, the second high-level turn-off port TOFF2H, and the second low-level turn-off port TOFF2L are time configuration ports, and the analog voltage values ​​input to each port correspond to the delay parameters of different stages of IGBT switching.

[0036] The input voltages of the first high-level port TON1H, the second high-level port TON2H, the first high-level port TOFF1H, and the second high-level port TOFF2H correspond to the delay time in the tens digit; the input voltages of the first low-level port TON1L, the second low-level port TON2L, the first low-level port TOFF1L, and the second low-level port TOFF2L correspond to the delay time in the units digit.

[0037] For example, when configuring a delay TON1 for the first turn-on phase (the IC remains unchanged before IGBT turn-on), inputting 5V to the TON1H port and 4V to the TON1L port, combined with the 10MHz reference clock (minimum accuracy 0.1μs) of the time information reading module 2, we can calculate TON1 = (5×10+4)×0.1μs = 5.4μs; similarly, inputting 3V to the TON2H port and 2V to the TON2L port for the second turn-on phase (the IC rise phase during IGBT turn-on), we can obtain TON2 = (3×10+2)×0.1μs = 3.2μs; The configuration logic of TOFF1 (IC unchanged stage before shutdown) and TOFF2 (IC decreasing stage during shutdown) in the shutdown phase is the same. For example, if 4V is input to TOFF1H and 2V is input to TOFF1L, TOFF1 = (4×10+2)×0.1μs = 4.2μs can be obtained; if 3V is input to TOFF2H and 1V is input to TOFF2L, TOFF2 = (3×10+1)×0.1μs = 3.1μs can be obtained; The analog voltage signals output from each port are transmitted to the time information reading module 2 to provide raw parameters for subsequent digital time command conversion;

[0038] The VONREF and VOFFREF reference voltage ports are voltage reference ports. These two ports are used to input reference voltages adapted to the critical stages of IGBT switching, directly providing the voltage switching basis for the drive voltage regulation module 3. The VONREF port, through an external adjustable reference source, receives a voltage input (adjustable according to the IGBT model, typically 7-11V) to control the drive voltage during the IC rising phase of IGBT turn-on, suppressing current spikes. The VOFFREF port, through an external adjustable reference source, receives a voltage input (typically -5 to -9V) to control the drive voltage during the IC falling phase of IGBT turn-off, suppressing voltage overshoot. The voltage signals from both ports are directly transmitted to the turn-on and turn-off voltage switching circuits of the drive voltage regulation module 3, serving as the reference values ​​for the staged voltage output.

[0039] Specifically, the time information reading module 2 includes a channel selection module, a conversion module, a data processing module, and a data storage module, which are electrically connected in sequence; the data storage module is electrically connected to the drive voltage adjustment module 3; the channel selection module is electrically connected to the first high-level on port TON1H, the first low-level on port TON1L, the second high-level on port TON2H, the second low-level on port TON2L, the first high-level off port TOFF1H, the first low-level off port TOFF1L, the second high-level off port TOFF2H, and the second low-level off port TOFF2L, respectively; the channel selection module is used to sequentially turn on the channels according to time order. The first high-order port TON1H, the first low-order port TON1L, the second high-order port TON2H, the second low-order port TON2L, the first high-order port TOFF1H, the first low-order port TOFF1L, the second high-order port TOFF2H, and the second low-order port TOFF are configured to transmit the time configuration parameters provided by each port to the conversion module. The conversion module is used to convert the time configuration parameters into digital signals. The data processing module is used to perform a summation operation between the high and low orders of the digital signals to generate delay data. The data storage module is used to temporarily store the delay data and output it to the drive voltage adjustment module 3.

[0040] In this embodiment, the time information reading module 2, in conjunction with the reference clock provided by the external 10MHz oscillation circuit, achieves accurate processing of the parameters of the eight time configuration ports. The specific implementation method is as follows:

[0041] The channel selection module has eight built-in analog switches (corresponding to the first high-order port TON1H, the first low-order port TON1L, the second high-order port TON2H, the second low-order port TON2L, the first high-order port TOFF1H, the first low-order port TOFF1L, the second high-order port TOFF2H, and the second low-order port TOFF2L, respectively). Driven by internal timing control signals, the switches sequentially turn on each port in the order of "first the turn-on phase, then the turn-off phase; first the high-order ports, then the low-order ports." For example, in the first cycle... In the first cycle, the high-order port TON1H is activated; in the second cycle, the low-order port TON1L is activated; in the third cycle, the high-order port TON2H is activated; in the fourth cycle, the low-order port TON2L is activated; and in subsequent cycles, the high-order port TOFF1H, the low-order port TOFF1L, the high-order port TOFF2H, and the low-order port TOFF2L are activated sequentially. Only one port is activated at a time, and its input analog voltage-form time configuration parameters are transmitted separately to the conversion module to avoid crosstalk between multiple ports affecting accuracy.

[0042] The conversion module uses an eight-bit successive approximation A / D converter. Its input range matches the voltage input range of the time configuration port, which can convert the analog voltage signal transmitted by the channel selection module into an eight-bit binary digital signal. For example, when the input voltage is 5V, the A / D converter outputs the digital signal "00000101"; when the input voltage is 4V, it outputs the digital signal "00000100".

[0043] The data processing module has a built-in addition unit that performs summation operations on the converted digital signals.

[0044] During the activation phase, the digital signal corresponding to the first activation high-order port TON1H (high-order time parameter, 1 bit corresponds to 10 × 0.1 μs = 1 μs) is summed with the digital signal corresponding to the first activation low-order port TON1L (low-order time parameter, 1 bit corresponds to 1 × 0.1 μs = 0.1 μs) to generate the data for the first activation phase delay TON1 (e.g., “00000101” + “00000100” = “00001001”, corresponding to TON1 = (5 × 1 + 4 × 0.1) μs = 5.4 μs); similarly, the digital signal corresponding to the second activation high-order port TON2H and the second activation low-order port TON2L is summed. The digital signals are summed to generate the data for the second-stage turn-on delay TON2 (e.g., when TON2H=3V and TON2L=2V, the turn-on delay TON2=(3×1+2×0.1)μs=3.2μs). During the turn-off phase, the same logic is used: the digital signals of the first turn-off high-order port TOFF1H and the first turn-off low-order port TOFF1L are summed to generate the data for the first-stage turn-off delay TOFF1; the digital signals of the second turn-off high-order port TOFF2H and the second turn-off low-order port TOFF2L are summed to generate the data for the second-stage turn-off delay TOFF2. Finally, four complete sets of delay data are obtained.

[0045] The data storage module uses an eight-bit D-type latch to store the four sets of delayed data generated by the data processing module in four independent storage units. The enable terminal of the storage unit is synchronized with the timing signal of the drive voltage adjustment module 3. When the drive voltage adjustment module 3 (on / off stage timing circuit) needs to call the delayed data, the output terminal of the corresponding storage unit of the storage module is turned on, and the data of the first stage delay TON1 and the second stage delay TON2 are transmitted to the on stage timing circuit, and the data of the first stage delay TOFF1 and the second stage delay TOFF2 are transmitted to the off stage timing circuit, providing accurate digital time instructions for the generation of subsequent timing trigger signals.

[0046] Through the above process, the time information reading module 2 can accurately convert the externally input analog voltage parameters into digital time data that can be recognized by the drive voltage adjustment module 3. The entire process adopts time-division processing and group operation logic, which effectively ensures the processing accuracy and transmission reliability of the time parameters, and provides an accurate timing control basis for multi-level voltage delay drive.

[0047] Specifically, the drive voltage adjustment module 3 includes an on-phase timing circuit, an off-phase timing circuit, an on-phase voltage switching circuit, and an off-phase voltage switching circuit; the on-phase timing circuit and the on-phase reference voltage port VONREF are electrically connected to the on-phase voltage switching circuit; the off-phase timing circuit and the off-phase reference voltage port VOFFREF are electrically connected to the off-phase voltage switching circuit; the on-phase timing circuit and the off-phase timing circuit are used to read the delay data and generate corresponding timing trigger signals; the on-phase voltage switching circuit and the off-phase voltage switching circuit are used to output gate drive voltage according to the timing trigger signals.

[0048] In this embodiment, the core function of the drive voltage adjustment module 3 is to take the delayed data output by the time information reading module 2, first generate a timing signal through the timing circuit, and then output a voltage through the voltage switching circuit to adapt to the gate drive voltage that is compatible with the IGBT turn-on / turn-off characteristics.

[0049] During the IGBT turn-on process, the turn-on timing circuit first reads the turn-on-related delay data from the data storage module, and generates two sets of timing trigger signals, t1 and t2, according to preset time nodes, in conjunction with a 10MHz reference clock signal. The t1 signal indicates that the IGBT has entered the "IC rising phase" from the "IC constant phase", and the t2 signal indicates that the IGBT has entered the "IC steady phase" from the "IC rising phase". These two sets of signals are synchronously transmitted to the turn-on voltage switching circuit. The turn-on voltage switching circuit receives the reference voltage input from the turn-on reference voltage port VONREF, and outputs a dynamically adjusted drive voltage to the IGBT gate based on its internal logic to meet the voltage switching requirements during the turn-on process.

[0050] Similarly, during the IGBT turn-off process, the turn-off timing circuit reads the turn-off-related delay data from the data storage module and generates two sets of timing trigger signals, t3 and t4. The t3 signal indicates that the IGBT has entered the "IC decreasing phase" from the "IC unchanged phase", and the t4 signal indicates that the IGBT has entered the "IC zeroing phase" from the "IC decreasing phase". These two sets of signals are synchronously transmitted to the turn-off voltage switching circuit. The turn-off voltage switching circuit receives the reference voltage input from the turn-off reference voltage port VOFFREF and outputs a drive voltage to the IGBT emitter based on its internal logic to realize the voltage switching requirements during the turn-off process.

[0051] Specifically, the activation phase timing circuit includes a detection trigger EF0, a first eight-bit timer, a first selector array, a first eight-bit adder EF10, a first AND gate G1, a second AND gate G2, a first OR gate, and a first storage trigger EF9. The positive output of the detection trigger EF0 is connected to the reset terminal of the first eight-bit timer and the clock terminal of the first storage trigger EF9. The first eight-bit timer includes a first trigger EF1, a second trigger EF2, a third trigger EF3, a fourth trigger EF4, a fifth trigger EF5, a sixth trigger EF6, a seventh trigger EF7, and an eighth trigger EF8 connected in series. The first selector array includes eight first selectors. The control terminals of the eight first selectors are electrically connected to the data storage module and the output terminal of the first eight-bit adder EF10. The data input terminals of the eight first selectors are connected to the first storage trigger EF9. The first flip-flop EF1, the second flip-flop EF2, the third flip-flop EF3, the fourth flip-flop EF4, the fifth flip-flop EF5, the sixth flip-flop EF6, the seventh flip-flop EF7, and the eighth flip-flop EF8 are electrically connected; the data output terminals of the eight first selectors are connected to the input terminals of the first AND gate G1 and the second AND gate G2; the input terminal of the first eight-bit adder EF10 is connected to the data storage module; the output terminal of the first AND gate G1 is connected to the input terminal of the first storage flip-flop EF9, and the output terminal of the first storage flip-flop EF9 is connected to the turn-on voltage switching circuit; the output terminal of the second AND gate G2 is connected to the second input terminal of the first OR gate and the turn-on voltage switching circuit; the first input terminal of the first OR gate is connected to an external reference clock signal, and the output terminal of the first OR gate is connected to the clock terminal of the first eight-bit timer.

[0052] Specifically, the shutdown phase timing circuit includes a second 8-bit timer, a second selector array, a second 8-bit adder EF19, a third AND gate G3, a fourth AND gate G4, a second OR gate, and a second storage flip-flop EF20; the inverting output of the detection flip-flop EF0 is connected to the reset terminal of the second 8-bit timer and the clock terminal of the second storage flip-flop EF20, respectively; the second 8-bit timer includes an eleventh flip-flop EF11, a twelfth flip-flop EF12, a thirteenth flip-flop EF13, a fourteenth flip-flop EF14, a fifteenth flip-flop EF15, a sixteenth flip-flop EF16, a seventeenth flip-flop EF17, and an eighteenth flip-flop EF18 connected in series; the second selector array includes eight second selectors; the control terminals of the eight second selectors are electrically connected to the data storage module and the output terminal of the second 8-bit adder EF19, respectively; the data input terminals of the eight second selectors are connected to the eleventh flip-flop... EF11, the twelfth flip-flop EF12, the thirteenth flip-flop EF13, the fourteenth flip-flop EF14, the fifteenth flip-flop EF15, the sixteenth flip-flop EF16, the seventeenth flip-flop EF17, and the eighteenth flip-flop EF18 are electrically connected; the data output terminals of the eight second selectors are connected to the input terminals of the third AND gate G3 and the fourth AND gate G4; the input terminal of the second eight-bit adder EF19 is connected to the data storage module; the output terminal of the third AND gate G3 is connected to the input terminal of the second storage flip-flop EF20, and the output terminal of the second storage flip-flop EF20 is connected to the turn-on voltage switching circuit; the output terminal of the fourth AND gate G4 is connected to the second input terminal of the second OR gate and the turn-on voltage switching circuit; the first input terminal of the second OR gate is connected to the reference clock signal, and the output terminal of the second OR gate is connected to the clock terminal of the second eight-bit timer.

[0053] In this embodiment, the core function of the activation stage timing circuit is to convert activation-related delay data into t1 and t2 signals. Its working principle is as follows:

[0054] The detection trigger EF0 is a D-type trigger, and its input is connected to an external PWM drive instruction (the IGBT turn-on instruction when PWM=1). When PWM=1 is detected, the positive output (Q terminal) of EF0 outputs a high level, which is divided into two paths: one path is transmitted to the reset terminal of the first eight-bit timer to release the initial reset state of the first eight-bit timer (when the reset terminal is high, the timer can respond to the clock signal); the other path is transmitted to the clock terminal of the first storage trigger EF9 to provide a clock synchronization reference for the subsequent latching of the t1 signal. At the same time, the first input terminal of the first OR gate is connected to a 10MHz external reference clock signal. At this time, since the second AND gate G2 has not yet output a high level (t2=0), the first OR gate only transmits the 10MHz clock signal to the clock terminal of the first eight-bit timer (i.e., the CP terminal of each trigger EF1~EF8), triggering the first eight-bit timer to start counting.

[0055] The first eight-bit timer consists of eight series-connected T-type flip-flops (first flip-flop EF1 to eighth flip-flop EF8). Driven by a 10MHz clock, it operates according to binary counting rules: the first flip-flop EF1 is the least significant bit (LSB), and its output toggles once for each clock pulse received; the eighth flip-flop EF8 is the most significant bit (MSB), and its output toggles once for every eight clock pulses received. The outputs of the eight flip-flops (Q1 to Q8) together form an eight-bit binary counting signal (Q<7:0>), which reflects the current cumulative counting time in real time (e.g., when the count is "00001011", the corresponding counting time = 11 × 0.1μs = 1.1μs).

[0056] The two input terminals of the first eight-bit adder EF10 read the first-stage delay TON1 (e.g., 5.4μs, corresponding to the digital signal "00101011") and the second-stage delay TON2 (e.g., 3.2μs, corresponding to the digital signal "00011010") from the data storage module, respectively. The total delay TO = TON1 + TON2 = 8.6μs is generated through addition, corresponding to the digital signal "01000110", and the signal is transmitted to one of the control terminals of the first selector array.

[0057] The first selector array contains eight selectors (MUX1~MUX8). The two data input terminals of each selector are respectively connected to the output signal (Q) and the inverted signal (Qn) of the corresponding T flip-flop (e.g., MUX1 is connected to Q1 and Qn1 of the first flip-flop EF1, and MUX8 is connected to Q8 and Qn8 of the eighth flip-flop EF8). The control terminals of the first selector array are divided into two groups: one group is connected to the digital signal output by the data storage module (to enable the first stage delay TON1), which is used to match the "TON1 timing node"; the other group is connected to the digital signal output by the first eight-bit adder EF10 (total delay TO), which is used to match the "TO timing node". The first selector array determines whether to output Q or Qn by the level of the control terminal: when the control terminal is high, it outputs the Q signal; when it is low, it outputs the Qn signal. Finally, the eight selectors output eight matching signals (S1<7:0>) for the "TON1 node" and eight matching signals (S2<7:0>) for the "TO node", and transmit them to the input terminals of the first AND gate G1 and the second AND gate G2 respectively.

[0058] Generation and latching of the t1 signal: When the counting signal Q<7:0> of the first eight-bit timer is fully matched with the turn-on first stage delay TON1 (S1<7:0>), the first AND gate G1 outputs a high level; this high level is transmitted to the input terminal (D terminal) of the first storage flip-flop EF9. At this time, the clock terminal of the first storage flip-flop EF9 has been synchronized by the high level output of the detection flip-flop EF0. Therefore, the output terminal (Q terminal) of the first storage flip-flop EF9 latches the high level and continues to output, that is, generates the t1=1 signal (marking that the IGBT has entered the "IC rising stage" from the "IC unchanged stage"), and transmits the t1 signal synchronously to the turn-on voltage switching circuit;

[0059] Generation of the t2 signal: When the counting signal Q<7:0> of the first eight-bit timer is fully matched with the total delay TO (S2<7:0>), the second AND gate G2 outputs a high level, which generates the t2=1 signal (marking that the IGBT has entered the "IC steady stage" from the "IC rising stage"). This high level is divided into two paths: one path is transmitted to the turn-on voltage switching circuit as the trigger signal for the second stage voltage switching; the other path is transmitted to the second input of the first OR gate. At this time, the first OR gate still maintains a 10MHz clock signal output to ensure that the timer continues to count until the turn-on ends.

[0060] In this embodiment, the core function of the shutdown phase timing circuit is to convert the shutdown-related delay data into t3 and t4 signals. Its working principle is as follows:

[0061] When the external PWM instruction becomes 0 (IGBT turn-off instruction), the inverting output terminal (Qn terminal) of the detection flip-flop EF0 outputs a high level (Q terminal outputs a low level, opposite to the turn-on phase); this high level is divided into two paths: one path is transmitted to the reset terminal of the second 8-bit timer to release its initial reset state; the other path is transmitted to the clock terminal of the second storage flip-flop EF20 to provide a synchronization reference for the latching of the t3 signal; at the same time, the first input terminal of the second OR gate is connected to a 10MHz external reference clock signal (shared with the turn-on phase). Since the fourth AND gate G4 has not yet output a high level (t4=0), the second OR gate transmits the 10MHz clock signal to the clock terminal of the second 8-bit timer (CP terminal of the eleventh flip-flop EF11 to the eighteenth flip-flop EF18), triggering the second 8-bit timer to start counting;

[0062] The second eight-bit timer consists of eight series-connected T-type flip-flops (EF11~EF18). Its counting logic is the same as that of the first eight-bit timer. Its output (Q11~Q18) forms an eight-bit binary counting signal (Q'<7:0>), which reflects the cumulative timing duration during the off-phase.

[0063] The two input terminals of the second 8-bit adder EF19 read the first stage delay TOFF1 (e.g., 4.2μs, corresponding to the digital signal "00100010") and the second stage delay TOFF2 (e.g., 3.1μs, corresponding to the digital signal "00011111") from the data storage module, generate the total delay TC=TOFF1+TOFF2 (e.g., 7.3μs, corresponding to the digital signal "00111011") through addition, and transmit it to a set of control terminals of the second selector array;

[0064] The second selector array contains eight 1-to-2 selectors (MUX9~MUX16). The data input of each selector is connected to the Q and Qn signals of the corresponding eleventh flip-flop EF11~eighteenth flip-flop EF18. The control terminals of the second selector array are divided into two groups: one group is connected to the digital signal output by the data storage module (turning off the first stage delay TOFF1), used to match the "TOFF1 timing node"; the other group is connected to the digital signal output by the first eight-bit adder EF10 (total delay TC), used to match the "TC timing node". The selector determines whether to output Q or Qn by the level of the control terminal: when the selector control terminal is high, it outputs the Q signal; when it is low, it outputs the Qn signal. Finally, the eight selectors output eight matching signals S3<7:0> for the "TOFF1 node" and eight matching signals S4<7:0> for the "TC node", and transmit them to the input terminals of the third AND gate G3 and the fourth AND gate G4, respectively.

[0065] Generation and latching of the t3 signal: When the counting signal Q'<7:0> of the second eight-bit timer is fully matched with the first stage turn-off delay TOFF1 (S3<7:0>), the third AND gate G3 outputs a high level; this high level is transmitted to the input (D terminal) of the second storage flip-flop EF20, and combined with the clock synchronization signal of the inverted output (Qn) of the detection flip-flop EF0, the output of the second storage flip-flop EF20 latches the high level, generating the t3=1 signal (marking that the IGBT has entered the "IC falling stage" from the "IC unchanged stage"), and is transmitted to the turn-off voltage switching circuit;

[0066] Generation of the t4 signal: When the counting signal Q'<7:0> of the second eight-bit timer is perfectly matched with the total delay TC (S4<7:0>), the fourth AND gate G4 outputs a high level, that is, the t4=1 signal is generated; the t4 signal is divided into two paths: one path is transmitted to the shutdown voltage switching circuit to control the voltage switching of the second stage of shutdown; the other path is transmitted to the second input of the second OR gate to maintain the clock signal driving the timer until the shutdown process ends.

[0067] Specifically, the turn-on voltage switching circuit includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5, a sixth transmission gate TG6, a seventh transmission gate TG7, a power supply voltage terminal VCC, and a first drive output terminal G; the power supply voltage terminal VCC is connected to the input terminals of the first transmission gate TG1 and the second transmission gate TG2; the turn-on reference voltage port VONREF is connected to the input terminal of the third transmission gate TG3; the output terminal of the second AND gate G2 is connected to the control terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3; the output terminal of the first storage trigger EF9 is connected to the fourth transmission gate TG7. The control terminal of 4 is connected to the control terminal of the fifth transmission gate TG5; the output terminal of the detection trigger EF0 is connected to the control terminal of the sixth transmission gate TG6 and the control terminal of the seventh transmission gate TG7; the output terminal of the first transmission gate TG1 is connected to the input terminal of the fourth transmission gate TG4; the output terminals of the second transmission gate TG2 and the third transmission gate TG3 are connected to the input terminal of the fifth transmission gate TG5; the output terminals of the fourth transmission gate TG4 and the fifth transmission gate TG5 are connected to the input terminal of the sixth transmission gate TG6; the input terminal of the seventh transmission gate TG7 is grounded; and the output terminals of the sixth transmission gate TG6 and the seventh transmission gate TG7 are connected to the first drive output terminal G.

[0068] Specifically, the shutdown voltage switching circuit includes an eighth transmission gate TG8, a ninth transmission gate TG9, a tenth transmission gate TG10, an eleventh transmission gate TG11, a twelfth transmission gate TG12, a thirteenth transmission gate TG13, a fourteenth transmission gate TG14, and a second drive output terminal E; the power supply voltage terminal VCC is connected to the input terminals of the eighth transmission gate TG8 and the ninth transmission gate TG9; the shutdown reference voltage port VOFFREF is connected to the input terminal of the tenth transmission gate TG10; the output terminal of the fourth AND gate G4 is connected to the control terminals of the eighth transmission gate TG8, the ninth transmission gate TG9, and the tenth transmission gate TG10; the output terminal of the second storage trigger EF20 is connected to the control terminal of the eleventh transmission gate TG11 and the... The control terminal of the fifth transmission gate TG5 is connected; the output terminal of the detection trigger EF0 is connected to the control terminals of the thirteenth transmission gate TG13 and the fourteenth transmission gate TG14; the output terminal of the eighth transmission gate TG8 is connected to the input terminal of the eleventh transmission gate TG11; the output terminals of the ninth transmission gate TG9 and the tenth transmission gate TG10 are connected to the input terminal of the twelfth transmission gate TG12; the output terminals of the eleventh transmission gate TG11 and the twelfth transmission gate TG12 are connected to the input terminal of the thirteenth transmission gate TG13; the input terminal of the fourteenth transmission gate TG14 is grounded; and the output terminals of the thirteenth transmission gate TG13 and the fourteenth transmission gate TG14 are connected to the second drive output terminal E.

[0069] In this embodiment, the turn-on voltage switching circuit and the turn-off voltage switching circuit receive the t1 and t2 signals output by the turn-on stage timing circuit and the t3 and t4 signals output by the turn-off stage timing circuit, respectively. Combined with the voltage inputs from the power supply voltage terminal VCC, the turn-on reference voltage port VONREF, and the turn-off reference voltage port VOFFREF, and according to the characteristic requirements of different IGBT switching stages, they output adaptive drive voltages to the first drive output terminal G (IGBT gate) and the second drive output terminal E (IGBT emitter). The specific circuit working principle is as follows:

[0070] First, regarding the switching circuit for power-on:

[0071] Control signal sources: The output of the second AND gate G2 corresponds to the t2 signal (high level is t2=1, low level is t2=0), the output of the first storage flip-flop EF9 corresponds to the t1 signal (high level is t1=1, low level is t1=0), and the output of the detection flip-flop EF0 corresponds to the PWM_G signal (high level when PWM=1, i.e., the enable signal during the turn-on phase).

[0072] Voltage input sources: VCC input 15V (for IGBT fast switching requirements), VONREF input 9V (for IC rise phase control di / dt requirements), and TG7 input grounded (0V, only for use in non-on phase).

[0073] The specific connection methods of each transmission gate in the turn-on voltage switching circuit are as follows:

[0074] The input terminal of the first transmission gate TG1 is connected to the power supply voltage terminal VCC, and the output terminal is connected to the input terminal of the fourth transmission gate TG4. The first control terminal of the first transmission gate TG1 receives the t2n signal (the inverted signal of t2), and the second control terminal of the first transmission gate TG1 receives the t2 signal through an inverter; that is, when t2=1, the first transmission gate TG1 is turned off, and when t2=0, the first transmission gate TG1 is turned on.

[0075] The input terminal of the second transmission gate TG2 is connected to the power supply voltage terminal VCC, and the output terminal is connected to the input terminal of the fifth transmission gate TG5. The first control terminal of the second transmission gate TG2 receives the t2 signal, and the second control terminal of the first transmission gate TG1 receives the t2n signal (the inverse signal of t2) through an inverter; that is, when t2=1, the second transmission gate TG2 is turned on, and when t2=0, the second transmission gate TG2 is turned off.

[0076] The input of the third transmission gate TG3 is connected to the on-reference voltage port VONREF, and the output is connected to the input of the fifth transmission gate TG5. The first control terminal of the third transmission gate TG3 receives the t2n signal (the inverted signal of t2), and the second control terminal of the third transmission gate TG3 receives the t2 signal through an inverter; that is, when t2=1, the third transmission gate TG3 is off, and when t2=0, the third transmission gate TG3 is on.

[0077] The output of the fourth transmission gate TG4 is connected to the input of the sixth transmission gate TG6. The first control terminal of the fourth transmission gate TG4 receives the t1n signal (the inverted signal of t1), and the second control terminal of the fourth transmission gate TG4 receives the t1 signal through an inverter. That is, when t1=1, the fourth transmission gate TG4 is turned off, and when t1=0, the fourth transmission gate TG4 is turned on.

[0078] The output of the fifth transmission gate TG5 is connected to the input of the sixth transmission gate TG6. The first control terminal of the fifth transmission gate TG5 receives the t1 signal, and the second control terminal of the fourth transmission gate TG4 receives the t1n signal (the inverted signal of t1) through an inverter. That is, when t1=1, the fifth transmission gate TG5 is turned on, and when t1=0, the fifth transmission gate TG5 is turned off.

[0079] The input terminal of the sixth transmission gate TG6 is connected to the first drive output terminal G, the first control terminal of the sixth transmission gate TG6 is connected to the PWM signal (PWM_G), and the second control terminal of the sixth transmission gate TG6 is connected to the PWM inverted signal (PWM_Gn) through an inverter; that is, when PWM=1, the sixth transmission gate TG6 is turned on, and when PWM=0, the sixth transmission gate TG6 is turned off.

[0080] The input terminal of the seventh transmission gate TG7 is grounded, and the output terminal is connected to the first drive output terminal G. The first control terminal of the seventh transmission gate TG7 is connected to the PWM inverting signal (PWM_Gn), and the second control terminal of the seventh transmission gate TG7 is connected to the PWM signal (PWM_G) through an inverter. That is, when PWM=1, the seventh transmission gate TG7 is turned off, and when PWM=0, the seventh transmission gate TG7 is turned on.

[0081] The voltage switching control during the turn-on phase is divided into the following three stages:

[0082] Phase 1: The IC remains unchanged during the IGBT turn-on process. At this time, t1=0, t2=0, and PWM=1. The first transmission gate TG1, the fourth transmission gate TG4, and the sixth transmission gate TG6 are turned on. The power supply voltage VCC is output to the first drive output terminal G (IGBT gate) through the first transmission gate TG1, the fourth transmission gate TG4, and the sixth transmission gate TG6, i.e., VG=VCC=15V.

[0083] Phase 2, the IC rising phase of the IGBT turn-on process, at which time t1=1, t2=0, PWM=1; the third transmission gate TG3, the fifth transmission gate TG5, and the sixth transmission gate TG6 are turned on, and the voltage of the reference voltage port VONREF is output to the first drive output terminal G (IGBT gate) through the third transmission gate TG3, the fifth transmission gate TG5, and the sixth transmission gate TG6, that is, VG=VONREF;

[0084] Phase 3, the IC steady-state phase of the IGBT turn-on process, at which time t1=1, t2=1, PWM=1; the second transmission gate TG2, the fifth transmission gate TG5, and the sixth transmission gate TG6 are turned on, and the power supply voltage VCC is output to the first drive output terminal G (IGBT gate) through the second transmission gate TG2, the fifth transmission gate TG5, and the sixth transmission gate TG6, that is, VG=VCC=15V;

[0085] When PWM=0 (non-on stage), the sixth transmission gate TG6 is cut off and the seventh transmission gate TG7 is turned on. At this time, the first drive output terminal G is grounded through the seventh transmission gate TG7, and VG=0V.

[0086] Secondly, regarding the shutdown voltage switching circuit:

[0087] Control signal sources: The output of the fourth AND gate G4 corresponds to the t4 signal (high level is t4=1, low level is t4=0), the output of the second storage flip-flop EF20 corresponds to the t3 signal (high level is t3=1, low level is t3=0), and the inverted output of the detection flip-flop EF0 corresponds to the PWM_G signal (low level when PWM=0, i.e., the enable signal during the turn-off phase).

[0088] Voltage input sources: VCC input 15V (for IGBT fast switching requirements), VOFFREF input -7V for turn-off reference voltage, and grounded input of the fourteenth transmission gate TG14 (0V, only for use during non-turn-off phase).

[0089] The specific connection methods of each transmission gate in the shutdown voltage switching circuit are as follows:

[0090] The input terminal of the eighth transmission gate TG8 is connected to the power supply voltage terminal VCC, and the output terminal is connected to the input terminal of the eleventh transmission gate TG11. The first control terminal of the eighth transmission gate TG8 receives the t4n signal (the inverted signal of t4), and the second control terminal of the eighth transmission gate TG8 receives the t4 signal through an inverter; that is, when t4=1, the eighth transmission gate TG8 is turned off, and when t4=0, the eighth transmission gate TG8 is turned on.

[0091] The input terminal of the ninth transmission gate TG9 is connected to the power supply voltage terminal VCC, and the output terminal is connected to the input terminal of the twelfth transmission gate TG12. The first control terminal of the ninth transmission gate TG9 receives the t4 signal, and the second control terminal of the ninth transmission gate TG9 receives the t4n signal (the inverted signal of t4) through an inverter; that is, when t4=1, the ninth transmission gate TG9 is turned on, and when t4=0, the ninth transmission gate TG9 is turned off.

[0092] The input of the tenth transmission gate TG10 is connected to the off reference voltage port VOFFREF, and the output is connected to the input of the twelfth transmission gate TG12. The first control terminal of the tenth transmission gate TG10 receives the t4n signal (the inverted signal of t4), and the second control terminal of the tenth transmission gate TG10 receives the t4 signal through an inverter; that is, when t4=1, the tenth transmission gate TG10 is off, and when t4=0, the tenth transmission gate TG10 is on.

[0093] The output of the eleventh transmission gate TG11 is connected to the input of the thirteenth transmission gate TG13. The first control terminal of the eleventh transmission gate TG11 receives the t3n signal (the inverted signal of t3), and the second control terminal of the eleventh transmission gate TG11 receives the t3 signal through an inverter. That is, when t3=1, the eleventh transmission gate TG11 is turned off, and when t3=0, the eleventh transmission gate TG11 is turned on.

[0094] The output of the twelfth transmission gate TG12 is connected to the input of the thirteenth transmission gate TG13. The first control terminal of the twelfth transmission gate TG12 receives the t3 signal, and the second control terminal of the twelfth transmission gate TG12 receives the t3n signal (the inverted signal of t3) through an inverter. That is, when t3=1, the twelfth transmission gate TG12 is turned on, and when t3=0, the twelfth transmission gate TG12 is turned off.

[0095] The input terminal of the thirteenth transmission gate TG13 is connected to the second drive output terminal E. The first control terminal of the thirteenth transmission gate TG13 is connected to the PWM inverting signal (PWM_Gn). The second control terminal of the thirteenth transmission gate TG13 is connected to the PWM signal (PWM_G) through an inverter. That is, when PWM=1, the thirteenth transmission gate TG13 is turned off, and when PWM=0, the thirteenth transmission gate TG13 is turned on.

[0096] The input terminal of the fourteenth transmission gate TG14 is grounded, and the output terminal is connected to the second drive output terminal E. The first control terminal of the fourteenth transmission gate TG14 is connected to the PWM signal (PWM_G), and the second control terminal of the fourteenth transmission gate TG14 is connected to the PWM inverted signal (PWM_Gn) through an inverter. That is, when PWM=1, the fourteenth transmission gate TG14 is turned on, and when PWM=0, the fourteenth transmission gate TG14 is turned off.

[0097] The voltage switching control during the shutdown phase consists of the following three stages:

[0098] Phase 1, the IC remains unchanged during the IGBT turn-off process. At this time, t3=0, t4=0, and PWM=0. The eighth transmission gate TG8, the eleventh transmission gate TG11, and the thirteenth transmission gate TG13 are turned on. The power supply voltage VCC is output to the second drive output terminal E (IGBT emitter) through the eighth transmission gate TG8, the eleventh transmission gate TG11, and the thirteenth transmission gate TG13, i.e., VE=VCC=15V.

[0099] Phase 2, the IC falling phase of the IGBT turn-off process, at which time t3=1, t4=0, PWM=0; the tenth transmission gate TG10, the twelfth transmission gate TG12, and the thirteenth transmission gate TG13 are turned on, and the voltage of the turn-off reference voltage port VOFFREF is output to the second drive output terminal E (IGBT emitter) through the tenth transmission gate TG10, the twelfth transmission gate TG12, and the thirteenth transmission gate TG13, that is, VE=VOFFREF;

[0100] Phase 3, the IC zeroing stage of the IGBT turn-off process, at this time t3=1, t4=1, PWM=0; the ninth transmission gate TG9, the twelfth transmission gate TG12, and the thirteenth transmission gate TG13 are turned on, and the power supply voltage VCC is output to the second drive output terminal E (IGBT emitter) through the ninth transmission gate TG9, the twelfth transmission gate TG12, and the thirteenth transmission gate TG13, that is, VE=VCC=15V;

[0101] When PWM=1 (non-shutdown phase), the thirteenth transmission gate TG13 is turned off and the fourteenth transmission gate TG14 is turned on. At this time, the second drive output terminal E is grounded through the fourteenth transmission gate TG14, and VE=0V.

[0102] A second aspect of the present invention provides a PCB board on which a multi-stage voltage delay drive circuit as described above is printed.

[0103] Reference Figure 6 A third aspect of the present invention provides a chip, the chip including any of the multi-stage voltage delay drive circuits described above.

[0104] In this embodiment, the chip is an HVIC chip, which specifically includes:

[0105] Multi-level voltage delay drive module 0101 (i.e., multi-level voltage delay drive circuit);

[0106] 10MHz oscillation circuit 0102 (serves as the timing reference source of the chip, providing a 10MHz clock signal to the turn-on / turn-off timing circuit of the multi-level voltage delay drive module 0101);

[0107] Schmitt threshold circuit 0103 (The Schmitt threshold circuit performs level shaping on the input PWM drive signal to eliminate signal edge jitter).

[0108] Filter circuit 0104 (adopts RC low-pass filter structure to filter the analog voltage signal at the external parameter input port, suppress voltage fluctuations caused by external electromagnetic interference, and ensure the stability of input parameters).

[0109] VREG / VCC level conversion circuit (converts the externally input 5V logic voltage into the 15V drive voltage required by the chip).

[0110] Undervoltage protection circuit 0105 (real-time monitoring of the 15V supply voltage output by the VREG / VCC level conversion circuit; when the voltage is lower than the undervoltage threshold, it outputs an undervoltage fault signal to the fault logic circuit 0109, triggering the multi-level voltage delay drive module 0101 to stop outputting the drive voltage).

[0111] Temperature protection circuit 0106 (integrated internal temperature sensor, real-time acquisition of chip junction temperature, when the junction temperature exceeds the overheating threshold, outputs an overheating fault signal to fault logic circuit 0109, and controls drive output circuit 0110 to cut off IGBT drive signal through fault logic circuit to prevent chip and IGBT from being damaged due to high temperature).

[0112] Fault output circuit 0107 (outputs a high-level fault signal to the external control system to realize external reporting of the fault status, which facilitates the system to troubleshoot and reset the fault).

[0113] ITRIP overcurrent protection circuit 0108 (monitors the collector current of the IGBT through a sampling resistor. When the collector current exceeds the set threshold, it outputs an overcurrent fault signal to the fault logic circuit 0109 to quickly cut off the drive signal and prevent the IGBT from burning out due to overcurrent).

[0114] Fault logic circuit 0109 (The fault logic circuit receives fault signals such as undervoltage, overheating, and overcurrent, and determines whether to trigger protection action. As long as any fault signal is valid, it immediately controls the multi-stage voltage delay drive module to stop driving).

[0115] The drive output circuit 0110 receives the gate drive voltage and emitter drive voltage output by the multi-level voltage delay drive module 0101, amplifies the drive signal through a high-voltage DMOS transistor, and outputs it to the gate and emitter of the IGBT respectively.

[0116] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A multi-stage voltage delay drive circuit, characterized by, include: The system includes an external parameter input module, a time information reading module, and a drive voltage adjustment module; the external parameter input module is electrically connected to both the time information reading module and the drive voltage adjustment module, and the time information reading module is electrically connected to the drive voltage adjustment module. The external parameter input module is used to receive time configuration parameters and voltage reference parameters; The time information reading module includes a channel selection module, a conversion module, a data processing module, and a data storage module that are electrically connected in sequence; the conversion module is used to convert the time configuration parameters into digital signals; the data processing module is used to perform a summation operation between the high and low bits of the digital signals to generate delayed data; The data storage module is used to temporarily store the delay data and output it to the drive voltage regulation module; The drive voltage adjustment module is used to output a gate drive voltage adapted to the IGBT switching characteristics in stages according to the digital signal and the voltage reference parameters. The drive voltage regulation module includes an on-phase timing circuit, an off-phase timing circuit, an on-phase voltage switching circuit, and an off-phase voltage switching circuit. The activation phase timing circuit includes a detection trigger EF0, a first eight-bit timer, a first selector array, a first eight-bit adder EF10, a first AND gate G1, a second AND gate G2, a first OR gate, and a first storage trigger EF9. The positive output terminal of the detection trigger EF0 is connected to the reset terminal of the first eight-bit timer and the clock terminal of the first storage trigger EF9, respectively. The first eight-bit timer includes a first flip-flop EF1, a second flip-flop EF2, a third flip-flop EF3, a fourth flip-flop EF4, a fifth flip-flop EF5, a sixth flip-flop EF6, a seventh flip-flop EF7, and an eighth flip-flop EF8 connected in series. The first selector array includes eight first selectors; the control terminals of the eight first selectors are electrically connected to the data storage module and the output terminal of the first eight-bit adder EF10, respectively; the data input terminals of the eight first selectors are electrically connected to the first flip-flop EF1, the second flip-flop EF2, the third flip-flop EF3, the fourth flip-flop EF4, the fifth flip-flop EF5, the sixth flip-flop EF6, the seventh flip-flop EF7, and the eighth flip-flop EF8, respectively; the data output terminals of the eight first selectors are connected to the input terminals of the first AND gate G1 and the second AND gate G2. The input of the first eight-bit adder EF10 is connected to the data storage module; The output of the first AND gate G1 is connected to the input of the first storage flip-flop EF9, and the output of the first storage flip-flop EF9 is connected to the turn-on voltage switching circuit; the output of the second AND gate G2 is connected to the second input of the first OR gate and the turn-on voltage switching circuit. The first input terminal of the first OR gate is connected to an external reference clock signal, and the output terminal of the first OR gate is connected to the clock terminal of the first eight-bit timer.

2. The multi-stage voltage delay drive circuit according to claim 1, characterized in that: The external parameter input module includes a first high-level on port TON1H, a first low-level on port TON1L, a second high-level on port TON2H, a second low-level on port TON2L, a first high-level off port TOFF1H, a first low-level off port TOFF1L, a second high-level off port TOFF2H, a second low-level off port TOFF2L, an on reference voltage port VONREF, and a off reference voltage port VOFFREF. The first high-level on port TON1H, the first low-level on port TON1L, the second high-level on port TON2H, the second low-level on port TON2L, the first high-level off port TOFF1H, the first low-level off port TOFF1L, the second high-level off port TOFF2H, and the second low-level off port TOFF2L are all electrically connected to the time information reading module. The on reference voltage port VONREF and the off reference voltage port VOFFREF are electrically connected to the drive voltage adjustment module.

3. The multi-stage voltage delay drive circuit according to claim 2, characterized in that: The data storage module is electrically connected to the drive voltage adjustment module; the channel selection module is electrically connected to the first high-level port TON1H, the first low-level port TON1L, the second high-level port TON2H, the second low-level port TON2L, the first high-level port TOFF1H, the first low-level port TOFF1L, the second high-level port TOFF2H, and the second low-level port TOFF2L, respectively; the channel selection module is used to sequentially turn on the first high-level port TON1H, the first low-level port TON1L, the second high-level port TON2H, the second low-level port TON2L, the first high-level port TOFF1H, the first low-level port TOFF1L, the second high-level port TOFF2H, and the second low-level port TOFF2L in chronological order, so as to transmit the time configuration parameters provided by each port to the conversion module.

4. The multi-stage voltage delay drive circuit according to claim 3, characterized in that: The turn-on timing circuit and the turn-on reference voltage port VONREF are electrically connected to the turn-on voltage switching circuit; the turn-off timing circuit and the turn-off reference voltage port VOFFREF are electrically connected to the turn-off voltage switching circuit; the turn-on timing circuit and the turn-off timing circuit are used to read the delay data and generate corresponding timing trigger signals; the turn-on voltage switching circuit and the turn-off voltage switching circuit are used to output gate drive voltage according to the timing trigger signals.

5. The multi-stage voltage delay drive circuit according to claim 4, characterized in that: The shutdown phase timing circuit includes a second eight-bit timer, a second selector array, a second eight-bit adder EF19, a third AND gate G3, a fourth AND gate G4, a second OR gate, and a second storage flip-flop EF20. The inverted output terminal of the detection trigger EF0 is connected to the reset terminal of the second eight-bit timer and the clock terminal of the second storage trigger EF20, respectively. The second eight-bit timer includes the eleventh flip-flop EF11, the twelfth flip-flop EF12, the thirteenth flip-flop EF13, the fourteenth flip-flop EF14, the fifteenth flip-flop EF15, the sixteenth flip-flop EF16, the seventeenth flip-flop EF17, and the eighteenth flip-flop EF18 connected in series. The second selector array includes eight second selectors; the control terminals of the eight second selectors are electrically connected to the output terminals of the data storage module and the second eight-bit adder EF19, respectively; the data input terminals of the eight second selectors are electrically connected to the eleventh flip-flop EF11, the twelfth flip-flop EF12, the thirteenth flip-flop EF13, the fourteenth flip-flop EF14, the fifteenth flip-flop EF15, the sixteenth flip-flop EF16, the seventeenth flip-flop EF17, and the eighteenth flip-flop EF18, respectively; the data output terminals of the eight second selectors are connected to the input terminals of the third AND gate G3 and the fourth AND gate G4. The input of the second eight-bit adder EF19 is connected to the data storage module; The output of the third AND gate G3 is connected to the input of the second storage flip-flop EF20, and the output of the second storage flip-flop EF20 is connected to the turn-on voltage switching circuit; the output of the fourth AND gate G4 is connected to the second input of the second OR gate and the turn-on voltage switching circuit. The first input of the second OR gate is connected to the reference clock signal, and the output of the second OR gate is connected to the clock terminal of the second eight-bit timer.

6. The multi-stage voltage delay drive circuit according to claim 5, characterized in that: The turn-on voltage switching circuit includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5, a sixth transmission gate TG6, a seventh transmission gate TG7, a power supply voltage terminal VCC, and a first drive output terminal G; The power supply voltage terminal VCC is connected to the input terminals of the first transmission gate TG1 and the second transmission gate TG2; the turn-on reference voltage port VONREF is connected to the input terminal of the third transmission gate TG3; the output terminal of the second AND gate G2 is connected to the control terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3; the output terminal of the first storage trigger EF9 is connected to the control terminals of the fourth transmission gate TG4 and the fifth transmission gate TG5; the output terminal of the detection trigger EF0 is connected to the control terminals of the sixth transmission gate TG6 and the seventh transmission gate TG7; the output terminal of the first transmission gate TG1 is connected to the input terminal of the fourth transmission gate TG4; the output terminals of the second transmission gate TG2 and the third transmission gate TG3 are connected to the input terminal of the fifth transmission gate TG5; the output terminals of the fourth transmission gate TG4 and the fifth transmission gate TG5 are connected to the input terminal of the sixth transmission gate TG6; the input terminal of the seventh transmission gate TG7 is grounded; and the output terminals of the sixth transmission gate TG6 and the seventh transmission gate TG7 are connected to the first drive output terminal G.

7. The multi-stage voltage delay drive circuit according to claim 6, characterized in that: The shutdown voltage switching circuit includes an eighth transmission gate TG8, a ninth transmission gate TG9, a tenth transmission gate TG10, an eleventh transmission gate TG11, a twelfth transmission gate TG12, a thirteenth transmission gate TG13, a fourteenth transmission gate TG14, and a second drive output terminal E; The power supply voltage terminal VCC is connected to the input terminals of the eighth transmission gate TG8 and the ninth transmission gate TG9; the shutdown reference voltage port VOFFREF is connected to the input terminal of the tenth transmission gate TG10; the output terminal of the fourth AND gate G4 is connected to the control terminals of the eighth transmission gate TG8, the ninth transmission gate TG9, and the tenth transmission gate TG10; the output terminal of the second storage trigger EF20 is connected to the control terminal of the eleventh transmission gate TG11 and the control terminal of the fifth transmission gate TG5; the output terminal of the detection trigger EF0 is connected to the control terminal of the thirteenth transmission gate TG13 and the input terminal of the fifth transmission gate TG5. The control terminal of the fourteenth transmission gate TG14 is connected; the output terminal of the eighth transmission gate TG8 is connected to the input terminal of the eleventh transmission gate TG11; the output terminals of the ninth transmission gate TG9 and the tenth transmission gate TG10 are connected to the input terminal of the twelfth transmission gate TG12; the output terminals of the eleventh transmission gate TG11 and the twelfth transmission gate TG12 are connected to the input terminal of the thirteenth transmission gate TG13; the input terminal of the fourteenth transmission gate TG14 is grounded; and the output terminals of the thirteenth transmission gate TG13 and the fourteenth transmission gate TG14 are connected to the second drive output terminal E.

8. A PCB board, characterized in that, The PCB board is printed with a multi-level voltage delay drive circuit as described in any one of claims 1-7.

9. A chip, characterized in that, The chip includes a multi-stage voltage delay drive circuit as described in any one of claims 1-7.

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