A multi-code general decoding method, system, device and medium based on a memory-computing integrated device

Abstract

The application relates to a multi-code general decoding method, system, device and medium based on a memory-computing integrated device, which comprises the following steps: representing the common features of different types of decoding tasks in a probabilistic graph model; obtaining the initial log-likelihood ratio of each variable node in the probabilistic graph model corresponding to different types of to-be-decoded data; constructing a general memory-computing integrated device array containing different types of decoding arrays, and respectively configuring the blocking state of each cross node in the corresponding decoding array according to the code word features of different types of to-be-decoded data; inputting the initial log-likelihood ratio of different types of to-be-decoded data into the corresponding row of the general memory-computing integrated device array, performing iterative calculation through the corresponding column of the general memory-computing integrated device array based on the message passing process between the variable nodes and the check nodes, and outputting the decoding result of different types of to-be-decoded data when the corresponding column output meets the termination condition. The application can be widely applied in the field of decoding technology.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of communication, relates to the field of signal decoding technology, and particularly relates to a multi-code universal decoding method, system, device and medium based on a memory-computing integrator. BACKGROUND

[0002] In modern wireless communication systems, in order to overcome channel noise and fading and ensure high reliability of data transmission, channel coding technology plays an indispensable role. In current and future communication standards, three main channel coding schemes, LDPC code (low-density parity-check code), Turbo code and Polar code (polar code), occupy a core position due to their excellent error correction performance.

[0003] Under the background of long-term coexistence of current 4G and 5G networks, both user terminals such as smart phones and Internet of Things modules and network side devices must be able to seamlessly switch between different network standards. This means that the baseband processor of a modern communication chip must have the ability to support and decode three different code types, Turbo code, LDPC code and Polar code. The traditional "chimney" design scheme is to provide a set of independent decoding hardware for each code type, but this will lead to bloated chip area, high cost and very low hardware resource utilization, which is contrary to the pursuit of low power consumption and low cost by mobile devices.

[0004] Moreover, the decoding process involves a large number of discrete fixed-point number operations, and the energy efficiency of a communication baseband based on traditional digital circuits is severely limited by the power consumption cost of random memory access and the energy overhead of discrete fixed-point number operations in the digital domain. The existing digital circuit processing paradigm cannot fundamentally achieve an energy efficiency breakthrough. SUMMARY

[0005] To solve the above problems, the purpose of the present application is to provide a multi-code universal decoding method, system, device and medium based on a memory-computing integrator, which, through algorithmic innovation, performs equivalent modification of Turbo code and Polar code to make them "similar to LDPC", and constructs a universal memory-computing integrator array containing different decoding arrays, thereby unifying the three seemingly different code types into a shared hardware decoding architecture based on the belief propagation (BP) algorithm to improve decoding efficiency.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a multi-code universal decoding method based on a memory-computing integrator, comprising:

[0008] characterizing the common features of different types of decoding tasks with a probabilistic graphical model;

[0009] obtain initial log-likelihood ratios of each variable node in a probability graph model corresponding to different types of data to be decoded;

[0010] construct a general-purpose memory-computing integrator array including different types of decoding arrays, and configure resistance states of each cross node in each decoding array according to different types of data to be decoded, respectively;

[0011] input initial log-likelihood ratios of different types of data to be decoded into corresponding rows of the general-purpose memory-computing integrator array, perform iterative calculation through corresponding columns of the general-purpose memory-computing integrator array based on a message passing process between variable nodes and check nodes, and output decoding results of different types of data to be decoded when output of the corresponding column meets a termination condition.

[0012] In a second aspect, the present application provides a general-purpose decoding system based on a memory-computing integrator, comprising:

[0013] a unified preprocessing unit configured to represent common features of different types of decoding tasks by a probability graph model;

[0014] an initialization unit configured to obtain initial log-likelihood ratios of each variable node in a probability graph model corresponding to different types of data to be decoded;

[0015] a general-purpose decoder construction unit configured to construct a general-purpose memory-computing integrator array including different types of decoding arrays, and configure resistance states of each cross node in each decoding array according to different types of data to be decoded, respectively;

[0016] an iterative calculation unit configured to input initial log-likelihood ratios of different types of data to be decoded into corresponding rows of the general-purpose memory-computing integrator array, perform iterative calculation through corresponding columns of the general-purpose memory-computing integrator array based on a message passing process between variable nodes and check nodes, and output decoding results of different types of data to be decoded when output of the corresponding column meets a termination condition.

[0017] In a third aspect, the present application provides a computer-readable storage medium storing one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the general-purpose decoding method based on a memory-computing integrator.

[0018] In a fourth aspect, the present application provides a computing device, comprising: one or more processors and a memory, the memory storing one or more programs and being configured to be executed by the one or more processors, the one or more programs including instructions for performing the general-purpose decoding method based on a memory-computing integrator.

[0019] The present application has the following advantages due to the above technical solutions:

[0020] 1. The application provides a multi-code general-purpose storage and calculation integrated device architecture array, which can simultaneously meet the multi-code communication requirements of supporting LDPC, Turbo and polar codes, and fundamentally overcome the inherent defects of large hardware resource overhead and high power consumption, so that it can be applied to low-power edge devices with strict cost and power consumption restrictions.

[0021] 2. The application fully utilizes the characteristics of the storage and calculation integrated device, loads static variables in the probability graph calculation process to the storage and calculation integrated device array to overcome the energy overhead caused by storage access in the iteration process, and converts the traditional discrete digital operation into current, voltage and other continuous physical variable operation, thereby avoiding the energy overhead caused by digital domain discrete fixed-point number operation, and fundamentally improving the energy efficiency.

[0022] Therefore, the application can be widely applied to the field of signal decoding technology. BRIEF DESCRIPTION OF DRAWINGS

[0023] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not meant to limit the present application. Throughout the drawings, the same reference numerals are used for the same components. In the drawings:

[0024] Figure 1 is a multi-code general-purpose decoding method flowchart based on the storage and calculation integrated device provided in the embodiments of the application;

[0025] Figure 2 is a multi-code general-purpose storage and calculation integrated device array schematic diagram based on the storage and calculation integrated device provided in the embodiments of the application;

[0026] Figure 3 is a node resistance state configuration schematic diagram of one decoding array provided in the embodiments of the application;

[0027] Figure 4 is a structure schematic diagram of the Min module in the embodiments of the application. DETAILED DESCRIPTION

[0028] To make the purposes, technical solutions and advantages of the embodiments of the application clearer, the technical solutions of the embodiments of the application will be described clearly and completely below in combination with the drawings of the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the described embodiments of the application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the application.

[0029] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0030] In some embodiments of the present application, a multi-code general decoding method based on a memory-computing integrated device is provided, which comprises: representing common features of different types of decoding tasks by a probabilistic graph model; obtaining initial log-likelihood ratios of each variable node in the probabilistic graph model corresponding to different types of data to be decoded; constructing a general memory-computing integrated device array containing different types of decoding matrices, and respectively configuring the resistance states of each cross node in the corresponding decoding array according to different types of data to be decoded; inputting the initial log-likelihood ratios of different types of data to be decoded into the general memory-computing integrated device array, and performing iterative calculation through the corresponding columns of the general memory-computing integrated device array based on the message passing process between the variable nodes and the check nodes, and outputting the decoding results of different types of data to be decoded when the corresponding columns output meet the termination condition. The present application realizes the simultaneous decoding of different types of code words through the general memory-computing integrated device array, which effectively improves the decoding efficiency while reducing power consumption.

[0031] Correspondingly, in some other embodiments of the present application, a multi-code general decoding system, device and medium based on a memory-computing integrated device are provided.

[0032] Embodiment 1

[0033] As shown in Figure 1 , the present application provides a multi-code general decoding method based on a memory-computing integrated device, which comprises the following steps:

[0034] S1, representing common features of different types of decoding tasks by a probabilistic graph model, and uniformly converting different types of decoding tasks into a message passing process between variable nodes and check nodes.

[0035] In order to be able to uniformly process different types of decoding tasks, the present embodiment represents the common features of different types of decoding tasks as a probabilistic graph model, and processes the probabilistic graph model by using a memory-computing integrated device array.

[0036] For any (N, K) code word, where, , the code length is N, and the number of information bits is K. The sending end can encode the code word with the number of information bits K into N-K parity bits. ​​​​, and then modulate it into codewords based on BPSK (only as an example, but not limited to) , and send it to the decoding end. Due to noise interference in the transmission process, the decoding end will receive codewords , denoted as , and the decoding task of the decoding end is to recover to , so as to obtain the original codewords of the sending end according to each .

[0037] In this embodiment, the above decoding process is characterized based on a probabilistic graphical model. The probabilistic graphical model can include a plurality of variable nodes, a plurality of check nodes, and a plurality of undirected edges. The undirected edges are used to connect the variable nodes and the check nodes that have a connection relationship. Each variable node uniquely corresponds to a column vector in the check matrix, and each check node uniquely corresponds to a row vector in the check matrix. If the element in the check matrix with the row order equal to and the column order equal to is 1, then the variable node with the first numbering order equal to has a connection relationship with the check node with the second numbering order equal to . If the element in the check matrix with the row order equal to and the column order equal to is 0, then the variable node with the first numbering order equal to does not have a connection relationship with the check node with the second numbering order equal to . The first numbering order is the arrangement number of a certain variable node in all variable nodes, and the second numbering order is the arrangement number of a certain check node in all check nodes.

[0038] This embodiment converts the decoding task into a problem of estimating unknown variables based on observed variables and check matrices by using a probabilistic graphical model. The computational architecture of the probabilistic graphical model includes:

[0039] The variable nodes represent unknown variables , where each belongs to a state set space , where , .

[0040] The check nodes represent the coupling relationship between the unknown variables, the observed variables, and the check matrix.

[0041] S2, according to the received different types of data to be decoded, create target check matrices and probabilistic graphical models corresponding to different types of data to be decoded.

[0042] In order to solve the decoding process using the probabilistic graphical model computation architecture of step S1, this embodiment performs an equivalent transformation of Polar code and Turbo code into "LDPC-like" code, obtains the target parity matrix corresponding to different types of codewords, and then unifies the three seemingly different code types into a shared multi-codeword universal in-memory array.

[0043] In this embodiment, when creating target parity-check matrices corresponding to different types of data to be decoded based on the received different types of data to be decoded, the process includes:

[0044] When the data to be decoded is an LDPC code, the parity check matrix of the LDPC code is directly used as its target parity check matrix;

[0045] When the data to be decoded is a Polar code, a bipartite factor graph is constructed based on the received Polar code. Redundant nodes in the bipartite factor graph are pruned and optimized, and the resulting sparse parity-check matrix of the Polar code is used as its target parity-check matrix.

[0046] When the data to be decoded is a Turbo code, the short loop structure in the initial parity check matrix is ​​eliminated, and the resulting Turbo code extended parity check matrix is ​​used as its target parity check matrix.

[0047] The following is a detailed explanation.

[0048] LDPC code is a type of ( , Linear block code, code length is The information sequence length is The parity-check matrix (PCM) of an LDPC code is uniquely determined by its parity-check matrix. The PCM matrix consists of 0s and 1s, with the number of 1s being much smaller than the number of 0s, exhibiting sparsity. Each row of the PCM matrix corresponds to a parity node in the unified probabilistic graph computation architecture, i.e., a parity-check equation; each column corresponds to a variable node in the unified probabilistic graph computation architecture, i.e., a bit of the codeword. A point in the PCM matrix with an element of 1 represents an edge between the variable node and the parity node.

[0049] Polar codes are a typical type of non-systematic code, meaning that the codeword itself does not explicitly contain the original information bits; instead, the original information bits are implicitly embedded in the encoded codeword through a linear transformation. Polar codes typically use the Kronecker product (Kronecker multiplication). Construct the generating matrix Where F is a 2*2 classical polarization nucleus, which can be represented as ; This is the number of Kronecker products, which is also equivalent to the "polarization depth" of the polar code; Given the code length, it can be represented as The actual encoding process is as follows: codeword ,in, It is an input bit sequence consisting of information bits and frozen bits. This embodiment uses ( , Taking polar codes as an example, this section introduces the process of constructing a bipartite factor graph for Polar codes. First, starting from the encoded polarization relation / butterfly network mapped by the generator matrix, each polarization process / butterfly intermediate node is considered a variable node (VN), and local XOR and equality connection relationships are considered check nodes (CN). The original polarization relation / butterfly network is then flattened into a bipartite factor graph, yielding the set of variable nodes and the set of factor variables, respectively:

[0050] The set of variable nodes, including the Channel Variable Node (VNCH): corresponding to the rightmost node in the bipartite factorization graph. Each variable node has an initial value set to the channel output LLR value; Hidden Variable Node (VNH): Polar code intermediate layer (stage=1,2,…, -1) Node, with no initial information, so the initial LLR is set to 0; Frozen Variable Node (VNF): The node at the leftmost position of the input bit sequence that is frozen.

[0051] The set of verification nodes includes XOR constraint nodes: degree 3, indicating that the bits of the three connected variable nodes satisfy the XOR constraint (modulo 2 sum is 0); and replica nodes: degree 2, indicating that the bits of the two connected variable nodes are equal.

[0052] The total number of variable nodes is There are [number] verification nodes. There are 15 nodes (of which XOR nodes and replica nodes each account for half).

[0053] In this embodiment, to reduce redundancy during the tiling process, the bipartite factor graph needs to be pruned. The following redundant nodes are deleted according to the pruning algorithm: frozen variable nodes, check nodes with a degree of 1, check nodes with a degree of 2, and hidden variable nodes with a degree of 1 or 2, to obtain a simplified bipartite factor graph.

[0054] Specifically, the pruning algorithm can follow the following process:

[0055] Delete VNF

[0056] while true do

[0057] delete CN of degree 1 and its connected VN

[0058] delete CN of degree 2 and merge its connected VNH and VNCH

[0059] delete VNH of degree 1 and its connected CN

[0060] delete VNH of degree 2 and merge its connected CN

[0061] delete CN of degree 2 and merge its connected VNH

[0062] if parity check matrix unchanged

[0063] return parity check matrix

[0064] end if

[0065] end while

[0066] Based on the simplified bipartite factor graph, the check node corresponding to each check node is extracted to construct a Polar code sparse check matrix. Each row of the Polar code sparse check matrix corresponds to a check node (whether it is an XOR node or a copy node) in the simplified bipartite factor graph, and each column corresponds to a variable node. When the variable node is connected to the check node, the corresponding element position in the Polar code sparse check matrix is set to 1, otherwise it is set to 0.

[0067] For Turbo code, algebraic constraints are established based on two Recursive Systematic Convolutional code (RSC) components of the Turbo encoder. Let the input information sequence , systematic bits and check bits . Among them, the check bits are obtained from two generator polynomials. Taking an 8-state RSC component as an example, the corresponding generator polynomials are:

[0068] where and are the feedback polynomial and feedforward polynomial set inside the RSC encoder, respectively.

[0069] Specifically, the embodiment can map the above generation polynomials (including feedback polynomials and feedforward polynomials, internal settings of the RSC encoder) to binary coefficient vectors [1, 0, 1, 1] and [1, 1, 0, 1] on the Galois field GF(2). Perform cyclic shift (the first row is filled with 0 to the length , the second row is obtained by cyclically right shifting the first row filled with 0 to the length by one bit, and the third row is obtained by cyclically right shifting the second row by one bit again) to obtain the cyclic shift matrix and . For example, when is equal to 8 and the generation polynomial is used, an 8*8 cyclic shift matrix can be constructed as follows:

[0070]

[0071] The embodiment can horizontally splice the constructed and to obtain the component check matrix .

[0072] wherein the component check matrix satisfies represents a vector obtained by splicing the system bits and the check bits . The dot product symbol represents the vector dot product of two row vectors.

[0073] Subsequently, according to the interleaving rule, the interleaving effect of the second RSC component encoder can be written as a permutation matrix , and the corresponding check relationship is right multiplied by to obtain:

[0074]

[0075] Similarly, it satisfies . In combination with the above component check matrix, the overall Turbo code check matrix (code rate 1 / 3, unchanged) can be obtained, that is, the initial check matrix is:

[0076]

[0077] wherein the initial check matrix has a size of (the number of encoded information bits ), and satisfies the check relationship.

[0078] Subsequently, the embodiment can create a corresponding initial probability graph model according to the initial check matrix, identify and eliminate short loop structures in the initial check matrix and the initial probability graph model, to obtain a Turbo code target check matrix and a probability graph model.​

[0079] Specifically, the embodiment needs to systematically eliminate the 4-cycles in the initial check matrix and the initial probabilistic graph model after creating the initial check matrix and the initial probabilistic graph model.

[0080] It should be noted that one 4-cycle corresponds to a pattern in the check matrix: the elements at the four intersection points of two rows (such as c_i and c_j) and two columns (such as v_p and v_q) are all 1. This indicates that two check equations simultaneously constrain the same pair of variable nodes. Therefore, the 4-cycles are eliminated and replaced. First, all the four 1s constituting the 4-cycle are cleared. Then, a new variable node v_pq is introduced in the initial probabilistic graph model, and a new check equation (that is, a row is added in the initial check matrix) is added to define it: v_pq ⊕ v_p ⊕ v_q = 0. The original two check equations c_i and c_j are modified so that they are associated through the newly introduced v_pq node instead of directly connecting v_p and v_q at the same time. All the 4-cycles in the initial check matrix are traversed, and the above operation is repeated for all detected 4-cycles. The initial check matrix and the initial probabilistic graph model after eliminating all the 4-cycles are determined as the target check matrix and the probabilistic graph model of the final Turbo code, respectively.

[0081] It should be noted that the embodiment fundamentally eliminates the short cycle structure that is most harmful to decoding performance by replacing each 4-cycle in the initial check matrix and the initial probabilistic graph model with a larger 6-cycle. Due to the structural characteristics of Turbo codes, the short cycles in the initial check matrix and the initial probabilistic graph model are mainly such 4-cycles. Therefore, after this round of expansion optimization, usually no further processing is needed. Finally, a 4-cycle-free Turbo code check matrix is obtained, which is more suitable for high-performance iterative decoding.

[0082] It can be understood that, compared with the initial check matrix and the initial probabilistic graph model, the number of variable nodes in the target check matrix and the probabilistic graph model of the Turbo code obtained after optimization increases.

[0083] S3, obtaining the initial log-likelihood ratio of each variable node in the probabilistic graph model corresponding to different types of to-be-decoded data as an initial input.

[0084] As can be seen from step S1, since the variable nodes included in the probabilistic graph model corresponding to different types of code words are of different types, when calculating the initial log-likelihood ratio of each variable node in the probabilistic graph model, the variable node types need to be calculated respectively. It is assumed that the target check matrix is represented as H, and the number of rows and columns of H is n and k, respectively. ​The number of 1s in the target verification matrix is ​​assumed to be... For LDPC codes, there are At this point, directly based on the received data a symbol The initial log-likelihood ratio for each variable node can be calculated; for Polar codes, it is based on the data received by the decoder. a symbol calculate There are one channel variable node (VNCH), and the initial log-likelihood ratio of other variable nodes is set to 0; for Turbo codes, it is based on the data received by the decoder. Each symbol is used to calculate the initial variable node, and when expanding the variable node, the initial log-likelihood ratio of the expanded variable node is set to 0.

[0085] Specifically, with ( , Taking Polar codes as an example, the code length of a Polar code is... The number of information bits is When the bitrate is fixed at 1 / 2, When acquiring the initial input, there are two types based on the variable node type: for channel variable nodes, based on the input received by the decoder... a symbol (i.e. ) to perform calculations, because a symbol Corresponding to There are 10 channel variable nodes. Therefore, the initial log-likelihood ratio for each initial variable node is calculated using the following formula:

[0086]

[0087] in, For the first The initial log-likelihood ratio of each variable node. For the first The set of sub-constellation symbols with bits 0 and 1. The symbols received by the decoder. The symbols sent by the sending end. This represents noise power.

[0088] Taking BPSK as an example, let's assume the actual received signal is represented as follows: ,but .

[0089] For non-VNCH variable nodes, there is no prior channel information; therefore, this invention assumes their initial log-likelihood ratio is 0, i.e. ; thereby obtaining all An initial log-likelihood ratio of a variable node which can be considered as an initial passing message from a variable node to a check node .

[0090] Wherein, the initial input can be calculated by other digital circuits, or not calculated, or directly input from the outside, which is not limited by the present application.

[0091] Wherein, loading the initial input in the form of voltage to the input part of the memory-computing integrated array means setting the input of the memory-computing integrated array as a voltage value vector proportional to the initial log-likelihood ratio.

[0092] S4, constructing a general memory-computing integrated array containing different types of decoding arrays, and configuring the resistance state of each cross node in each decoding array according to different types of data to be decoded respectively.

[0093] Specifically, the following steps are included:

[0094] S41, dividing the general memory-computing integrated array into regions to obtain decoding arrays for decoding different types of data to be decoded.

[0095] In this embodiment, as shown in the figure, Figure 2 the general memory-computing integrated array is divided into regions and used for decoding different types of data to be decoded, which is recorded as LDPC decoding array, Polar decoding array and Turbo decoding array in this embodiment for the convenience of description. However, due to the inconsistency of the number of rows and columns in the target check matrix of LDPC code, Polar code and Turbo code, it is necessary to reserve sufficient margin for different decoding arrays. Specifically:

[0096] From the input, for LDPC code, the code length is equal to the number of columns of the target check matrix, while for Polar code or Turbo code, the code length is less than the number of columns of the target check matrix Therefore, it is necessary to consider reserving sufficient array row margins under different code words or code lengths. For the memory-computing integrated array rows that are not used, the input rows can be all set to zero (high resistance state). In this embodiment, the number of rows of the LDPC decoding array, the Polar decoding array and the Turbo decoding array can be set to the maximum value of the number of columns in different target check matrices.

[0097] From the output, for LDPC, the first bits of the code word need to be output from the bits for subsequent processing, at this time ; for Polar or Turbo code, the first bits of the code word need to be output from the The bit codeword is used for subsequent processing. Therefore, it is also necessary to consider reserving sufficient output part array column margins under different codewords / code lengths. For unused memristor array output columns, all output values can be forced to high level. In this embodiment, the column numbers of the LDPC decoding array, the Polar decoding array and the Turbo decoding array are set to the maximum number of elements with value 1 in different target check matrices.

[0098] Alternatively, in the general memory-computing integrated array, different types of decoding arrays can be arranged in the form of a diagonal matrix in a whole piece of memory-computing integrated array. Different rows of the whole piece of memory-computing integrated array are distinguished according to the decoding arrays, and different types of data to be decoded can be received at the same time. Alternatively, different types of decoding arrays can be arranged in independent memory-computing integrated arrays. The inputs of each independent memory-computing integrated array are connected to the corresponding peripheral circuit to realize the decoding calculation of different types of data to be decoded.

[0099] S42, according to the target check matrix of different types of data to be decoded, the decoding array of the corresponding type is regionally divided to obtain the input part, the output part, the iteration part and the check part corresponding to different decoding arrays, and the node resistance state of each part is configured.

[0100] Specifically, the following steps are included:

[0101] S421, according to the target check matrix of different types of data to be decoded, the decoding array of the corresponding type is regionally divided to obtain the input part, the output part, the iteration part and the check part.

[0102] Taking the Polar code as an example, when the Polar decoding array is regionally divided according to the sparse check matrix of the Polar code, it can be divided into an iteration part, a check part, an input part and an output part, as shown in Figure 3 . Among them, the iteration part (see the dark gray part in Figure 3 the memory-computing integrated array) is a square matrix, and the row and column numbers are equal to , that is, the number of 1s in the Polar code sparse check matrix; the check part (see the light gray part in Figure 3 the memory-computing integrated array) is spliced with the iteration part from the column dimension, and the row and column numbers of the check part are the same as those of the iteration part; the output part (see the yellow part in Figure 3 the memory-computing integrated array) is spliced with the check part from the column dimension, and the column number of the output part is equal to the code length ; the input part (see the pink part in Figure 3 the memory-computing integrated array) is spliced with the iteration part, the check part and the output part from the row dimension, and the row number of the input part is equal to the column number of the Polar code sparse check matrix .

[0103] The storage-computing integrated device is a device with storage and computing performance, such as a resistive random access memory, a phase change memory, a magnetic memory, a flash memory, and the like.

[0104] S422, analyze the decoding process of different types of to-be-decoded data, and determine the message passing process of the iteration part, the check part, and the output part in each decoding array.

[0105] Specifically, still taking the Polar code decoding process as an example, it can be known that the Polar code decoding process can be roughly divided into two parts, one is to calculate the confidence of the variable node to the check node and the a posteriori log likelihood ratio of the variable node according to the confidence of the check node to the variable node in the previous iteration, and the other is to calculate the confidence of the check node to the variable node according to the confidence of the variable node to the check node.

[0106] In the Polar decoding array, the main function is to calculate the confidence of the variable node to the check node and the a posteriori log likelihood ratio of the variable node. Specifically, the iteration part is used to calculate the confidence of the variable node to the check node; the check part is used to calculate the a posteriori log likelihood ratio of the variable node after iteration; and the output part is used to calculate the a posteriori log likelihood ratio of the variable node, which is consistent with the calculation result of the check part, that is, each column of the output part is the variable node corresponding to all VNCH nodes.

[0107] Based on the above analysis, the calculation formula of the iteration part can be represented as:

[0108]

[0109] wherein, is the confidence of the variable node to the check node ; is the confidence of the check node to the variable node ; is the set of all check nodes connected to the variable node , that is, the variable node participates in the check relationship of the check equation corresponding to all the check nodes, and the check node refers to other check nodes in the set except the check node ; is the initial log likelihood ratio of the variable node .

[0110] The calculation formula of the check part can be represented as:

[0111]

[0112] in, For variable nodes The posterior log-likelihood ratio.

[0113] The calculation formula for the output part is the same as that for the verification part, but it only needs to calculate the posterior log-likelihood ratio of the variable nodes corresponding to all VNCH nodes.

[0114] S423. The message passing process of each part is equivalently converted into the form of vector-matrix multiplication to obtain the configuration matrix corresponding to each part. After concatenating the configuration matrices of each part, the blocking state configuration is performed on each cross node corresponding to different types of decoding arrays.

[0115] In this embodiment, in order to utilize vector-matrix multiplication in the Polar decoding array for computation... and Simultaneously, in conjunction with the peripheral circuitry for subsequent calculations, the results of the iteration section, the verification section, and the output section need to be arranged into a vector form.

[0116] For the iteration part, firstly, each variable node is processed according to the numbering order of the verification nodes. To the verification node Message delivery By arranging them, we can obtain Row vectors:

[0117]

[0118] in, For the sparse parity-check matrix of the Polar code, This refers to the order of a given variable node among all variable nodes. This refers to the order of a given check node among all check nodes. The elements in the table correspond to different variable nodes, and the order of their numbers is as follows: The confidence level of the verification node is calculated; by concatenating the row vectors, the result vector can be obtained. And vector The length is ,vector Each element in the vector represents the confidence level from a variable node to a verification node calculated using an undirected edge. In this embodiment, vectors are used respectively. and To represent vectors The sequence of variable nodes and check nodes corresponding to each element, for example, The 5th element is ,but The 5th element is , The fifth element in the middle is .

[0119] Secondly, arrange the passing message of each check node to variable node in the order of check node number, and get . . . .

[0120] Finally, the calculation of the above iteration part (i.e. formula (7)) can be calculated by vector-matrix multiplication form:

[0121]

[0122] Wherein, the initial log-likelihood ratio vector is , the matrix is the first iteration configuration function matrix, and the element in is , with the size of ; the matrix is the second iteration configuration function matrix, and the element in is , with the size of .

[0123] It can be seen that the vector is arranged by , but actually the calculation required in formula (7) is , that is, the message from check node to variable node is excluded, and only the confidence of the check node to variable node is retained, through the first iteration configuration function matrix and the second iteration configuration function matrix, to realize from to , and finally get the result vector.

[0124] Similarly, in order to calculate in the Polar decoding array by vector-matrix multiplication, the result of the check part also needs to be arranged into a vector, wherein the specific arrangement of the check part is: , represents the posterior log-likelihood ratio of variable node , and is the Mth element in the vector .

[0125] Then the calculation of the check part (i.e. formula (8)) can be calculated by vector-matrix multiplication form:

[0126]

[0127] wherein, is a check configuration function matrix, and the element in is of size , and the matrix is the same as the above.

[0128] Let wherein represents a sequence number set of the variable node VNCH, and the specific arrangement of the output part is: , represents the a posteriori log-likelihood ratio of the variable node , that is, the output part needs to calculate the a posteriori log-likelihood ratio of the variable node corresponding to VNCH.

[0129] Then the output part calculation can also be calculated in the form of vector-matrix multiplication:

[0130]

[0131] wherein the matrix is a first output configuration function matrix, and the element in is of size , and the matrix is a second output configuration function matrix, and the element in is of size .

[0132] Finally, the three equations in equation (10) to equation (12) are spliced to obtain:

[0133]

[0134] According to the splicing matrix , the resistance state of the storage-computing integrated device array is configured, wherein the element value in the splicing matrix is 1, and the corresponding cross node in the Polar decoding array is configured to a low resistance state, and the element value in the splicing matrix is 0, and the corresponding cross node in the Polar decoding array is configured to a high resistance state. Take as the input of the Polar decoding array, wherein is the common input of the iteration part, the check part and the output part, is the input of the input part, and the corresponding output can be obtained.

[0135] Similarly, the resistance states of each cross node in the Turbo decoding array and the LDPC decoding array can be configured according to the target check matrix of the Turbo code and the LDPC code, respectively.

[0136] S5, inputting the initial log-likelihood ratios of different types of data to be decoded into corresponding rows of the general storage-computation integrated array, performing iterative computation through corresponding columns of the general storage-computation integrated array, and outputting the decoding result of the corresponding type of data to be decoded when the corresponding column outputs a result satisfying a termination condition.

[0137] Specifically, the method comprises the following steps:

[0138] S51, designing a peripheral circuit for performing hard decision and check on the computation result output by each decoding array in the general storage-computation integrated array.

[0139] In this embodiment, the peripheral circuit comprises a Min module, a hard decision module and a check module. The Min module is configured to perform computation on the message passing from the check node to the variable node output by the iteration part, and input the computation result in the form of an analog quantity into the iteration part again. The hard decision module is configured to perform hard decision on the a posteriori log-likelihood ratio of each variable node output by the check part, and output the hard decision result to the check module. If the a posteriori log-likelihood ratio is < 0, the hard decision result is 1 (high level); if the a posteriori log-likelihood ratio is > 0, the hard decision result is 0 (low level). The check module is configured to perform exclusive OR on the hard decision result, and if the result is 0, it represents that the check condition (i.e. the syndrome is 0) is satisfied, at which time the decoding iteration is stopped, the hard decision module performs hard decision on the a posteriori log-likelihood ratio of each variable node output by the output part, and outputs the decision result as the final decoding result, obtaining . .

[0140] In this embodiment, since the variable nodes output in the same check equation are arranged in adjacent positions, they are connected to the same Min module (as shown in FIG. 5B), and the minimum sum operation is realized through the Min module. Specifically, the Min module has a multiple-input and multiple-output structure, the level of each output is the modulus of the minimum of the product of the levels of other paths and the product of the levels of other paths, and then a coefficient is scaled through a resistor, that is, the confidence of the check node to the variable node is calculated. Figure 4

[0141]

[0142] , wherein is the confidence of the check node to the variable node . ​​is a normalization coefficient, used to scale or weight the belief of the check node update. The introduction of the normalization coefficient is to improve the performance of the Min-Sum decoding algorithm, so that the Min-Sum approximation is closer to the exact signal processing algorithm; is a variable node to a check node belief; is a set of all variable nodes connected to the check node , i.e. these variable nodes belong to the same check equation .

[0143] Optionally, the check module can also use the following scheme instead: first, use a cascade multiplier to multiply the a posteriori log-likelihood ratios output by all variable nodes, and then use a comparator to determine the output result of the cascade multiplier, output low level if greater than 0, otherwise output high level, and determine whether the check condition is met according to the high or low level output.

[0144] S52, after loading the initial input, the hard decision module is used to perform hard decision on the a posteriori log-likelihood ratio of each variable node output by the check part in the different decoding array, and the check module is used to check the hard-decision code word, if the termination condition is met (i.e. the maximum number of times is reached or the is met), the iteration is stopped, and the final decoding result of the corresponding type of data to be decoded is output , otherwise, step S53 is entered.

[0145] S53, load the a posteriori log-likelihood ratio of each variable node output by the iteration part into the Min module, use the Min module to calculate the message passing from the check node to the variable node, and input the calculation result into the iteration part of the corresponding decoding array again to complete the iteration.

[0146] S54, repeat step S53, if the termination condition is met, stop iteration, and output the final decoding result of the different types of data to be decoded .

[0147] In this embodiment, in the LDPC decoding array, the check output part is the final decoding result output, in the Polar decoding array, the decision result of the column corresponding to the VNCH node needs to be picked out from the columns of the check output part as the final decoding output, and in the Turbo decoding array, the decision result of the column corresponding to the initial variable node also needs to be picked out from the columns of the check output part as the final decoding output.

[0148] Embodiment 2

[0149] The embodiment 1 above provides a multi-code general decoding method based on a memory-computing integrator. Correspondingly, the embodiment provides a multi-code general decoding system based on a memory-computing integrator. The system provided by the embodiment can implement the multi-code general decoding method based on a memory-computing integrator of the embodiment 1. The system can be implemented in software, hardware, or a combination of software and hardware. For example, the system can include integrated or separate functional modules or functional units to perform the corresponding steps in the methods of the embodiment 1. Since the system of the embodiment is basically similar to the method embodiment, the description process of the embodiment is relatively simple, and the related parts can be referred to the part of the description of the embodiment 1. The embodiment of the system provided by the embodiment is merely illustrative.

[0150] The multi-code general decoding system based on a memory-computing integrator provided by the embodiment includes:

[0151] A unified preprocessing unit is configured to represent common features of different types of decoding tasks by using a probabilistic graphical model.

[0152] An initialization unit is configured to obtain initial log-likelihood ratios of each variable node in a target probabilistic graphical model corresponding to different types of to-be-decoded data.

[0153] A general decoder construction unit is configured to construct a general memory-computing integrator array including different types of decoding arrays, and configure blocking states of each cross node in the corresponding decoding array according to different types of to-be-decoded data.

[0154] An iterative calculation unit is configured to input initial log-likelihood ratios of different types of to-be-decoded data into corresponding rows of the general memory-computing integrator array, perform iterative calculation through corresponding columns of the general memory-computing integrator array based on a message passing process between variable nodes and check nodes, and output decoding results of different types of to-be-decoded data when the corresponding column outputs a result satisfying a termination condition.

[0155] Further, the unified preprocessing unit includes:

[0156] A target check matrix creation unit is configured to create a target check matrix corresponding to different types of to-be-decoded data according to the received different types of to-be-decoded data.

[0157] A probabilistic graphical model representation unit is configured to create a corresponding probabilistic graphical model according to the target check matrix of different types of to-be-decoded data. The probabilistic graphical model includes a plurality of variable nodes, a plurality of check nodes, and a plurality of undirected edges. The undirected edges are used to connect variable nodes and check nodes having a connection relationship. Each variable node uniquely corresponds to a column vector in the target check matrix, and each check node uniquely corresponds to a row vector in the target check matrix.

[0158] Further, the general decoder construction unit includes:

[0159] an array partition unit, configured to partition a general-purpose memory-computing integrated array into regions to obtain decoding arrays for decoding different types of to-be-decoded data;

[0160] a node configuration unit, configured to partition the decoding arrays of the corresponding types according to target check matrices of the different types of to-be-decoded data, to obtain input parts, output parts, iteration parts, and check parts corresponding to the different decoding arrays, and to configure node resistances of the parts.

[0161] Further, in the array partition unit:

[0162] the decoding arrays of different types are arranged in the form of diagonal matrices in a whole piece of the memory-computing integrated array, and different rows of the whole piece of the memory-computing integrated array are distinguished according to the decoding arrays to simultaneously receive the different types of to-be-decoded data;

[0163] or, the decoding arrays of different types are arranged in independent memory-computing integrated arrays, and input rows of the independent memory-computing integrated arrays are used to respectively receive to-be-decoded data of the corresponding types.

[0164] Further, the node configuration unit comprises:

[0165] a region partition unit, configured to partition the decoding arrays of the corresponding types according to target check matrices of the different types of to-be-decoded data to obtain input parts, output parts, iteration parts, and check parts;

[0166] a decoding analysis unit, configured to analyze decoding processes of the different types of to-be-decoded data to determine message passing processes of the iteration parts, the check parts, and the output parts in the decoding arrays;

[0167] a resistance configuration unit, configured to equivalently convert the message passing processes of the parts into a form of vector-matrix multiplication to obtain configuration matrices corresponding to the parts, and to perform resistance configuration on the decoding arrays by splicing the configuration matrices of the parts.

[0168] Further, in the region partition unit:

[0169] the iteration part is a square matrix, and the number of rows and the number of columns of the iteration part are equal to the number of 1s in the target check matrix;

[0170] the check part is spliced with the iteration part in the dimension of columns, and the number of rows and the number of columns of the check part are the same as those of the iteration part;

[0171] the output part is spliced with the check part in the dimension of columns, and the number of columns of the output part is equal to the code length;

[0172] The input part is spliced from the dimension of rows with the iteration part, the check part and the output part, and the number of rows of the input part is equal to the number of columns of the target check matrix.

[0173] Embodiment 3

[0174] The embodiment provides a processing device corresponding to the multi-code general decoding method based on a memory-computing integrator provided in the embodiment 1, and the processing device can be a processing device for a client, such as a mobile phone, a notebook computer, a tablet computer, a desktop computer or the like, to execute the method in the embodiment 1.

[0175] The processing device includes a processor, a memory, a communication interface and a bus, the processor, the memory and the communication interface are connected through the bus to complete the communication between each other. The memory stores a computer program capable of running on the processor, and the processor executes the multi-code general decoding method based on the memory-computing integrator provided in the embodiment 1 when the computer program is run.

[0176] Preferably, the memory can be a high-speed random access memory (RAM: Random Access Memory), and can also include a non-volatile memory, for example, at least one disk memory.

[0177] Preferably, the processor can be a central processing unit (CPU), a digital signal processor (DSP) or various types of general-purpose processors, which are not limited here.

[0178] Embodiment 4

[0179] The multi-code general decoding method based on the memory-computing integrator in the embodiment 1 can be specifically implemented as a computer program product, and the computer program product can include a computer readable storage medium, which is loaded with computer readable program instructions for executing the multi-code general decoding method based on the memory-computing integrator in the embodiment 1.

[0180] The computer readable storage medium can be a tangible device that keeps and stores instructions for use by an instruction execution device. The computer readable storage medium can be, for example but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device or any combination of the above.

[0181] Those skilled in the art will appreciate that embodiments of the application can be devised for a method, a system, or a computer program product. Accordingly, the present application can be embodied in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0182] The present application is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing device or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0183] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0184] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0185] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing the technical solutions of the present application, but not for limiting it. Although the present application is described in detail with reference to the above embodiments, those skilled in the field should understand that the specific embodiments of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A multi-code general decoding method based on a memory-computing integrator, characterized in that, The method comprises the following steps: characterizing the common features of different types of decoding tasks by using a probabilistic graph model; obtaining initial log-likelihood ratios of each variable node in the probabilistic graph model corresponding to different types of data to be decoded; constructing a general-purpose memory-computing integrated array containing different types of decoding arrays, and configuring the resistance state of each cross node in the corresponding decoding array according to different types of data to be decoded; inputting the initial log-likelihood ratios of different types of data to be decoded into the corresponding rows of the general-purpose memory-computing integrated array, performing iterative calculation through the corresponding columns of the general-purpose memory-computing integrated array based on the message passing process between variable nodes and check nodes, and outputting the decoding results of different types of data to be decoded when the corresponding columns output the results meeting the termination condition; the characterization of the common features of different types of decoding tasks by using a probabilistic graph model comprises: creating a target check matrix corresponding to different types of data to be decoded according to the received different types of data to be decoded; creating a corresponding probabilistic graph model according to the target check matrix of different types of data to be decoded, the probabilistic graph model comprising a plurality of variable nodes, a plurality of check nodes and a plurality of undirected edges; the undirected edges are used to connect the variable nodes and the check nodes having a connection relationship, each variable node uniquely corresponds to a column vector in the target check matrix, and each check node uniquely corresponds to a row vector in the target check matrix; the construction of a general-purpose memory-computing integrated array containing different types of decoding arrays, and the configuration of the resistance state of each cross node in the corresponding decoding array according to different types of data to be decoded, comprises: array partitioning of the general-purpose memory-computing integrated array to obtain decoding arrays for decoding different types of data to be decoded; region partitioning of the corresponding type of decoding array according to the target check matrix of different types of data to be decoded to obtain the input part, the output part, the iteration part and the check part corresponding to different decoding arrays, and the configuration of the node resistance state of each part.

2. The multi-code general decoding method based on the storage-computing integrator according to claim 1, wherein, the creation of a target check matrix corresponding to different types of data to be decoded according to the received different types of data to be decoded comprises: when the data to be decoded is an LDPC code, directly taking the check matrix of the LDPC code as the target check matrix thereof; when the data to be decoded is a Polar code, constructing a binary factor graph according to the received Polar code, pruning and optimizing the redundant nodes in the binary factor graph, and taking the obtained Polar code sparse check matrix as the target check matrix thereof; when the data to be decoded is a Turbo code, constructing an initial check matrix and eliminating the short loop structure in the initial check matrix, and taking the obtained Turbo code extended check matrix as the target check matrix thereof.

3. The multi-code general decoding method based on the storage-computing integrator according to claim 1, wherein, the array partitioning of the general-purpose memory-computing integrated array to obtain decoding arrays for decoding different types of data to be decoded comprises: arranging different types of decoding arrays in the form of diagonal matrices in a whole piece of memory-computing integrated array, and differentiating the rows of the whole piece of memory-computing integrated array according to the decoding arrays to simultaneously receive different types of data to be decoded. Or, different types of decoding arrays are arranged in independent different memory-computing integrated arrays, and the input row of each independent memory-computing integrated array is arranged to receive data to be decoded of a corresponding type.

4. The multi-code general decoding method based on the storage-computing integrator according to claim 1, wherein, The target check matrix according to the different types of data to be decoded is used to divide the corresponding decoding array into regions, so as to obtain the input part, the output part, the iteration part and the check part corresponding to different decoding arrays, and the node resistance state of each part is configured, including: The target check matrix according to the different types of data to be decoded is used to divide the corresponding decoding array into regions, so as to obtain the input part, the output part, the iteration part and the check part corresponding to different decoding arrays, and the node resistance state of each part is configured, including: The decoding process of different types of data to be decoded is analyzed to determine the message passing process between the variable nodes and the check nodes in the iteration part, the check part and the output part of each decoding array. The message passing process between the variable nodes and the check nodes in each part is equivalent to the form of vector-matrix multiplication, so as to obtain the configuration matrix corresponding to each part, and the configuration matrix of each part is spliced to configure the resistance state of each decoding array.

5. The multi-code general decoding method based on the storage-computing integrator according to claim 4, characterized in that, The decoding array includes: The iteration part is a square matrix, and the number of rows and columns is equal to the number of 1s in the target check matrix; The check part is spliced with the iteration part from the column dimension, and the number of rows and columns of the check part is the same as that of the iteration part; The output part is spliced with the check part from the column dimension, and the number of columns of the output part is equal to the code length; The input part is spliced with the iteration part, the check part and the output part from the row dimension, and the number of rows of the input part is equal to the number of columns of the target check matrix.

6. A multi-code general decoding system based on a memory-compute integrator, characterized in that, It includes: A unified preprocessing unit is configured to represent the common features of different types of decoding tasks by using a probabilistic graph model; An initialization unit is configured to obtain the initial log-likelihood ratio of each variable node in the probabilistic graph model corresponding to different types of data to be decoded; A general decoder construction unit is configured to construct a general memory-computing integrated array including different types of decoding arrays, and configure the resistance state of each cross node in the corresponding decoding array according to different types of data to be decoded; An iteration calculation unit is configured to input the initial log-likelihood ratio of different types of data to be decoded into the corresponding row of the general memory-computing integrated array, perform iteration calculation through the corresponding column of the general memory-computing integrated array based on the message passing process between the variable nodes and the check nodes, and output the decoding result of different types of data to be decoded when the corresponding column outputs a result meeting a termination condition. The common features of different types of decoding tasks are represented by using a probabilistic graph model, including: According to the received different types of data to be decoded, a target check matrix corresponding to different types of data to be decoded is created; A corresponding probabilistic graph model is created according to the target check matrix of different types of data to be decoded, and the probabilistic graph model includes a plurality of variable nodes, a plurality of check nodes and a plurality of undirected edges; the undirected edges are used to connect the variable nodes and the check nodes having a connection relationship, each variable node uniquely corresponds to a column vector in the target check matrix, and each check node uniquely corresponds to a row vector in the target check matrix. The construction comprises a general memory-computing integrated device rack array containing different types of decoding arrays, and the resistance states of each cross node in the corresponding decoding array are configured according to different types of data to be decoded, including: The general memory-computing integrated device array is divided into arrays to obtain decoding arrays for decoding different types of data to be decoded; According to the target check matrix of different types of data to be decoded, the decoding array of the corresponding type is divided into regions to obtain the input part, the output part, the iteration part and the check part corresponding to different decoding arrays, and the node resistance state of each part is configured.

7. A computer-readable storage medium storing one or more programs, the one or more programs comprising instructions that when executed by a computer cause the computer to perform a method of any of claims 1-6. The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the memory-computing integrated device-based multi-code general decoding methods of claims 1-5.

8. A computing device, comprising: Including: One or more processors and memories, the memories have one or more programs stored therein and are configured to be executed by the one or more processors, the one or more programs include instructions for executing any of the memory-computing integrated device-based multi-code general decoding methods of claims 1-5.

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