Low-temperature low-noise InP-based HEMT device structure
By employing a graded buffer layer and an InP-based HEMT device design with a high indium and graded dual-channel structure, the problems of lattice mismatch and large leakage current were solved, improving the high-frequency and low-noise performance of the device and achieving high transconductance and high saturation current density.
Patent Information
- Application Number
- CN202511284505.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-09
- Publication Date
- 2025-12-12
AI Technical Summary
Existing InP-based HEMT devices suffer from lattice mismatch and high leakage current during actual fabrication, which affects their performance in high frequency and low noise.
The InP-based HEMT device design employs a gradient buffer layer and a high-indium and gradient dual-channel structure, including a substrate layer, buffer layer, channel layer, isolation layer, barrier layer, and cap layer. By gradually changing the composition design, the lattice matching and electron mobility are optimized, the lattice mismatch stress is reduced, and the electron mobility and noise performance are improved.
This achieves high density, improves the transconductance of power devices, enhances electron migration rate at low temperatures, reduces lattice defects, and improves the high-frequency and low-noise characteristics of the devices.
Smart Images
Figure CN121126818A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, specifically a low-temperature, low-noise InP-based HEMT device structure, employing a gradient composition buffer layer and a high-indium and gradient dual-channel layer. Background Technology
[0002] With the rapid development of the electronic information industry, society's demand for information processing and transmission speed is constantly increasing, placing higher requirements on communication technology and higher expectations on the performance of high-frequency semiconductor devices. Currently, commonly used materials for high-frequency semiconductor devices include silicon (Si), indium phosphide (InP), gallium nitride (GaN), and gallium arsenide (GaAs). Among them, Si is the most commonly used semiconductor material, widely used in CMOS technology, possessing good thermal stability and mechanical strength, but its low electron mobility and narrow bandgap make it unsuitable for high-frequency and high-temperature applications. GaAs is a direct bandgap semiconductor with high electron mobility and a wide bandgap, suitable for high-frequency and high-power electronic devices, and widely used in optoelectronics and microwave fields, such as lasers and solar cells. InP material, due to its extremely high electron mobility, performs excellently in high-speed electronic devices, and its high thermal conductivity helps in effective heat dissipation during high-frequency operation, a property not possessed by other semiconductor materials. Furthermore, the integration of InP and Si can leverage the cost-effectiveness and mature manufacturing technology of Si while maintaining the high-performance characteristics of InP.
[0003] The application and noise performance development of InP-based HEMT (High Electron Mobility Transistor) technology in low-noise amplifiers (LNAs) have been important research directions in the microwave and radio frequency fields in recent years. InP HEMTs, due to their excellent electron mobility and low noise characteristics, have been widely used in LNA designs at both low and room temperature. Li Xiao et al. used InP and In... 0.53 Ga 0.47 As composite channels significantly improve the on-state breakdown voltage of devices; Zhang Jiajia and Zhong Yinghui et al. proposed an InGaAs / InAs / InAlGaAs composite channel to improve the radiation resistance of InP-based power devices. Zhou Shuxing et al. proposed a three-layer composite channel structure based on InGaAs with different compositions, improving its radiation resistance. Yin Junjian et al. proposed an In... 0.80 Ga 0.20 As / In 0.53 Ga 0.47 The composite channel structure of As improves the high saturation current density and DC transconductance of power devices and increases the cutoff frequency, but this device uses 300nm In... 0.52 Ga 0.48As a buffer layer, this leads to problems such as lattice mismatch and excessive leakage current in actual device fabrication. Summary of the Invention
[0004] This invention proposes an InP-based HEMT device structure, employing a gradient buffer layer and a high-indium and gradient dual-channel structure, aiming to optimize the device's noise performance under low-temperature conditions.
[0005] To achieve the above objectives, this invention proposes an InP-based HEMT device structure design employing a gradient buffer layer and a high-indium and gradient dual-channel structure, comprising, from bottom to top: a substrate layer, a first buffer layer, a second buffer layer, a first channel layer, a second channel layer, an isolation layer, a δ-Si doped layer, a barrier layer, an etch stop layer, and a cap layer; wherein,
[0006] The substrate layer is composed of InP;
[0007] The first buffer layer is composed of In 0.52 Al 0.48 As;
[0008] The second buffer layer uses a gradient composition, with In as the component. z Al 1-z As, z: 0.52~0.60, the z value gradually increases from bottom to top in the thickness direction;
[0009] The first channel layer uses a graded composition, with In as the composition. x Ga 1-x As, x: 0.60~0.80; the x value gradually increases from bottom to top in the thickness direction;
[0010] The second channel layer is composed of In y Ga 1-y As, 0.75 <y<0.85;
[0011] The isolation layer is composed of In 0.52 Al 0.48 As;
[0012] The barrier layer is composed of In 0.52 Al 0.48 As;
[0013] The etching stop layer is composed of InP;
[0014] The cap layer component is In 0.53 Ga 0.47 As.
[0015] In the preferred case,
[0016] The thickness of the first buffer layer is 430–480 nm;
[0017] The thickness of the second buffer layer is 45–55 nm;
[0018] The thickness of the first channel layer is 6–8 nm;
[0019] The thickness of the second channel layer is 7–9 nm;
[0020] The thickness of the isolation layer is 4–6 nm;
[0021] The thickness of the barrier layer is 10–12 nm;
[0022] The thickness of the etching stop layer is 3–5 nm;
[0023] The thickness of the cap layer is 19–21 nm.
[0024] Furthermore, the distribution of z-values in the second buffer layer component along the thickness direction is as follows:
[0025] 0-15nm, z=0.52,
[0026] 15-30nm, z=0.56
[0027] 30-40nm, z=0.58
[0028] 40-(45~55)nm, z=0.60.
[0029] Furthermore, the distribution of x-values in the thickness direction of the first channel layer component is as follows:
[0030] 0-2nm, x=0.60,
[0031] 2-4nm, x=0.65,
[0032] 4-5nm, x=0.70
[0033] 5-5.5nm, x=0.75
[0034] 5.5-(6~8)nm, x=0.80,
[0035] In specific cases: the doping concentration of the δ-Si doped layer is 3×10⁻⁶. 12 cm -2 ~7×10 12 cm -2 .
[0036] Specifically: the cap layer is doped with Si as the dopant, and its concentration is 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 .
[0037] This invention proposes an InP-based HEMT with a high-indium and graded-component dual-channel structure and a graded-component buffer layer. Employing a composite InGaAs dual-channel structure and a high-indium-content upper channel layer, one advantage is enhanced electron mobility within the channel at low operating temperatures, improving transconductance and cutoff frequency. Another advantage is increased conduction band energy difference at the InAlAs and InGaAs heterojunction interface. Simultaneously, the graded-component InGaAs material used in the lower channel layer exhibits excellent electron mobility and provides lattice matching for the growth of the first channel layer. The graded-component buffer layer effectively reduces lattice mismatch stress and thermal stress, minimizing lattice defects in the epitaxial layer. The novel synergistic effect of the high-indium and graded-component dual-channel structure and the graded-component buffer layer enables the HEMT device to possess a high-density two-dimensional electron gas and excellent electron mobility characteristics, thereby achieving high saturation current density and excellent DC transconductance performance. Furthermore, the isolation layer is designed to be around 5nm, ensuring good noise performance. The above design ensures that the device has high electron mobility while also having good noise performance. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the InP-based HEMT epitaxial structure proposed in this invention.
[0039] Figure 2 This is a schematic diagram of the InP-based HEMT device structure proposed in this invention.
[0040] Figure 3 The Vg-Id curve is shown in the DC test simulation of the InP-based HEMT proposed in this invention.
[0041] Figure 4 The Vd-Id curve is shown in the DC test simulation of the InP-based HEMT proposed in this invention.
[0042] Explanation of the labels in the attached drawings:
[0043] 01. Substrate layer; 02. First buffer layer; 03. Second buffer layer; 04. First channel layer; 05. Second channel layer; 06. Isolation layer; 07. δ-Si doped layer; 08. Barrier layer; 09. Etch stop layer; 10-cap layer; 10-1. Source cap layer; 10-2. Drain cap layer; 12. Source metal electrode; 13. Drain metal electrode; 14. Passivation layer; 15. Gate metal electrode. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the following detailed description of this invention is provided in conjunction with specific embodiments and with reference to the accompanying drawings. However, the implementation of this invention is not limited thereto.
[0045] The application and noise performance development of InP-based HEMT (High Electron Mobility Transistor) technology in low-noise amplifiers (LNAs) have been important research directions in the microwave and radio frequency fields in recent years. Due to its excellent electron mobility and low noise characteristics, InP HEMTs have been widely used in LNA designs at both low and room temperature.
[0046] Therefore, this invention proposes an InP-based HEMT device structure, employing a graded buffer layer and a high-indium and graded dual-channel structure, the epitaxial structure and device structure of which are as follows: Figure 1 and Figure 2 As shown.
[0047] like Figure 1 As shown, the epitaxial structure of the composite channel InP-based HEMT, from bottom to top, consists of: a semi-insulating substrate, an undoped buffer layer, an undoped graded composition buffer layer, an undoped graded composition first channel layer, an undoped high-In composition second channel layer, an undoped isolation layer, a δ-Si doped layer, an undoped barrier layer, an undoped etch stop layer, and an n-Si doped layer. + Source (drain) level cap layer.
[0048] Table 1 Epitaxial layer materials and doping conditions
[0049]
[0050] like Figure 1 As shown, substrate 01 uses a semi-insulating InP substrate, which can effectively reduce parasitic current and improve the signal-to-noise ratio of the device. Furthermore, the semi-insulating InP substrate can isolate signals between different devices, preventing crosstalk. Due to its high resistivity, it can reduce high-frequency losses, resulting in better device performance under high-frequency conditions; therefore, RF devices all use semi-insulating substrates.
[0051] The first buffer layer 02 is located above the substrate layer 01. Its main function is to provide a transition layer that matches the InP substrate lattice, reducing stress and defects caused by lattice mismatch. The undoped nature helps maintain the high electron mobility of the material, avoids the influence of impurity scattering on electron transport, and provides a good growth basis for the subsequent gradient buffer layer and channel layer.
[0052] The second buffer layer 03 uses a gradient composition, with In as the component. z Al 1-zAs, z: 0.52–0.60, with the z-value gradually increasing from bottom to top along the thickness direction; the thickness is 45–55 nm. The z-value distribution along the thickness direction is: 0–15 nm, z = 0.52; 15–30 nm, z = 0.56; 30–40 nm, z = 0.58; 40–(45–55) nm, z = 0.60. This gradient structure design can further optimize lattice matching. By gradually changing the composition of In and Al, the lattice constant of the buffer layer is better matched with that of the subsequent channel layer. This gradient structure helps reduce lattice mismatch stress at the interface, lowers the defect density of the epitaxial layer, and improves material quality and electron transport performance.
[0053] The first channel layer 04 uses a gradient composition, with In as the composition. x Ga 1-x As, x: 0.60~0.80; the x value gradually increases from bottom to top in the thickness direction; the thickness is 6~8nm. The distribution of x value in the thickness direction is: 0-2nm, x=0.60; 2-4nm, x=0.65; 4-5nm, x=0.70; 5-5.5nm, x=0.75; 5.5-(6~8)nm, x=0.80. This gradient design can provide a gradually changing band structure, which is beneficial to electron injection and transport. As the In composition gradually increases, the band gap gradually decreases, forming a band gradient that is conducive to electron migration, thereby improving electron mobility and carrier concentration.
[0054] The high In composition of the second channel layer 05 results in a lower band gap, which further enhances electron mobility and improves the transconductance and cutoff frequency of the device. Simultaneously, the high In composition of the material contributes to higher electron mobility, which helps improve the high-frequency performance and low-noise characteristics of the device.
[0055] The primary function of the isolation layer 06 is to reduce parasitic capacitance between the gate and the channel, thereby improving the high-frequency performance of the device. Its undoped nature helps maintain the material's high resistivity, further reducing the impact of parasitic capacitance and improving device stability and reliability. The isolation layer increases the difficulty of attracting electrons from the δ-Si doped layer into the channel. Designing the isolation layer thickness to 5nm allows for better electron introduction into the channel layer while also exhibiting good noise performance.
[0056] The δ-Si doped layer 07 is located between the isolation layer 06 and the barrier layer 08. The role of the δ-Si doped layer is to introduce electrons into the channel layer structure of the device to form a two-dimensional electron gas (2DEG). This doping method can improve the conductivity of the channel layer while maintaining the high mobility of the material, thereby enhancing the driving capability of the device.
[0057] The barrier layer 08 forms a Schottky contact with the gate metal, which can effectively control the electron density in the channel and improve the switching characteristics of the device. The undoped barrier layer helps maintain the high electron mobility of the material, reduces the impact of impurity scattering on electron transport, and further improves device performance.
[0058] The main function of the etch stop layer 09 is to provide an etching stop marker during device manufacturing, protecting the underlying channel layer and buffer layer from etching damage.
[0059] The cap layer 10 provides low-resistance ohmic contacts, reducing the contact resistance between the source and drain and improving the current drive capability of the device. This highly doped cap layer effectively reduces the resistance of ohmic contacts, improving the efficiency and performance of the device.
[0060] Each of the aforementioned epitaxial layers can be fabricated using molecular beam epitaxy (MBE) or chemical vapor deposition (MOCVD) techniques. After micro / nano fabrication, the epitaxial structure is used to create a HEMT device, the structure of which is shown below. Figure 2 As shown.
[0061] The cap layer 10 in the epitaxial structure is processed into a source cap layer 10-1 and a drain cap layer 10-2, on which a source metal electrode 12 and a drain metal electrode 13 are deposited respectively.
[0062] The gate metal electrode 15 is processed into a T-shaped gate electrode, with a narrow gate that contacts the semiconductor surface at the bottom, which is close to the semiconductor surface and improves the cutoff frequency of the device; at the same time, the gate cap width is increased, which effectively reduces the gate resistance.
[0063] Finally, a passivation layer 14 is grown on the metal gate. The passivation layer is a key structure for reducing surface defects of the device, suppressing current collapse effect and improving reliability.
[0064] DC simulation of the HEMT device structure of this invention was performed using Sentaurus TCAD software, and the Vg-Id curve and Vd-Id curve were obtained, as shown in the figures below. Figure 3 and Figure 4 As shown.
[0065] like Figure 3 As shown, under the condition of Vds = 1.0V, the drain current (Id) exhibits obvious threshold voltage and high transconductance characteristics as it changes with the gate voltage (Vgs). When Vgs is below the threshold voltage, Id is almost zero, indicating that the device is in the off state; when Vgs exceeds the threshold voltage, Id increases rapidly, indicating that the device has entered the saturation region.
[0066] The advantages are as follows: ① The curve shows that the device has a low threshold voltage, indicating that it can be turned on at low voltage, which is suitable for low power consumption applications; ② After Vgs exceeds the threshold voltage, Id increases rapidly, indicating that the device has high transconductance and can provide high gain; ③ The steep rise of the curve indicates that the device has good switching characteristics and can achieve fast switching at low voltage.
[0067] like Figure 4 As shown, under different Vgs conditions, the drain current (Id) exhibits different characteristics as a function of the drain voltage (Vds). When Vgs is low (e.g., Vgs = -1V), Id increases slowly with increasing Vds, indicating that the device is in the off state; when Vgs is high (e.g., Vgs = 1.5V), Id increases rapidly with increasing Vds, indicating that the device has entered the saturation region.
[0068] The advantages are as follows: ① Under high Vgs conditions, Id increases rapidly with the increase of Vds, indicating that the device has high saturation current and can provide high output power; ② In the low Vds range, Id is linearly related to Vds, indicating that the device has good linearity and is suitable for high frequency applications; ③ Under low Vgs conditions, Id is almost zero, indicating that the device has low leakage current in the off state, which improves the energy efficiency of the device.
[0069] Simulation results show that the HEMT device structure of this invention has significant advantages in DC characteristics, mainly attributed to the design of the graded buffer layer and the high indium and graded dual-channel structure. The graded buffer layer effectively reduces lattice mismatch stress and improves material quality; the graded dual-layer composite channel provides a high-density two-dimensional electron gas and excellent electron mobility characteristics, thereby achieving high transconductance and high saturation current density.
[0070] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. However, it should be understood that the implementation of the present invention is not limited to the above embodiments. Any changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principle of the present invention should be considered equivalent substitutions and included within the protection scope of the present invention.
Claims
1. A low-temperature, low-noise InP-based HEMT device structure, characterized in that, From bottom to top, the layers are: substrate layer, first buffer layer, second buffer layer, first channel layer, second channel layer, isolation layer, δ-Si doped layer, barrier layer, etch stop layer, and cap layer; among which, The substrate layer is composed of InP; The first buffer layer is composed of In 0.52 Al 0.48 As; The second buffer layer uses a gradient composition, with In as the component. z Al 1-z As, z: 0.52~0.60, the z value gradually increases from bottom to top in the thickness direction; The first channel layer uses a graded composition, with In as the composition. x Ga 1-x As, x: 0.60~0.80; the x value gradually increases from bottom to top in the thickness direction; The second channel layer is composed of In y Ga 1-y As, 0.75 <y<0.85; The isolation layer is composed of In 0.52 Al 0.48 As; The barrier layer is composed of In 0.52 Al 0.48 As; The etching stop layer is composed of InP; The cap layer component is In 0.53 Ga 0.47 As.
2. The InP-based HEMT device structure according to claim 1, characterized in that, The thickness of the first buffer layer is 430–480 nm; The thickness of the second buffer layer is 45–55 nm; The thickness of the first channel layer is 6–8 nm; The thickness of the second channel layer is 7–9 nm; The thickness of the isolation layer is 4–6 nm; The thickness of the barrier layer is 10–12 nm; The thickness of the etching stop layer is 3–5 nm; The thickness of the cap layer is 19–21 nm.
3. The InP-based HEMT device structure according to claim 2, characterized in that, The distribution of z-values in the thickness direction of the second buffer layer component is as follows: 0-15nm, z=0.52, 15-30nm, z=0.56 30-40nm, z=0.58 40-(45~55)nm, z=0.
60.
4. The InP-based HEMT device structure according to claim 2, characterized in that, The distribution of x-values in the thickness direction of the first channel layer component is as follows: 0-2nm, x=0.60, 2-4nm, x=0.65, 4-5nm, x=0.70 5-5.5nm, x=0.75 5.5-(6~8)nm, x=0.
80.
5. The InP-based HEMT device structure according to claim 1, characterized in that: The doping concentration of the δ-Si doped layer is 3×10⁻⁶. 12 cm -2 ~7×10 12 cm -2 .
6. The InP-based HEMT device structure according to claim 1, characterized in that: The cap layer is doped with Si as the dopant at a concentration of 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 .