Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof. The semiconductor device is provided with a first voltage area and a second voltage area. The preparation method comprises the following steps: providing a substrate, the substrate comprising a substrate, an isolation structure and a mask layer, the mask layer having a first opening, the first opening being located in the first voltage area and exposing at least part of the substrate; etching the substrate based on the first opening to form a first gate medium groove in the first voltage area; forming a protective layer on at least the sidewall and the bottom of the first gate medium groove; forming a second opening in the mask layer located in the second voltage area, the second opening exposing at least part of the substrate located in the second voltage area; etching the substrate based on the second opening to form a second gate medium groove in the second voltage area; removing the protective layer; forming a first gate medium layer in the first gate medium groove and a second gate medium layer in the second gate medium groove. The application can reduce the preparation process complexity of the semiconductor device with different voltage areas.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In semiconductor devices, different voltage regions are typically used to form transistors with different start-up voltages. In traditional technology, the gate dielectric layers of transistors in different voltage regions are formed through two separate processes, which is complex. Summary of the Invention

[0003] Based on this, this application provides a method for fabricating semiconductor devices that can reduce process complexity.

[0004] A method for fabricating a semiconductor device, the semiconductor device having a first voltage region and a second voltage region, the method comprising:

[0005] A substrate is provided, the substrate including a substrate, an isolation structure and a mask layer, the isolation structure being partially located within the substrate and protruding upward from the substrate, the mask layer covering the substrate and the isolation structure, and having a first opening within the mask layer, the first opening being located in a first voltage region and at least exposing a portion of the substrate;

[0006] Based on the first opening, the substrate is etched to form a first gate dielectric trench in the first voltage region;

[0007] A protective layer is formed at least on the sidewalls and bottom of the first gate dielectric trench;

[0008] A second opening is formed within the mask layer located in the second voltage region, the second opening exposing at least a portion of the substrate located in the second voltage region;

[0009] The substrate is etched based on the second opening to form a second gate dielectric trench in the second voltage region;

[0010] Remove the protective layer;

[0011] A first gate dielectric layer is formed in the first gate dielectric trench, and a second gate dielectric layer is formed in the second gate dielectric trench.

[0012] In one embodiment, the formation of a protective layer at least on the sidewalls and bottom of the first gate dielectric trench includes:

[0013] The protective layer is formed within the first gate dielectric trench and on the mask layer, and the surface of the protective layer away from the substrate is flat.

[0014] In one embodiment, the protective layer is formed by spin coating.

[0015] In one embodiment, the first opening also exposes a portion of the isolation structure located in the first voltage region, and the step of etching the substrate based on the first opening to form a first gate dielectric trench in the first voltage region further includes:

[0016] The isolation structure is first etched based on the first opening to form a first groove on the side of the isolation structure near the substrate, the first groove exposing the substrate;

[0017] And / or,

[0018] The second opening also exposes a portion of the isolation structure located in the second voltage region. Prior to etching the substrate based on the second opening to form a second gate dielectric trench in the second voltage region, the method further includes:

[0019] A second etching is performed on the isolation structure based on the second opening to form a second groove on the side of the isolation structure near the substrate, the second groove exposing the substrate.

[0020] In one embodiment, while etching to form the first groove, the isolation structure exposed by the first opening is etched thinned to form a first step portion, and the first groove is located between the first step portion and the substrate;

[0021] And / or,

[0022] While etching to form the second groove, the isolation structure exposed by the second opening is etched thin to form a second step portion, and the second groove is located between the second step portion and the substrate.

[0023] In one embodiment, the substrate further includes an ion implantation barrier layer covering the substrate and the isolation structure, with the mask layer located on the side of the ion implantation barrier layer away from the substrate.

[0024] The first etching of the isolation structure based on the first opening includes:

[0025] Based on the first opening, the ion implantation barrier layer and the isolation structure located in the first voltage region are sequentially wet etched;

[0026] And / or,

[0027] A second etching is performed on the isolation structure based on the second opening, including:

[0028] Based on the two openings, the ion implantation barrier layer and the isolation structure located in the second voltage region are sequentially wet-etched.

[0029] In one embodiment, the recess depth of the first groove relative to the substrate is greater than or equal to the etching depth of the first gate dielectric trench; and / or, the recess depth of the second groove relative to the substrate is greater than or equal to the etching depth of the second gate dielectric trench.

[0030] In one embodiment, a first gate dielectric layer is formed in the first gate dielectric trench, and a second gate dielectric layer is formed in the second gate dielectric trench, including:

[0031] The substrate exposed by the first gate dielectric trench and the substrate exposed by the second gate dielectric trench are subjected to thermal oxidation treatment to form a first gate dielectric layer in the first gate dielectric trench and a second gate dielectric layer in the second gate dielectric trench.

[0032] A semiconductor device is fabricated according to the above-described semiconductor device fabrication method.

[0033] A semiconductor device, the semiconductor device having a first voltage region and a second voltage region, comprising:

[0034] Substrate;

[0035] An isolation structure, partially located within the substrate;

[0036] A first gate dielectric layer is located within the substrate of the first voltage region;

[0037] The second gate dielectric layer is located within the substrate of the second voltage region;

[0038] The first gate dielectric layer extends from the substrate into a portion of the isolation structure, and the isolation structure to which the first gate dielectric layer extends has a first step portion adjacent to the first gate dielectric layer, and the surface of the first step portion away from the substrate is lowered.

[0039] And / or, the second gate dielectric layer extends from the substrate into a portion of the isolation structure, and the isolation structure to which the second gate dielectric layer extends has a second step portion adjacent to the second gate dielectric layer, and the surface of the second step portion away from the substrate is lowered.

[0040] In the aforementioned semiconductor device fabrication method, after forming the first gate dielectric trench, a first gate dielectric layer is not directly formed within the first gate dielectric trench. Instead, a protective layer is formed within the first gate dielectric trench. Then, a second opening is formed within a mask layer located in the second voltage region without removing the mask layer. This allows the previously formed mask layer to still be used as an etching mask during the formation of the second gate dielectric trench, eliminating the need for repeated deposition and removal of the mask layer at different voltages (the first voltage region and the second voltage region), thus effectively reducing process complexity. Furthermore, the first and second gate dielectric layers can be formed simultaneously, further reducing process complexity and cost. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a method for fabricating a semiconductor device provided in one embodiment;

[0043] Figures 2-13 This is a schematic cross-sectional view of the structure obtained during the fabrication process of a semiconductor device provided in one embodiment; wherein, Figures 2 to 6 This is a schematic diagram of the cross-sectional structure of the first voltage region; Figures 8 to 11 This is a schematic diagram of the cross-sectional structure of the second voltage region; Figure 7 In the figure, (a) is a schematic diagram of the cross-sectional structure of the first voltage region, and (b) is a schematic diagram of the cross-sectional structure of the second voltage region; Figure 12 In the figure, (a) is a schematic diagram of the cross-sectional structure of the first voltage region, and (b) is a schematic diagram of the cross-sectional structure of the second voltage region; Figure 13 In the figure, (a) is a schematic diagram of the cross-sectional structure of the first voltage region, and (b) is a schematic diagram of the cross-sectional structure of the second voltage region;

[0044] Figure 14 The figures provided are schematic cross-sectional views of different voltage regions of a semiconductor device provided in one embodiment, wherein (a) is a schematic cross-sectional view of the first voltage region and (b) is a schematic cross-sectional view of the second voltage region.

[0045] Explanation of reference numerals in the attached figures:

[0046] 100 - Substrate, 110 - Substrate, 120 - Isolation structure, 121 - First step, 122 - Second step, 130 - Mask layer, 140 - Ion implantation barrier layer, 200 - Protective layer, 310 - First gate dielectric layer, 320 - Second gate dielectric layer, 410 - First photoresist layer, 420 - Second photoresist layer, 11 - First opening, 12 - Second opening, 21 - First gate dielectric trench, 22 - Second gate dielectric trench, 31 - First photoresist opening, 32 - Second photoresist opening, 41 - First groove, 42 - Second groove, 50 - Third opening, A1 - First voltage region, A2 - Second voltage region. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0052] In one embodiment, a method for fabricating a semiconductor device is provided. The semiconductor device includes a first voltage region A1 and a second voltage region A2. The first voltage region A1 and the second voltage region A2 are used to form transistors with different start-up voltages.

[0053] Please see Figure 1 The fabrication method of semiconductor devices includes the following steps:

[0054] Step S10, please refer to Figure 3 A substrate 100 is provided, the substrate 100 includes a substrate 110, an isolation structure 120 and a mask layer 130, the isolation structure 120 is partially located within the substrate 110 and divides the substrate 110 into a plurality of substrates 110, the mask layer 130 covers the substrate 110 and the isolation structure 120, and the mask layer 130 has a first opening 11, the first opening 11 is located in a first voltage region A1 and at least exposes a portion of the substrate 110;

[0055] For step S20, please refer to... Figure 6 Based on the first opening 11, the substrate 110 is etched to form the first gate dielectric trench 21 in the first voltage region A1;

[0056] For step S30, please refer to... Figure 7A protective layer 200 is formed at least on the sidewalls and bottom of the first gate dielectric trench 21;

[0057] For step S40, please refer to... Figure 9 A second opening 12 is formed in the mask layer 130 located in the second voltage region A2, and the second opening 12 exposes at least a portion of the substrate 110 located in the second voltage region A2.

[0058] For step S50, please refer to... Figure 11 Based on the second opening 12, the substrate 110 is etched to form a second gate dielectric trench 22 in the second voltage region A2;

[0059] For step S60, please refer to... Figure 12 Remove the protective layer 200;

[0060] For step S70, please refer to... Figure 13 A first gate dielectric layer 310 is formed in the first gate dielectric trench 21, and a second gate dielectric layer 320 is formed in the second gate dielectric trench 22.

[0061] In step S10, the substrate 110 may include, but is not limited to, a silicon substrate 110.

[0062] The isolation structure 120 may be, but is not limited to, an insulating material such as silicon oxide. Part of the isolation structure 120 is located within the substrate 110, thereby dividing the substrate 110 into multiple active regions. Transistors and the like can be formed within these active regions.

[0063] Please see Figure 2 After forming the isolation structure 120 within the substrate 110, a mask layer 130 covering the substrate 110 and the isolation structure 120 can be formed. The material of the mask layer 130 may include, but is not limited to, silicon nitride. See then... Figure 3 A patterned first photoresist layer 410 can be formed on the mask layer 130. The patterned first photoresist layer 410 can have a first photoresist opening 31 in the first voltage region A1. Then, based on the first photoresist opening 31, the mask layer 130 is etched, so that the etched mask layer 130 has a first opening 11 located in the first voltage region A1.

[0064] After the first opening 11 is formed, the patterned first photoresist layer 410 can be retained or removed.

[0065] In step S20, the first gate dielectric trench 21 is used to form the first gate dielectric layer 310 of the first transistor located in the first voltage region A1. The depth of the first gate dielectric trench 21 is related to the startup voltage of the first transistor and can be set according to actual needs.

[0066] Please see Figure 5as well as Figure 6 After the first gate dielectric trench 21 is formed, the first photoresist layer 410 can be removed.

[0067] In step S30, please refer to Figure 7 The protective layer 200 is formed at least on the sidewalls and bottom of the first gate dielectric trench 21.

[0068] Specifically, the protective layer 200 can be located only within the first gate dielectric trench 21, or it can be located both within the first gate dielectric trench 21 and on the mask layer 130. Regardless of whether the protective layer 200 is located only within the first gate dielectric trench 21 or both within the first gate dielectric trench 21 and on the mask layer 130, within the first gate dielectric trench 21, the protective layer 200 can fill the first gate dielectric trench 21 completely or not. The specific configuration can be determined according to actual requirements.

[0069] In step S40, as an example, please refer to Figure 7 When the protective layer 200 is located within the first gate dielectric trench 21 and on the mask layer 130, a second photoresist layer 420 can be first coated on the protective layer 200. Then, the second photoresist layer 420 is exposed and developed to form a patterned second photoresist layer 420. The patterned second photoresist layer 420 may have a second photoresist opening 32 in the second voltage region A2. Then, please refer to... Figure 8 as well as Figure 9 The protective layer 200 and the mask layer 130 can be etched sequentially based on the second photoresist opening 32. After etching, a third opening 50 can be formed in the protective layer 200, and a second opening 12 can be formed in the mask layer 130. The second opening 12 and the third opening 50 can be arranged opposite to each other.

[0070] At this point, when the second photoresist layer 420 is applied, a protective layer 200 is formed within the first gate dielectric trench 21. This protective layer 200 can fill the first gate dielectric trench 21 or at least reduce its depth and width. This facilitates better and more uniform application of the second photoresist layer 420, thereby improving photolithography accuracy.

[0071] As another example, the second photoresist layer 420 can also be used as the protective layer 200. In this case, after the protective layer 200 (second photoresist layer 420) is formed, it can be directly exposed and developed to pattern it and form the second photoresist opening 32. Then, the mask layer 130 is etched based on the second photoresist opening 32 to form the second opening 12 within the mask layer 130.

[0072] As another example, the protective layer 200 may be located only within the first gate dielectric trench 21. In this case, the protective layer 200 may, for example, fill the first gate dielectric trench 21. Then, a second photoresist layer 420 may be formed on the protective layer 200 and the mask layer 130. The second photoresist layer 420 is then exposed and developed to form a patterned second photoresist layer 420, which may have a second photoresist opening 32 in the second voltage region A2. The mask layer 130 may then be etched based on the second photoresist opening 32 to form a second opening 12 within the mask layer 130.

[0073] At this point, it is also easier to coat the second photoresist layer 420 more evenly, thereby improving the photolithography accuracy.

[0074] After the second opening 12 is formed in the mask layer 130, the patterned second photoresist layer 420 can be retained or removed.

[0075] In step S50, please refer to Figure 11 In the second voltage region A2, a second gate dielectric trench 22 is etched to form. Meanwhile, in the first voltage region A1, the substrate 110 exposed by the first gate dielectric trench 21 is covered (or covered by the protective layer 200) by the protective layer 200 and the second photoresist layer 420, so that it will not be etched.

[0076] Please see Figure 12 After the second gate dielectric trench 22 is formed, the second photoresist layer 420 can be removed.

[0077] The depth of the second gate dielectric trench 22 may be different from the depth of the first gate dielectric trench 21.

[0078] The second gate dielectric trench 22 is used to form the second gate dielectric layer 320 of the second transistor located in the second voltage region A2. The depth of the second gate dielectric trench 22 is related to the startup voltage of the second transistor and can be set according to actual needs.

[0079] As an example, the first voltage region A1 can be a high-voltage region, and the second voltage region A2 can be a medium-voltage region or a low-voltage region. The startup voltage of the first transistor can be greater than the startup voltage of the second transistor.

[0080] At this time, the depth of the second gate dielectric trench 22 located in the second voltage region A2 can be less than the depth of the first gate dielectric trench 21 located in the first voltage region A1.

[0081] Of course, in other examples, the arrangement of the first voltage region A1 and the second voltage region A2 can also be different. The startup voltage of the first transistor can also be lower than the startup voltage of the second transistor.

[0082] In step S60, please refer to Figure 12 After the protective layer 200 is removed, the first gate dielectric trench 21 exposes the substrate 110 located in the first voltage region A1 again. At the same time, the substrate 110 located in the second voltage region A2 is also exposed by the second gate dielectric trench 22.

[0083] In step S70, please refer to Figure 13 The first gate dielectric layer 310 and the second gate dielectric layer 320 may be formed simultaneously, but are not limited to.

[0084] A first gate dielectric layer 310 is formed within a first gate dielectric trench 21, and a second gate dielectric layer 320 is formed within a second gate dielectric trench 22. The depth of the second gate dielectric trench 22 is different from the depth of the first gate dielectric trench 21, which allows the thickness of the second gate dielectric layer 320 to be different from the thickness of the first gate dielectric layer 310. Based on this, a second transistor and a first transistor with different start-up voltages can be formed in the second voltage region A2 and the first voltage region A1, respectively.

[0085] Please see Figure 14 After the first gate dielectric layer 310 and the second gate dielectric layer 320 are formed, the mask layer 130 can be removed.

[0086] In this embodiment, after forming the first gate dielectric trench 21, the first gate dielectric layer 310 is not directly formed in the first gate dielectric trench 21. Instead, a protective layer 200 is formed within the first gate dielectric trench 21. Then, a second opening 12 is formed within the mask layer 130 located in the second voltage region A2, without removing the mask layer 130. This allows the previously formed mask layer 130 to still be used as an etching mask during the formation of the second gate dielectric trench 22, eliminating the need for repeated deposition and removal of the mask layer 130 at different voltages (first voltage region A1 and second voltage region A2), thus effectively reducing process complexity. Furthermore, the first gate dielectric layer 310 and the second gate dielectric layer 320 can be formed simultaneously, further reducing process complexity and cost.

[0087] In one embodiment, see Figure 13 Step S70 includes:

[0088] Step S70a: The substrate 110 exposed by the first gate dielectric trench 21 and the substrate 110 exposed by the second gate dielectric trench 22 are subjected to thermal oxidation treatment to form a first gate dielectric layer 310 in the first gate dielectric trench 21 and a second gate dielectric layer 320 in the second gate dielectric trench 22.

[0089] The first gate dielectric layer 310 and the second gate dielectric layer 320 can be formed simultaneously by oxidation, thereby reducing the complexity of the process.

[0090] It is understood that the thickness of the first gate dielectric layer 310 depends on the depth of the first gate dielectric trench 21, and the thickness of the second gate dielectric layer 320 depends on the depth of the second gate dielectric trench 22. Specifically, the depth of the gate dielectric trench affects its surface area, and the surface area affects the rate of wet oxidation. The larger the surface area, the faster the gate dielectric layer is formed. At the same time, as the thickness of the gate dielectric layer formed by thermal oxidation of the substrate 110 gradually increases, so that the gate dielectric layer extends beyond the surface of the substrate 110 to a certain extent, the substrate 110 will no longer be oxidized.

[0091] Therefore, a first gate dielectric layer 310 and a second gate dielectric layer 320 with different thicknesses can be formed simultaneously in the same thermal oxidation process.

[0092] In one embodiment, step S30 includes:

[0093] For step S30a, please refer to Figure 7 A protective layer 200 is formed in the first gate dielectric trench 21 and on the mask layer 130, and the surface of the protective layer 200 away from the substrate 110 is flat.

[0094] At this time, the protective layer 200 can fill the first gate dielectric trench 21, thereby facilitating the better and more uniform coating of the second photoresist layer 420 in subsequent processes, thus improving photolithography accuracy.

[0095] In one embodiment, in step S30a, the protective layer 200 is formed by spin coating. Spin coating allows for the direct formation of a protective layer 200 with a flat upper surface (the surface away from the substrate 110), thus simplifying the fabrication process of the protective layer 200.

[0096] As an example, the material of the protective layer 200 may include organic materials. For instance, the material of the protective layer 200 may include spin-coated carbon (SOC), etc.

[0097] Organic materials such as spin-coated carbon (SOC) have high fluidity and can easily fill the first gate dielectric trench 21, forming a protective layer 200 with a flat upper surface.

[0098] Please also see Figure 11 as well as Figure 12 Organic materials such as spin-coated carbon (SOC) can be removed simultaneously with the second patterned photoresist, which can effectively reduce the complexity of the process.

[0099] Of course, in other embodiments, the protective layer 200 can also be in other forms, and the material of the protective layer 200 is not limited to organic materials such as spin-coated carbon (SOC). For example, the protective material layer can also be formed by a deposition process, and then the protective material layer can be CMP polished to form a protective layer 200 with a flat upper surface.

[0100] In one embodiment, see Figure 3 The first opening 11 also exposes part of the structure of the isolation structure 120 located in the first voltage region A1.

[0101] As an example, in the first voltage region A1, there may be a first opening 11 between adjacent isolation structures 120, the first opening 11 can expose a portion of the substrate 110 and a portion of the structure of the isolation structure 120 located on one side of the substrate 110.

[0102] Before step S20, please refer to Figure 4 It also includes:

[0103] Step S11: The isolation structure 120 is first etched based on the first opening 11 to form a first groove 41 on the side of the isolation structure 120 near the substrate 110, and the first groove 41 exposes the substrate 110.

[0104] The isolation structure 120 is typically in the shape of an inverted trapezoid. If the substrate 110 is directly etched based on the first opening 11 to form the first gate dielectric trench 21, then during the etching process of the first gate dielectric trench 21, the corners of the isolation structure 120 may block the etching of parts of the substrate 110 near the isolation structure 120, resulting in sharp-cornered structures. These sharp-cornered structures are prone to charge accumulation, which increases the risk of leakage current in the first transistor formed based on the first gate dielectric trench 21, leading to unstable electrical performance of the first transistor.

[0105] In this embodiment, before forming the first gate dielectric trench 21, a first groove 41 is first formed on the side of the isolation structure 120 near the substrate 110. This allows the corners of the isolation structure 120 to no longer block or reduce the blocking of the substrate 110 near the isolation structure 120 during the etching process of the first gate dielectric trench 21. This avoids the formation of sharp corner structures or reduces the height of sharp corner structures, thereby effectively improving the leakage problem.

[0106] It is understandable that after the first groove 41 is formed, when the first gate dielectric trench 21 is formed, the first groove 41 becomes part of the first gate dielectric trench 21.

[0107] In one embodiment, see Figure 4 In step S11, while etching to form the first groove 41, the isolation structure 120 exposed by the first opening 11 is etched and thinned to form the first step portion 121. The first groove 41 is located between the first step portion 121 and the substrate 110.

[0108] As an example, in step S11, the first etching can be performed using wet etching. Wet etching has anisotropic characteristics, and the height of the upper surface of the isolation structure 120 before etching is greater than the height of the upper surface of the substrate 110. Therefore, during the process of etching the isolation structure 120 exposed by the first opening 11 using wet etching, the isolation structure 120 will be etched not only longitudinally but also laterally, so that the isolation structure 120 will be etched away more quickly near the substrate 110, thereby forming the first groove 41 and the first step portion 121.

[0109] Of course, in other examples, the first etching is not limited to wet etching; for example, the first etching can also be carried out by dry etching under suitable conditions.

[0110] The first step portion 121 is formed by etching and thinning the isolation structure 120, so the height of the upper surface of the first step portion 121 can be reduced to be comparable to the height of the upper surface of the substrate 110, and the height difference between the two can be less than or equal to 30 Å.

[0111] At this time, after the first gate dielectric layer 310 is formed in the first gate dielectric trench 21 in the subsequent steps, the height of the upper surface of the first step portion 121 can be equivalent to the height of the first gate dielectric layer 310, so that when the first gate of the first transistor is formed in the subsequent steps, the first gate is formed on a relatively flat surface.

[0112] In one embodiment, see Figure 4 The substrate 100 also includes an ion implantation barrier layer 140. The ion implantation barrier layer 140 protects the upper surface of the substrate 110 during the subsequent doping of the substrate 110 to form the source and drain regions of the transistor.

[0113] An ion implantation barrier layer 140 covers the substrate 110 and the isolation structure 120. A mask layer 130 is located on the side of the ion implantation barrier layer 140 away from the substrate 110.

[0114] Step S11 includes:

[0115] Step S11a: Based on the first opening 11, wet etching is performed sequentially on the ion implantation barrier layer 140 and the isolation structure 120 located in the first voltage region A1.

[0116] For example, the material of the ion implantation barrier layer 140 can be the same as the material of the isolation structure 120. In this case, the etching of the isolation structure 120 can be performed during the step of etching the ion implantation barrier layer 140 of the first voltage region A1, so that no additional etching step of the isolation structure 120 is required.

[0117] In one embodiment, the recess depth of the first groove 41 relative to the substrate 110 is greater than or equal to the etching depth of the first gate dielectric trench 21. In this case, after etching to form the first gate dielectric trench 21, almost no sharp corner structure is formed, thereby more effectively improving the leakage problem.

[0118] Of course, the recess depth of the first groove 41 relative to the substrate 110 can also be slightly less than the etching depth of the first gate dielectric trench 21, which can also reduce the risk of leakage current compared to not forming the first groove 41.

[0119] In one embodiment, see Figure 9 The second opening 12 also exposes part of the structure of the isolation structure 120 located in the second voltage region A2.

[0120] As an example, in the second voltage region A2, a second opening 12 may be provided between adjacent isolation structures 120, the second opening 12 may expose a portion of the substrate 110 and a portion of the structure of the isolation structure 120 located on one side of the substrate 110.

[0121] Before step S50, please refer to Figure 10 It also includes:

[0122] Step S41: The isolation structure 120 is etched a second time based on the second opening 12 to form a second groove 42 on the side of the isolation structure 120 near the substrate 110, and the second groove 42 exposes the substrate 110.

[0123] The isolation structure 120 is typically in the shape of an inverted trapezoid. If the substrate 110 is directly etched based on the second opening 12 to form the second gate dielectric trench 22, during the etching process of the second gate dielectric trench 22, the corners of the isolation structure 120 may obstruct the etching, resulting in a portion of the substrate 110 near the isolation structure 120 not being etched, forming a sharp-cornered structure. Sharp-cornered structures tend to accumulate charge, thereby increasing the risk of leakage current in the second transistor formed based on the second gate dielectric trench 22, leading to unstable electrical performance of the second transistor.

[0124] In this embodiment, before forming the second gate dielectric trench 22, a second groove 42 is first formed on the side of the isolation structure 120 near the substrate 110. This allows the corners of the isolation structure 120 to no longer block or reduce the blocking of the substrate 110 near the isolation structure 120 during the etching process of the second gate dielectric trench 22. This avoids the formation of sharp corner structures or reduces the height of sharp corner structures, thereby effectively improving the leakage problem.

[0125] It can be understood that after the second groove 42 is formed, when the second gate dielectric trench 22 is formed, the second groove 42 becomes part of the second gate dielectric trench 22.

[0126] In one embodiment, in step S41, please refer to Figure 10 While etching to form the second groove 42, the isolation structure 120 exposed by the second opening 12 is etched and thinned to form the second step portion 122. The second groove 42 is located between the second step portion 122 and the substrate 110.

[0127] As an example, in step S41, the second etching can be performed using wet etching. Wet etching has anisotropic characteristics, and the height of the upper surface of the isolation structure 120 before etching is greater than the height of the upper surface of the substrate 110. Therefore, during the process of etching the isolation structure 120 exposed by the second opening 12 using wet etching, the isolation structure 120 is etched not only longitudinally but also laterally, so that the isolation structure 120 is etched away more quickly near the substrate 110, thereby forming the second groove 42 and the second step portion 122.

[0128] Of course, in other examples, the second etching is not limited to wet etching; for example, the second etching can also be carried out by dry etching under suitable conditions.

[0129] The second step portion 122 is formed by etching and thinning the isolation structure 120, so the height of the upper surface of the second step portion 122 can be reduced to be comparable to the height of the upper surface of the substrate 110, and the height difference between the two can be less than or equal to 30 Å.

[0130] At this time, after the second gate dielectric layer 320 is formed in the second gate dielectric trench 22 in the subsequent steps, the height of the upper surface of the second step portion 122 can be comparable to the height of the second gate dielectric layer 320, so that when the second gate of the second transistor is formed in the subsequent steps, the second gate is formed on a relatively flat surface.

[0131] In one embodiment, see Figure 10 The substrate also includes an ion implantation barrier layer 140. The ion implantation barrier layer 140 protects the upper surface of the substrate 110 during the subsequent doping of the substrate 110 to form the source and drain regions of the transistor.

[0132] An ion implantation barrier layer 140 covers the substrate 110 and the isolation structure 120. A mask layer 130 is located on the side of the ion implantation barrier layer 140 away from the substrate 110.

[0133] Step S41 includes:

[0134] Step S41a: Based on the second opening 12, wet etching is performed sequentially on the ion implantation barrier layer 140 and the isolation structure 120 located in the second voltage region A2.

[0135] For example, the material of the ion implantation barrier layer 140 can be the same as the material of the isolation structure 120. In this case, the etching of the isolation structure 120 can be performed during the step of etching the ion implantation barrier layer 140 of the second voltage region A2, thus eliminating the need for an additional etching step for the isolation structure 120.

[0136] In one embodiment, the recess depth of the second groove 42 relative to the substrate 110 is greater than or equal to the etching depth of the second gate dielectric trench 22. In this case, after etching to form the second gate dielectric trench 22, almost no sharp corner structure is formed, thereby more effectively improving the leakage problem.

[0137] Of course, the recess depth of the second groove 42 relative to the substrate 110 can also be slightly less than the etching depth of the second gate dielectric trench 22, which can also reduce the risk of leakage current compared to not forming the second groove 42.

[0138] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0139] In one embodiment, a semiconductor device is also provided, which is formed according to the semiconductor device fabrication method of any of the above embodiments.

[0140] In one embodiment, see Figure 14 The invention also provides a semiconductor device having a first voltage region A1 and a second voltage region A2. The semiconductor device includes a substrate 110, an isolation structure 120, a first gate dielectric layer 310, and a second gate dielectric layer 320.

[0141] The isolation structure 120 is partially located within the substrate 110 and divides the substrate 110 into multiple active regions. A first gate dielectric layer 310 is located within the substrate 110 in the first voltage region A1 and is used to form a first transistor in the first voltage region A1. A second gate dielectric layer 320 is located within the substrate 110 in the second voltage region A2 and is used to form a second transistor in the second voltage region A2.

[0142] The first gate dielectric layer 310 extends from the substrate 110 into a portion of the isolation structure 120, thereby preventing or improving the sharp corner structure formed by the substrate 110 between the first gate dielectric layer 310 and the isolation structure 120, thereby reducing the risk of leakage.

[0143] Furthermore, the isolation structure 120 to which the first gate dielectric layer 310 extends has a first step portion 121. The first step portion 121 is adjacent to the first gate dielectric layer 310, and the surface of the first step portion 121 away from the substrate 110 is lowered.

[0144] At this time, the first step portion 121 of the first gate dielectric layer 310 facilitates the formation of the first gate of the first transistor based on the first gate dielectric layer 310 on a flat surface.

[0145] And / or, the second gate dielectric layer 320 extends from the substrate 110 into a portion of the isolation structure 120, thereby preventing or improving the sharp corner structure formed by the substrate 110 between the second gate dielectric layer 320 and the isolation structure 120, thereby reducing the risk of leakage.

[0146] Furthermore, the isolation structure 120 to which the second gate dielectric layer 320 extends has a second step portion 122. The second step portion 122 is adjacent to the second gate dielectric layer 320, and the surface of the second step portion 122 away from the substrate 110 is lowered.

[0147] At this time, the second step portion 122 facilitates the formation of the second gate of the second transistor based on the second gate dielectric layer 320 on a flat surface.

[0148] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device is provided with a first voltage region and a second voltage region, and the method includes: A substrate is provided, the substrate including a substrate, an isolation structure and a mask layer, the isolation structure being partially located within the substrate and protruding upward from the substrate, the mask layer covering the substrate and the isolation structure, and having a first opening within the mask layer, the first opening being located in a first voltage region and at least exposing a portion of the substrate; Based on the first opening, the substrate is etched to form a first gate dielectric trench in the first voltage region; A protective layer is formed at least on the sidewalls and bottom of the first gate dielectric trench; A second opening is formed within the mask layer located in the second voltage region, the second opening exposing at least a portion of the substrate located in the second voltage region; The substrate is etched based on the second opening to form a second gate dielectric trench in the second voltage region; Remove the protective layer; A first gate dielectric layer is formed in the first gate dielectric trench, and a second gate dielectric layer is formed in the second gate dielectric trench.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The protective layer formed at least on the sidewalls and bottom of the first gate dielectric trench includes: The protective layer is formed within the first gate dielectric trench and on the mask layer, and the surface of the protective layer away from the substrate is flat.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The protective layer is formed by spin coating.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first opening also exposes a portion of the isolation structure located in the first voltage region. Prior to etching the substrate based on the first opening to form the first gate dielectric trench in the first voltage region, the method further includes: The isolation structure is first etched based on the first opening to form a first groove on the side of the isolation structure near the substrate, the first groove exposing the substrate; And / or, The second opening also exposes a portion of the isolation structure located in the second voltage region. Prior to etching the substrate based on the second opening to form a second gate dielectric trench in the second voltage region, the method further includes: A second etching is performed on the isolation structure based on the second opening to form a second groove on the side of the isolation structure near the substrate, the second groove exposing the substrate.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, While etching to form the first groove, the isolation structure exposed by the first opening is etched and thinned to form a first step portion, and the first groove is located between the first step portion and the substrate; And / or, While etching to form the second groove, the isolation structure exposed by the second opening is etched thin to form a second step portion, and the second groove is located between the second step portion and the substrate.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The substrate further includes an ion implantation barrier layer that covers the substrate and the isolation structure, with the mask layer located on the side of the ion implantation barrier layer away from the substrate. The first etching of the isolation structure based on the first opening includes: Based on the first opening, the ion implantation barrier layer and the isolation structure located in the first voltage region are sequentially wet etched; And / or, A second etching is performed on the isolation structure based on the second opening, including: Based on the two openings, the ion implantation barrier layer and the isolation structure located in the second voltage region are sequentially wet-etched.

7. The method for fabricating a semiconductor device according to any one of claims 4-6, characterized in that, The first groove has a recess depth relative to the substrate that is greater than or equal to the etching depth of the first gate dielectric trench; and / or, the second groove has a recess depth relative to the substrate that is greater than or equal to the etching depth of the second gate dielectric trench.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming a first gate dielectric layer within the first gate dielectric trench and forming a second gate dielectric layer within the second gate dielectric trench, comprising: The substrate exposed by the first gate dielectric trench and the substrate exposed by the second gate dielectric trench are subjected to thermal oxidation treatment to form a first gate dielectric layer in the first gate dielectric trench and a second gate dielectric layer in the second gate dielectric trench.

9. A semiconductor device, characterized in that, The semiconductor device is prepared according to any one of claims 1-8.

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