A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device, and is applied to BCD (Bipolar-CMOS-DMOS, that is, bipolar transistor (Bipolar), complementary metal oxide semiconductor (CMOS), and diffusion metal oxide semiconductor (DMOS) are integrated on the same chip). The method comprises the following steps: forming a shallow trench on a semiconductor substrate, filling a first material in the shallow trench; forming a deep trench in part of the shallow trench, and depositing a second material in the deep trench; the second material and the first material are different insulating filling materials; in a subsequent etching process, the etching rates of the different insulating filling materials are different, which causes a gap to appear in a contact area of the shallow trench and the deep trench due to the different etching rates, and affects the stability of the device. Therefore, a top area of the deep trench is formed into a back etching area, a third material is deposited in the back etching area, so that the overlapping area of the deep trench and the shallow trench is deposited with the same material. Therefore, the defects existing in the semiconductor device manufacturing process are reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for preparing a semiconductor device and the semiconductor device itself. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.

[0003] Deep trench isolation (DTI) is a technique used in integrated circuit manufacturing. It achieves electrical isolation between different devices by etching deep trenches on a silicon wafer and filling them with insulating material. Shallow trench isolation (STI) achieves electrical isolation between components by etching relatively shallow trenches on the surface of the silicon wafer and filling these trenches with insulating material.

[0004] In the existing technology, the steps involved in the fabrication of semiconductor devices are relatively complex. The parameters for chemical mechanical polishing in this process are too small, which causes some crystal defects, resulting in a relatively high current passing through the transistor even when it is in the off state.

[0005] Therefore, reducing defects in the fabrication process of semiconductor devices is a technical problem that needs to be solved. Summary of the Invention

[0006] This application provides a method for fabricating a semiconductor device, which can reduce defects present during the fabrication process. This application also provides a semiconductor device.

[0007] The specific plan is as follows:

[0008] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate, forming shallow trenches on the semiconductor substrate, filling the shallow trenches with a first material; forming deep trenches in a portion of the shallow trenches, depositing a second material in the deep trenches, the second material being a different material from the first material; forming an etch-back region in the top region of the deep trenches filled with the second material, depositing a third material in the etch-back region, the etch-back region being the overlapping region of the shallow trenches and the deep trenches.

[0009] Optionally, forming a shallow trench on the semiconductor substrate and filling the shallow trench with a first material includes: forming a passivation oxide layer and a first hard mask layer on the epitaxial layer of the semiconductor substrate; forming the shallow trench on the semiconductor substrate by photolithography and etching; depositing the first material on the semiconductor substrate where the shallow trench is formed, wherein the deposited first material at least fills the shallow trench; and removing the first material on the semiconductor substrate by etching and / or polishing processes, wherein the removal process stops at the first hard mask layer.

[0010] Optionally, it also includes: removing the first hard mask layer while retaining the passivation oxide layer.

[0011] Optionally, it further includes: depositing a second hard mask layer on the passivation oxide layer and the surface of the shallow trench; the step of forming a deep trench in a portion of the shallow trench includes: defining the area where the deep trench needs to be formed by photolithography; performing an etching process to form a deep trench penetrating the portion of the shallow trench in the area corresponding to the portion of the shallow trench; and removing the photoresist.

[0012] Optionally, depositing the second material in the deep trench includes: depositing the second material on the surface of the second hard mask layer and in the deep trench using chemical vapor deposition.

[0013] Optionally, after obtaining the filled deep trench and the first insulating layer formed of the second material, the process further includes: removing the second material on the semiconductor substrate by etching and / or chemical mechanical polishing, and the removal process stops at the second hard mask layer.

[0014] Optionally, forming a back-etch region in the top region of the deep trench filled with the second material, and depositing the third material in the back-etch region, includes: etching the second material already filled in the top region of the deep trench to a set depth to form the back-etch region.

[0015] Optionally, it also includes: depositing the third material using high-density plasma chemical vapor deposition on the etch-back region and the surface of the second hard mask layer.

[0016] Optionally, the third material is the same as the first material.

[0017] Optionally, after obtaining the filled etched area and the second insulating layer formed by the third material, the process further includes: removing the third material on the semiconductor substrate by etching and / or chemical mechanical polishing, and the removal process stops at the second hard mask layer.

[0018] Optionally, it also includes: removing the second hard mask layer while retaining the passivation oxide layer.

[0019] Optionally, before depositing the second material in the deep trench, the method further includes: forming a sidewall oxide layer on the sidewall surface of the deep trench; bottom etching the deep trench and performing ion implantation at the bottom.

[0020] Optionally, it may also include filling the passivation oxide layer with polycrystalline silicon.

[0021] Secondly, embodiments of this application provide a semiconductor device, comprising: a semiconductor substrate, shallow trenches formed on the semiconductor substrate, deep trenches formed in a portion of the shallow trenches, the shallow trenches being filled with a first material, the deep trenches being filled with a second material, and a third material different from the second material being filled in the overlapping region between the top of the deep trenches and the shallow trenches.

[0022] Compared with the prior art, this application has the following advantages:

[0023] The semiconductor device fabrication method provided in this application includes a semiconductor substrate, shallow trenches formed on the semiconductor substrate, and a first material filled in the shallow trenches; deep trenches formed in a portion of the shallow trenches, and a second material deposited in the deep trenches, the second material being a different material from the first material; an etchback region formed at the top of the deep trenches filled with the second material, and a third material deposited in the etchback region, the etchback region being the overlapping area of ​​the shallow trenches and the deep trenches. Since the first material filling the shallow trenches and the second material deposited in the deep trenches are different insulating fillers, the different etching rates of the different insulating fillers in the subsequent etching process of semiconductor device fabrication will cause steps to form at the contact area between the shallow trenches and the deep trenches due to the different etching rates. This can lead to downward gaps or even inverted V-shaped depressions at the contact surfaces, potentially causing leakage and other electrical problems after device formation, affecting device stability. In this embodiment, after filling the shallow trench with a first material and depositing the deep trench with a second material, the top region of the deep trench is etched to form a back-etch region, and a third material is deposited in the back-etch region, thereby ensuring that the overlapping region of the deep trench and the shallow trench is deposited with the same material. Therefore, the etching rate of the material in this overlapping region is the same, preventing the formation or expansion of gaps at the junction of the two, reducing defects present during semiconductor device fabrication, and thus improving the electrical stability of the formed device. Attached Figure Description

[0024] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0025] Figure 2 This is a schematic diagram illustrating an example of forming a passivation oxide layer and a first hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.

[0026] Figure 3 This is a schematic diagram illustrating an example of forming a shallow trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.

[0027] Figure 4 This is a schematic diagram illustrating an example of removing the first photoresist layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0028] Figure 5 This is a schematic diagram illustrating an example of filling a shallow trench with a first material in a method for fabricating a semiconductor device according to an embodiment of this application.

[0029] Figure 6 This is a schematic diagram illustrating an example of removing a first material from a semiconductor substrate and retaining it in a first hard mask layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0030] Figure 7 This is a schematic diagram illustrating an example of removing the first hard mask layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0031] Figure 8 This is a schematic diagram illustrating an example of forming a second hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.

[0032] Figure 9 This is a schematic diagram illustrating an example of forming a deep trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.

[0033] Figure 10 This is a schematic diagram illustrating an example of removing the second photoresist layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0034] Figure 11 This is a schematic diagram illustrating an example of a method for fabricating a semiconductor device according to an embodiment of this application, including forming a sidewall oxide layer in a deep trench, bottom etching, and ion implantation.

[0035] Figure 12 This is a schematic diagram of an example of depositing a second material in a deep trench in a method for fabricating a semiconductor device provided in an embodiment of this application.

[0036] Figure 13 This is a schematic diagram illustrating an example of removing a second material from the semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0037] Figure 14 This is a schematic diagram of an example of the overlapping area of ​​shallow and deep trenches provided in an embodiment of this application.

[0038] Figure 15This is a schematic diagram illustrating an example of forming a back etch region in the top region of a deep trench in a method for fabricating a semiconductor device according to an embodiment of this application.

[0039] Figure 16 This is a schematic diagram illustrating an example of depositing a third material in the etch-back region during the fabrication of a semiconductor device provided in this application embodiment.

[0040] Figure 17 This is a schematic diagram illustrating an example of removing a third material from a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0041] Figure 18 This is a schematic diagram illustrating an example of removing a second hard mask layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0042] Figure 19 This is a schematic diagram illustrating an example of forming polycrystalline silicon on a portion of the surface of a shallow trench in a method for fabricating a semiconductor device according to an embodiment of this application.

[0043] Figure 20 This is a schematic diagram of an example of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0044] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0045] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0046] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0047] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0048] In existing technologies, the formation of shallow and deep trenches on the semiconductor substrate during semiconductor device fabrication occurs before the formation of the interlayer dielectric layer. The fabrication process in the overlapping region of the shallow and deep trenches is relatively complex. The parameters used in the chemical mechanical polishing process during this phase are often too small, resulting in some crystal defects that allow relatively high current to flow even when the transistor is in the off state.

[0049] Therefore, reducing defects in the fabrication process of semiconductor devices is a technical problem that needs to be solved.

[0050] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0051] The following, combined with Figures 1-19 This application describes a method for fabricating a semiconductor device according to embodiments.

[0052] Figure 1 The flowchart of the method for fabricating a semiconductor device provided in the embodiments of this application includes the following steps S101 to S103.

[0053] Step S101: Provide a semiconductor substrate, form a shallow trench on the semiconductor substrate, and fill the shallow trench with a first material.

[0054] This step is used to form shallow trenches on the provided semiconductor substrate and fill the shallow trenches with a first material.

[0055] In semiconductor manufacturing, the semiconductor substrate is the base used to form semiconductor devices. Semiconductor substrate materials include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The semiconductor substrate material can be selected according to actual needs during the fabrication process.

[0056] Figure 2 This is a schematic diagram illustrating an example of forming a passivation oxide layer and a first hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application. The semiconductor substrate may include a P-type substrate 01, an N-type buried layer 02, and a P-type epitaxial layer 03. The P-type epitaxial layer 03 is located above the P-type substrate 01, and the N-type buried layer 02 is disposed in the middle portion between the P-type epitaxial layer 03 and the P-type substrate 01.

[0057] A P-type substrate is typically a single-crystal silicon wafer doped with P-type impurities. A P-type substrate is a semiconductor wafer (hereinafter referred to as a wafer) where holes are the primary charge carriers, used as a substrate for manufacturing integrated circuits, power devices, or sensors. The P-type substrate provides mechanical support for the devices manufactured on it and serves as the operating platform for the semiconductor devices. P-type substrates exhibit P-type conductivity (hole concentration > electron concentration) by doping with acceptor impurities (such as boron, gallium, etc.).

[0058] An N-type buried layer (NBL) is a highly concentrated N-type doped region buried beneath a P-type epitaxial layer, typically fabricated during the initial stages of substrate preparation or before epitaxial growth. Specifically, the NBL region is defined on the surface of a P-type silicon substrate using photolithography, and then formed through high-dose ion implantation and high-temperature annealing. High-dose ion implantation refers to the implantation of N-type impurities (such as arsenic (As) or antimony (Sb)), typically with a dose of 10-1. 15 -10 16 cm -2 Energy ranges from 50 to 200 keV. High-temperature annealing refers to the diffusion of implanted ions at temperatures of 1000-1200℃, forming a deep junction (1-5μm deep) and activating impurities. One function of the N-type buried layer is to reduce collector / drain resistance: in bipolar transistors (BJTs) or power MOSFETs, NBLs act as low-resistance paths, improving current transport efficiency. Isolation and latch-up prevention: in CMOS processes, NBLs can block the conduction of parasitic PNP transistors, preventing latch-up. Reducing substrate interference: shielding noise or substrate leakage current.

[0059] After NBL is formed, a P-type epitaxial layer is formed on the semiconductor substrate.

[0060] A p-type epitaxial layer is a single-crystal thin film with p-type conductivity, formed on the surface of a semiconductor substrate (such as silicon or gallium arsenide) using epitaxial growth techniques. Its main purpose is to provide specific electrical properties (such as hole conductivity, reduced resistance, and increased breakdown voltage) or structural optimization (such as reduced defect density) for semiconductor devices by precisely controlling doping and crystal structure. Epitaxial growth techniques include chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). CVD involves introducing silicon-containing gases (such as silane (SiH4), dichlorosilane (SiH2Cl2), or silicon tetrachloride (SiCl4)) and p-type dopant sources (such as borane (B2H6)) into a high-temperature reaction chamber, where a chemical reaction causes silicon atoms to deposit on the substrate surface, gradually forming a single-crystal layer. MBE, on the other hand, operates in an ultra-high vacuum environment, where silicon and dopant elements (such as boron) are evaporated, and atomic or molecular beams are directly sprayed onto the substrate surface, causing a reaction and growth into a single-crystal layer.

[0061] The process of forming shallow trenches on a semiconductor substrate and filling them with a first material can be summarized as follows: forming a passivation oxide layer, forming a first hard mask layer, photoresist coating and exposure, development, etching shallow trenches, trench cleaning, and filling the shallow trenches with the first material.

[0062] In summary, forming a shallow trench on the semiconductor substrate includes: forming a passivation oxide layer and a first hard mask layer on the epitaxial layer of the semiconductor substrate; forming the shallow trench on the semiconductor substrate by photolithography and etching; depositing a first material on the semiconductor substrate where the shallow trench is formed, wherein the deposited first material at least fills the shallow trench; and removing the first material on the semiconductor substrate by etching and / or polishing processes, wherein the removal process stops at the first hard mask layer.

[0063] The following is a detailed description with reference to the accompanying drawings.

[0064] like Figure 2 As shown, a passivation oxide layer 04 and a first hard mask layer 05 are formed sequentially from bottom to top on the P-type epitaxial layer 03 to help precisely control the depth and shape of the shallow trench, while protecting the semiconductor substrate from erosion or wear in subsequent process steps.

[0065] A passivation oxide layer is a thin layer of silicon dioxide (SiO2) formed on a semiconductor substrate (e.g., a silicon substrate). Its function is to prevent contamination or oxidation of the silicon surface, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device. Passivation oxide layers can be generated through thermal oxidation or chemical vapor deposition. Thermal oxidation is a process of growing silicon dioxide by exposing the substrate to a high-temperature environment of oxygen or water vapor. Thermal oxidation includes dry oxidation and wet oxidation. Dry oxidation uses pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxidation uses water vapor to react with silicon to generate the oxide layer. Wet oxidation has a faster growth rate than dry oxidation, but the oxide layer density is lower than that of dry oxidation.

[0066] Chemical vapor deposition (CVD) is a material preparation technique that deposits solid thin films on a substrate surface through a gas-phase chemical reaction. The core principle is to utilize a gaseous precursor to undergo a chemical reaction under specific conditions, generating a solid product that is deposited on the substrate, while gaseous byproducts are removed from the system.

[0067] A hard mask layer is a thin film material with high hardness and high etch selectivity used for pattern transfer in semiconductor manufacturing. It is located between the photoresist and the material to be etched. The hard mask layer protects the passivation oxide layer and the semiconductor substrate from over-etching during subsequent etching steps.

[0068] Hard mask layers include, but are not limited to: silicon nitride (Si3N4) hard mask layers, silicon dioxide (SiO2) hard mask layers, metal hard mask layers, and amorphous carbon hard mask layers. In this embodiment, the hard mask layer is specifically a silicon nitride (Si3N4) hard mask layer.

[0069] The process of forming the shallow trench on the semiconductor substrate by photolithography and etching includes: defining the area where the shallow trench needs to be formed on a first hard mask layer of the semiconductor substrate by photolithography; and starting etching on the first hard mask layer to a first preset position on the semiconductor substrate to form the shallow trench.

[0070] Photolithography is a process that uses optical exposure to transfer a design pattern from a photomask onto a photoresist layer on the wafer surface. It creates a precise temporary pattern on the wafer surface, providing a template for subsequent etching or ion implantation.

[0071] Etching is a process that removes substrate material not protected by photoresist using physical or chemical methods, permanently transferring the photolithographic pattern onto a wafer. Its purpose is to precisely replicate the pattern to form device structures (such as gates and interconnect trenches). Etching includes wet etching and dry etching. Wet etching uses chemical solutions (such as hydrofluoric acid for silicon dioxide and phosphoric acid for silicon nitride) to selectively dissolve the material. Dry etching utilizes active ions or free radicals in plasma for etching, including physical etching (ion bombardment, such as Ar...). + Sputtering or chemical etching (gas reaction, such as carbon tetrafluoride plasma etching of silicon).

[0072] Figure 3 This is a schematic diagram illustrating an example of forming a shallow trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.

[0073] A first photoresist layer 06 is applied to the first hard mask layer 05, and the area where shallow trenches need to be formed is defined on the first hard mask layer 05 by exposure and development. According to the depth and shape required for etching the shallow trenches, a shallow trench 07 is formed through the first hard mask layer 05, the passivation oxide layer 04, and to a first predetermined position on the epitaxial layer 03 of the semiconductor substrate by an etching process.

[0074] Then, remove Figure 3 The first photoresist layer 06 is exposed until the surface of the first hard mask layer 05 is revealed, as shown in the image. Figure 4 As shown.

[0075] Subsequently, a first material is filled into the shallow trench. This first material is an insulating filler, primarily used to isolate different device regions, reduce crosstalk, and improve the overall performance of the integrated circuit. The insulating filler material includes, but is not limited to: silicon dioxide (SiO2), silicon nitride (Si3N4), borosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, and high molecular weight organic polymers.

[0076] Trench filling is a process in semiconductor manufacturing where material (e.g., dielectric, metal, or polysilicon) is deposited into etched trenches, vias, or other high aspect ratio structures. The primary goals are to achieve void-free filling, high uniformity, and process compatibility. Void-free filling prevents electrical failures or reduced mechanical strength due to incomplete trench filling. High uniformity includes consistent material thickness throughout the trench. Process compatibility ensures seamless integration of the trench filling process with subsequent semiconductor device fabrication processes (e.g., etching or chemical mechanical polishing).

[0077] The filling process used to fill the shallow trench with the first material is related to the material type of the first material, the aspect ratio of the trench, and the requirements of subsequent processes. The filling process may include, but is not limited to: (1) High-density plasma chemical vapor deposition: shallow trenches are deposited by high-energy plasma to achieve good step coverage and gap filling ability. This makes the first material filling the shallow trench achieve the effect of high filling density and few voids. (2) Sub-atmospheric pressure chemical vapor deposition: oxides are deposited under low pressure, which makes the filling uniformity of the shallow trench better. (3) Atomic layer deposition: atomic-level thin films are deposited layer by layer. This method is suitable for nanoscale shallow trenches and can achieve good shape preservation and no voids. The filling process used in the embodiments of this application is to deposit the first material on the semiconductor substrate forming the shallow trench by at least one of the above methods, so that the shallow trench after filling achieves the effects of high and uniform filling density, few voids, and no voids.

[0078] Figure 5 This is a schematic diagram illustrating an example of filling a shallow trench with a first material in a method for fabricating a semiconductor device according to an embodiment of this application. During the process of filling the shallow trench with the first material, the first material is also deposited on the surface of the first hard mask layer 05 of the semiconductor substrate and on the surface of the top of the shallow trench. Figure 5 The first material layer 08 is shown. The first material layer 08 may contain particles or unevenness, so it needs to be removed to make the surface smooth.

[0079] Removing the first material on the semiconductor substrate by etching and / or polishing processes includes at least one of the following methods: removing the first material on the semiconductor substrate by etching; removing the first material on the semiconductor substrate by polishing. Figure 6 This diagram illustrates the process after removing the first material from the semiconductor substrate, revealing the first hard mask layer 05. The etching rate of the first material differs from the etching rate of the first hard mask layer; the time to stop the etching process can be determined by the change in etching rate during the etching of the first material.

[0080] Grinding is a key technology for planarizing the surface of semiconductor substrates through mechanical or chemical mechanical action. It is primarily used to eliminate surface irregularities, improve surface roughness, control material thickness, or achieve global planarization. Grinding processes include, but are not limited to: Mechanical Grinding, Chemical Mechanical Polishing (CMP), and Electrochemical Mechanical Polishing (ECMP). Mechanical Grinding uses diamond or alumina grinding wheels to directly cut the material surface and is suitable for rough grinding of the back side of wafers. Chemical Mechanical Polishing combines chemical etching (oxidants in the slurry) with mechanical friction (polishing pads) to achieve material removal and is used for global planarization of polysilicon layers, copper interconnects, and shallow trenches. Electrochemical Mechanical Polishing introduces an electric field based on Chemical Mechanical Polishing to electrochemically dissolve and assist in material removal, reducing mechanical stress. It is suitable for ultra-thin devices and is mainly used for stress-free polishing of copper interconnects.

[0081] If the first material is polycrystalline silicon, chemical mechanical polishing (also known as chemical mechanical abrasion) is typically used to remove the first material from the semiconductor substrate. This embodiment of the application selects chemical mechanical polishing, which combines chemical reaction and mechanical abrasion to achieve higher flatness and smoothness.

[0082] The first material layer 08 and the first hard mask layer 05 are made of different materials. The different materials have the following differences, and the grinding process of the first material can be judged based on the following aspects: (1) Optical endpoint detection: The first material layer 08 and the first hard mask layer 05 have different refractive indices, and the intensity and wavelength of the reflected light will change. The grinding process of the first material is determined by monitoring the changes in the reflected light generated during the grinding process. (2) Friction monitoring: The friction between the first material layer 08 and the first hard mask layer 05 and the grinding head is different. The grinding process of the first material is determined by monitoring the difference in the friction coefficient between the grinding head and the grinding surface. (3) Acoustic endpoint detection: The changes in the sound characteristics of the interface between different materials are monitored by ultrasonic waves or other acoustic methods to determine whether the grinding process of the first material is complete.

[0083] Then, the first hard mask layer is removed, while the passivation oxide layer is retained.

[0084] Figure 7This is a schematic diagram showing the process after removing the first hard mask layer 05 in the semiconductor device fabrication method provided in this application embodiment. As mentioned above, the first hard mask layer 05 is a mask layer deposited to form a shallow trench structure, and its thickness and material settings are designed to match the etching depth of the shallow trench or etching process parameters. In subsequent processes, a deep trench isolation structure needs to be further formed, therefore, a second hard mask layer needs to be deposited after removing the aforementioned first hard mask layer.

[0085] Step S102: A deep trench is formed in part of the shallow trench, and a second material is deposited in the deep trench, the second material being a different material from the first material.

[0086] This step is used to form deep trenches, and the deep trenches are located in the area where some of the shallow trenches are located. The aspect ratio of the shallow trenches is smaller than that of the deep trenches.

[0087] The process of forming deep trenches on a semiconductor substrate and filling them with a second material can be summarized as follows: forming a second hard mask layer, applying and exposing photoresist, developing, forming deep trenches, cleaning the trenches, and filling the deep trenches with the second material.

[0088] Therefore, in forming deep trenches, the first steps are to form a second hard mask layer and then apply and expose the photoresist. Specifically:

[0089] A second hard mask layer is deposited on the passivation oxide layer and the surface of the shallow trench; the step of forming a deep trench in a portion of the shallow trench includes: defining the area where the deep trench needs to be formed by photolithography; performing an etching process to form a deep trench penetrating the portion of the shallow trench in the area corresponding to the portion of the shallow trench; and removing the photoresist.

[0090] refer to Figures 8-10 , Figure 8 A schematic diagram illustrating an example of forming a second hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application; Figure 9 This is a schematic diagram illustrating an example of forming a deep trench on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 10 This is a schematic diagram illustrating an example of removing the second photoresist layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0091] A second hard mask layer 09 is formed on the surface of the passivation oxide layer 04 and the shallow trench 07. The second hard mask layer 09 and the first hard mask layer 05 can be made of the same material, such as silicon nitride, or they can be made of different materials. The thickness of the second hard mask layer 09 is determined according to the requirements of the etching window of the subsequent deep trench etching process and the process window of the subsequent deep trench filler removal process. That is, in the embodiments of this application, the second hard mask layer 09 is not only the hard mask layer of the deep trench etching process, but also the stop layer of the deep trench filler (e.g., deposited insulating layer) removal process (e.g., CMP). Furthermore, the second hard mask layer 09 is also the hard mask layer of the subsequent etch-back process, and the stop layer of the filler removal process in the etch-back region, which is removed only after the filler in the etch-back region has been polished.

[0092] After forming the second hard mask layer 09, the area for forming the deep trench is defined by photolithography, including: applying a second photoresist layer 10 to areas on the second hard mask layer 09 that do not require etching, thereby defining the area on the second hard mask layer 09 where the deep trench needs to be formed. The second photoresist layer 10 is used to precisely control the etching area of ​​the deep trench and protect the parts that do not need to be etched.

[0093] like Figure 9 As shown, based on the required depth and shape of the deep trench, etching is performed on the second hard mask layer 09 at a position corresponding to a portion of the shallow trench 07, forming a deep trench 11 that penetrates the second hard mask layer 09, the passivation oxide layer 04, and extends to a second predetermined position on the epitaxial layer 03 of the semiconductor substrate. The depth of the second predetermined position is greater than the depth of the first predetermined position.

[0094] Then, remove Figure 9 The second photoresist layer 10 is applied until the surface of the second hard mask layer 09 is exposed, as shown in the image. Figure 10 As shown. The next step is to fill the deep trench with a second material.

[0095] Before filling the deep trench with a second material, the method further includes: forming a sidewall oxide layer on the sidewall surface of the deep trench; bottom etching the deep trench and performing ion implantation at the bottom. Figure 11 This is a schematic diagram showing the formation of a sidewall oxide layer 13 on the sidewall of the deep trench and the implantation of ions 14 at the bottom of the deep trench.

[0096] The sidewall oxide layer 13 is used to protect the sidewalls of the deep trench and prevent ions from being implanted into unwanted areas during ion implantation after bottom etching. The sidewall oxide layer 13 can be silicon oxide. The sidewall oxide layer can be formed on the sidewalls of the deep trench and on the surface of the second hard mask layer on the epitaxial layer of the semiconductor substrate by thermal oxidation or chemical vapor deposition.

[0097] It should be noted that forming the sidewall oxide layer 13 and performing ion implantation at the bottom of the deep trench are optional process steps. In other embodiments, the sidewall oxide layer 13 may not be formed, ion implantation may not be performed, and insulating material may be directly filled into it.

[0098] The ion implantation process involves placing a wafer into an ion implanter, selecting appropriate dopant elements based on design requirements, and determining the implantation energy and dosage. The implantation energy determines the depth to which ions can penetrate, while the dosage controls the doping concentration. For ion implantation at the bottom of deep trenches, higher energy is typically required to ensure ions reach the trench bottom. Performing ion implantation is used to customize the electrical properties of different regions within a semiconductor device to meet specific application requirements.

[0099] In addition, a high-temperature annealing process is required after ion implantation. This step helps activate the implanted impurity atoms and repairs crystal damage caused by ion bombardment.

[0100] After forming a sidewall oxide layer on the sidewalls of the deep trench and performing bottom ion implantation, the process further includes: depositing a second material within the deep trench; specifically: depositing the second material on the surface of the second hard mask layer and within the deep trench using chemical vapor deposition. After the second material is deposited, a... Figure 12 The deep trench 11 filled with the second material and the first insulating layer 15 located on the upper side of the second hard mask layer 09 are shown.

[0101] Deep trench filling with a second material typically requires a high aspect ratio process to ensure a void-free and uniform filling.

[0102] In this embodiment, a second material is deposited in the deep trench using chemical vapor deposition (CVD), specifically by generating a solid thin film through a chemical reaction of a vapor precursor. Suitable CVD methods for filling deep trenches with a second material include: low-pressure CVD, which deposits at low pressure (0.1~10 Torr) to achieve good film uniformity, and at temperatures of 500℃~800℃, without requiring compatibility with back-end processes; and plasma-enhanced CVD, which utilizes plasma to activate the reactive gas and lower the deposition temperature (200℃~400℃). This method enables highly conformal deposition, uniformly covering the sidewalls and bottom of the deep trench, avoiding the problem of excessively thick tops and thin bottoms caused by diffusion limitations due to thermal oxidation deposition. Furthermore, the second material can be selected from various insulating filler materials, including but not limited to: silicon dioxide (SiO2), silicon nitride (Si3N4), borosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, and high-molecular-weight organic polymers.

[0103] The second material deposited on the surface of the second hard mask layer 09 is formed to ensure that the second material can fill the deep trench. Therefore, after obtaining the filled deep trench and the first insulating layer formed by the second material, the process further includes: removing the second material on the semiconductor substrate by etching and / or chemical mechanical polishing, and the removal process stops at the second hard mask layer. This includes removing the second material by at least one of the following methods: removing the second material on the semiconductor substrate by etching; removing the second material on the semiconductor substrate by chemical mechanical polishing. The removed second material is... Figure 12 After the first insulating layer 15 shown is removed, the second hard mask layer is exposed, resulting in... Figure 13 A schematic diagram.

[0104] The second material is an insulating filler material, which is a different insulating filler material from the first material. Its main purpose is also to isolate different device areas, reduce crosstalk, and improve the overall performance of integrated circuits.

[0105] Because the second material filling the deep trenches and the first material filling the shallow trenches are different insulating materials, the etching rates of different insulating materials differ in subsequent etching processes during semiconductor device fabrication. This can create contact areas between the shallow and deep trenches (such as...). Figure 14 The contact area 16 shown is formed by different etching rates, resulting in steps. The contact surface will form downward gaps or even inverted V-shaped depressions, which will have an isolation effect. After the device is formed, electrical problems such as leakage may occur, affecting the stability of the device.

[0106] To improve the above-mentioned problems, in this embodiment of the application, the deep trench is etched back to a certain depth from the surface, and then filled with the same material as the filling material in the shallow trench structure, or with a different material with similar properties to the filling material in the shallow trench structure, so that the etching rate of the material in the shallow trench and deep trench regions is the same or similar, thereby avoiding the generation or expansion of the contact seam between the two, and thus improving the electrical stability of the formed device.

[0107] Step S103: A back-etch region is formed in the top region of the deep trench filled with the second material, and a third material is deposited in the back-etch region, wherein the back-etch region is the overlapping region of the shallow trench and the deep trench.

[0108] This step involves re-etching the top region of the deep trenches already filled with the second material, creating a re-etched area. This area is then used to redeposit the third material, preventing gaps from forming due to different etching rates in subsequent etching processes at the overlap between the deep and shallow trenches. The re-etching process uses the etching technology described above. Etching parameters are set to precisely control the etching depth of the top region of the deep trenches, ensuring that a predetermined amount of third material can be filled in the subsequent filling process. The overlapping area is filled with the same third material, ensuring the same etching rate for both the deep and shallow trenches, thus preventing gaps from forming or widening at the contact surface between the shallow and deep trenches.

[0109] The step of forming a back-etch region in the top region of the deep trench that has been filled with the second material, and depositing the third material in the back-etch region, includes: etching the second material that has been filled in the top region of the deep trench to a set depth to form the back-etch region.

[0110] Figure 15 This is a schematic diagram illustrating an example of forming a back-etch region in the top region of a deep trench in a method for fabricating a semiconductor device according to an embodiment of this application. A second material that has already been filled is re-etched to a set depth in the top region of the deep trench to obtain a back-etch region 17, which is the overlapping region of the shallow trench and the deep trench.

[0111] The process of depositing the third material includes: depositing the third material using high-density plasma-chemical vapor deposition on the etch-back region and the surface of the second hard mask layer. Figure 16 The image shows the etched area 17, which has been filled with the third material, and the second insulating layer 18 located on the upper side of the second hard mask layer 09.

[0112] High-density plasma chemical vapor deposition (HDP-CVD) is a thin film deposition technique that enhances chemical reactions with high-density plasma to achieve high fidelity and high filler capacity. Its key feature is the use of high-density plasma (typically generated by inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) sources) to decompose reactant gases, thereby achieving low-temperature, high-speed, and void-free thin film deposition.

[0113] High-density plasma chemical vapor deposition (HDPV) can utilize gas systems including, but not limited to: 1. Deposition gases, including but not limited to: silicon source gases (SiH4 (silane), Si(OC2H5)4 (TEOS, tetraethoxysilane), SiCl4 (silicon tetrachloride)); oxygen source gases (O2 (oxygen), O3 (ozone)); nitrogen source gases (NH3 (ammonia), N2 (nitrogen)). 2. Etching / sputtering gases: A key characteristic of HDPV is the simultaneous deposition and physical sputtering etching to eliminate overhangs and achieve void-free filling. Common gases include, but are not limited to: Ar (argon), He (helium). 3. Doping gases: Used to adjust film properties. Common gases include, but are not limited to: PH3 (phosphine) or B2H6 (diborane): used for depositing silicon phosphide glass (PSG) or borosilicate glass (BPSG) to improve fluidity and dielectric properties. CF4 (carbon tetrafluoride) or C2F6 (hexafluoroethane) (less commonly used): used to adjust film stress or etching selectivity.

[0114] The third material is the same as the first material. This ensures that the overlapping areas of deep trenches and shallow trenches have the same etching rate, reducing gaps formed at the junctions of the overlapping areas due to different etching rates, thereby reducing crystal defects.

[0115] In addition, the third material can be a dissimilar material similar to the first material, which can ensure that the overlapping areas of deep trenches and shallow trenches have similar etching rates, and can also prevent the contact seams between deep trenches and shallow trenches from being generated or expanded, thereby improving the electrical stability of the formed device.

[0116] The third material deposited on the surface of the second hard mask layer 09 is formed to ensure that the third material can fill the etch-back region. Therefore, after obtaining the etch-back region filled with the third material and the second insulating layer formed by the third material, the process further includes: removing the third material on the semiconductor substrate by etching and / or chemical mechanical polishing, and the removal process stops at the second hard mask layer. This includes removing the third material by at least one of the following methods: removing the third material on the semiconductor substrate by etching; removing the third material on the semiconductor substrate by chemical mechanical polishing. The removed third material is as follows: Figure 16 After the second insulating layer 18 shown is removed, the second hard mask layer is exposed, resulting in... Figure 17 A schematic diagram.

[0117] The etching and chemical mechanical polishing processes used to remove the second insulating layer can be found in the descriptions of the etching and chemical mechanical polishing processes above.

[0118] Then, the second hard mask layer is removed, while the passivation oxide layer is retained. Figure 18The diagram shows the structure for removing the second hard mask layer 09 while retaining the passivation oxide layer 04. The purpose of retaining the passivation oxide layer is to prevent contamination or oxidation of the silicon surface during subsequent polysilicon filling, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device.

[0119] After the above steps, the process further includes: filling the passivation oxide layer with polycrystalline silicon. For example... Figure 19 As shown, polysilicon 18 is filled on the surface of the passivation oxide layer 04 and the surface of the partially shallow trench filled with the first material to form a gate electrode. The passivation oxide layer serves as the gate dielectric, and the polysilicon covers it to form the electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.

[0120] The above describes the implementation process of the semiconductor device fabrication method provided in the embodiments of this application.

[0121] Since the first material used to fill shallow trenches and the second material used to deposit deep trenches are different insulating materials, the different etching rates of these materials in subsequent etching processes during semiconductor device fabrication can cause steps to form at the contact area between the shallow and deep trenches due to these different etching rates. This can lead to downward gaps or even inverted V-shaped depressions at the contact surface, potentially causing electrical problems such as leakage after device fabrication and affecting device stability. In this embodiment, after filling the shallow trenches with the first material and depositing the second material in the deep trenches, the top region of the deep trenches is etched to form a back-etching region. A third material is then deposited in this back-etching region. The third material can be the same as the first material or a similar but different shaped material, ensuring that the overlapping area of ​​the deep and shallow trenches is deposited with the same material. Therefore, the etching rate of the material in this overlapping area is the same, which also prevents the formation or expansion of gaps at the contact point, reduces defects in the semiconductor device fabrication process, and improves the electrical stability of the formed device.

[0122] A second embodiment of this application provides a semiconductor device, comprising: a semiconductor substrate, shallow trenches formed on the semiconductor substrate, deep trenches formed within a portion of the shallow trenches, the shallow trenches being filled with a first material, the deep trenches being filled with a second material, and a third material different from the second material being filled in the overlapping region between the top of the deep trenches and the shallow trenches. The semiconductor device provided in this embodiment can be obtained by the fabrication method of the semiconductor device provided in the first embodiment of this application; details can be found in the detailed description of the fabrication method of the semiconductor device provided in the first embodiment of this application, which will not be repeated here.

[0123] The semiconductor device provided in the second embodiment of this application is applied to BCD (Bipolar-CMOS-DMOS), which integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip. Figure 20 As shown, the structure includes a semiconductor substrate 01, an epitaxial layer 03 on the semiconductor substrate, and an active layer 19 disposed on the semiconductor substrate. The active layer 19 includes an NPN bipolar junction transistor (NPN BJT) 1901, a complementary metal-oxide-semiconductor (CMOS) transistor 1902, an N-channel laterally diffused metal-oxide-semiconductor (N-LDMOS) transistor 1903, and a P-channel laterally diffused metal-oxide-semiconductor (P-LDMOS) transistor 1904. The NPN transistor is one of the core components of a bipolar transistor, primarily used for high-precision analog signal processing, high-speed switching, or driving circuits.

[0124] NPN, CMOS, N-LDMOS, and P-LDMOS differ in structure, voltage, and function, as follows: NPN provides high-precision analog signals but is susceptible to noise interference; CMOS provides low-voltage data logic but is sensitive to leakage current; DMOS (N-LDMOS and P-LDMOS) handles high-voltage / high-current loads but may introduce substrate noise. N-LDMOS has a higher electron mobility than hole mobility, resulting in lower on-resistance and faster switching speed. P-LDMOS has a lower hole mobility, leading to higher on-resistance and lower efficiency, typically requiring a larger area to achieve the same current capability as N-LDMOS.

[0125] The shallow trenches and deep trenches provided in this application are used to isolate the above devices, which can achieve the following beneficial effects: (1) LDMOS devices usually operate under high voltage (tens to hundreds of volts). When N-LDMOS and P-LDMOS devices are adjacent, their drift regions may be laterally broken down or leak due to high electric fields. By filling the deep trenches with insulating material, a physical isolation barrier is formed, which blocks the lateral movement of charge carriers, reduces the electric field coupling between the two devices, avoids parasitic conduction under high voltage (e.g., punch-through effect), as well as problems such as thermal coupling and noise interference. (2) The high voltage (tens to hundreds of volts) of the drain of DMOS can easily diffuse laterally through the substrate, causing adjacent devices to break down. Deep trench isolation walls are used to isolate DMOS from CMOS / NPN, and to physically block the lateral extension of the high voltage electric field (especially the isolation between N-LDMOS and P-LDMOS) to prevent the carriers in the drift region from being injected into the substrate; the current path of the source / body / substrate of DMOS forming parasitic NPN or PNP (Positive-Negative-Positive, PNP type bipolar junction transistor (PNPBipolar Junction Transistor, abbreviated as PNP BJT) is cut off to avoid accidental conduction under high voltage. (3) The parasitic SCR (silicon controlled rectifier) ​​structure in CMOS is prone to latch-up due to transient triggering. Deep trench isolation walls completely isolate the parasitic path between NMOS and PMOS, isolate the noise sensitive area, and reduce the parasitic capacitance between the source / drain region of CMOS and the substrate. (4) The collector of NPN forms a parasitic PNP with the P-type substrate, which leads to leakage. Deep trench isolation walls are used to block the base current path of parasitic PNP to ensure the stability of NPN performance.

[0126] To improve the isolation effect of shallow trenches / deep trenches on the aforementioned devices and prevent gaps from forming in subsequent etching processes due to different etching rates caused by different filling materials in the overlapping areas of shallow and deep trenches, thus avoiding problems such as leakage and crosstalk, this embodiment of the application, after filling the shallow trenches with a first material and depositing the deep trenches with a second material, etches the top region of the deep trenches to form a back-etch region, and deposits a third material in the back-etch region. The third material can be the same as the first material or a similar but different shaped material, so that the overlapping areas of the deep and shallow trenches are deposited with the same material. Therefore, the etching rate of the material in the overlapping area is the same, which can also prevent the formation or expansion of gaps at the junction of the two, reducing defects in the semiconductor device fabrication process. Based on this, NPN, CMOS, N-LDMOS, and P-LDMOS devices in BCDs can be effectively isolated and protected, effectively improving the stability of the devices.

[0127] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, a passivation oxide layer and a first hard mask layer are formed on the semiconductor substrate, etching is started on the first hard mask layer to a first preset position on the semiconductor substrate to form a shallow trench, and a first material is filled in the shallow trench; Remove the first hard mask layer, and retain the passivation oxide layer; A second hard mask layer is deposited on the passivated oxide layer; Through an etching process, etching begins on the second hard mask layer at the position corresponding to part of the shallow trench, and extends to the second preset position on the epitaxial layer of the semiconductor substrate to form a deep trench. A second material is deposited in the deep trench, and the second material is a different material from the first material. The second material, which has been filled in the top region of the deep trench, is etched to a set depth to form a back-etch region. A third material is deposited in the back-etch region, which is the overlapping region of the shallow trench and the deep trench. The third material is the same material as the first material, or a similar dissimilar material, so that the material deposited in the overlapping region has the same etching rate. The third material on the semiconductor substrate is removed, and the removal process stops at the second hard mask layer.

2. The method according to claim 1, characterized in that, Also includes: The shallow trenches are formed on the semiconductor substrate by photolithography and etching. A first material is deposited on the semiconductor substrate forming the shallow trench, the deposited first material at least filling the shallow trench; The first material on the semiconductor substrate is removed by etching and / or polishing processes, and the removal process stops at the first hard mask layer.

3. The method according to claim 1, characterized in that, Also includes: The area where the deep trench needs to be formed is defined by photolithography. An etching process is performed to form a deep trench that penetrates a portion of the shallow trench in the region corresponding to a portion of the shallow trench; Remove the photoresist.

4. The method according to claim 3, characterized in that, The deposition of the second material within the deep trench includes: The second material is deposited on the surface of the second hard mask layer and in the deep trench using chemical vapor deposition.

5. The method according to claim 4, characterized in that, After obtaining the filled deep trench and the first insulating layer formed of the second material, the process further includes: The second material on the semiconductor substrate is removed by etching and / or chemical mechanical polishing, and the removal process stops at the second hard mask layer.

6. The method according to claim 1, characterized in that, The deposition of a third material in the etched region includes: The third material is deposited in the etched region and on the surface of the second hard mask layer using high-density plasma chemical vapor deposition.

7. The method according to claim 1, characterized in that, The removal of the third material from the semiconductor substrate further includes: The third material on the semiconductor substrate is removed by etching and / or chemical mechanical polishing.

8. The method according to claim 7, characterized in that, Also includes: Remove the second hard mask layer and retain the passivation oxide layer.

9. The method according to claim 1, characterized in that, Before depositing the second material within the deep trench, the method further includes: A sidewall oxide layer is formed on the sidewall surface of the deep trench; The deep trench is etched at the bottom and then ion implanted at the bottom.

10. The method according to claim 9, characterized in that, Also includes: Polycrystalline silicon is filled on the passivated oxide layer.

11. A semiconductor device, prepared according to any one of claims 1-10, characterized in that, include: A semiconductor substrate, shallow trenches formed on the semiconductor substrate, deep trenches formed in a portion of the shallow trenches, the shallow trenches being filled with a first material, the deep trenches being filled with a second material, and a third material different from the second material being filled in the overlapping area between the top of the deep trenches and the shallow trenches.

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