A low noise hybrid domain CMOS detector readout circuit and readout method
By using a low-noise hybrid domain CMOS detector readout circuit, the problem of balancing high sensitivity and wide dynamic range within a single frame image is solved, achieving high signal-to-noise ratio low-light detection and wide dynamic range, which is applicable to fields such as aerospace remote sensing, medical imaging, deep space exploration and marine remote sensing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INSTITUTE OF TECHNICAL PHYSICS CHINESE ACADEMY OF SCIENCES
- Filing Date
- 2026-03-30
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies struggle to achieve both high sensitivity and a large dynamic range within a single frame image, and reference voltage source noise severely impacts low-light detection performance.
A low-noise mixed-domain CMOS detector readout circuit is adopted, including a capacitor feedback transimpedance amplifier unit, a switched capacitor reference unit, an analog domain readout unit, and a time domain quantization unit. By filtering out reference voltage source noise and combining the high sensitivity of the analog domain with the anti-saturation characteristics of the time domain, adaptive readout with a wide dynamic range is achieved.
A seamless transition between high sensitivity and large dynamic range is achieved within a single frame image, significantly improving the signal-to-noise ratio of low-light detection, eliminating reset noise and comparator offset, and extending the linear response range of the detector.
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Figure CN122120642A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of integrated circuits and photoelectric detection technology, and in particular to a low-noise mixed-domain CMOS detector readout circuit and readout method. Background Technology
[0002] Visible light CMOS detectors play an irreplaceable role in fields such as aerospace remote sensing, medical imaging, deep space exploration, and marine remote sensing. Especially in applications such as hyperspectral imaging, the illumination intensity of the detected scene spans an extremely wide dynamic range. The same frame of image contains both extremely weak dark target signals and extremely strong light signals generated by direct sunlight or specular reflection, with light intensity differences reaching up to 6 orders of magnitude (120dB).
[0003] The readout circuit (ROIC), as a core component of the detector, directly determines the image quality. However, existing technologies suffer from the following technical problems when achieving large dynamic range imaging:
[0004] 1. The contradiction between dynamic range and detection sensitivity. Using a small integrating capacitor to achieve high conversion gain and improve sensitivity to weak signals results in a low maximum integrated charge, making it prone to saturation and signal loss under strong light. Conversely, using a large integrating capacitor to receive strong light signals leads to a decrease in conversion gain, and the large capacitor introduces a larger kT / C noise equivalent to a higher number of noise electrons, resulting in a lower signal-to-noise ratio and limiting dark-area detection capabilities. Traditional analog readout circuits cannot simultaneously achieve the high sensitivity of a small capacitor and the large dynamic range of a large capacitor within a single frame image.
[0005] 2. Existing dynamic range extension technologies have limitations. Multi-level gain switching techniques typically require multiple frames to determine the appropriate gain level, making real-time readout of a single frame impossible. Furthermore, they introduce charge injection errors during single-frame switching, and the multi-level capacitor network occupies a large pixel area, reducing the fill factor. Logarithmic readout techniques utilize the subthreshold characteristics of MOSFETs, but their low-light response is severely nonlinear, and the fixed-mode noise introduced by device mismatch is significant, making it difficult to meet the requirements of high-precision quantitative detection. Resetting pixels multiple times within the exposure cycle to avoid saturation introduces additional reset noise, and frequent reset operations reduce the effective integration time, resulting in lost image information.
[0006] 3. Noise Limitation of Signal-to-Noise Ratio Due to Input Stage Reference Voltage Source. In conventional CTIA readout circuits, the non-inverting input of the operational amplifier is directly connected to an external reference voltage source. The virtual short characteristic determines the potential of the inverting input, thereby setting the detector's operating bias. The broadband thermal noise and power supply ripple from the reference source output are directly coupled to the input, causing detector bias jitter and severely limiting the imaging signal-to-noise ratio under low-light conditions.
[0007] Therefore, existing technologies struggle to resolve the trade-off between a large dynamic range and high sensitivity, and reference voltage source noise significantly impacts low-light detection performance. Consequently, a novel readout circuit architecture is urgently needed that can suppress reference source noise and combine high sensitivity in the analog domain with anti-saturation characteristics in the time domain to achieve adaptive readout with a wide dynamic range. Summary of the Invention
[0008] The purpose of this invention is to provide a low-noise mixed-domain CMOS detector readout circuit and readout method, which mainly solves the problems existing in the prior art. It is applicable to visible light imaging applications that require both high sensitivity and high dynamic range, such as aerospace remote sensing, medical imaging, deep space exploration, marine remote sensing and hyperspectral imaging, and has significant industrial practical value.
[0009] To achieve the above objectives, the technical solution adopted by the present invention is to provide a low-noise mixed-domain CMOS detector readout circuit, characterized in that it includes a capacitor feedback transimpedance amplifier unit, a switched capacitor reference unit, an analog domain readout unit, a time domain quantization unit, and an output selection unit.
[0010] The capacitor feedback transimpedance amplifier unit is used to convert the current signal output by the pixel unit into a voltage signal; the switched capacitor reference unit is connected between the external reference voltage source and the non-inverting input terminal of the capacitor feedback transimpedance amplifier unit, and is used to filter out the noise of the reference voltage source by using the RC low-pass filter characteristics during the reset phase, and to maintain the reference potential of the capacitor feedback transimpedance amplifier by storing charge in the capacitor during the integration phase.
[0011] Both the analog domain readout unit and the time domain quantization unit are coupled to the output of the capacitor feedback transimpedance amplifier unit; the analog domain readout unit is used to acquire and output analog voltage signals; the time domain quantization unit is used to output digital time code values by detecting saturation time.
[0012] The output selection unit is used to select one of the analog voltage signal and the digital time code value as the final output; the output selection unit outputs the analog voltage signal by default, and switches to outputting the digital time code value when it detects that the output voltage of the capacitor feedback transimpedance amplifier reaches a preset saturation threshold.
[0013] Furthermore, the switched capacitor reference unit includes a sampling switch module and a holding capacitor module;
[0014] During the reset phase, the sampling switch module is turned on, and the on-resistance of the sampling switch module and the holding capacitor module form a RC low-pass filter to filter the noise output by the reference voltage source.
[0015] During the integration phase, the sampling switch module is turned off, causing the non-inverting input of the capacitor feedback transimpedance amplifier unit to be in a high-impedance state, and the stored charge on the holding capacitor module is used to maintain the reference potential of the capacitor feedback transimpedance amplifier.
[0016] Furthermore, the analog domain readout unit adopts a correlated dual sampling structure, including a reset sampling module and a signal sampling module; the reset sampling module acquires voltage at the reset time; the signal sampling module acquires voltage at the end of integration time, and outputs a differential analog signal based on the reset sampling module.
[0017] Furthermore, the capacitor feedback transimpedance amplifier unit includes an operational amplifier and a feedback loop connected between its inverting input terminal and its output terminal; the operational amplifier adopts a folded cascode structure, its input differential pair transistors are PMOS transistors, and the load stage adopts a cascode current mirror structure; the feedback loop includes multiple parallel integrating capacitor modules and corresponding control switch modules, and the gain level can be configurably adjusted by selecting different values of the integrating capacitor modules connected.
[0018] Furthermore, the time-domain quantization unit includes a threshold comparison module and a counting module;
[0019] The first input terminal of the threshold comparison module is coupled to the output terminal of the capacitor feedback transimpedance amplifier unit, and the second input terminal is connected to the threshold voltage corresponding to the saturation threshold, which is used to monitor the relationship between the output voltage of the capacitor feedback transimpedance amplifier unit and the saturation threshold in real time; the counting module starts counting during the integration period and latches the current count value when the threshold comparison module flips.
[0020] The saturation threshold is less than the saturation voltage of the output stage of the capacitor feedback transimpedance amplifier unit, and is located within the high linearity range of the output signal of the capacitor feedback transimpedance amplifier unit.
[0021] Furthermore, the counting module is a bidirectional counting module; during the reset phase, the bidirectional counting module performs counting in the first direction to quantize the state of the reset level; during the integration phase, the bidirectional counting module performs counting in the second direction to quantize the state of the signal level; wherein, the first direction counting and the second direction counting are in opposite directions, and the final output digital time code value is the algebraic sum of the two counts, which is used to eliminate reset noise and comparator offset.
[0022] Furthermore, the threshold comparison module is a hysteresis comparator structure; the hysteresis comparator structure includes a cross-coupled positive feedback load to form a hysteresis window to prevent output jitter caused by fluctuations in the input voltage near the threshold.
[0023] Furthermore, the output selection unit includes a multiplexing module; the first input terminal of the multiplexing module is coupled to the output terminal of the analog domain readout unit, the second input terminal is coupled to the output terminal of the time domain quantization unit, and the control terminal is coupled to the output terminal of the threshold comparison module in the time domain quantization unit; the multiplexing module selects to output the analog voltage signal or the digital time code value according to the toggle flag bit provided by the threshold comparison module.
[0024] The present invention also provides a low-noise mixed-domain CMOS detector readout method, using the above-described low-noise mixed-domain CMOS detector readout device, characterized by comprising the following steps:
[0025] In step S100, during the reset phase, the external reference voltage source is connected to the non-inverting input of the capacitor feedback transimpedance amplifier through the switched capacitor reference unit, and a low-noise DC bias is established by utilizing the RC low-pass filter characteristics formed by the switch on-resistance and holding capacitor.
[0026] In step S200, during the integration phase, the switched capacitor reference unit is disconnected, the charge stored in the holding capacitor is used to maintain the reference potential of the capacitor feedback transimpedance amplifier, and the current signal of the pixel unit is converted into a voltage signal using the capacitor feedback transimpedance amplifier.
[0027] In step S300, during the integration process, the output voltage of the capacitor feedback transimpedance amplifier is acquired in parallel using the analog domain readout unit; at the same time, the time domain quantization unit is used to count on one hand and monitor in parallel whether the output voltage of the capacitor feedback transimpedance amplifier reaches the saturation threshold on the other hand; then steps S400 and S500 are executed simultaneously.
[0028] In step S400, the analog domain readout unit continuously acquires the analog voltage signal of the capacitor feedback transimpedance amplifier unit, and proceeds to step S600.
[0029] In step S500, the time-domain quantization unit continues to count until the output voltage of the capacitor feedback transimpedance amplifier unit reaches the saturation threshold, then latches the current count value and outputs it as a digital time code value; proceed to step S600.
[0030] In step S600, the time-domain quantization unit monitors the output voltage of the capacitor feedback transimpedance amplifier unit; if the output voltage of the capacitor feedback transimpedance amplifier does not reach the saturation threshold, proceed to step S700, otherwise proceed to step S800.
[0031] Step S700: The analog voltage signal acquired by the analog domain readout unit is used as the final output to complete one sampling.
[0032] Step S800: The digital time code value obtained by counting in the time domain quantization unit is used as the final output to complete one sampling.
[0033] Furthermore, the generation of the digital time code value includes the following sub-steps:
[0034] Step S501: During the reset phase, the bidirectional counting module in the time-domain quantization unit is used to perform counting in the first direction and quantize the reset level state.
[0035] Step S502: During the integration phase, the bidirectional counting module is used to count in the second direction, which is opposite to the first direction, until the output voltage of the capacitor feedback transimpedance amplifier reaches the saturation threshold, and then the count value is latched.
[0036] Step S503: The algebraic sum of the first direction count and the second direction count is output as the digital time code value, thereby eliminating reset noise and comparator offset.
[0037] In view of the above technical features, the low-noise mixed-domain CMOS detector readout circuit and readout method of the present invention have the following significant advantages compared with the prior art:
[0038] 1. This invention uses a switched capacitor circuit as the reference input for CTIA, which effectively filters out broadband thermal noise and power supply ripple from the reference voltage source, and significantly improves the signal-to-noise ratio of low-light detection.
[0039] 2. This invention eliminates the need to segment the exposure time. The analog path is responsible for high sensitivity in low light, while the time-domain path is responsible for anti-saturation in strong light. It achieves high dynamic range in a single frame. It combines the high sensitivity of analog circuits with the large dynamic range of time-domain circuits, enabling seamless connection and continuous detection from weak light signals to strong saturated light signals, and significantly expanding the linear response range of the detector.
[0040] 3. The analog domain readout unit and the time domain quantization unit of this invention operate in parallel, eliminating signal loss dead zones. The analog domain readout unit employs a dual-buffer structure, providing strong driving capability. The time domain quantization unit incorporates a comparator with a hysteresis structure, offering excellent anti-interference capabilities.
[0041] 4. The low-noise mixed-domain CMOS detector readout circuit of the present invention is fabricated using 5V 0.5μm standard CMOS process, which can be integrated on-chip without special process steps. Attached Figure Description
[0042] Figure 1 This is a circuit architecture diagram of a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention;
[0043] Figure 2This is a circuit schematic diagram of a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention;
[0044] Figure 3 This is a circuit diagram of the capacitive feedback transimpedance amplifier unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention.
[0045] Figure 4 This is a circuit schematic of a switched capacitor reference unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention.
[0046] Figure 5 This is a timing diagram of the switched capacitor reference unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention.
[0047] Figure 6 This is a circuit schematic diagram of the threshold comparison module in the time-domain quantization unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention.
[0048] Figure 7 This is a schematic diagram of the output of the analog domain readout unit and the time domain quantization unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention when the light intensity is medium to high.
[0049] Figure 8 This is a schematic diagram of the output of the analog domain readout unit and the time domain quantization unit in a preferred embodiment of the low-noise mixed-domain CMOS detector readout circuit of the present invention when the light intensity is low to medium.
[0050] Figure 9 This is a flowchart of a preferred embodiment of the low-noise mixed-domain CMOS detector readout method of the present invention.
[0051] In the diagram: 100 - Capacitor feedback transimpedance amplifier unit, 200 - Switched capacitor reference unit, 300 - Analog domain readout unit, 400 - Time domain quantization unit, 500 - Output selection unit, 600 - Pixel unit.
[0052] 101 - Operational amplifier, 102 - Feedback loop;
[0053] 201 - Sampling switch module; 202 - Holding capacitor module;
[0054] 301 - Reset sampling module; 302 - Signal sampling module;
[0055] 401 - Threshold comparison module, 402 - Counting module. Detailed Implementation
[0056] The present invention will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0057] Please see Figure 1 This invention discloses a low-noise mixed-domain CMOS (Complementary Metal-Oxide-Semiconductor) detector readout circuit. As shown in the figure, a preferred embodiment includes a capacitive feedback transimpedance amplifier unit 100 (CTIA), a switched capacitor reference unit 200, an analog domain readout unit 300, a time-domain quantization unit 400, and an output selection unit 500.
[0058] The capacitive feedback transimpedance amplifier unit converts the current signal output by the pixel unit 600 into a voltage signal. Its inverting input is connected to the column bus of the pixel unit 600, and its non-inverting input is connected to the switched-capacitor reference unit 200. The switched-capacitor reference unit 200 is positioned between the external reference voltage source and the non-inverting input of the capacitive feedback transimpedance amplifier unit 100. It is used to filter noise from the reference voltage source during the reset phase and to maintain the reference potential during the integration phase. The analog domain readout unit 300 and the time domain quantization unit 400 are simultaneously coupled to the output of the capacitive feedback transimpedance amplifier unit 100, forming a parallel readout architecture. The output selection unit 500 selects one of the outputs. The output selection unit 500 defaults to outputting the analog voltage signal acquired by the analog domain readout unit 300, but when it detects that the output voltage of the capacitive feedback transimpedance amplifier unit 100 reaches a preset saturation threshold, it switches the output to the digital time code value provided by the time domain quantization unit 400. The circuit in this embodiment is fabricated using a 5V 0.5μm standard CMOS process and can be integrated on-chip without special process steps.
[0059] Please see Figures 1 to 8 The capacitor feedback transimpedance amplifier unit 100 includes an operational amplifier 101 and a feedback loop 102 connected between its inverting input terminal and its output terminal. Figure 3The circuit structure of operational amplifier 101 is shown, which employs a folded cascode structure. Its input differential pair uses PMOS transistors (M2, M3), which have lower flicker noise (1 / f noise) compared to NMOS devices, thus facilitating the detection of weak signals. The load stage uses a cascode current mirror structure (M4 to M7) to provide high output impedance, ensuring the op-amp has high open-loop gain (>80dB). At a 5V supply voltage, this op-amp guarantees high linearity of the CTIA integration voltage. The feedback loop 102 consists of multiple parallel integrating capacitor modules and corresponding control switch modules, forming configurable gain levels. Specifically, the integrating capacitor modules include Cint1, Cint2, and Cint3, with capacitance values of 50fF, 100fF, and 1pF, respectively, and the corresponding control switches are S1, S2, and S3. By controlling different integrating capacitor module values via external switches, the gain level can be configurably adjusted. Transmission gate structures are used in the switches to suppress charge injection effects.
[0060] Figure 4 The structure of the switched-capacitor reference unit 200 is shown. The switched-capacitor reference unit 200 is positioned between the external reference source Vref and the non-inverting input of the CTIA, and includes a sampling switch module 201 (SH / SHF) and a holding capacitor module 202 (C_SH). The sampling switch module 201 employs a parallel NMOS and PMOS transmission gate structure to reduce charge injection effects. The Vref terminal voltage is set to 1V, which is greater than the minimum common-mode input voltage of the operational amplifier 101, ensuring normal operation of the op-amp.
[0061] Figure 5 The timing diagram of the switched-capacitor reference unit 200 is shown. During the reset phase (t1 to t2): the control signal of the sampling switch module 201 is high, and the switch is turned on. At this time, the on-resistance Ron of the sampling switch module 201, the input resistance of the chip PAD (totaling 1k ohms), and the holding capacitor module 202 (10pF) form an RC low-pass filter to filter the noise output from the reference voltage source and establish a low-noise DC bias. The cutoff frequency of this RC low-pass filter is approximately 15.9MHz, which can effectively filter out broadband thermal noise from the reference source. During the integration phase (after t2): the control signal of the sampling switch module 201 becomes low, and the switch is turned off, causing the non-inverting input of the CTIA to be in a high-impedance state. At this time, the stored charge on the holding capacitor module 202 is used to maintain the reference potential (1V) of the CTIA, thereby isolating the power supply ripple and noise of the voltage source. Through the above operation, the switched-capacitor reference unit 200 establishes a clean reference potential during the reset phase and cuts off the noise coupling path during the integration phase, significantly improving the signal-to-noise ratio of low-light detection.
[0062] exist Figure 2The upper right section shows the circuit structure of the analog domain readout unit 300, which employs a correlated double sampling (CDS) structure, specifically including a reset sampling module 301 and a signal sampling module 302. The reset sampling module 301 consists of a switch R and a corresponding sampling capacitor, while the signal sampling module 302 consists of a switch S and a corresponding sampling capacitor. Both branches are connected to an analog buffer to output a differential analog signal.
[0063] Please combine Figure 8 In this scenario, under low to medium light intensity conditions, the CTIA output voltage rises linearly and does not reach the nonlinear region threshold. In this embodiment, the preset saturation threshold Vsat is set to 4V, which is less than the saturation voltage of the CTIA output stage (approximately 4.5V) and lies within the high linearity range of the CTIA output signal (typically 0V to 4.2V). At this time, the threshold comparison module 401 does not output a toggle flag, so the analog channel operates normally. The analog domain readout unit 300 includes two sampling actions: reset sampling and signal sampling. At the reset moment, switch R is closed, and the reset sampling module 301 acquires the CTIA reset voltage and stores it on the sampling capacitor, completing the reset sampling. At the end of the integration (e.g., Figure 7 At 50 μs (as shown), switch S is closed, and signal sampling module 302 acquires the integrated voltage of CTIA and stores it on the sampling capacitor, completing signal sampling. The subsequent analog buffer outputs the two sampled voltages as a differential analog signal. By subtracting the reset voltage from the integrated voltage, the reset noise (kT / C noise) of CTIA and the fixed-mode noise (FPN) of the operational amplifier can be effectively eliminated, thereby obtaining a high signal-to-noise ratio analog voltage signal under low-light conditions.
[0064] exist Figure 2 The lower right portion shows the circuit structure of the time-domain quantization unit 400, which includes a threshold comparison module 401 and a counting module 402. The threshold comparison module 401 employs a hysteresis comparator structure, with its first input coupled to the CTIA output and its second input connected to a preset saturation threshold voltage Vsat (set to 4V in this embodiment). The counting module 402 is a bidirectional counter that starts counting during the integration period and latches the count value in response to the toggling flag bit output by the threshold comparison module 401. Further reference... Figure 6The threshold comparison module 401 is specifically a hysteresis comparator structure. This comparator introduces a cross-coupled positive feedback structure composed of M3 and M6 at the input stage, forming a hysteresis window (in this embodiment, the hysteresis window width is approximately 50mV). When the input voltage fluctuates near the threshold, the positive feedback mechanism adjusts the threshold to prevent output jitter caused by input voltage fluctuations near the threshold. Two stages of inverters are connected after the hysteresis comparator for digital signal shaping, ensuring steep edges on the output signal. The counting module 402 is a bidirectional counting module, including a reset quantization stage and a signal quantization stage. In the reset quantization stage, the bidirectional counting module performs a first-direction count (e.g., downward counting) to quantize the state of the reset level. This count value includes information about reset noise and comparator offset. In the signal quantization stage, i.e., after entering the integration stage, the bidirectional counting module starts from the first-direction count value and performs a second-direction count in the opposite direction (e.g., upward counting) until the CTIA output voltage reaches the saturation threshold, triggering the comparator to flip and latching the count value. If the comparator does not flip within a preset fixed time window (e.g., 50μs), the analog voltage is output normally. Finally, the difference between the reset quantization result and the signal quantization result is output, meaning the final output digital time code value is the algebraic sum of the counts in the first and second directions. Since reset noise and comparator offset exist simultaneously in both counts, they can be eliminated through algebraic summation, thus directly obtaining pure signal timing information in the digital domain. Through the aforementioned time-domain CDS technique, reset noise, low-frequency noise, and comparator offset are effectively eliminated, ensuring high purity of the digital output signal.
[0065] Please combine Figure 7 In the scenario described, under medium to high light intensity, the CTIA output voltage rises rapidly, exceeding Vsat before the integration ends. At this point, the threshold comparison module 401 outputs a toggle flag, triggering the counting module 402 to latch the current count value. This count value represents the time Tint required for the CTIA output voltage to integrate from the reset level to the saturation threshold, serving as the readout result under high light intensity, i.e., the digital time code value. Figure 6 In the output count value DN=13545, the algebraic sum of the counts in the first direction and the counts in the second direction is given.
[0066] exist Figure 1 and Figure 2The system also includes an output selection unit 500, which is composed of a multiplexer module (MUX). The first input of the output selection unit 500 is coupled to the output of the analog domain readout unit 300, the second input is coupled to the output of the time-domain quantization unit 400, and the control terminal is coupled to the output of the threshold comparison module 401 in the time-domain quantization unit 400. Based on the toggle flag provided by the threshold comparison module 401, the output selection unit 500 selects to output either an analog voltage signal or a digital time code value. Specifically, when the toggle flag is low (CTIA output voltage has not reached the saturation threshold), an analog voltage signal is output; conversely, when the toggle flag is high (CTIA output voltage has reached the saturation threshold), a digital time code value is output. This achieves dynamic range expansion within a single frame.
[0067] Please see Figure 9 The present invention also discloses a low-noise mixed-domain CMOS (complementary metal-oxide-semiconductor) detector readout method, using the readout circuit in the above embodiments. As shown in the figure, a preferred embodiment includes the following steps:
[0068] Step S100, CTIA reset stage
[0069] During the reset phase, an external reference voltage source is connected to the non-inverting input of the capacitor feedback transimpedance amplifier unit through a switched capacitor reference unit, and a low-noise DC bias is established by utilizing the RC low-pass filter characteristics formed by the switch on-resistance and holding capacitor.
[0070] Step S200, CTIA integration stage.
[0071] During the integration phase, the switched-capacitor reference unit is disconnected, using its own holding capacitor to store charge and maintain the reference potential of the capacitor feedback transimpedance amplifier unit. Simultaneously, the capacitor feedback transimpedance amplifier unit converts the current signal of the pixel unit into a voltage signal through the integration process.
[0072] Step S300: Read the output voltage.
[0073] During integration, the analog domain readout unit acquires the output voltage of the capacitor feedback transimpedance amplifier unit. Simultaneously, the time-domain quantization unit counts in parallel and monitors whether it has reached the saturation threshold. Then, steps S400 and S500 are executed simultaneously.
[0074] Step S400: Sample the analog voltage signal.
[0075] The analog domain readout unit continuously acquires the analog voltage signal from the capacitor feedback transimpedance amplifier unit. Proceed to step S600;
[0076] Step S500: Count the digital time code value.
[0077] The time-domain quantization unit continuously counts until the output voltage of the capacitor feedback transimpedance amplifier unit reaches the saturation threshold. Then, the current count value is latched and output as a digital time code value. The process then proceeds to step S600. The generation of the digital time code value includes the following sub-steps:
[0078] Step S501, reset phase.
[0079] The first direction is counted using a bidirectional counting module to quantize the reset level state.
[0080] Step S502, digital integration stage.
[0081] A bidirectional counting module is used to count in a second direction, opposite to the first direction, until the output voltage of the capacitor feedback transimpedance amplifier unit reaches the saturation threshold, at which point the count value is latched. If the saturation threshold is not reached, latching is not triggered, and the system will re-enter step S501 for reset upon the next sampling.
[0082] Step S503, digital differential output.
[0083] If the saturation threshold is reached, the algebraic sum of the first direction count and the second direction count is calculated as the digital time code value to eliminate reset noise and comparator offset.
[0084] Step S600: Determine the saturation threshold.
[0085] When the output voltage of the time-domain quantization unit monitoring capacitor feedback transimpedance amplifier unit is lower than the saturation threshold, it proceeds to step S700; otherwise, it proceeds to step S800.
[0086] Step S700: Output analog voltage signal.
[0087] The analog voltage signal acquired by the analog domain readout unit is used as the final output to complete one sampling.
[0088] Step S800: Output the digital time code value.
[0089] The digital time code value obtained by counting the time domain quantization unit is used as the final output to complete one sampling.
[0090] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A low-noise mixed-domain CMOS detector readout circuit, characterized in that, It includes a capacitor feedback transimpedance amplifier unit, a switched capacitor reference unit, an analog domain readout unit, a time domain quantization unit, and an output selection unit; The capacitor feedback transimpedance amplifier unit is used to convert the current signal output by the pixel unit into a voltage signal; the switched capacitor reference unit is connected between the external reference voltage source and the non-inverting input terminal of the capacitor feedback transimpedance amplifier unit, and is used to filter out the noise of the reference voltage source by using the RC low-pass filter characteristics during the reset phase, and to maintain the reference potential of the capacitor feedback transimpedance amplifier by storing charge in the capacitor during the integration phase. Both the analog domain readout unit and the time domain quantization unit are coupled to the output of the capacitor feedback transimpedance amplifier unit; the analog domain readout unit is used to acquire and output analog voltage signals; the time domain quantization unit is used to output digital time code values by detecting saturation time. The output selection unit is used to select one of the analog voltage signal and the digital time code value as the final output; the output selection unit outputs the analog voltage signal by default, and switches to outputting the digital time code value when it detects that the output voltage of the capacitor feedback transimpedance amplifier reaches a preset saturation threshold.
2. The low-noise mixed-domain CMOS detector readout circuit according to claim 1, characterized in that, The switched capacitor reference unit includes a sampling switch module and a holding capacitor module; During the reset phase, the sampling switch module is turned on, and the on-resistance of the sampling switch module and the holding capacitor module form a RC low-pass filter to filter the noise output by the reference voltage source. During the integration phase, the sampling switch module is turned off, causing the non-inverting input of the capacitor feedback transimpedance amplifier unit to be in a high-impedance state, and the stored charge on the holding capacitor module is used to maintain the reference potential of the capacitor feedback transimpedance amplifier.
3. The low-noise mixed-domain CMOS detector readout circuit according to claim 1, characterized in that, The analog domain readout unit adopts a correlated dual sampling structure, including a reset sampling module and a signal sampling module; the reset sampling module acquires voltage at the reset time; the signal sampling module acquires voltage at the end of integration time, and outputs a differential analog signal based on the reset sampling module.
4. The low-noise mixed-domain CMOS detector readout circuit according to claim 1, characterized in that, The capacitor feedback transimpedance amplifier unit includes an operational amplifier and a feedback loop connected between its inverting input and output terminals. The operational amplifier adopts a folded cascode structure, its input differential pair transistors are PMOS transistors, and the load stage adopts a cascode current mirror structure. The feedback loop includes multiple parallel integrating capacitor modules and corresponding control switch modules. The gain level can be configurably adjusted by selecting different values of the integrating capacitor modules.
5. The low-noise mixed-domain CMOS detector readout circuit according to claim 1, characterized in that, The time-domain quantization unit includes a threshold comparison module and a counting module; The first input terminal of the threshold comparison module is coupled to the output terminal of the capacitor feedback transimpedance amplifier unit, and the second input terminal is connected to the threshold voltage corresponding to the saturation threshold, which is used to monitor the relationship between the output voltage of the capacitor feedback transimpedance amplifier unit and the saturation threshold in real time; the counting module starts counting during the integration period and latches the current count value when the threshold comparison module flips. The saturation threshold is less than the saturation voltage of the output stage of the capacitor feedback transimpedance amplifier unit, and is located within the high linearity range of the output signal of the capacitor feedback transimpedance amplifier unit.
6. The low-noise mixed-domain CMOS detector readout circuit according to claim 5, characterized in that, The counting module is a bidirectional counting module; during the reset phase, the bidirectional counting module performs counting in the first direction to quantify the state of the reset level; During the integration phase, the bidirectional counting module performs a second-direction count to quantize the signal level state; wherein the first-direction count is opposite to the second-direction count, and the final output digital time code value is the algebraic sum of the two counts, which is used to eliminate reset noise and comparator offset.
7. The low-noise mixed-domain CMOS detector readout circuit according to claim 5, characterized in that, The threshold comparison module is a hysteresis comparator structure; the hysteresis comparator structure includes a cross-coupled positive feedback load to form a hysteresis window to prevent output jitter caused by fluctuations in the input voltage near the threshold.
8. The low-noise mixed-domain CMOS detector readout circuit according to claim 1, characterized in that, The output selection unit includes a multiplexing module; the first input terminal of the multiplexing module is coupled to the output terminal of the analog domain readout unit, the second input terminal is coupled to the output terminal of the time domain quantization unit, and the control terminal is coupled to the output terminal of the threshold comparison module in the time domain quantization unit. The multiplexing module selects to output the analog voltage signal or the digital time code value based on the flip flag provided by the threshold comparison module.
9. A low-noise mixed-domain CMOS detector readout method, using the low-noise mixed-domain CMOS detector readout circuit as described in any one of claims 1 to 8, characterized in that, Includes the following steps: In step S100, during the reset phase, the external reference voltage source is connected to the non-inverting input of the capacitor feedback transimpedance amplifier through the switched capacitor reference unit, and a low-noise DC bias is established by utilizing the RC low-pass filter characteristics formed by the switch on-resistance and holding capacitor. In step S200, during the integration phase, the switched capacitor reference unit is disconnected, the charge stored in the holding capacitor is used to maintain the reference potential of the capacitor feedback transimpedance amplifier, and the current signal of the pixel unit is converted into a voltage signal using the capacitor feedback transimpedance amplifier. In step S300, during the integration process, the output voltage of the capacitor feedback transimpedance amplifier is acquired in parallel using the analog domain readout unit; at the same time, the time domain quantization unit is used to count on one hand and monitor in parallel whether the output voltage of the capacitor feedback transimpedance amplifier reaches the saturation threshold on the other hand. Then, steps S400 and S500 are executed simultaneously. In step S400, the analog domain readout unit continuously acquires the analog voltage signal of the capacitor feedback transimpedance amplifier unit, and proceeds to step S600. In step S500, the time-domain quantization unit continues to count until the output voltage of the capacitor feedback transimpedance amplifier unit reaches the saturation threshold, then latches the current count value and outputs it as a digital time code value; proceed to step S600. In step S600, the time-domain quantization unit monitors the output voltage of the capacitor feedback transimpedance amplifier unit; if the output voltage of the capacitor feedback transimpedance amplifier does not reach the saturation threshold, proceed to step S700, otherwise proceed to step S800. Step S700: The analog voltage signal acquired by the analog domain readout unit is used as the final output to complete one sampling. Step S800: The digital time code value obtained by counting in the time domain quantization unit is used as the final output to complete one sampling.
10. The low-noise mixed-domain CMOS detector readout method according to claim 9, characterized in that, The generation of the digital time code value includes the following sub-steps: Step S501: During the reset phase, the bidirectional counting module in the time-domain quantization unit is used to perform counting in the first direction and quantize the reset level state. Step S502: During the integration phase, the bidirectional counting module is used to count in the second direction, which is opposite to the first direction, until the output voltage of the capacitor feedback transimpedance amplifier reaches the saturation threshold, and then the count value is latched. Step S503: The algebraic sum of the first direction count and the second direction count is output as the digital time code value, thereby eliminating reset noise and comparator offset.