Pixel circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving module (10), a first storage module (20) and a locking control module (30), the driving module (10) generates a driving current according to a potential difference between a control end and a first end of the driving module (10); the first end of the first storage module (20) is electrically connected with the control end of the driving module (10), and the second end of the first storage module (20) is electrically connected with the first end of the driving module (10); the control end of the locking control module (30) is set to access a locking control signal, and the first end is electrically connected with the control end of the driving module (10); the second end of the first storage module (20) or the second end of the locking control module (30) is set to access a data signal; the locking control module (30) is set to respond to the turn-off of a locking control signal at the signal locking moment so as to enable the potential of the control end of the driving module (10) to float, and the first storage module (20) is set to store the voltage associated with the data signal accessed at the signal locking moment.

Description

Pixel circuit and driving method thereof, and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 1, 2023, with application number 202310187094.7. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0003] With the continuous development of display technology, the application range of display panels is becoming increasingly wider, and people's requirements for display panels are also becoming higher and higher. The pixel circuit in the display panel plays a vital role in driving the light-emitting devices to emit stable light. However, during the driving process of the pixel circuit, the data writing effect is poor, which affects the display quality of the display panel.

[0004] Summary of the Invention

[0005] The present application provides a pixel circuit and a driving method thereof, and a display panel, so as to improve the data writing effect of the pixel circuit, thereby improving the display effect of the display panel.

[0006] An embodiment of the present application provides a pixel circuit, including:

[0007] a driving module configured to generate a driving current according to a potential difference between the control terminal and the first terminal of the driving module, so as to drive the light emitting device to emit light;

[0008] a first storage module, wherein a first end of the first storage module is electrically connected to the control end of the driving module, and a second end of the first storage module is electrically connected to the first end of the driving module;

[0009] a locking control module, wherein a control end of the locking control module is configured to receive a locking control signal, a first end of the locking control module being electrically connected to the control end of the driving module; and a second end of the first storage module or a second end of the locking control module being configured to receive a data signal;

[0010] The locking control module is configured to float the potential of the control terminal of the driving module in response to the locking control signal being turned off at the signal locking moment, and the first storage module is configured to store a voltage associated with the data signal input at the signal locking moment.

[0011] Optionally, the first storage module includes: a first capacitor, a first end of the first capacitor serving as the first end of the first storage module, and a second end of the first capacitor serving as the second end of the first storage module;

[0012] The locking control module includes: a first transistor; the gate of the first transistor serves as the control end of the locking control module, the first electrode of the first transistor serves as the first end of the locking control module, and the second electrode of the first transistor serves as the second end of the locking control module.

[0013] Optionally, the second end of the first storage module is configured to access the data signal, and the second end of the locking control module is configured to connect to a first reference signal line;

[0014] The pixel circuit further includes:

[0015] a first data transmission module, configured to be turned on during a data writing phase to transmit the data signal to an output end of the first data transmission module; wherein the data writing phase includes the signal locking moment;

[0016] a second storage module connected between the output terminal of the first data transmission module and the second terminal of the first storage module, and configured to couple the potential jump of the output terminal of the first data transmission module to the second terminal of the first storage module;

[0017] Optionally, the first data transmission module includes: a second transistor, wherein the gate of the second transistor is configured to be connected to the first scan line, the first electrode of the second transistor is configured to be connected to the data line, and the second electrode of the second transistor serves as the output end of the first data transmission module;

[0018] The second storage module includes: a second capacitor, a first end of the second capacitor is electrically connected to the output end of the first data transmission module, and a second end of the second capacitor is electrically connected to the second end of the first storage module.

[0019] Optionally, the pixel circuit further includes:

[0020] a first reset module, electrically connected to the output terminal of the first data transmission module, configured to be turned on before the data writing phase and to reset the second storage module using a first reset signal; a second reset module, electrically connected to the second terminal of the driver module, configured to be turned on during a threshold compensation phase, causing the first terminal of the driver module to discharge through the driver module and the second reset module, so that the first storage module stores the threshold voltage of the driver module; wherein the threshold compensation phase is provided before the data writing phase;

[0021] The first light-emitting control module is connected in series with the driving module and the light-emitting device between the first power supply and the second power supply, and is configured to be turned on in the initialization stage and the light-emitting stage; wherein the initialization stage is set before the threshold compensation stage, and the light-emitting stage is set after the data writing stage.

[0022] Optionally, the second end of the locking control module is configured to receive the data signal;

[0023] The pixel circuit further includes:

[0024] a second data transmission module, configured to be turned on during a data writing phase to transmit the data signal to an output end of the second data transmission module; wherein the data writing phase includes the signal locking moment;

[0025] a third storage module, connected between the output terminal of the second data transmission module and the second terminal of the locking control module, and configured to couple the potential jump of the output terminal of the second data transmission module to the second terminal of the locking control module;

[0026] a reference signal transmission module, configured to transmit a second reference signal to the second end of the first storage module in response to being turned on by a transmission control signal; wherein the reference signal transmission module is turned off simultaneously with the locking control module or the reference signal transmission module is turned off later than the locking control module;

[0027] Optionally, the locking control signal is multiplexed into the transmission control signal;

[0028] Optionally, the second data transmission module includes: a third transistor, wherein the gate of the third transistor is configured to be connected to the second scan line, the first electrode of the third transistor is configured to be connected to the data line, and the second electrode of the third transistor serves as the output end of the second data transmission module;

[0029] The third storage module includes: a third capacitor, a first end of the third capacitor is electrically connected to the output end of the second data transmission module, and a second end of the third capacitor is electrically connected to the second end of the locking control module;

[0030] The reference signal transmission module includes: a fourth transistor, the gate of the fourth transistor is configured to be connected to the transmission control signal line, the first electrode of the fourth transistor is connected to the second reference signal line, and the second electrode of the fourth transistor is connected to the second end of the first storage module.

[0031] Optionally, the pixel circuit further includes:

[0032] a third reset module, electrically connected to the output end of the second data transmission module, and configured to reset the third storage module using a second reset signal before the data writing phase;

[0033] A second light-emitting control module is connected between the first power source and the second end of the driving module and is configured to be turned on during a light-emitting phase; wherein the light-emitting phase is configured after the data writing phase;

[0034] a third light-emitting control module, connected between the first terminal of the driving module and the anode of the light-emitting device, and configured to be turned on before the data writing phase and during the light-emitting phase;

[0035] Wherein, the second end of the first storage module is directly electrically connected to the first end of the driving module, or is electrically connected to the first end of the driving module through the third light emitting control module;

[0036] Optionally, the control end of the third reset module and the control end of the third light emitting control module are connected to the same control signal line.

[0037] Optionally, the second end of the locking control module is configured to receive the data signal;

[0038] The pixel circuit further includes:

[0039] a fourth storage module, wherein a first end of the fourth storage module is electrically connected to a second end of the first storage module, and a second end of the fourth storage module is connected to a first power supply;

[0040] Optionally, the fourth storage module includes: a fourth capacitor, a first end of the fourth capacitor serves as the first end of the fourth storage module, and a second end of the fourth capacitor serves as the second end of the fourth storage module.

[0041] Optionally, the pixel circuit further includes:

[0042] a fourth reset module, electrically connected to the second end of the first storage module, configured to be turned on during an initialization phase and turned off during a threshold compensation phase; wherein the threshold compensation phase is set before the data writing phase, the initialization phase is set before the threshold compensation phase, and the data writing phase includes the signal locking moment;

[0043] a fifth reset module, electrically connected to the first end of the first storage module, configured to be turned on before the data writing phase, and to transmit a third reset signal to the first end of the first storage module;

[0044] The fourth light-emitting control module is connected between the first power supply and the second end of the driving module, and is configured to be turned on before the data writing phase and during the light-emitting phase; wherein the light-emitting phase is configured after the data writing phase.

[0045] An embodiment of the present application further provides a display panel, comprising: the pixel circuit provided by any embodiment of the present application.

[0046] The embodiment of the present application further provides a pixel circuit driving method for driving the pixel circuit provided by any embodiment of the present application; the driving method comprises: a data writing phase and a light emitting phase; wherein the data writing phase includes a signal locking moment;

[0047] In the data writing phase, before the signal locking moment, the locking control signal controls the locking control module to be turned on, so that the potential difference across the first storage module changes with the change of the data signal;

[0048] At the signal locking moment, the locking control signal performs a potential jump, controls the locking control module to be turned off, and causes the potential of the control end of the driving module to float, and the first storage module stores a voltage associated with the data signal input at the signal locking moment;

[0049] In the light-emitting stage, the driving module generates a driving current according to the voltage stored by the first storage module at the signal locking moment, and drives the light-emitting device to emit light.

[0050] In the pixel circuit provided by the embodiments of the present application, a new data writing method is provided by providing a driver module, a first storage module, and a lock control module. This allows the data writing path in the pixel circuit to pass through the first storage module and the lock control module without passing through the driver module itself. Therefore, the embodiments of the present application can improve the data writing performance of the pixel circuit, thereby improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0052] FIG2 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0053] FIG3 is a driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0054] FIG4 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0055] FIG5 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0056] FIG6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0057] FIG7 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0058] FIG8 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0059] FIG9 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0060] FIG10 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0061] FIG11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0062] FIG12 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0063] FIG13 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0064] FIG14 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The present invention provides a pixel circuit. FIG1 is a schematic diagram of the structure of a pixel circuit provided by the present invention. Referring to FIG1 , the pixel circuit includes: a driving module 10 , a first storage module 20 , and a locking control module 30 .

[0066] The driver module 10 is configured to generate a driving current based on the potential difference between the control terminal G and the first terminal S of the driver module 10, thereby driving the light-emitting device to emit light. A first terminal of the first storage module 20 is electrically connected to the control terminal G of the driver module 10, and a second terminal of the first storage module 20 is electrically connected to the first terminal S of the driver module 10. A control terminal of the lock control module 30 receives a lock control signal Ssd, and a first terminal of the lock control module 30 is electrically connected to the control terminal G of the driver module 10. The second terminal of the first storage module 20 or the second terminal of the lock control module 30 is configured to receive a data signal Vdata ( FIG. 1 illustrates the second terminal of the first storage module 20 receiving the data signal Vdata as an example). The lock control module 30 is configured to, in response to the lock control signal Ssd being turned off at the signal lock time, float the potential of the control terminal G of the driver module 10. The first storage module 20 is configured to store a voltage associated with the data signal Vdata received at the signal lock time.

[0067] Exemplarily, the driving module 10 may include a driving transistor, the gate of the driving transistor serving as the control terminal G of the driving module 10, the source of the driving transistor serving as the first terminal S of the driving module 10, and the drain of the driving transistor serving as the second terminal D of the driving module 10. The second terminal of the first storage module 20 or the second terminal of the locking control module 30 may be directly or indirectly connected to the data signal Vdata. The connection terminal configured to access the data signal Vdata is defined as the data connection terminal. Then, directly accessing the data signal Vdata means that the data connection terminal is directly connected to the data line. Indirectly accessing the data signal Vdata means that the data connection terminal is connected to the data line through other modules, that is, after the other modules process the data signal Vdata, the signal containing the information of the data signal Vdata is transmitted to the data connection terminal.

[0068] The first storage module 20 may include a storage device such as a capacitor, which is configured to store the potential difference between the control terminal G and the first terminal S of the storage drive module 10. Taking a capacitor as an example, the storage device has the following characteristics: when both ends of the capacitor are connected to a source signal, the potential difference between the two ends of the capacitor can change with the change of any source signal; when either end of the capacitor is connected to a passive signal and the potential is floating, regardless of whether the potential of the source signal at the other end of the capacitor changes, the potential difference between the two ends of the capacitor is fixed, and the potential difference stored by the capacitor when the source signal at the floating end disappears is maintained. When one end of the capacitor is connected to a passive signal, if the source signal at the other end of the capacitor maintains a fixed potential and does not provide a potential change, the potential at both ends of the capacitor remains unchanged, and the potential difference between the two ends remains unchanged; if the source signal potential at the other end of the capacitor changes, based on the coupling effect of the capacitor, the potential at the end not connected to the source signal will also change with the change of the source signal, but the potential difference between the two ends of the capacitor remains unchanged. Based on the above characteristics, one end of the first storage module 20 can be directly or indirectly connected to the data signal Vdata, and the other end of the first storage module 20 can be directly or indirectly connected to a fixed power supply. Furthermore, any moment within the row time during which the data signal Vdata maintains the data voltage required by the pixel circuit of this row can be set as the signal locking moment. The row time can be understood as the time during which the data signal Vdata maintains the data voltage required by the pixel circuit of this row, or the interval time during which the data signal Vdata is refreshed. At the signal locking moment, the first storage module 20 can be controlled to be disconnected from the data signal Vdata and / or the fixed power supply, so that the first storage module 20 stores the voltage associated with the data signal Vdata at the signal locking moment. The voltage stored in the first storage module 20 can be the potential difference between the two ends of the first storage module 20; the voltage associated with the data signal Vdata can be understood as a voltage that carries information of the data signal Vdata, such as a voltage that has a multiple relationship with the data voltage or a voltage that has other functional relationships with the data voltage that can be calculated based on the data transmission process and the storage characteristics of the first storage module 20.

[0069] The lock control module 30 may include a switching device such as a transistor. The lock control module 30 may be located at the end of the first storage module 20 connected to a fixed power source, or at the end of the first storage module 20 receiving the data signal Vdata. The moment when the lock control signal Ssd changes from the on-state potential of the lock control module 30 to the off-state potential can be used as the signal lock moment. For example, if the lock control module 30 is located at the end of the first storage module 20 connected to a fixed power source, at the potential transition edge when the lock control signal Ssd changes from the on-state potential to the off-state potential, the lock control module 30 is disconnected, causing the control terminal G of the driver module 10 to float, thus cutting off the fixed power source of the first storage module 20. The first storage module 20 can then store and maintain the potential difference at the moment of the lock control signal Ssd potential transition. For example, when the lock control module 30 is located at the end of the first storage module 20 connected to a fixed power source, the pixel circuit may further include a data writing module, such as a transistor, connected to the other end of the first storage module 20 and configured to control whether the data signal Vdata can be transmitted to the first storage module 20. When the locking control module 30 is arranged at one end of the first storage module 20 for connecting to the data signal Vdata, the pixel circuit may further include an auxiliary storage device, such as a capacitor, which is connected to the other end of the first storage module 20 to indirectly provide a fixed power supply signal to the other end of the first storage module 20.

[0070] From the above analysis, it can be seen that for the pixel circuit provided in the embodiment of the present application, the data writing path passes through the first storage module 20 and the locking control module 30, without passing through the channel of the driving transistor. At the potential jump edge of the locking control signal Ssd, that is, the signal locking moment, the potential stored in the first storage module 20 is locked, and the data writing is completed. Therefore, in the embodiment of the present application, there is no need to wait for the gate potential of the driving transistor to slowly change, and fast data writing can be achieved. As long as the data writing phase is set to include the signal locking moment, and the signal locking moment is within the row time when the data signal Vdata maintains the data voltage required by the pixel circuit of this row, the first storage module 20 can be controlled to correctly store the voltage signal associated with the data voltage of this row, thereby achieving a correct data writing process.

[0071] Furthermore, the duration of the data writing phase can exceed the row time. In this embodiment, the data voltage information of the adjacent rows is allowed to enter the pixel circuit of the current row. Before the potential jump of the locking control signal Ssd, the potentials of multiple nodes in the data writing path can follow the voltage change of the data signal Vdata. Compared with the pixel circuit in the related art (such as the pixel circuit of the 7T1C architecture), there is no risk that the data voltage of the subsequent row cannot be turned on due to the inability to turn on the drive transistor, making the writing irreversible. Therefore, the data voltage of the previous row or multiple rows is allowed to enter the pixel circuit of the current row. Moreover, after the potential jump of the locking control signal Ssd, the potential difference between the control terminal G and the first terminal S of the driving module 10 is maintained by the first storage module 20. Even if the data signal Vdata undergoes a voltage jump again, it will not affect the maintenance of the potential difference between the control terminal G and the first terminal S of the driving module 10. Therefore, the conduction pulse width of the control signal related to the data writing process can be greater than the row time. This can effectively reduce the risk of failure of the scanning circuit used to provide the above-mentioned control signal, improve the stability of the control signal, and ensure the effect of data writing.

[0072] In the subsequent light-emitting stage, the locking control signal Ssd maintains the cut-off potential, so that the locking control module 30 remains turned off, the first storage module 20 maintains the voltage stored at the signal locking moment, and the driving module 10 generates a driving current based on the voltage to drive the light-emitting device to emit light at the target brightness corresponding to the data signal Vdata at the signal locking moment.

[0073] In summary, the pixel circuit provided in the embodiment of the present application provides a new data writing method by providing a driver module 10, a first storage module 20, and a lock control module 30, so that the data writing path in the pixel circuit passes through the first storage module 20 and the lock control module 30, without passing through the driver module 10 itself. Therefore, by controlling the lock control module 30 to change from an on state to an off state at the signal lock moment, the data information at that moment can be locked, so that the first storage module 20 can quickly and correctly store the voltage associated with the data signal Vdata connected at the signal lock moment. In addition, by setting the data writing phase to include the signal lock moment, and the signal lock moment being within the row time during which the data signal Vdata maintains the data voltage required by the pixel circuit of the row, a correct data writing process can be achieved. This embodiment has no limit on the maintenance duration of the data writing phase. During the data writing process, the data voltage information of the adjacent rows is allowed to enter the pixel circuit of the row. Therefore, the conduction pulse width of the control signal related to the data writing process can be greater than the row time. This can effectively reduce the risk of failure of the scanning circuit used to provide the control signal, improve the stability of the control signal, and ensure the effect of data writing. Therefore, the on-pulse width of the scanning signal associated with the data writing process can be greater than the line time, which can effectively reduce the risk of poor scanning circuit performance, improve the stability of the scanning signal, and ensure the effectiveness of data writing. Therefore, the structure of the pixel circuit provided in the embodiments of the present application can improve the data writing performance of the pixel circuit, thereby improving the display quality of the display panel.

[0074] The functional modules in the pixel circuit are functionally described in the above embodiments. The following describes the possible structures of each functional module and explains other possible functional modules and control timings in the pixel circuit.

[0075] FIG2 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Referring to FIG2 , based on the above embodiment, optionally, the first storage module 20 includes: a first capacitor Cst1, wherein the first end of the first capacitor Cst1 serves as the first end of the first storage module 20, and the second end of the first capacitor Cst1 serves as the second end of the first storage module 20. In this embodiment, the first storage module 20 is composed of a single capacitor, which simplifies the structure of the first storage module 20 and facilitates implementation.

[0076] Continuing with FIG. 2 , based on the above embodiment, the locking control module 30 optionally includes a first transistor M1; the gate of the first transistor M1 serves as a control terminal of the locking control module 30, the first electrode of the first transistor M1 serves as a first terminal of the locking control module 30, and the second electrode of the first transistor M1 serves as a second terminal of the locking control module 30. In this embodiment, the locking control module 30 is composed of a single transistor, which simplifies the structure of the locking control module 30 and facilitates its implementation.

[0077] 2 , in one embodiment, optionally, the second end of the first storage module 20 is configured to indirectly access the data signal Vdata, and the second end of the lock control module 30 is connected to the first reference signal line and accesses the first reference signal Vref1. The first reference signal Vref1 is, for example, a DC signal with a fixed potential.

[0078] FIG2 mainly shows the structure related to the data writing process in the pixel circuit. For example, in addition to the first storage module 20 and the locking control module 30, the structure related to the data writing process also includes: a first data transmission module 610 and a second storage module 620 to assist in data writing. The second storage module 620 is connected between the output end of the first data transmission module 610 and the second end of the first storage module 20. The first data transmission module 610 is configured to be turned on during the data writing phase and transmit the data signal Vdata to the output end of the first data transmission module 610; the second storage module 620 is configured to couple the potential jump of the output end of the first data transmission module 610 to the second end of the first storage module 20. The data writing phase includes the signal locking moment.

[0079] The first data transmission module 610 includes a second transistor M2, the gate of which is connected to the first scan line and receives the first scan signal S1; a first electrode of the second transistor M2 is connected to the data line and receives the data signal Vdata; and a second electrode of the second transistor M2 serves as the output terminal of the first data transmission module 610. The second storage module 620 includes a second capacitor Cst2, the first terminal N1 of the second capacitor Cst2 being electrically connected to the output terminal of the first data transmission module 610, and the second terminal of the second capacitor Cst2 being electrically connected to the second terminal of the first storage module 20.

[0080] The following describes the data writing process for the pixel circuit, taking FIG3 as an example, with all transistors being P-type transistors. For example, for the data signal Vdata, the data voltage Vb is the data voltage required by the pixel circuit for the current row, the data voltage Va is the data voltage for the previous row, and the data voltage Vc is the data voltage for the next row. Taking the data writing phase T3 lasting for three row times h as an example, the data writing phase T3 for the pixel circuit includes:

[0081] Before signal lock time ts, the lock control signal Ssd and the first scan signal S1 are both at a low voltage. The first transistor M1 and the second transistor M2 are both turned on, transmitting the first reference signal Vref1 to the first terminal of the first capacitor Cst1 via the first transistor M1, and transmitting the data signal Vdata to the first terminal N1 of the second capacitor Cst2 via the second transistor M2. When the data signal Vdata changes from the data voltage Va to the data voltage Vb, the second capacitor Cst2 couples the potential change of its first terminal N1 to the second terminal of the first capacitor Cst1. The potential difference across the first capacitor Cst1 follows the potential change of the second terminal of the first capacitor Cst1.

[0082] The signal lock time ts occurs during the period when the data signal Vdata maintains the data voltage Vb. At the signal lock time ts, the rising edge of the lock control signal Ssd occurs, causing the lock control signal Ssd to jump to a high potential, while the first scan signal S1 remains at a low potential. The first transistor M1 is turned off, and the second transistor M2 is turned on. The first end of the first capacitor Cst1 (i.e., the gate of the drive transistor DTFT) floats, the fixed signal source of the first capacitor Cst1 is cut off, and the potential difference across the first capacitor Cst1 is locked. At this point, the information of the data signal Vdata is stored in the first capacitor Cst1.

[0083] After signal lock time ts, the lock control signal Ssd is high, and the first scan signal S1 remains low. The first transistor M1 is turned off, and the second transistor M2 is turned on. The first terminal of the first capacitor Cst1 remains floating, and the data signal Vdata is transmitted to the first terminal N1 of the second capacitor Cst2 via the second transistor M2. When the data signal Vdata changes from the data voltage Vb to the data voltage Vc, the potentials of the first terminal N1 of the second capacitor Cst2 and the first and second terminals of the first capacitor Cst1 change accordingly. However, the potential difference across the first capacitor Cst1 remains unchanged from the potential difference at signal lock time ts.

[0084] From the above, it can be seen that although the turn-on pulse of the first scan signal S1 is wider than the line time h, the three data voltage values ​​of the data signal Vdata successively enter the first terminal N1 of the second capacitor Cst2 during the data writing phase T3, but only the voltage associated with the data voltage Vb is actually collected and locked by the first capacitor Cst1.

[0085] A complete pixel circuit using the above-mentioned data writing structure is described below. Figure 4 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Referring to Figure 4, on the basis of the above-mentioned embodiment, optionally, the pixel circuit further includes: a first reset module 410, a second reset module 420 and a first light-emitting control module 510. Among them, the first reset module 410 is electrically connected to the output end of the first data transmission module 610. The second reset module 420 is electrically connected to the second end D of the driving module 10. The first light-emitting control module 510 is connected in series with the driving module 10 and the light-emitting device L between the first power supply and the second power supply.

[0086] The first reset module 410 includes a fifth transistor M5, a gate of which is connected to the first control signal Re1, a first electrode of which is connected to the first reset signal Vini1, and a second electrode of which is electrically connected to the output terminal of the first data transmission module 610. The second reset module 420 includes a sixth transistor M6, a gate of which is connected to the first control signal Re1, a first electrode of which is connected to the first reference signal Vref1, and a second electrode of which is electrically connected to the second terminal D of the driver module 10. The first light control module 510 includes a seventh transistor M7 and an eighth transistor M8, a gate of which is connected to the first light control signal EM1, a first electrode of which is connected to the first power supply and the first power supply signal VDD, and a second electrode of which is electrically connected to the first terminal S of the driver module 10. The first electrode of the eighth transistor M8 is electrically connected to the second terminal D of the driver module 10, a second electrode of which is electrically connected to the anode of the light-emitting device L, and a cathode of the light-emitting device L is connected to the second power supply and the second power supply signal VSS. The first power signal VDD and the second power signal VSS are DC signals with different potentials, for example, the first power signal VDD is a high potential signal and the second power signal VSS is a low potential signal. The first reset signal Vini1 can be a DC signal with a fixed potential.

[0087] FIG5 is a schematic diagram of a driving timing of another pixel circuit provided in an embodiment of the present application. In conjunction with FIG4 and FIG5 , illustratively, the driving process of the pixel circuit includes:

[0088] During the initialization phase T1, the first light-emitting control signal EM1 is at a low level, turning on the seventh transistor M7 and the eighth transistor M8. The first scan signal S1 is at a high level, turning off the second transistor M2. After the low-level pulses of the first control signal Re1 and the lock control signal Ssd arrive successively, the first transistor M1, the fifth transistor M5, and the sixth transistor M6 are all turned on. The first reset signal Vini1 is transmitted to the first terminal N1 of the second capacitor Cst2 via the fifth transistor M5. The first reference signal Vref1 is transmitted to the gate of the drive transistor DTFT via the first transistor M1. Simultaneously, the first reference signal Vref1 is transmitted to the drain of the drive transistor DTFT via the sixth transistor M6 and further transmitted to the anode of the light-emitting device L via the eighth transistor M8, thereby resetting the anode of the light-emitting device L. The first power supply signal VDD is transmitted to the source of the drive transistor DTFT via the seventh transistor M7. During this phase, the first capacitor Cst1 and the second capacitor Cst2 are both discharged and reset.

[0089] During the threshold compensation phase T2, the first control signal Re1 and the lock control signal Ssd are both at a low potential, and the first scan signal S1 and the first light-emitting control signal EM1 are both at a high potential. The seventh transistor M7 and the eighth transistor M8 are both turned off. The first reset signal Vini1 continues to be transmitted to the first terminal N1 of the second capacitor Cst2 via the fifth transistor M5. The first reference signal Vref1 continues to be transmitted to the gate of the driving transistor DTFT via the first transistor M1. The source of the driving transistor DTFT is discharged through the driving transistor DTFT and the sixth transistor M6. The source potential of the driving transistor DTFT gradually decreases from the potential of the first power supply signal VDD until Vref1-Vth1, at which point the driving transistor DTFT is turned off, completing the threshold compensation of the driving transistor DTFT. At this point, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the driving transistor DTFT.

[0090] During the data writing phase T3, upon entering the data writing phase, the lock control signal Ssd and the first scan signal S1 are both at a low level, while the first control signal Re1 and the first light-emitting control signal EM1 are both at a high level. The fifth transistor M5 and the sixth transistor M6 are turned off, while the first transistor M1 and the second transistor M2 remain on. The data signal Vdata is written to the first terminal N1 of the second capacitor Cst2 via the second transistor M2, causing the potential at the first terminal N1 of the second capacitor Cst2 to jump from the first reset signal Vini1 to the current data voltage Va of the data signal Vdata. The first reference signal Vref1 continues to be transmitted through the first transistor M1 to the gate of the drive transistor DTFT. Since the potential of the first terminal N1 of the second capacitor Cst2 jumps, the potential jump amount of the first terminal N1 of the second capacitor Cst2 coupled to the potential jump amount of the second terminal of the first capacitor Cst1 through the second capacitor Cst2 is (Vdata-Vini1)·(Cst2) / (Cst1+Cst2+Cgs). Therefore, the voltage difference between the two ends of the first capacitor Cst1 becomes: Vth1+(Vdata-Vini1)·(Cst2) / (Cst1+Cst2+Cgs), where Cgs is the capacitance between the gate and source of the driving transistor DTFT.

[0091] At the signal locking time ts, the locking control signal Ssd jumps to a high potential, turning off the first transistor M1 and floating the first end of the first capacitor Cst1 (i.e., the gate of the driving transistor DTFT). At this time, the data signal Vdata maintains the data voltage Vb, so the potential difference across the first capacitor Cst1 is locked to: Vth1 + (Vb - Vini1) · (Cst2) / (Cst1 + Cst2 + Cgs). In other words, the information of the data signal Vdata of this row and the threshold voltage information of the driving transistor DTFT are both stored in the first capacitor Cst1. For example, the rising edge of the first control signal Re1 can be set to lead the rising edge of the locking control signal Ssd by one row time, i.e., 1h.

[0092] After the signal lock time ts, the lock control signal Ssd maintains a high potential, the first transistor M1 remains off, and the first end of the first capacitor Cst1 remains floating. The data signal Vdata can still be transmitted to the first end N1 of the second capacitor Cst2 through the second transistor M2. When the data signal Vdata jumps to the data voltage Vc, this voltage enters the pixel circuit, but the potential jump amount coupled from the second capacitor Cst2 to the second end of the first capacitor Cst1 is simultaneously coupled to the first end of the first capacitor Cst1 by the first capacitor Cst1. The data voltage Vc is equivalent to being invalidated, and the potential difference across the first capacitor Cst1 remains Vth1+(Vb-Vini1)·(Cst2) / (Cst1+Cst2+Cgs).

[0093] During the light-emitting phase T4, the first light-emitting control signal EM1 is at a low level, while the first control signal Re1, the lock control signal Ssd, and the first scan signal S1 are all at a high level. The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are all off, while the seventh transistor M7 and the eighth transistor M8 are both on. The drive transistor DTFT generates a drive current to illuminate the light-emitting device L. The drive current is a function of Vgs-Vth1, where Vgs is equal to the potential difference across the first capacitor Cst1. When the structure of the pixel circuit is determined, the first capacitor Cst1, the second capacitor Cst2, and Cgs are also fixed. Therefore, the drive current is actually a function of Vdata-Vini1. That is, the magnitude of the drive current is independent of the threshold voltage Vth1 of the drive transistor DTFT, thus achieving threshold compensation.

[0094] In summary, the time span of the data writing phase T3 exceeds 1 row time h. In this embodiment, in the data writing phase T3, the data signal Vdata has three values ​​in succession. Only the data voltage Vb at the signal locking moment ts is valid for the pixel circuit of this row. The rising edge of the locking control signal Ssd is equivalent to a sampling action, which locks the data voltage Vb at this time and stores the data voltage Vb in the first capacitor Cst1. Although the data voltages of adjacent rows can enter this circuit, they are equivalent to being invalid. The embodiment of the present application provides a 7T2C pixel circuit architecture as a whole. Separating the threshold compensation process and the data writing process during the driving process is conducive to extending the threshold compensation time and improving the threshold compensation effect on the driving transistor DTFT, thereby improving the brightness uniformity of the display panel, while taking into account the realization of high-frequency refresh and high resolution of the display panel.

[0095] For example, the transistors in the pixel circuit can all be P-type transistors, manufactured using a low-temperature polysilicon (LTPS) process to fully utilize the advantages of LTPS transistors such as high mobility, strong driving capability, and mature technology, while reducing the manufacturing cost of the display panel.

[0096] The above embodiment exemplifies that the transistors in the pixel are all composed of P-type transistors, but this is not intended to limit the present application. In other embodiments, some or all of the transistors can be replaced with N-type transistors as needed, and the potential of the control signal connected to the transistor can be adjusted accordingly. For example, as shown in Figure 6, the transistors in the relevant structure for writing data can be replaced with N-type transistors.

[0097] FIG7 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. FIG7 primarily illustrates the structure associated with the data writing process. Referring to FIG7 , in another embodiment, the second terminal of the lock control module 30 is optionally configured to indirectly receive the data signal Vdata. Exemplarily, the structure associated with the data writing process, in addition to the first storage module 20 and the lock control module 30, further includes: a second data transmission module 710, a third storage module 720, and a reference signal transmission module 730. The third storage module 720 is connected between the output terminal of the second data transmission module 710 and the second terminal of the lock control module 30, and the reference signal transmission module 730 is electrically connected to the second terminal of the first storage module 20. The second data transmission module 710 is configured to conduct during the data writing phase and transmit the data signal Vdata to the output terminal of the second data transmission module 710. The third storage module 720 is configured to couple the potential jump at the output terminal of the second data transmission module 710 to the second terminal of the lock control module 30. The reference signal transmission module 730 is configured to conduct in response to the transmission control signal Sc and transmit the second reference signal Vref2 to the second terminal of the first storage module 20. The transmission control signal Sc controls the reference signal transmission module 730 to be turned off simultaneously with or later than the lock control module 30, thereby preventing the second terminal of the first storage module 20 from floating prematurely, thereby preventing the first storage module 20 from correctly storing the voltage associated with the data signal Vdata at the signal lock time ts. The second reference signal Vref2 is, for example, a DC signal with a fixed potential.

[0098] Optionally, the lock control signal Ssd can be multiplexed into the transmission control signal Sc, thereby controlling the lock control module 30 and the reference signal transmission module 730 to be simultaneously turned off at the signal lock time ts. This configuration can reduce the number of signal lines in the display panel, simplifying the display panel structure and facilitating the wiring design of the display panel.

[0099] The second data transmission module 710 includes a third transistor M3, the gate of which is connected to the second scan line and receives the second scan signal S2; a first electrode of the third transistor M3 is connected to the data line and receives the data signal Vdata; and a second electrode of the third transistor M3 serves as the output terminal of the second data transmission module 710. The third storage module 720 includes a third capacitor Cst3, the first end of which is electrically connected to the output terminal of the second data transmission module 710, and the second end of which is electrically connected to the second terminal of the lock control module 30. The reference signal transmission module 730 includes a fourth transistor M4, the gate of which is connected to the transmission control signal line and receives the transmission control signal Sc; a first electrode of the fourth transistor M4 is connected to the second reference signal line and receives the second reference signal Vref2, and a second electrode of the fourth transistor M4 is connected to the second terminal of the first storage module 20.

[0100] The application of the structure is described below in conjunction with a pixel circuit that applies the data writing structure. Figure 8 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Referring to Figure 8, on the basis of the above embodiment, optionally, the pixel circuit further includes: a third reset module 430, a second light-emitting control module 520 and a third light-emitting control module 530. Among them, the third reset module 430 is electrically connected to the output end of the second data transmission module 710. The second light-emitting control module 520 is connected between the first power supply and the second end D of the driving module 10, and the third light-emitting control module 530 is connected between the first end S of the driving module 10 and the anode of the light-emitting device L.

[0101] The third reset module 430 includes a ninth transistor M9, a gate of which is connected to the second control signal Re2, a first electrode of which is connected to the second reset signal Vcom, and a second electrode of which is electrically connected to the output terminal of the second data transmission module 710. The second light-emission control module 520 includes a tenth transistor M10, a gate of which is connected to the second light-emission control signal EM2, a first electrode of which is connected to the first power supply signal VDD, and a second electrode of which is electrically connected to the drain of the driving transistor DTFT. The third light-emission control module 530 includes an eleventh transistor M11, a gate of which is connected to the third light-emission control signal EM3, a first electrode of which is electrically connected to the source of the driving transistor DTFT (the first terminal S of the driving module 10), and a second electrode of which is electrically connected to the anode of the light-emitting device L. The second reset signal Vcom is, for example, a DC signal with a fixed potential.

[0102] Optionally, the control end of the third reset module 430 and the control end of the third light emitting control module 530 may be connected to the same control signal line, that is, the third light emitting control signal EM3 may be multiplexed into the second control signal Re2 to reduce the number of signal lines in the display panel.

[0103] FIG9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application. Combining FIG8 and FIG9 , taking the example of multiplexing the lock control signal Ssd into the transmission control signal Sc and multiplexing the third light control signal EM3 into the second control signal Re2, and assuming that all transistors are N-type transistors, the driving process of the pixel circuit includes:

[0104] During the threshold compensation phase T2, the lock control signal Ssd and the third light-emitting control signal EM3 are both at a high level, while the second scan signal S2 and the second light-emitting control signal EM2 are both at a low level. The first transistor M1, the fourth transistor M4, the ninth transistor M9, and the eleventh transistor M11 are all turned on, while the third transistor M3 and the tenth transistor M10 are both turned off. The second reset signal Vcom is transmitted to the first end of the third capacitor Cst3 via the ninth transistor M9. The second reference signal Vref2 is transmitted to the anode of the light-emitting device L via the fourth transistor M4 and further transmitted to the source of the drive transistor DTFT via the eleventh transistor M11. The first power supply signal VDD is transmitted to the drain of the drive transistor DTFT via the tenth transistor M10 and further transmitted to the gate of the drive transistor DTFT via the first transistor M1. At the start of the threshold compensation phase T2, the gate potential of the driving transistor DTFT is momentarily raised to a level slightly lower than the first power supply signal VDD, turning on the driving transistor DTFT. A driving current flows from the drain of the driving transistor DTFT, through the driving transistor DTFT, the eleventh transistor M11, and the fourth transistor M4, toward the second reference signal line (i.e., the signal line configured to provide the second reference signal Vref2), until the gate and drain potentials of the driving transistor DTFT drop to Vref2 + Vth1. At this point, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the driving transistor DTFT.

[0105] During the data writing phase T3, upon entering the data writing phase T3, the third light-emitting control signal EM3 transitions to a low level, the second scan signal S2 transitions to a high level, the lock control signal Ssd remains high, and the second light-emitting control signal EM2 remains low. The ninth transistor M9 and the eleventh transistor M11 are turned off, and the third transistor M3 is turned on. The data signal Vdata is written to the first terminal of the third capacitor Cst3 via the third transistor M3, causing the potential at the first terminal of the third capacitor Cst3 to transition from the second reset signal Vcom to the current data voltage Va of the data signal Vdata. The source of the drive transistor DTFT floats, maintaining the potential of the second reference signal Vref2. The second reference signal Vref2 is still transmitted to the second terminal of the first capacitor Cst1 via the fourth transistor M4. Since the potential of the first end of the third capacitor Cst3 jumps, the potential jump amount is coupled through the third capacitor Cst3 and transmitted to the first end of the first capacitor Cst1 through the first transistor M1. The potential jump amount is (Vdata-Vcom)·(Cst3) / (Cst1+Cst3+Cgs). Therefore, the voltage difference between the two ends of the first capacitor Cst1 becomes: Vth1+(Vdata-Vcom)·(Cst3) / (Cst1+Cst3+Cgs), where Cgs is the capacitance between the gate and source of the driving transistor DTFT.

[0106] At signal lock time ts, the falling edge of the lock control signal Ssd arrives, dropping to a low potential. This turns off the first transistor M1 and the fourth transistor M4, leaving the first and second terminals of the first capacitor Cst1 floating. Both the data signal source and the fixed signal source of the first capacitor Cst1 are disconnected. At this point, the data signal Vdata is the data voltage Vb, so the potential difference across the first capacitor Cst1 is locked to: Vth1 + (Vb - Vcom) · (Cst3) / (Cst1 + Cst3 + Cgs). In other words, the information about the row's data signal Vdata and the threshold voltage of the drive transistor DTFT are both stored in the first capacitor Cst1.

[0107] After the signal locking time ts, the locking control signal Ssd maintains a low potential, the first transistor M1 and the fourth transistor M4 remain turned off, and the data signal Vdata can still be transmitted to the first end N1 of the third capacitor Cst3 through the third transistor M3. However, since the first transistor M1 is turned off, the potential jump amount coupled by the third capacitor Cst3 cannot be transmitted to the first end of the first capacitor Cst1, and the potential difference across the first capacitor Cst1 still remains Vth1+(Vb-Vcom)·(Cst3) / (Cst1+Cst3+Cgs).

[0108] During the light-emitting phase T4, the second light-emitting control signal EM2 and the third light-emitting control signal EM3 are both at a high level, and the lock control signal Ssd and the second scan signal S2 are both at a low level. The first transistor M1, the third transistor M3, and the fourth transistor M4 are all turned off. The tenth transistor M10 and the eleventh transistor M11 are both turned on, and the driving transistor DTFT generates a driving current to illuminate the light-emitting device L. The ninth transistor M9 is turned on, and the second reset signal Vcom is transmitted to the first end of the third capacitor Cst3 through the ninth transistor M9, completing the resetting of the third capacitor Cst3. Similarly, since the driving current is a function of Vgs-Vth1, where Vgs is equal to the potential difference across the first capacitor Cst1, the actual driving current is a function of (Vb-Vcom)·(Cst3) / (Cst1+Cst3+Cgs), and the driving current is independent of the threshold voltage Vth1 of the driving transistor DTFT.

[0109] The above embodiment exemplifies a scheme in which the second end of the first capacitor Cst1 is indirectly connected to the source of the driving transistor DTFT, that is, connected to the source of the driving transistor DTFT through the eleventh transistor M11, but this is not intended to limit the present application. In other embodiments, as shown in FIG10 , the second end of the first capacitor Cst1 can also be directly connected to the source of the driving transistor DTFT. The driving timing corresponding to the pixel circuit shown in FIG10 can still refer to FIG9 . The difference in the driving process is that: in the threshold compensation stage T2, the discharge path of the driving transistor DTFT directly passes through the fourth transistor M4 and no longer passes through the eleventh transistor M11, and the second reference signal Vref2 is transmitted to the anode of the light-emitting device L through the eleventh transistor M11 after passing through the fourth transistor M4.

[0110] The above embodiment exemplifies that the transistors in the pixel are all composed of N-type transistors, but this is not intended to limit the present application. In other embodiments, some or all of the transistors can be replaced with P-type transistors as needed, and the potential of the control signal connected to the transistor can be adjusted accordingly.

[0111] Figure 11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application. Referring to Figure 11, in another embodiment, optionally, the second end of the locking control module 30 is connected to the data signal Vdata. Figure 11 mainly shows the structure related to the data writing process in the pixel circuit. Exemplarily, in the structure related to the data writing process, in addition to the first storage module 20 and the locking control module 30, it also includes: a fourth storage module 80, the first end of the fourth storage module 80 is electrically connected to the second end of the first storage module 20, and the second end of the fourth storage module 80 is connected to the first power supply and connected to the first power supply signal VDD. The fourth storage module 80 includes: a fourth capacitor Cst4, the first end of the fourth capacitor Cst4 serves as the first end of the fourth storage module 80, and the second end of the fourth capacitor Cst4 serves as the second end of the fourth storage module 80.

[0112] The application of the structure is described below in conjunction with a pixel circuit that uses the data writing structure. Figure 12 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Referring to Figure 12, based on the above embodiment, the pixel circuit optionally further includes: a fourth reset module 440, a fifth reset module 450, and a fourth light-emitting control module 540. The fourth reset module 440 is electrically connected to the second end of the first storage module 20; the fifth reset module 450 is electrically connected to the first end of the first storage module 20; and the fourth light-emitting control module 540 is connected between the first power supply and the second end D of the driving module 10.

[0113] The fourth reset module 440 includes a twelfth transistor M12, the gate of which is connected to the third control signal Re3, the first electrode of which is connected to the third reference signal Vref3, and the second electrode of which is electrically connected to the second end of the first capacitor Cst1. The fifth reset module 450 includes a thirteenth transistor M13, the gate of which is connected to the fourth control signal Re4, the first electrode of which is connected to the third reset signal Vini2, and the second electrode of which is electrically connected to the first end of the first capacitor Cst1. The fourth light-emitting control module 540 includes a fourteenth transistor M14, the first electrode of which is connected to the first power supply signal VDD, and the second electrode of which is electrically connected to the drain of the driving transistor DTFT. The second end of the first capacitor Cst1 is directly electrically connected to the source of the driving transistor DTFT and the anode of the light-emitting device L. Both the third reference signal Vref3 and the third reset signal Vini2 can be DC signals with a fixed potential.

[0114] FIG13 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application. Combining FIG12 and FIG13 , taking the case where all transistors are N-type transistors as an example, the driving process of the pixel circuit includes:

[0115] During the initialization phase T1, the lock control signal Ssd is at a low potential, and the third control signal Re3, the fourth control signal Re4, and the fourth light-emitting control signal EM4 are all at a high potential. The first transistor M1 is turned off, and the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned on. The third reference signal Vref3 is transmitted via the twelfth transistor M12 to the second end of the first capacitor Cst1, the first end of the fourth capacitor Cst4, and the anode of the light-emitting device L. The third reset signal Vini2 is transmitted via the thirteenth transistor M13 to the first end of the first capacitor Cst1, and the first power supply signal VDD is transmitted via the fourteenth transistor M14 to the drain of the drive transistor DTFT. During the initialization phase, the first capacitor Cst1, the fourth capacitor Cst4, and the anode of the light-emitting device L are all reset.

[0116] During the threshold compensation phase T2, the third control signal Re3 changes to a low potential. The twelfth transistor M12 is turned off, the first power signal VDD continues to be transmitted to the drain of the driving transistor DTFT via the fourteenth transistor M14, and the third reset signal Vini2 continues to be transmitted to the first end of the first capacitor Cst1 via the thirteenth transistor M13. The driving transistor DTFT is turned on, and the first power signal VDD charges the source of the driving transistor DTFT via the fourteenth transistor M14 and the driving transistor DTFT. The potential of the source of the driving transistor DTFT gradually rises until the driving transistor DTFT is turned off, completing the threshold compensation of the driving transistor DTFT. At this point, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the driving transistor DTFT.

[0117] During the data writing phase T3, upon entering the data writing phase, the lock control signal Ssd is at a high level, and the third control signal Re3, the fourth control signal Re4, and the fourth light-emitting control signal EM4 are all at low levels. The first transistor M1 is turned on, and the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned off. The data signal Vdata is transmitted to the first end of the first capacitor Cst1 via the first transistor M1. The potential of the first end of the first capacitor Cst1 changes from the third reset signal Vini2 to the data signal Vdata. The fourth capacitor Cst4 is connected to the first power supply signal VDD to control the potential jump across the first capacitor Cst1. The voltage drop across the first capacitor Cst1 is: (Vdata - Vini2)·(Cst4 + Coled) / (Cst4 + Vgs + Cst1 + Coled) + Vth1; where Cgs is the capacitance between the gate and source of the drive transistor DTFT, and Coled is the parasitic capacitance of the light-emitting device L. In this embodiment, the fourth capacitor Cst4 is mainly provided to provide a larger proportional factor, that is, to make (Cst4+Coled) / (Cst4+Vgs+Cst1+Coled) larger, so as to ensure the sensitivity of data voltage writing and reduce the variation range of the data voltage.

[0118] At signal lock time ts, the lock control signal Ssd drops to a low level, turning off the first transistor M1 and floating the first terminal of the first capacitor Cst1. The data signal source for the first capacitor Cst1 is cut off. At this point, the data signal Vdata maintains the data voltage Vb, so the potential difference across the first capacitor Cst1 is locked to: (Vb - Vini2) · (Cst4 + Coled) / (Cst4 + Vgs + Cst1 + Coled) + Vth1. In other words, the information about the row's data signal Vdata and the threshold voltage of the drive transistor DTFT are both stored in the first capacitor Cst1, completing the data write process.

[0119] During the light-emitting phase T4, the fourth light-emitting control signal EM4 is at a high level, while the lock control signal Ssd, the third control signal Re3, and the fourth control signal Re4 are all at low levels. The fourteenth transistor M14 is turned on, and the driver transistor DTFT generates a drive current to illuminate the light-emitting device L. The drive current is a function of Vgs-Vth1, where Vgs is equal to the potential difference across the first capacitor Cst1. Therefore, the drive current is actually a function of Vdata-Vini2, and its magnitude is independent of the threshold voltage Vth1 of the driver transistor DTFT.

[0120] The above embodiment exemplifies that the transistors in the pixel circuit are all composed of N-type transistors, but this is not intended to limit the present application. In other embodiments, some or all of the transistors can be replaced with P-type transistors as needed, and the potential of the control signal connected to the transistor can be adjusted accordingly.

[0121] In summary, the embodiments of the present application provide a novel data writing structure and related drive timing, which can be applied to various types of pixel circuits and can solve the problem of cross-data writing effects in the related art. During the data writing process in the related art, the data writing path needs to pass through the channel of the driving transistor. Therefore, during the data writing phase of the pixel circuit of the row, the data signal must maintain the data voltage required by the row. During the data writing process, the data voltage of the adjacent row is not allowed to enter the row to avoid the situation where the data voltage of the previous row is written and the data voltage of the row cannot be written because the transistor cannot be turned on, or the data voltage of the next row can turn on the transistor again, resulting in erroneous writing. Therefore, the conduction pulse width of the scanning signal cannot exceed the row time. In addition, the data writing process must at least maintain the time for the gate of the transistor to be charged from the initial potential to the sum of the data voltage and the threshold voltage of the driving transistor and then turned off, which limits the speed of data writing in the pixel circuit. As users' requirements for the display quality and functions of display panels become increasingly higher, the row time is continuously shortened. A short row time will cause the data writing phase to end prematurely, the data voltage cannot be fully written to the gate of the transistor, and the data writing effect cannot be guaranteed. Moreover, due to process limitations and the influence of parasitic capacitance, it is difficult for the scanning circuit to generate a scanning signal with a too narrow on-pulse. When the line time is short, it is difficult for the scanning circuit to provide a stable scanning signal, which further affects the data writing effect.

[0122] The data writing structure provided in the embodiment of the present application utilizes the potential jump edge of the locking control signal to sample the data signal, and the sampling time is extremely short and fast when writing data. At the same time, the conduction pulse width of the scanning signal is allowed to be greater than the line time. Even in a high refresh frequency scenario, there is no need to provide a scanning signal with a pulse width that is too narrow, which brings convenience to the design of pixel circuits and scanning circuits in high refresh frequency scenarios. In addition, the pixel circuit using this data writing structure can realize the separation of the threshold compensation stage and the data writing stage, so that the threshold compensation time can be lengthened without being restricted by the line time to achieve a better compensation effect, thereby improving display uniformity, and allowing the threshold compensation stages of pixel circuits in different rows to overlap in time. The increase in the threshold compensation time does not affect the refresh frequency of the display panel. Therefore, the pixel circuit provided in the embodiment of the present application can improve the data writing effect and the threshold compensation effect of the pixel circuit, and can take into account the realization of high resolution and high refresh frequency of the display panel.

[0123] The present application also provides a method for driving a pixel circuit, which is used to drive the pixel circuit provided by any embodiment of the present application, and has corresponding effects. The driving method may include: a data writing phase and a light emitting phase; wherein the data writing phase includes a signal locking moment. Exemplarily, the driving method includes:

[0124] In the data writing phase, before the signal locking moment, the locking control signal controls the locking control module to be turned on, so that the potential difference across the first storage module changes with the change of the data signal.

[0125] At the signal locking moment, the locking control signal undergoes a potential jump, controlling the locking control module to be turned off, causing the potential of the control end of the driving module to float, and the first storage module stores a voltage associated with the data signal received at the signal locking moment.

[0126] In the light-emitting stage, the driving module generates a driving current according to the voltage stored by the first storage module at the signal locking moment, and drives the light-emitting device to emit light.

[0127] The driving method of the pixel circuit provided in the embodiment of the present application provides a new data writing method, so that the data writing path in the pixel circuit passes through the first storage module and the locking control module without passing through the driving module itself. Therefore, by controlling the locking control module to change from the on state to the off state at the signal locking moment, the data information at that moment can be locked, so that the first storage module can quickly and correctly store the voltage associated with the data signal connected at the signal locking moment. By setting the data writing phase to include the signal locking moment, and the signal locking moment is located within the row time when the data signal maintains the data voltage required by the pixel circuit of this row, a correct data writing process can be achieved. This embodiment has no limit on the maintenance time of the data writing phase. During the data writing process, the data voltage information of the adjacent rows is allowed to enter the pixel circuit of this row. Therefore, the conduction pulse width of the control signal related to the data writing process can be greater than the row time, which can effectively reduce the risk of poor scanning circuits for providing control signals, improve the stability of the control signal, and ensure the effect of data writing. Therefore, the embodiment of the present application can improve the data writing effect of the pixel circuit, thereby improving the display effect of the display panel.

[0128] In the embodiments of the pixel circuit, driving methods are described for different pixel circuits. These driving methods can all be considered as driving methods for the pixel circuit provided in the embodiments of the present application, and repeated content will not be repeated here.

[0129] The embodiment of the present application also provides a display panel, including the pixel circuit provided in any embodiment of the present application, and having the corresponding effect. Figure 14 is a structural schematic diagram of a display panel provided in an embodiment of the present application. Referring to Figure 14, illustratively, a plurality of pixel circuits 100 are arranged in an array in the display area AA of the display panel. The display panel also includes a scanning circuit 101 and a plurality of first scanning lines LS1, and the scanning circuit 101 is configured to provide a locking control signal to the pixel circuit 100 through the first scanning line LS1. In addition, the display panel also includes a driving chip 102 and a plurality of data lines Ld, and the driving chip 102 is configured to provide a data signal to the pixel circuit 100 through the data line Ld.

Claims

1. A pixel circuit, comprising: A driving module, configured to generate a driving current according to a potential difference between the control terminal and the first terminal of the driving module, so as to drive the light emitting device to emit light; a first storage module, wherein a first end of the first storage module is electrically connected to a control end of the driving module, and a second end of the first storage module is electrically connected to a first end of the driving module; A locking control module, wherein a control end of the locking control module is configured to receive a locking control signal, and a first end of the locking control module is electrically connected to the control end of the driving module; The second end of the first storage module or the second end of the locking control module is configured to receive a data signal; The locking control module is configured to float the potential of the control end of the driving module in response to the locking control signal being turned off at the signal locking moment, and the first storage module is configured to store a voltage associated with the data signal connected at the signal locking moment.

2. The pixel circuit according to claim 1, wherein: The first storage module comprises: a first capacitor, a first end of the first capacitor serving as a first end of the first storage module, and a second end of the first capacitor serving as a second end of the first storage module; The locking control module comprises: a first transistor; a gate of the first transistor serves as a control end of the locking control module, a first electrode of the first transistor serves as a first end of the locking control module, and a second electrode of the first transistor serves as a second end of the locking control module.

3. The pixel circuit according to claim 1, wherein: The second end of the first storage module is configured to access the data signal, and the second end of the locking control module is configured to connect to a first reference signal line; The pixel circuit further includes: A first data transmission module, configured to be turned on during a data writing phase, and to transmit the data signal to an output end of the first data transmission module; wherein the data writing phase includes the signal locking moment; The second storage module is connected between the output end of the first data transmission module and the second end of the first storage module, and is configured to couple the potential jump of the output end of the first data transmission module to the second end of the first storage module.

4. The pixel circuit according to claim 3, further comprising: A first reset module, electrically connected to the output end of the first data transmission module, configured to be turned on before the data writing phase, and to reset the second storage module using a first reset signal; A second reset module is electrically connected to the second end of the driving module and is configured to be turned on during the threshold compensation phase so that the first end of the driving module discharges through the driving module and the second reset module. so that the first storage module stores the threshold voltage of the driving module; wherein the threshold compensation stage is arranged before the data writing stage; The first light-emitting control module is connected in series with the driving module and the light-emitting device between the first power supply and the second power supply, and is configured to be turned on in the initialization stage and the light-emitting stage; wherein the initialization stage is set before the threshold compensation stage, and the light-emitting stage is set after the data writing stage.

5. The pixel circuit according to claim 1, wherein: The second end of the locking control module is configured to receive the data signal; The pixel circuit further includes: A second data transmission module, configured to be turned on during a data writing phase, and to transmit the data signal to an output end of the second data transmission module; wherein the data writing phase includes the signal locking moment; A third storage module, connected between the output end of the second data transmission module and the second end of the locking control module, configured to couple the potential jump of the output end of the second data transmission module to the second end of the locking control module; A reference signal transmission module is configured to transmit a second reference signal to the second end of the first storage module in response to the transmission control signal being turned on; wherein the reference signal transmission module is turned off at the same time as the locking control module or the reference signal transmission module is turned off later than the locking control module.

6. The pixel circuit according to claim 5, wherein: The locking control signal is multiplexed into the transmission control signal.

7. The pixel circuit according to claim 5, further comprising: a third reset module, electrically connected to the output end of the second data transmission module, and configured to use a second reset signal to reset the third storage module before the data writing phase; A second light-emitting control module is connected between the first power source and the second end of the driving module and is configured to be turned on in a light-emitting phase; wherein the light-emitting phase is configured after the data writing phase; A third light emitting control module, connected between the first end of the driving module and the anode of the light emitting device, and configured to be turned on before the data writing phase and during the light emitting phase; The second end of the first storage module is directly electrically connected to the first end of the driving module, or is electrically connected to the first end of the driving module through the third light emitting control module. 8 . The pixel circuit according to claim 7 , wherein a control end of the third reset module and a control end of the third light emitting control module are connected to the same control signal line.

9. The pixel circuit according to claim 1, wherein: The second end of the locking control module is configured to receive the data signal; The pixel circuit further includes: A fourth storage module, wherein a first end of the fourth storage module is electrically connected to a second end of the first storage module, and a second end of the fourth storage module is connected to a first power supply.

10. The pixel circuit according to claim 9, further comprising: a fourth reset module, electrically connected to the second end of the first storage module, configured to be turned on in an initialization phase and turned off in a threshold compensation phase; wherein the threshold compensation phase is set before the data writing phase, the initialization phase is set before the threshold compensation phase, and the data writing phase includes the signal locking moment; A fifth reset module, electrically connected to the first end of the first storage module, configured to be turned on before the data writing phase, and to transmit a third reset signal to the first end of the first storage module; The fourth light-emitting control module is connected between the first power supply and the second end of the driving module, and is configured to be turned on before the data writing stage and during the light-emitting stage; wherein the light-emitting stage is configured after the data writing stage.

11. The pixel circuit according to claim 3, wherein: The first data transmission module comprises: a second transistor, a gate of the second transistor is configured to be connected to a first scan line, a first electrode of the second transistor is configured to be connected to a data line, and a second electrode of the second transistor serves as an output end of the first data transmission module; The second storage module includes: a second capacitor, a first end of the second capacitor is electrically connected to the output end of the first data transmission module, and a second end of the second capacitor is electrically connected to the second end of the first storage module.

12. The pixel circuit according to claim 5, wherein: The second data transmission module comprises: a third transistor, a gate of the third transistor is configured to be connected to the second scan line, a first electrode of the third transistor is configured to be connected to the data line, and a second electrode of the third transistor serves as an output end of the second data transmission module; The third storage module comprises: a third capacitor, a first end of the third capacitor is electrically connected to the output end of the second data transmission module, and a second end of the third capacitor is electrically connected to the second end of the locking control module; The reference signal transmission module includes: a fourth transistor, a gate of the fourth transistor is configured to be connected to a transmission control signal line, a first electrode of the fourth transistor is connected to a second reference signal line, and a second electrode of the fourth transistor is connected to a second end of the first storage module.

13. The pixel circuit according to claim 7, wherein: The fourth storage module includes: a fourth capacitor, a first end of the fourth capacitor serves as the first end of the fourth storage module, and a second end of the fourth capacitor serves as the second end of the fourth storage module.

14. A display panel, comprising: The pixel circuit according to any one of claims 1 to 13.

15. A method for driving a pixel circuit, used for driving the pixel circuit according to any one of claims 1 to 13; The driving method comprises: a data writing stage and a light emitting stage; wherein the data writing stage comprises a signal locking moment; In the data writing phase, before the signal locking moment, the locking control signal controls the locking control module to be turned on, so that the potential difference across the first storage module changes with the change of the data signal; At the signal locking moment, the locking control signal performs a potential jump, controls the locking control module to be turned off, and makes the potential of the control end of the driving module float, and the first storage module stores the voltage associated with the data signal connected at the signal locking moment; In the light-emitting stage, the driving module generates a driving current according to the voltage stored by the first storage module at the signal locking moment, and drives the light-emitting device to emit light.

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