Interpolation layer for backside power delivery network

Abstract

In some embodiments, a structure includes an active element having a front side and a back side opposite the front side, the active element having active circuitry closer to the front side than the back side; and a power redistribution element having a front side hybrid bonded to the back side of the active element, the power redistribution element including a first plurality of contact pads on the front side of the power redistribution element and a second plurality of contact pads on the back side of the power redistribution element opposite the front side of the power redistribution element, a pitch of the first plurality of contact pads is less than a pitch of the second plurality of contact pads, and a power redistribution element configured to provide at least one of power and ground to the active element.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 493,627, filed March 31, 2023, entitled “Interposer for Backside Power Delivery Network,” the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0002] This disclosure relates to semiconductor device structures and methods. In particular, some embodiments relate to methods and structures for providing back-side power delivery. Background Technology

[0003] The methods described in this section are feasible, but not necessarily methods that have been previously conceived or implemented. Therefore, unless otherwise indicated, no method described in this section should be assumed to qualify as prior art solely by virtue of its inclusion in this section.

[0004] As features in semiconductor devices continue to shrink, the issue of power delivery is receiving increasing attention. Problems such as electrical isolation, feature size limitations due to the high density of circuit elements and interconnects, and losses due to the large number of metal layers make it difficult to efficiently deliver power to semiconductor devices. Attached Figure Description

[0005] These and other features, aspects, and advantages of this disclosure have been described with reference to the accompanying drawings of certain embodiments, which are intended to illustrate and not limit the disclosure. It should be understood that the drawings, which are incorporated in and constitute a part of this specification, are for illustrative purposes only and may not be to scale.

[0006] Figure 1A The illustration shows an example embodiment of a device structure that can provide power to the back side of an integrated device die.

[0007] Figure 1B An example embodiment of a power delivery die with a redistribution layer is illustrated.

[0008] Figure 2 An example embodiment of a power delivery die with a redistribution layer and contact pads is illustrated.

[0009] Figure 3 An example embodiment of a stacked structure is illustrated, in which the power delivery die interfaces with components via an interpolation layer.

[0010] Figure 4 The illustration shows a top view of an example embodiment of the contact pad layout for an interpolation layer.

[0011] Figures 5A-5C Various example patterns of contact pads for interpolation layers are illustrated according to some embodiments.

[0012] Figure 6 An example embodiment of a power delivery die with a separated voltage plane is illustrated.

[0013] Figure 7A and Figure 7B The illustration shows an example embodiment of a power delivery die having more than one power line or ground line in the same plane.

[0014] Figure 8A and Figure 8B An example embodiment of a stacked structure including passive components is illustrated.

[0015] Figure 9A and Figure 9B An example embodiment of a power delivery die is illustrated.

[0016] Figure 10A and Figure 10B The direct joining process according to some embodiments is illustrated schematically. Summary of the Invention

[0017] The systems, methods, and apparatuses described herein each have several aspects, and each individual aspect is not solely responsible for its desired properties. Without limiting the scope of this disclosure, several non-limiting features will now be briefly described.

[0018] In one embodiment, the technology described herein relates to a structure comprising: an active element including: a front side and a back side opposite to the front side; a plurality of vias extending vertically from the back side through a portion of the active element; and an active region closer to the front side than the back side; a power redistribution element disposed on the back side of the active element, the power redistribution element including: a front side and a back side opposite to the front side; a first plurality of contact pads disposed on the front side; and a second plurality of contact pads disposed on the back side, wherein the pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads, wherein the first plurality of contact pads are electrically coupled to the plurality of vias.

[0019] In some aspects, the technology described herein relates to a structure that also includes a power delivery die comprising a front side and a back side opposite the front side, wherein the front side is electrically connected to a second plurality of contact pads of a power redistribution element.

[0020] In some aspects, the techniques described herein relate to a structure in which a power redistribution element is configured to carry power and ground, and is not configured to carry logic signals.

[0021] In some aspects, the techniques described herein relate to a structure in which the power redistribution element includes an interpolation layer.

[0022] In some aspects, the technology described herein relates to a structure in which the power redistribution element further includes a hybrid bonding layer disposed on the front side of the power redistribution element.

[0023] In some aspects, the technology described herein relates to a structure in which the power redistribution element further includes a hybrid bonding layer disposed on the back side of the power redistribution element.

[0024] In some aspects, the techniques described herein relate to a structure in which a power redistribution element is at least partially deposited on the back side of an active element.

[0025] In some aspects, the techniques described herein relate to a structure in which, after the active element is thinned, a power redistribution element is at least partially deposited on the back side of the active element.

[0026] In some aspects, the technology described herein relates to a structure in which the front side of a power delivery die is hybridly bonded to the back side of a power redistribution element.

[0027] In some aspects, the technology described herein relates to a structure in which the front side of a power delivery die is hybridly bonded to the back side of a power redistribution element, and wherein the front side of the power redistribution element is hybridly bonded to the back side of an active element.

[0028] In some aspects, the technology described herein relates to a structure that also includes passive elements disposed between the power delivery die and the power redistribution element.

[0029] In some aspects, the techniques described herein relate to a structure in which power is delivered through a power redistribution element to the back side of an active element.

[0030] In one embodiment, the technology described herein relates to a structure comprising: an active element having a front side and a back side opposite the front side, the active element having active circuitry arrangements closer to the front side than the back side; and a power redistribution element having a front side co-attached to the back side of the active element, the power redistribution element including a first plurality of contact pads on the front side of the power redistribution element and a second plurality of contact pads on the back side of the power redistribution element opposite the front side of the power redistribution element, wherein the pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads, and wherein the power redistribution element is configured to provide at least one of power and ground to the active element.

[0031] In some aspects, the technology described herein relates to a structure in which an active element includes a via extending from the back side of the active element to the active circuit device.

[0032] In some aspects, the technology described herein relates to a structure that further includes: a power delivery die having a front side and a back side opposite the front side, wherein the front side of the power delivery die is hybridly coupled to the back side of a power redistribution element.

[0033] In some aspects, the techniques described herein relate to a structure in which at least one of power and ground is carried through a power redistribution element and delivered to the back side of an active element.

[0034] In one embodiment, the technology described herein relates to an interpolation layer comprising: a front surface; a back surface opposite to the front surface; a redistribution layer; a first plurality of contact pads disposed on the front surface of the interpolation layer; and a second plurality of contact pads disposed on the back surface of the interpolation layer, wherein the first plurality of contact pads have a first pitch smaller than a second pitch of the second plurality of contact pads, wherein the first plurality of contact pads are configured to be electrically connected to vias on the back side of an active element, wherein the second plurality of contact pads are configured to be electrically connected to contact pads on a power delivery die, and wherein at least one of the front surface and the back surface comprises a hybrid bonding layer.

[0035] In some aspects, the techniques described herein relate to an interpolation layer in which a first pitch ranges from about 50 nm to about 1000 nm, and a second pitch ranges from about 1 μm to about 500 μm.

[0036] In some aspects, the techniques described herein relate to an interpolation layer having a thickness ranging from about 1 μm to about 50 μm.

[0037] In some respects, the techniques described herein involve an interpolation layer in which a second plurality of contact pads are arranged in a periodic pattern.

[0038] In some aspects, the techniques described herein relate to an interpolation layer in which the front surface includes a hybrid bonding layer.

[0039] In some aspects, the techniques described herein relate to an interpolation layer in which the back side surface includes a hybrid bonding layer.

[0040] In some aspects, the techniques described herein relate to an interpolation layer comprising multiple layers, each configured to carry a single voltage or ground, wherein each layer is separated from the other layers of the multiple layers by a dielectric material.

[0041] In some aspects, the technology described herein relates to an interpolation layer configured to transport power from a power delivery die at a back surface of the interpolation layer to a front surface of the interpolation layer, the front surface of which is electrically connected to a via on the back side of an active element.

[0042] In another embodiment, the technology described herein relates to a method comprising: forming a first interpolation layer including: a first front side; a first back side opposite to the first front side; a first front contact disposed on the first front side, the first front contact being arranged in the first front side arrangement and configured to be electrically connected to a via on the back side of a first active element; and a first back contact disposed on the first back side, the first back contact being arranged in the first back side pattern and configured to be electrically connected to a first power delivery die; and forming a first... The second intercalation layer includes: a second front side; a second back side opposite to the second front side; a second front side contact disposed on the second front side, the second front side contact being arranged in a second front side arrangement and configured to be electrically connected to a via on the back side of a second active element; and a second back side contact disposed on the second back side, the second back side contact being arranged in a second back side pattern and configured to be electrically connected to a second power delivery die, wherein the first front side arrangement is different from the second front side arrangement, and wherein the first back side pattern is the same as the second back side pattern.

[0043] In some aspects, the technology described herein relates to a method in which the first intercalation layer further includes a first front-side hybrid engagement surface disposed on the first front side.

[0044] In some aspects, the technology described herein relates to a method in which the first intercalation layer further includes a first back-side hybrid bonding surface disposed on the first back side.

[0045] In some aspects, the technology described herein relates to a method in which the pitch of a first back-side pattern and a second back-side pattern is greater than the pitch of a first front-side arrangement and a second front-side arrangement.

[0046] In some aspects, the techniques described herein relate to a method in which the pitch of a first front-side arrangement is from about 100 nm to about 500 nm, the pitch of a second front-side arrangement is from about 100 nm to about 500 nm, and the pitch of a first back-side pattern and a second back-side pattern is from about 20 μm to about 500 μm.

[0047] In some aspects, the technology described herein relates to a method in which a first interpolation layer is configured to deliver first power from a first power delivery die to a first back side of a first active element, and a second interpolation layer is configured to deliver second power from a second power delivery die to a second back side of a second active element.

[0048] In another embodiment, the technology described herein relates to a method comprising: forming a first interpolation layer including: a first front side; a first back side opposite to the first front side; a first front contact disposed on the first front side, the first front contact being arranged in a first front side arrangement and configured to be electrically connected to a via on the back side of a first active element; and a first back contact disposed on the first back side, the first back contact being arranged in a first back side pattern and configured to be electrically connected to a first power delivery die.

[0049] In some aspects, the technology described herein relates to a method in which the first intercalation layer further includes a first front-side hybrid engagement surface disposed on the first front side.

[0050] In some aspects, the technology described herein relates to a method in which the first intercalation layer further includes a first back-side hybrid bonding surface disposed on the first back side.

[0051] In some aspects, the techniques described herein relate to a method in which a first interpolation layer is configured to deliver first power from a first power delivery die to a first back side of a first active element.

[0052] In some aspects, the technology described herein relates to a method comprising: forming a second intercalation layer including: a second front side; a second back side opposite to the second front side; a second front side contact disposed on the second front side, the second front side contact being arranged in a second front side arrangement and configured to be electrically connected to a via on the back side of a second active element; and a second back side contact disposed on the second back side, the second back side contact being arranged in a second back side pattern and configured to be electrically connected to a second power delivery die.

[0053] In some aspects, the technology described herein relates to a method in which a first front arrangement differs from a second front arrangement.

[0054] In some aspects, the techniques described herein relate to a method in which a first back-side pattern is identical to a second back-side pattern.

[0055] In some aspects, the technology described herein relates to a method in which the pitch of a first back-side pattern and a second back-side pattern is greater than the pitch of a first front-side arrangement and a second front-side arrangement.

[0056] In some aspects, the techniques described herein relate to a method in which the pitch of a first front-side arrangement is from about 100 nm to about 500 nm, the pitch of a second front-side arrangement is from about 100 nm to about 500 nm, and the pitch of a first back-side pattern and a second back-side pattern is from about 20 μm to about 500 μm.

[0057] This disclosure also discloses and contemplates various combinations of the features, embodiments, and aspects described above and below.

[0058] Additional embodiments of this disclosure are described below with reference to the appended claims, which can serve as an additional summary of this disclosure. Detailed Implementation

[0059] Although several embodiments, examples, and descriptions are disclosed below, those skilled in the art will understand that the disclosure described herein extends beyond the specific disclosed embodiments, examples, and descriptions, and includes other uses of the disclosure and its obvious modifications and equivalents. Embodiments are described with reference to the accompanying drawings, wherein the same reference numerals always refer to the same elements. The terminology used in the description presented herein is not intended to be interpreted in any limiting or restrictive manner, but is used only in conjunction with the detailed description of some specific embodiments of the disclosure. Furthermore, embodiments may include several novel features. No single feature is solely responsible for its desired properties or is necessary for practicing the disclosure described herein.

[0060] Back-side power delivery can alleviate problems associated with increasing density and reducing feature size by decoupling power delivery from signal routing. However, implementing back-side power delivery can be challenging. Some embodiments described herein can make back-side power delivery easier and / or cheaper to deploy.

[0061] In traditional semiconductor devices, both signal transmission and power delivery occur through the front side of the device. However, as device features continue to shrink, it becomes increasingly difficult to deliver both power and signals through the front side of the device without compromising device performance. For example, as semiconductor devices become denser and more complex, with each new advanced process node increasing the number of transistors and computing units per unit area, the number of metal layers, including those feeding signal lines and power (or ground) lines to these transistors, also tends to increase, effectively increasing the path length of the power-carrying wires. This increased density of transistors in the active device region can lead to a corresponding increase in the density of power and signal circuitry. To accommodate this increased density, the cross-sectional area of ​​vias and other circuitry can be reduced. However, this can result in higher impedance and increased power losses. For example, reducing the cross-sectional area and increasing the length of power lines can lead to significant power losses due to the high resistance of the thin copper typically used for front-side power delivery. For instance, a device can be designed to accommodate approximately 10% power delivery losses (e.g., voltage drops) from the power supply during transmission through the metal layers to the active device region. However, significantly larger reductions are likely to be seen at smaller or more advanced manufacturing nodes, especially when there are a large number of metal layers (e.g., approximately 10, 15, 20, or even more). In some processes, metal interconnects can include alternative materials such as cobalt, which can reduce power loss, for example, at lower back-end line (BEOL) levels. However, the benefits of using other conductive materials are limited, and as semiconductor device features continue to shrink, different approaches are needed to address power and signal delivery barriers. Furthermore, power lines occupy a significant amount of physical area on the front side of the device. This may mean that semiconductor devices can be significantly larger in area to allow sufficient space for power and signal transmission lines to coexist on the front side of the device.

[0062] Back-side power delivery can mitigate some of the problems associated with scaling semiconductor devices to smaller process nodes. For example, back-side power delivery can alleviate congestion on the front side by eliminating or reducing the need for routing power via the front side. Back-side power delivery enables wider and thicker power delivery and / or signal transmission lines. Back-side power delivery can reduce the electrical path length between the power supply and the active device area. Such lines can have lower impedance, which can reduce power loss and / or improve signal integrity. Additionally, even without increasing the cross-sectional area of ​​the lines, back-side power delivery can improve signal integrity because, for example, the power delivery can be relatively far from the signal transmission lines, which can reduce the likelihood of electromagnetic interference from power delivery to signal transmission.

[0063] In addition to reduced losses and improved signal integrity, back-side power delivery can be used as a tool to enable designers to create more compact devices. As briefly mentioned above, when both power and signal are on the same side of the device, the semiconductor device may be larger than the additional semiconductor device required for the active device area. This design decision can play an increasingly important role in scaling as the benefits of moving to smaller, more advanced technology nodes provide a return on investment.

[0064] Figure 1A An example of providing power to the back side of an active component, such as an integrated device die, is schematically illustrated. Figure 1A In this embodiment, active element 101 may include a logic and signal stack 102 disposed near the front side 152 of active element 101. The logic and signal stack may include transistors, signal routing circuitry, and other components, including active devices, device units and circuits, or electronic components for processing, storing, or transmitting signals. Active element 101 may include a rear body portion 103 including a via 104 for delivering power to the active components of the logic and signal stack 102 via the back side 150 of active element 101. The via 104 may have electrical contacts with the logic and signal stack 102. In some embodiments, the via 104 may also be an embedded power rail, a nano TSV, a power TSV, a back-side contact to the source and drain, etc. A power delivery structure 170 having a power delivery die 105 may be joined (e.g., hybrid joined, as discussed in more detail herein) to the rear surface 150 of active element 101 via a joining interface 106. Active circuit devices (such as transistors) can be positioned closer to the front surface 152 than the rear surface 150.

[0065] Via 104 may be a blind via (e.g., a via that does not fully extend through the active element 101). In some embodiments, via 104 may include nanovias that are directly connected to transistors on the front side of the logic and signal stack 102, although in some embodiments, the via may not be directly connected to the transistors. In some embodiments, via 104 may be electrically connected to one or more metal layers (or signal layers) on the front side of the device to efficiently deliver power from the front side to the transistors. In some embodiments, via 104 may deliver power to the sides or back of the logic and signal stack 102 (e.g., to the transistors on the logic and signal stack 102). In some embodiments, the power delivery structure or via 104 can provide power from the front side of the transistor or device to the transistor or device cell (e.g., via buried power rails, plugs, etc., contacts from the front to the drain and source), from the side of the transistor or device cell (e.g., using buried power rails, power vias, nano TSVs, etc., electrical contacts to the source and drain regions), or from the back side via direct contact to the source / drain regions (e.g., back-side contacts or BSC). The via may include one or more conductive materials, such as, for example, polysilicon (which may have mechanical properties similar to a silicon substrate), cobalt, ruthenium, and / or tungsten. In some embodiments, vias may be formed relatively early during the semiconductor device fabrication process, prior to the completion of the front-end process. Therefore, in some embodiments, the use of copper and / or nickel may be preferably avoided, as copper and / or nickel can diffuse into the surrounding material and cause malfunctions or failures. Additionally, the relatively low melting point of copper may be problematic when high-temperature annealing and other high-temperature processing steps are performed to fabricate high-quality, advanced-node transistors. In some embodiments, vias can be formed after the front-end process is completed. In some embodiments, active components can be thinned to expose the formed vias before the front-end process is completed. In some embodiments, a "drilling and filling" method can be used. For example, holes can be formed after the active component is thinned, and these holes can be filled (e.g., via deposition) with a conductive material after the front-end process is completed.

[0066] like Figure 1BAs shown, the power delivery die 105 may include a redistribution layer 107. The redistribution layer 107 can be configured to distribute power and ground from the power delivery die 105 to the active element 101 via vias 104. However, implementing such a power delivery die can be challenging. For example, the pitch between vias 104 can be less than about 1 μm, for example, from about 20 nm to about 1000 nm, or in the range of about 20 nm to 100 nm, or about 50 nm to about 1000 nm, or about 100 nm to about 1000 nm, or from about 100 nm to about 500 nm. While direct bonding (e.g., hybrid bonding) can be used, alignment challenges can be significant. Furthermore, this approach presents design, manufacturing, and storage complexities for manufacturers of power delivery dies. Different components typically do not share a common layout for power vias. For example, the via layout can vary depending on the number of required voltages, the layout of transistors in logic and signal stacks, functional block layouts, etc. Therefore, if the redistribution layer is built into the power delivery die and interfaces directly with the components (e.g., directly with the power delivery vias of the components), different power delivery dies will need to be designed, manufactured, and stored for each different layout of the vias of different components, which adds design costs and creates logistical obstacles.

[0067] Therefore, it is advantageous to have a universal interpolation layer between the active element 101 and the power delivery die 105. The universal interpolation layer can have a standardized layout on one side for interfacing with the power delivery die 105, while the other side can be customized for each different type of active element 101. The manufacturer of the power delivery die can design a die that interfaces with the standardized layout of the interpolation layer, thus avoiding the need to customize the power delivery die for each type of element. It should be understood that some limited customization can still be performed. For example, depending on the size of the element, the power delivery die can be made larger or smaller (e.g., with more or fewer contacts). This customization can be relatively simple because, in some embodiments, the standardized layout can include a repeating pattern that can be easily expanded or shrunk to fit a particular size element or to accommodate a particular number of electrical connections.

[0068] In some embodiments, the interpolation layer may include a deposited redistribution layer, a reconfiguration layer, etc. In some embodiments, the interpolation layer may include an active circuitry, a semiconductor device, or a transistor. In some embodiments, the interpolation layer may not include an active circuitry, a semiconductor device, or a transistor. The interpolation layer may have a smaller coverage area, a larger coverage area, or the same coverage area as a logic die or another element. In some embodiments, the interpolation layer may extend beyond the edge of a logic die or another element. In some embodiments, the interpolation layer may be a single layer. In some embodiments, the interpolation layer may include multiple layers. For example, in some embodiments, the interpolation layer may include one or more deposited redistribution layers and one or more bonding (e.g., hybrid bonding) layers. For example, it may be desirable to bond the first or first few layers on the back side of the element, where the relatively small pitch may make direct bonding difficult. Because the interpolation layer carries only a limited number of signals (e.g., power, ground, and possibly some low-speed signaling), redistribution can be fairly simple, and the interpolation layer can be made thin. For example, the interpolation layer may have a thickness from about 0.5 μm to about 5 μm, such as from about 1 μm to about 2 μm. In some embodiments, the interpolation layer may have a thickness of less than approximately 700 μm. In another embodiment, the interpolation layer may be one or more routing layers deposited on the back side of a thinned logic die on exposed nanovias, extending the pitch of the nanovias on one side of the stacked routing layers to an extended standard pitch on the other side.

[0069] In some embodiments, the power delivery die may be bonded (e.g., hybrid bonding) to the interpolation layer. In some embodiments, the power delivery die may be surface-mounted or soldered (e.g., using a flip-chip process) to the interpolation layer. In some embodiments, the power delivery die may be bonded to the interpolation layer using thermocompression bonding. In some embodiments, wire bonding or a pin grid array may be used to provide external power to the power die.

[0070] Figure 2 An example of a power delivery die 105 with a standardized contact pad layout is shown. Figure 2 As shown, the power delivery die 105 may include a redistribution layer 108 and contact pads 109a-c. It is connected to vias 104 designed for electrical connection to active components 101. Figure 1B Unlike redistribution layer 107, redistribution layer 108 can be used to route power and ground signals to contact pads 109a-c with known patterns for electrical connection to the interpolation layer. For example, in Figure 2In the example embodiment, contact pads 109a-c include multiple (e.g., three) pads of different types. For example, the first pad 109a can provide ground, the second pad 109b can provide a first power supply voltage, and the third pad 109c can provide a second power supply voltage different from the first power supply voltage. It should be understood that this arrangement is only an example, and different arrangements can be used depending on the number of voltages to be provided and the layout of the active components 101.

[0071] Figure 3 An example embodiment of a stacked structure is illustrated, wherein a power delivery structure 170 interfaces with an active element 101 via an interpolation layer 110. In some embodiments, power can be delivered to the power delivery structure 170 from outside the stacked structure (e.g., via wiring connections, etc.) and can traverse the circuitry of the power delivery structure 170. In some embodiments, the power delivery structure 170 can modify voltage amplitude, frequency, clock signal, timing of power delivery, etc. In some embodiments, the power delivery structure 170 may include a power delivery die 105. In some embodiments, the power delivery structure 170 may additionally or alternatively include other structures, such as an integrated voltage regulator, and / or any other suitable active, passive, or dummy device.

[0072] The power delivery die 105 may have circuitry (e.g., transistors) to control power and the distribution to the active element 101. In some embodiments, the power delivery die 105 may include passive elements such as resistors, capacitors, inductors, etc. The contact pads 109a-c of the power delivery die 105 make electrical contacts with the contact pads 111a-c of the interpolation layer 110 at a bonding interface 113. The contact pads 142a-c make electrical contacts with the logic and signal stack 102 at a bonding interface 114. The contact pads 142a-c may have a first pitch p1 (e.g., the contact pads 142a-c of the interpolation layer 110 may have a minimum first pitch corresponding to the minimum pitch of the pads in the interpolation layer 110), and the contact pads 111a-c may have a second pitch p2. Pitch p1 may be smaller than pitch p2. In some embodiments, contact pads 142a-c may have a first width w1, and contact pads 111a-c may have a second width w2. Since ground pads do not carry current, in some embodiments they may be smaller than other pads (e.g., smaller width, diameter, etc.), while voltage and power delivery pads may be larger (e.g., larger width, diameter, etc.). Via 104 may have a pitch from about 50 nm to about 1000 nm, for example, from about 100 nm to about 500 nm. Pitch p1 may be similar to or the same as the pitch of via 104 (e.g., from about 50 nm to about 1000 nm), or may range from about 10 nm to about 5000 nm. Pitch p2 may be from about 0.2 μm to about 50 μm, about 1 μm to about 500 μm, or about 20 μm to about 500 μm, for example, from about 20 μm to about 100 μm. The intercalation layer 110 can be a thin structure that enables fan-out from fine vias to rough pads (e.g., contact pads 111a-c). Although contact pads 142a-c are... Figure 3 The arrangement is depicted in a regular repeating pattern, but it should be understood that such arrangement is not required. The contact pads 142a-c can be arranged according to the layout of the vias 104 of the active element 101, and they may or may not be arranged in a regular pattern.

[0073] In some embodiments, interpolation layer 110 (e.g., a power redistribution element) redistributes power. In some embodiments, interpolation layer 110 may redistribute signals (e.g., logic signals) in addition to power and / or ground signals. Signals received from power delivery die 105 by interpolation layer 110 via contact pads 111a-c can then be redistributed in redistribution layer 112 of interpolation layer 110. Redistribution layer 112 may be configured to provide power and ground signals to via 104 of active element 101. Interpolation layer 110 may be electrically communicated (e.g., electrically coupled) with via 104 of back face portion 103 of active element 101 at bonding interface 114. Power delivery die 105 may be bonded (e.g., hybrid bonded) to interpolation layer 110 via bonding interface 113. In some embodiments, redistribution layer 112 may be deposited on via 104 to form interpolation layer.

[0074] In some embodiments, the interpolation layer 110 may be bonded (e.g., direct bonding or hybrid bonding) to the back side of the active element 101. The interpolation layer 110 may be any power distribution element (e.g., a power redistribution element), which may be a separate element (e.g., a separate interpolation layer that may be bonded to the active element 101), or may be partially or entirely deposited on the back side of the active element 101. For example, in other embodiments, the interpolation layer 110 may be formed on the back side of the active element 101, for example using photolithography, deposition, etching, polishing, and other processes known to those skilled in the art. As briefly mentioned above, although in Figure 3 Interpolation layer 110 is shown as a single unit, but in some embodiments, interpolation layer 110 may include multiple layers or multiple sub-units, some of which may be deposited (e.g., one or more layers closest to the back side of active element 101), and other layers or sub-units may be directly bonded (e.g., hybrid bonding (e.g., one or more layers closest to power delivery die 105)).

[0075] Figure 4 The diagram shows a top view of the pad layout used for interpolation layers. (See diagram for example.) Figure 4As shown, contact pads 111a-c can be distributed in a regular pattern around the interpolation layer. For example, as discussed above, contact pad 111a can provide a first voltage (or ground), contact pad 111b can provide a second voltage (or ground), and contact pad 111c can provide a third voltage (or ground). In some embodiments, there may be more or fewer types of contact pads. For example, some embodiments may include two types of contact pads (e.g., one set of pads for providing ground and another set for providing power supply voltage). In some embodiments, larger contact pads 115a-c may be distributed around contact pads 111a-c, although in some embodiments, larger contact pads 115a-c may not be present. It should be understood that... Figure 4 For illustrative purposes only. In actual equipment, there may be more... Figure 4 More pads are shown in the diagram.

[0076] Figures 5A-5C Various example patterns of contact pads for interpolation layers according to some embodiments are illustrated. Figure 5A In the example, contact pads 111a-c are arranged in a horizontally and vertically repeating pattern, with each row offset by one position from the previous row. For example, in the second row starting from the top, the first contact pad on the left corresponds to the second contact pad in the first row starting from the top. This arrangement can help ensure that the distance between the contact pads and the vias that provide a specific power supply voltage (or ground) to the pads is relatively short, regardless of where the vias are on the component. For example, in Figure 5A The diagram illustrates three voltages (or ground), with each pad having the nearest neighbor that includes the other voltages (or ground). This design can be desirable for general interpolation layers used with components having arbitrary via layouts. However, this design may be suboptimal for specific component layouts. For example, in the case of components using FinFETs or Gate All-Around FETs (GAA FETs) (e.g., nanosheet GAA FETs and / or nanowire GAA FETs), the components of the component (e.g., FinFETs) are typically arranged in rows. Therefore, as... Figure 5B A depicted structure can be advantageous. For example, the contact pads 111a-c can be arranged in rows that are typically aligned with the FINFETs of the component. In some embodiments, each row can provide a specific supply voltage (or ground). This arrangement can, for example, simplify the redistribution layer, reduce the path length that power (or a specific voltage) must travel before reaching the transistor of the component (thus reducing power loss), and so on.

[0077] Figure 5C Another example pattern for a contact pad is illustrated according to some embodiments. Figure 5CIn this configuration, contact pads are clustered. For example, a first region may include contact pads of a first type (e.g., providing a first voltage or ground), and a second region may provide contact pads of a second type (e.g., providing a second voltage or ground). Within a given region, there may be more than one type of contact pad. For example, a region may include contact pads for providing a power supply voltage and contact pads for grounding. This arrangement may be desirable when, for example, components are arranged into regions (e.g., regions for general computing tasks typically performed by a CPU, regions for graphics tasks, regions for communication, etc.) and said regions have different power requirements, such as requiring different power supply voltages. In some embodiments, the component may be a reconfigurable component comprising multiple sub-components, which may be manufactured according to different processes and / or may have different power requirements. Such as Figure 5C The layout depicted in the text can be particularly advantageous in such elements.

[0078] Power delivery dies with periodic or other standardized patterns for interfacing with intercalation layers can have various configurations. In some embodiments, a power delivery die may have separate power planes (also referred to herein as voltage planes). For example, in some embodiments, a power delivery die may have separate power planes for each voltage to be provided to a device. A power delivery die may also have one or more planes for providing ground. In some embodiments, each voltage may be on its own voltage plane. In some embodiments, a combination of one or more voltages may be provided on the same plane, which may also include ground. In some embodiments, a ground plane may be provided between two voltage planes, which may provide separation and shielding between the two voltage planes. A power delivery die may have standardized interfaces (e.g., standardized arrangement of contact pads) that can interface with a thin intercalation layer to electrical contacts of a device, such as a semiconductor die, which may have significantly smaller pitch contacts and may not have a standardized layout.

[0079] Figure 6 An example embodiment of a portion of a power delivery die 105 is illustrated, wherein a separate voltage plane is used and can provide a desired pattern of contact pads. (See illustration.) Figure 6As illustrated, the power delivery die 105 may have a first voltage / ground line 116a, a second voltage / ground line 116b, and a third voltage / ground line 116c, each voltage line being primarily disposed within its own horizontal plane. The first voltage / ground line 116a, the second voltage / ground line 116b, and the third voltage / ground line 116c may be embedded within dielectric layers 160a, 160b, 160c, and 160d, which may provide electrical isolation between the planes. Vertical lines extend toward the surface of the power delivery die. These vertically extending lines may extend to the surface of the power delivery die 105 to form a pattern of contact pads, which may be bonded (e.g., directly bonded or hybrid bonded) to an intercalation layer. For example, in some embodiments, the vertically extending lines may form patterns such as… Figures 5A-5B The patterns shown are examples of those. As discussed above, having a ground plane between voltage planes can be advantageous. Thus, for example, in some embodiments, a first voltage / ground line 116a may carry a power supply voltage, and a third voltage / ground line 116c may carry a second power supply voltage, while a second voltage / ground line 116b may provide ground.

[0080] although Figure 6 While such designs can offer many advantages, forming multiple layers can be expensive and challenging, especially when many different voltages need to be supplied. Therefore, as mentioned above, in some embodiments, one or more voltage and / or ground lines can be provided in the same plane. Figure 7A and Figure 7B An embodiment is shown in which multiple power / ground wires exist in the same plane. Figure 7A A top view of this power / ground wire distribution is shown, while Figure 7B A cross-section of this embodiment is shown.

[0081] Figure 7A The illustration shows a top view of a power delivery die 105 according to some embodiments. The power delivery die 105 may include power delivery (or ground) lines 118a, 118b, and 118c. Power delivery lines 118a-c may all be in a common plane. Contact pads 119a, 119b, and 119c may be exposed on the main surface of the power delivery die, such as... Figure 7B As shown. The contact pads 119a-c can be arranged in a periodic or other pattern, such as... Figures 5A-5C As shown. The redistribution layer 120 can be used to route power from power delivery lines 118a-c to contact pads 119a-c. Power delivery lines 118a-c and contact pads 119a-c can be disposed in a dielectric material 162, which can provide electrical isolation.

[0082] In some embodiments, the power delivery die may be a passive device. For example, the power delivery die may redistribute power without additional functionality. In some embodiments, the power delivery die may include additional circuitry including devices and transistors, such as buffer circuitry, to increase voltage uniformity across the die. In some embodiments, discrete passive components may provide buffer circuitry to enable more uniform power delivery. Passive components may include, for example, resistors, capacitors, inductors, etc.

[0083] Figure 8A An example embodiment including a discrete passive component 121 is illustrated. Figure 8A In this configuration, the power delivery die 105 can be bonded (e.g., direct or hybrid bonding) to a passive element 121 at a bonding interface 122. The passive element 121 may include first contact pads 123a-c that electrically contact the contact pads 109a-c of the power delivery die 105. The passive element 121 can be bonded (e.g., direct or hybrid bonding) to an intercalation layer 110 at a bonding interface 124. The passive element may include second contact pads 127a-c that electrically contact the contact pads 111a-c of the intercalation layer 110. The intercalation layer may have contact pads 142a-c with a smaller pitch than the contact pads 111a-c, as referenced above. Figure 3 As described. Passive components may include, for example, buffer circuitry that enables more uniform power delivery. Passive components may include one or more capacitors, resistors, inductors, integrated voltage regulators (IVRs), etc. In some embodiments, the pitch between the first contact pads 123a-c may be different from (e.g., greater than) the pitch between the second contact pads 127a-c. In some embodiments, the dimensions (e.g., width or diameter) of the first contact pads 123a-c may be different from (e.g., greater than) the dimensions (e.g., width or diameter) of the second contact pads 127a-c.

[0084] Figure 8B Another example embodiment including a discrete passive element 125 is illustrated. Figure 8B In this configuration, the power delivery die 105 can be bonded (e.g., direct or hybrid) to the intercalation layer 110 at the bonding interface 113. The intercalation layer 110 can be bonded (e.g., direct or hybrid) to the passive element 125 at the bonding interface 128. The passive element 125 can be bonded (e.g., direct or hybrid) to the active element 101 at the bonding interface 130. Figure 8BThe intercalation layer depicted may have contact pads 111a-c and contact pads 144a-c. Contact pads 111a-c may be electrically connected to contact pads 109a-c of the power delivery die 105. The intercalation layer 110 may have a second set of contact pads 144a-c, which may be electrically connected to passive element 125 via contact pads 146a-c. The pitch of contact pads 144a-c may be less than, greater than, or approximately equal to the pitch of contact pads 111a-c. Passive element 125 may include contact pads 148a-c electrically connected to vias 104 of active element 101. Contacts 148a-c may have a pitch matching the pitch of vias 104. The pitch of contacts 148a-c may be... Figure 3 The contact pads 142a-c shown in the diagram have the same pitch p1. Figure 8A and Figure 8B As illustrated, the position of the passive components can vary within the stack and, depending on the specific implementation, can be placed on either side of the interpolation layer. For example, in Figure 8A In the figure, passive element 121 is disposed between power delivery die 105 and intercalation layer 110, while Figure 8D illustrates passive element 123 disposed between intercalation layer 110 and active element 101 (e.g., semiconductor die).

[0085] Figure 9A and Figure 9B An example embodiment of a power delivery die is illustrated. Figure 9A and Figure 9B In this context, different voltages can operate orthogonally to each other in different planes. Figure 9A and Figure 9BIn this configuration, a first voltage (or ground) can be carried by power rail 132 and distributed via power line 134. A second voltage (or ground) can be provided in another plane using power rail 136 and power line 138. Power rail 132, power line 134, power rail 136, and power line 138 can be disposed in a dielectric 164, which provides electrical isolation. Power line 134 and power line 138 can be electrically connected to contact pad 140. Power line 134 and power line 138 can be oriented perpendicularly to each other, which can reduce capacitive coupling between lines with different voltages, thereby enabling a more uniform power distribution. In some embodiments, the power line can be connected to only one power rail (as shown in power line 134). However, other implementations are possible. For example, the power line can be connected to one power rail at a first end and to another power rail at the opposite end of the power line (as shown in power line 138). This configuration can improve the uniformity of power distribution across the component. In some embodiments, a separate ground plane may be positioned between two power (or voltage) planes. In some embodiments, the two power planes may be on the same side of the interface. In some embodiments, the power planes may be assigned to a reconfigurable logic wafer, a reconfigurable power wafer, etc. Although in Figure 9A and Figure 9B Two layers are depicted, but additional layers are considered. For example, in some embodiments, each plane may have a conductor with a power or ground wire orthogonally running to the nearest adjacent plane, and the number of planes is not limited. In some embodiments, the width and thickness of the power and ground wires may be the same or different.

[0086] While the examples above illustrate power dies that interface with components via interpolation layers, this disclosure is not strictly limited to power delivery. In some embodiments, a power die may include other components such as power control circuitry, memory (e.g., static random access memory, dynamic random access memory, etc.), additional logic, capacitor components (or integrated passive devices), integrated voltage regulators (IVRs), etc. In some embodiments, a power delivery die may include analog circuitry, which tends to be less sophisticated and may therefore be better suited for older, larger technology nodes. direct connection

[0087] The various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly bonded to each other without an intermediate adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "direct bonding" structures. Direct bonding can involve the bonding of one material on one element to one material on another element (also referred to herein as "uniform" direct bonding), where the materials on the different elements do not need to be identical without the use of conventional adhesive materials. Direct bonding can also involve the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0088] In some implementations (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. Example uniform direct bonding processes include ZIBOND, commercially available from Adeia of San Jose, CA. ® The materials of opposing bonding layers on different components can be the same or different, and can include elemental or compound materials. For example, in some embodiments, without patterning with conductive features (e.g., without pads), the non-conductive bonding layer can be a blanket deposited on a portion of the substrate. In other embodiments, bonding layers can be patterned on one or two components and can be the same or different from each other, but without adhesive, a material from each component is directly bonded to the surface of the component (or on the surface of the smaller component if the components are of different sizes). In another embodiment of uniform direct bonding, one or both layers of non-conductive bonding layers can include one or more conductive features, but the conductive features are not involved in the bonding. For example, in some embodiments, opposing non-conductive bonding layers can be uniformly and directly bonded to each other, and a through-substrate via (TSV) can be subsequently formed through one component after bonding to provide electrical communication with the other component.

[0089] In various embodiments, bonding layers 1008a and / or 1008b (see...) Figures 10A-10BThe dielectric material may include non-conductive materials such as dielectric materials, or undoped semiconductor materials such as undoped silicon, which may include natural oxides. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon such as silicon carbide, silicon oxycarbonitride, low-k dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials including diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic, although they may include carbon. In some embodiments, the dielectric material at the bonding surface does not include polymeric materials such as epoxy resins (e.g., epoxy adhesives, cured epoxy resins, or epoxy composites such as FR-4), resins, or molding materials.

[0090] In other embodiments, the bonding layer may include a conductive material, such as a deposited conductive oxide material, for example, indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entire contents of which are incorporated herein by reference in their entirety as an example of providing a conductive bonding layer without short contact points through the interface.

[0091] In direct bonding, the first and second elements can be directly bonded to each other without an adhesive, which differs from the deposition process and thus creates a structurally different interface compared to the interface produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Furthermore, unlike the interface beneath the deposited layer, the interface between direct bonded structures can include defect regions in which nanoscale voids (nanoves) exist. Nanovoids may form due to activation of one or both surfaces of the bonded surfaces (e.g., exposure to plasma, as explained below).

[0092] The bonding interface between non-conductive bonding surfaces can include a higher concentration of material from activation and / or final chemical processing compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen concentration peak can be formed at the bonding interface. In some embodiments, the nitrogen concentration peak can be detected using secondary ion mass spectrometry (SIMS). In various embodiments, for example, nitrogen end-capping treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace the OH groups of a hydrolyzed (OH-endoplated) surface with NH2 molecules to produce a nitrogen-endoped surface. In embodiments utilizing oxygen plasma for activation, an oxygen concentration peak can be formed at the bonding interface between non-conductive bonding surfaces. In some embodiments, the bonding interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding can include covalent bonds stronger than van der Waals bonds. The bonding layer can also include a polished surface planarized to a high degree of smoothness.

[0093] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two components are joined together without an intermediate adhesive. In indirect bonding processes utilizing adhesives, an intermediate material is typically applied to one or both components to achieve a physical bond between them. For example, in some adhesive-based processes, flowable adhesives (such as organic adhesives, such as epoxy resins), which may include conductive fillers, can be applied to one or both components and cured to form a physical (rather than chemical or covalent) bond between the components. Typical organic adhesives lack strong chemical or covalent bonds with either component. In such processes, the bond between components is weak and / or easily reversed, such as by reheating or desoldering.

[0094] Conversely, direct bonding processes combine two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in a direct bonding process between nonconductive materials, one or both nonconductive features of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) such that strong chemical bonds (e.g., covalent bonds) are formed when the elements are brought into the contact, and these bonds are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, such as between opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature when brought into the contact. In some embodiments, the chemical bonds between opposing nonconductive materials can be strengthened after annealing the elements.

[0095] As noted above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to each other, and conductive features are directly bonded to conductive features of the elements being bonded. The non-conductive bonding materials and interfaces can be as described above, while the conductive bonding can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of two elements, heated to melt the alloy, and cooled to form a connection between the two elements. The resulting bond typically exhibits a sharp interface with conductors from both elements, which is reversed by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require melting or intermediate fusible metal alloys and can generate strong mechanical and electrical connections, often demonstrating the interdiffusion of conductive features in the bond, where grains grow between the elements at the bonding interface, even at much higher temperatures and pressures than thermocompression bonding.

[0096] Figure 10A and Figure 10B The illustration schematically shows cross-sectional side views of a first element 1002 and a second element 1004, according to some embodiments, before and after the process for forming a direct-joint structure, more particularly a hybrid-joint structure. Figure 10B In the illustrated hybrid bonding structure 1000, a first element 1002 and a second element 1004 are directly bonded to each other at a bonding interface 1018 without the need for an intermediate adhesive. A conductive feature 1006a of the first element 1002 can be electrically connected to a corresponding conductive feature 1006b of the second element 1004. In the illustrated hybrid bonding structure 1000, the conductive feature 1006a is directly bonded to the corresponding conductive feature 1006b without the need for solder or conductive adhesive.

[0097] In the illustrated embodiment, conductive features 1006a and 1006b are respectively embedded in a first bonding layer 1008a of the first element 1002 and a second bonding layer 1008b of the second element 1004, and can be considered as part of the first bonding layer 1008a of the first element 1002 and the second bonding layer 1008b of the second element 1004. Field regions of bonding layers 1008a and 1008b extend between and partially or completely surround the conductive features 1006a and 1006b. Bonding layers 1008a and 1008b may include layers of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. Non-conductive bonding layers 1008a and 1008b may be disposed on corresponding front sides 1014a and 1014b of the substrate portions 1010a and 1010b.

[0098] First element 1002 and second element 1004 may include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of elements 1002, 1004, and back-end line (BEOL) interconnect layers above such semiconductor portions. Bonding layers 1008a, 1008b may be provided during device manufacturing as part of such BEOL layers, as part of redistribution layers (RDLs), or as specific bonding layers added to existing devices, wherein bonding pads extend from underlying contacts. Active devices and / or circuitry may be patterned and / or additionally disposed in or on substrate portions 1010a, 1010b, and may be electrically connected to at least some of the conductive features 1006a, 1006b. Active devices and / or circuitry may be disposed on or near the front sides 1014a, 1014b of the substrate portions 1010a, 1010b, and / or on or near the opposite back sides 1016a, 1016b of the substrate portions 1010a, 1010b. In other embodiments, the substrate portions 1010a, 1010b may not include active circuitry, but may alternatively include dummy substrates, passive interpolation layers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers 1008a, 1008b are shown as being provided on the front side of the element, but similar bonding layers may be additionally or alternatively provided on the back side of the element.

[0099] In some embodiments, substrate portions 1010a and 1010b may have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different substrate portions may form heterojunction structures. The CTE difference between substrate portions 1010a and 1010b, particularly the CTE difference between the bulk semiconductor (typically single-crystal) portions of substrate portions 1010a and 1010b, may be greater than 5 ppm / ℃ or greater than 10 ppm / ℃. For example, the CTE difference between substrate portions 110a and 110b may be in the range of 5 ppm / ℃ to 100 ppm / ℃, 5 ppm / ℃ to 40 ppm / ℃, 10 ppm / ℃ to 100 ppm / ℃, or 10 ppm / ℃ to 40 ppm / ℃.

[0100] In some embodiments, one of the substrate portions 1010a and 1010b may include a photoelectric single-crystal material, including perovskite materials, for optical piezoelectric or thermoelectric applications, and the other portion of the substrate portions 1010a and 1010b may include a more conventional substrate material. For example, one portion of the substrate portions 1010a and 1010b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other portion of the substrate portions 1010a and 1010b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one portion of the substrate portions 1010a and 1010b may include a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other portion of the substrate portions 1010a and 1010b may include a non-group III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTEs, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the substrate portions 1010a and 1010b includes a semiconductor material, and the other of the substrate portions 1010a and 1010b includes an encapsulation material, such as a glass, organic, or ceramic substrate.

[0101] In some arrangements, the first element 1002 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the first element 1002 may include a carrier or substrate (e.g., a semiconductor wafer) comprising multiple (e.g., tens, hundreds, or more) device regions that, when monolithically spun, form multiple integrated device dies; however, in other embodiments, such a carrier may be a packaging substrate or a passive or active interpolation layer. Similarly, the second element 1004 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the second element 1004 may include a carrier or substrate (e.g., a semiconductor wafer). Therefore, the embodiments disclosed herein can be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and monolithically spun using a suitable monolithization process. After monolithization, the side edges of the monolithized structure (e.g., the side edges of two joined elements) can be substantially flush (substantially aligned xy dimensions) and / or the edges of the joint interface for both the joined elements and the monolithized elements can extend together, and may include markings indicating the common monolithization process for the joined structure (e.g., saw markings if a saw monolithization process is used).

[0102] Although only two elements 1002 and 1004 are shown, any suitable number of elements can be stacked in the bonding structure 1000. For example, a third element (not shown) can be stacked on top of the second element 1004, a fourth element (not shown) can be stacked on top of the third element, and so on. In this embodiment, through-substrate vias (TSVs) can be formed to provide vertical electrical communication between and / or among vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 1002. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided on the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonding structure, and a second insulating layer (which may include the same material or a different material as the first insulating layer) can be provided on top of the first insulating layer.

[0103] To achieve direct bonding between bonding layers 1008a and 1008b, bonding layers 1008a and 1008b can be prepared for direct bonding. Non-conductive bonding surfaces 1012a and 1012b on the upper or outer surfaces of bonding layers 1008a and 1008b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 1012a and 1012b can be less than 30 Å rms. For example, the roughness of the bonding surfaces 1012a and 1012b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be adjusted to make the conductive features 1006a and 1006b recessed relative to the field regions of bonding layers 1008a and 1008b.

[0104] Preparation for direct bonding may further include cleaning one or both of the bonding surfaces 1012a, 1012b, and exposing one or both of the bonding surfaces 1012a, 1012b to plasma and / or an etchant to activate at least one of the surfaces 1012a, 1012b. In some embodiments, one or both of the surfaces 1012a, 1012b may be terminated with a substance after activation or during activation (e.g., during the plasma and / or etching process). Without being theoretically limited, in some embodiments, the activation process may be performed to break the chemical bonds at the bonding surfaces(s) 1012a, 1012b, and the termination process may provide additional chemicals at the bonding surfaces(s) 1012a, 1012b that alter the chemical bonds and / or improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided with the same steps, such as plasma, to activate or terminate the surfaces(s) 1012a, 1012b. In other embodiments, one or both of the bonding surfaces 1012a, 1012b may be terminated in a separate process to enhance the additional material used for direct bonding. In various embodiments, the terminating material may include nitrogen. For example, in some embodiments, the bonding surfaces(s) 1012a, 1012b may be exposed to a nitrogen-containing plasma. Depending on the material of the bonding surfaces 1012a, 1012b, other terminating materials may be suitable to improve the bonding energy. Furthermore, in some embodiments, the bonding surfaces(s) 1012a, 1012b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 1018 between the first element 1002 and the second element 1004. Typically, fluorine concentration peaks appear at the interface between material layers. Additional examples of activation and / or termination treatments can be found in U.S. Patent No. 9,391,143, column 5, line 55 to column 7, line 3; column 8, line 52 to column 9, line 45; column 10, lines 24-36; column 11, lines 24-32, 42-47, 52-55 and 60-64; column 12, lines 3-14, 31-33 and 55-67; ​​column 14, lines 38-40 and 44-50; and in U.S. Patent No. 10,434,749, column 4, lines 41-50; column 5, lines 7-22, 39 and 55-61; column 8, lines 25-31, 35-40 and 49-56; and column 12, lines 46-61, the teachings of which are incorporated herein by reference.

[0105] Therefore, in the direct bonding structure 1000, the bonding interface 1018 between the two non-conductive materials (e.g., bonding layers 1008a, 1008b) may include a very smooth interface with high nitrogen (or other terminating material) content and / or fluorine concentration peaks at the bonding interface 1018. In some embodiments, the nitrogen and / or fluorine concentration peaks can be detected using various types of detection techniques, such as SIMS techniques. The polished bonding surfaces 1012a, 1012b may be slightly rougher after the activation process (e.g., approximately 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher). In some embodiments, activation and / or termination may result in a slightly smoother surface prior to bonding, such as where plasma treatment preferentially erodes high points on the bonding surface.

[0106] Non-conductive bonding layers 1008a and 1008b can be directly bonded to each other without adhesive. In some embodiments, elements 1002 and 1004 aggregate together at room temperature without the need for voltage application and without the need for external pressure or force exceeding that required to activate the contacts between the two elements 1002 and 1004. Individual contacts may result in direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 1008a and 1008b. Subsequent annealing of the bonding structure 1000 may cause direct bonding of conductive features 1006a and 1006b.

[0107] In some embodiments, prior to direct bonding, conductive features 1006a, 1006b are recessed relative to the surrounding field region such that, after dielectric bonding and before annealing, the total gap between opposing contacts is less than 15 nm, or less than 10 nm. Because the recess depth for conductive features 1006a, 1006b can vary on each element due to process variations, the indicated gap can represent the maximum or average gap between corresponding conductive features 1006, 1006b of the two bonded elements (before annealing). During annealing, conductive features 1006a, 1006b can expand and contact each other to form a metal-to-metal direct bond.

[0108] During annealing, the conductive features 1006a, 1006b (e.g., metallic materials) can expand, while the direct bonding between the surrounding non-conductive materials of the bonding layers 1008a, 1008b resists separation of the elements, causing thermal expansion to increase the internal contact pressure between the opposing conductive features. Annealing can also cause metal grains to grow at the bonding interface, allowing grains from one element to migrate at least partially to the other element and vice versa. Therefore, in some hybrid bonding embodiments, opposing conductive materials are bonded without heating above the melting temperature of the conductive materials, allowing the bond to be formed at a lower annealing temperature compared to welding or thermocompression bonding.

[0109] In various embodiments, conductive features 1006a, 1006b may include discrete pads, contacts, electrodes, or traces that are at least partially embedded in non-conductive field regions of bonding layers 1008a, 1008b. In some embodiments, conductive features 1006a, 1006b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0110] As noted above, in some embodiments, in Figure 1A In elements 1002 and 1004, prior to direct bonding, portions of the corresponding conductive features 1006a and 1006b can be recessed below the non-conductive bonding surfaces 1012a and 1012b, for example, recessed to less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, such as recessed in the range of 2 nm to 10 nm, or in the range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth can vary on the element. Therefore, the above recess depth range can be applied to individual conductive features 1006a and 1006b or to the average depth of the recess relative to a local non-conductive field region. Even for individual conductive features 1006a and 1006b, the vertical recess can vary on the feature, and therefore can be measured at or near the lateral midpoint or center of the cavity in which a given conductive feature 1006a or 1006b is formed, or can be measured at the side of the cavity.

[0111] Advantageously, hybrid bonding technologies (such as direct bonding interconnects, or DBI) ® The use of technology (commercially available from Adeia of San Jose, CA) enables high-density connections (e.g., for small or fine pitches in regular arrays) between conductive features 1006a, 1006b on the direct bonding interface 1018.

[0112] In some embodiments, the pitch p of conductive features 1006a, 1006b, such as conductive traces embedded in the bonding surface of one of the bonding elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of conductive features 1006a and 1006b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In various embodiments, conductive features 1006a and 1006b and / or the traces may comprise copper or a copper alloy, although other materials may be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as conductive features 1006a and 1006b, may comprise fine-grained metals (e.g., fine-grained copper). In addition, the main lateral dimensions (such as pad diameter) can also be small, for example, in the range of approximately 0.25 μm to 30 μm, in the range of approximately 0.25 μm to 5 μm, or in the range of approximately 0.5 μm to 5 μm.

[0113] For hybrid bonding elements 1002 and 1004, as shown, the orientations of one or more conductive features 1006a and 1006b from the opposing elements can be opposite each other. As is known in the art, conductive features can typically be formed with near-vertical sidewalls, particularly where directional reactive ion etching (RIE) defines the conductor sidewalls directly by etching the conductive material or indirectly by etching the surrounding insulator during the damascene process. However, some slight taper to the conductor sidewalls may be present, where the conductor becomes narrower away from the surface initially exposed to the etch. The taper can be even more pronounced when the conductor sidewalls are defined directly or indirectly by isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 1006b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 1008b of the upper element 1004 may taper or narrow upward away from the bonding surface 1012b. In contrast, at least one conductive feature 1006a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 1008a of the lower element 1002 may taper or narrow downward away from the bonding surface 1012a. Similarly, any bonding layer (not shown) on the back sides 1016a, 1016b of elements 1002, 1004 may taper or narrow away from the back side, having an opposite taper orientation to the front conductive features 1006a, 1006b of the same element.

[0114] As described above, during the annealing stage of the hybrid bonding process, conductive features 1006a and 1006b can expand and contact each other to form a metal-to-metal direct bond. In some embodiments, the materials of conductive features 1006a and 1006b of opposing elements 1002 and 1004 can diffuse into each other during the annealing process. In some embodiments, metal grains grow into each other at the bonding interface 1018. In some embodiments, the metal is copper or includes copper, which may have grains oriented along the 111 crystal plane to improve copper diffusion at the bonding interface 1018. In some embodiments, conductive features 1006a and 1006b may include a nanotwinned copper grain structure, which may facilitate the merging of conductive features during annealing. There are substantially no gaps between the non-conductive bonding layers 1008a and 1008b at or near the bonding conductive features 1006a and 1006b. In some embodiments, a barrier layer may be provided below and / or laterally surrounding the conductive features 1006a and 1006b (e.g., it may include copper). In other embodiments, however, no barrier layer may be provided below the conductive features 1006a and 1006b. Additional Examples

[0115] In the foregoing specification, the system and process have been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and changes can be made without departing from the broader spirit and scope of the embodiments disclosed herein. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

[0116] In fact, although systems and processes have been disclosed in the context of certain embodiments and examples, those skilled in the art will understand that various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the systems and processes, as well as their obvious modifications and equivalents. Furthermore, although several variations of embodiments of the systems and processes have been shown and described in detail, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. It is also contemplated that specific features of the embodiments and various combinations or sub-combinations of the embodiments can be implemented and will still fall within the scope of this disclosure. It should be understood that various features and embodiments of the disclosed embodiments can be combined or substituted with each other to form variations of embodiments of the disclosed systems and processes. No method disclosed herein needs to be performed in the order described. Therefore, the scope of the systems and processes disclosed herein should not be limited to the specific embodiments described above.

[0117] It should be understood that the systems and methods of this disclosure each have several novel embodiments, and each individual embodiment is not solely responsible for or claim to the desired properties disclosed herein. The various features and processes described above can be used independently of each other or can be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure.

[0118] Some features described in this specification in the context of a single embodiment may also be implemented in combinations of those single embodiments. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as acting in certain combinations, and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in certain circumstances, and the claimed combination may be directed as a sub-combination or a variation of a sub-combination. No single feature or group of features is required or indispensable for every and every embodiment.

[0119] It should also be understood that the conditional language used herein, such as in particular “can,” “could,” “might,” “may,” “e.g.,” etc., unless otherwise specifically stated or understood in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or steps that are not included in other embodiments. Therefore, such conditional language is generally not intended to imply that features, elements, and / or steps are required in any way for one or more embodiments, or that one or more embodiments must include logic for determining whether such features, elements, and / or steps are included in or to be performed in any particular embodiment, with or without author input or prompting. The terms “comprising,” “including,” “having,” etc., are synonymous and used inclusively in an open-ended manner, and do not exclude additional elements, features, actions, operations, etc. Additionally, the term “or” is used in its inclusive sense (and not in its exclusive sense) such that, for example, when used to connect a list of elements, the term “or” means one, some, or all of the elements in the list. Furthermore, the articles “a,” “an,” and “the” used in this application and the appended claims are to be interpreted as meaning “one or more” or “at least one,” unless otherwise stated. Similarly, although operations may be depicted in the drawings in a specific order, it should be understood that such operations need not be performed in the specific order shown or in a sequential order, or all illustrated operations, to achieve the desired result. Moreover, the drawings may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be incorporated into the schematically illustrated example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operations. Additionally, in other embodiments, operations may be rearranged or reordered. Additionally, other embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired result.

[0120] Furthermore, while the methods and apparatus described herein may allow for various modifications and substitutions, specific examples have been shown in the accompanying drawings and described in detail herein. However, it should be understood that embodiments are not limited to the specific forms or methods disclosed, but rather, embodiments will cover all modifications, equivalents, and substitutions falling within the spirit and scope of the various implementations described and the appended claims. Furthermore, any particular feature, aspect, method, characteristic, feature, quality, attribute, element, etc., of the disclosure herein in conjunction with an implementation or embodiment may be used in all other implementations or embodiments set forth herein. No method disclosed herein needs to be performed in the stated order. Methods disclosed herein may include certain actions taken by a practitioner; however, the method may also explicitly or implicitly include any third-party instructions regarding those actions. The scope of the disclosure herein also covers any and all overlapping, sub-scopes, and combinations thereof. Languages ​​such as “at most,” “at least,” “greater than,” “less than,” “between,” etc., include the listed numbers. Numbers preceded by terms such as “about” or “approximately” include the listed numbers and should be interpreted on a case-by-case basis (e.g., as reasonably accurate as possible in the case, such as ±5%, ±10%, ±15%, etc.). For example, "approximately 3.5 mm" includes "3.5 mm". Phrases preceded by terms such as "substantially" include the listed phrases and should be interpreted on a case-by-case basis (e.g., interpreted as reasonably as possible under the circumstances). For example, "substantially constant" includes "constant". Unless otherwise stated, all measurements are taken under standard conditions including temperature and pressure.

[0121] As used herein, the phrase “at least one” in a list of items refers to any combination of those items, including a single item. As an example, “at least one of the following: A, B, or C” is intended to cover: A; B; C; A and B; A and C; B and C; and A, B, and C. Unless otherwise explicitly stated, combinational language such as the phrase “at least one of X, Y, and Z” should be understood as generally used to convey the context that an item, term, etc., may be at least one of X, Y, or Z. Therefore, such combinational language is not generally intended to imply that certain embodiments require the presence of at least one of X, at least one of Y, and at least one of Z. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0122] Therefore, the claims are not intended to be limited to the embodiments shown herein, but should be accorded the widest scope consistent with the disclosure, principles and novel features disclosed herein.

Claims

1. A structure comprising: Active components, including: The front side and the back side opposite the front side; Multiple vias extend vertically from the back side through a portion of the active element; and The active region is closer to the front side than the back side; A power redistribution element is disposed on the back side of the active element, the power redistribution element comprising: The front side and the back side opposite the front side; The first plurality of contact pads are disposed on the front side; and The second plurality of contact pads are provided on the back side; The pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads. The first plurality of contact pads are electrically coupled to the plurality of vias.

2. The structure according to claim 1, further comprising: A power delivery die includes a front side and a back side opposite the front side, wherein the front side is electrically connected to the second plurality of contact pads of the power redistribution element.

3. The structure of claim 1, wherein the power redistribution element is configured to carry power and ground, and is not configured to carry logic signals.

4. The structure according to claim 1, wherein the power redistribution element includes an interpolation layer.

5. The structure according to claim 4, wherein the power redistribution element further comprises a hybrid bonding layer disposed on the front side of the power redistribution element.

6. The structure according to claim 4, wherein the power redistribution element further comprises a hybrid bonding layer disposed on the back side of the power redistribution element.

7. The structure of claim 1, wherein the power redistribution element is at least partially deposited on the back side of the active element.

8. The structure according to claim 7, wherein after the active element is thinned, the power redistribution element is at least partially deposited on the back side of the active element.

9. The structure of claim 7, wherein the front side of the power delivery die is co-bonded to the back side of the power redistribution element.

10. The structure of claim 2, wherein the front side of the power delivery die is co-bonded to the back side of the power redistribution element, and wherein the front side of the power redistribution element is co-bonded to the back side of the active element.

11. The structure according to claim 2 further includes a passive element disposed between the power delivery die and the power redistribution element.

12. The structure of claim 1, wherein power is delivered through the power redistribution element to the back side of the active element.

13. A structure comprising: An active element having a front side and a back side opposite to the front side, the active element having an active circuit arrangement closer to the front side than the back side; as well as A power redistribution element having a front side that is hybridly bonded to the back side of the active element, the power redistribution element including a first plurality of contact pads on the front side of the power redistribution element and a second plurality of contact pads on the back side of the power redistribution element opposite to the front side of the power redistribution element. Wherein the pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads, and The power redistribution element is configured to provide at least one of power and ground to the active element.

14. The structure of claim 13, wherein the active element includes a via extending from the back side of the active element to the active circuit device.

15. The structure according to claim 13, further comprising: A power delivery die having a front side and a back side opposite the front side. The front side of the power delivery die is hybridly bonded to the back side of the power redistribution element.

16. The structure of claim 13, wherein at least one of the power and ground is carried through the power redistribution element and delivered to the back side of the active element.

17. An interpolation layer, comprising: Front surface; The back surface is opposite to the front surface; Redistribution layer; A plurality of contact pads are disposed on the front surface of the intercalation layer; as well as The second plurality of contact pads are disposed on the back surface of the intercalation layer. The first plurality of contact pads have a first pitch, which is smaller than the second plurality of contact pads. The first plurality of contact pads are configured to be electrically connected to vias on the back side of the active component. The second plurality of contact pads are configured to be electrically connected to contact pads on the power delivery die, and The front surface and the back surface at least one of them include a hybrid bonding layer.

18. The interpolation layer of claim 17, wherein the first pitch is from about 50 nm to about 1000 nm, and The second pitch ranges from approximately 1 μm to approximately 500 μm.

19. The interpolation layer of claim 17, wherein the interpolation layer has a thickness from about 1 μm to about 50 μm.

20. The interpolation layer of claim 17, wherein the second plurality of contact pads are arranged in a periodic pattern.

21. The intercalation layer of claim 17, wherein the front surface comprises a hybrid bonding layer.

22. The intercalation layer of claim 17, wherein the back surface comprises a hybrid bonding layer.

23. The interpolation layer of claim 17, wherein the interpolation layer comprises a plurality of layers, wherein each layer is configured to carry a single voltage or ground, wherein each layer is separated from the other layers of the plurality of layers by a dielectric material.

24. The interpolation layer of claim 17, wherein the interpolation layer is configured to transport power from the circuit delivery die at the back surface of the interpolation layer to the front surface of the interpolation layer, the front surface of the interpolation layer being electrically connected to the via on the back side of the active element.

25. A method comprising: A first interpolation layer is formed, the first interpolation layer comprising: First front side; The first dorsal side is opposite to the first anterior side; A first front contact is disposed on the first front side, the first front contact is arranged in the first front side arrangement, and is configured to be electrically connected to a via on the back side of the first active element; and A first back-side contact is disposed on the first back side, the first back-side contact is arranged in a first back-side pattern, and is configured to be electrically connected to a first power delivery die; and A second interpolation layer is formed, the second interpolation layer comprising: Second front side; The second dorsal side is opposite to the second anterior side; A second front contact is disposed on the second front side, the second front contact is arranged in the second front side arrangement, and is configured to be electrically connected to a via on the back side of the second active element; and A second back-side contact is disposed on the second back side, the second back-side contact is arranged in the second back-side pattern, and is configured to be electrically connected to the second power delivery die. The first front side arrangement is different from the second front side arrangement, and The first back side pattern is the same as the second back side pattern.

26. The method of claim 25, wherein the first intercalation layer further comprises a first front-side hybrid bonding surface disposed on the first front side.

27. The method of claim 25, wherein the first intercalation layer further comprises a first back-side hybrid bonding surface disposed on the first back side.

28. The method of claim 25, wherein the pitch of the first back-side pattern and the second back-side pattern is greater than the pitch of the first front-side arrangement and the pitch of the second front-side arrangement.

29. The method of claim 28, wherein the pitch of the first front arrangement is from about 100 nm to about 500 nm. The pitch of the second front side arrangement is from approximately 100 nm to approximately 500 nm, and The pitch of the first back-side pattern and the second back-side pattern ranges from approximately 20 μm to approximately 500 μm.

30. The method of claim 25, wherein the first intercalation layer is configured to deliver first power from the first power delivery die to the first back side of the first active element, and wherein the second intercalation layer is configured to deliver second power from the second power delivery die to the second back side of the second active element.

31. A method comprising: A first interpolation layer is formed, the first interpolation layer comprising: First front side; The first dorsal side is opposite to the first anterior side; A first front contact is disposed on the first front side, the first front contact is arranged in the first front side arrangement, and is configured to be electrically connected to a via on the back side of the first active element; and A first back-side contact is disposed on the first back side, the first back-side contact is arranged in the first back-side pattern, and is configured to be electrically connected to the first power delivery die.

32. The method of claim 31, wherein the first intercalation layer further comprises a first front-side hybrid bonding surface disposed on the first front side.

33. The method of claim 31, wherein the first intercalation layer further comprises a first back-side hybrid bonding surface disposed on the first back side.

34. The method of claim 31, wherein the first interpolation layer is configured to deliver first power from the first power delivery die to the first back side of the first active element.

35. The method of claim 31, further comprising: A second interpolation layer is formed, the second interpolation layer comprising: Second front side; The second dorsal side is opposite to the second anterior side; A second front contact is disposed on the second front side, the second front contact is arranged in the second front side arrangement, and is configured to be electrically connected to a via on the back side of the second active element; and A second back-side contact is disposed on the second back side, the second back-side contact is arranged in the second back-side pattern, and is configured to be electrically connected to the second power delivery die.

36. The method of claim 35, wherein the first front arrangement is different from the second front arrangement.

37. The method of claim 36, wherein the first back-side pattern is the same as the second back-side pattern.

38. The method of claim 35, wherein the pitch of the first back-side pattern and the second back-side pattern is greater than the pitch of the first front-side arrangement and the pitch of the second front-side arrangement.

39. The method of claim 38, wherein the pitch of the first front arrangement is from about 100 nm to about 500 nm. The pitch of the second front side arrangement is from approximately 100 nm to approximately 500 nm, and The pitch of the first back-side pattern and the second back-side pattern ranges from approximately 20 μm to approximately 500 μm.

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