Concurrent forward error correction (FEC) and cyclic redundancy check (CRC)

Abstract

The invention relates to concurrent forward error correction (FEC) and cyclic redundancy check (CRC). An apparatus includes a receiver coupled with a link, the receiver including control logic to receive data bits corresponding to a first set of data. The control logic may also perform a forward error correction (FEC) operation on the data bits in response to receiving the data bits to generate error locations. The control logic may also perform a cyclic redundancy check (CRC) operation on the data bits to generate a first CRC value, wherein the CRC operation and the FEC operation are performed concurrently. The control logic may determine a second CRC value after performing the FEC operation, the second CRC value based on the error location, and the control logic may generate a third CRC value corresponding to the first set of data in response to performing the CRC operation and determining the second CRC value.

Description

TECHNICAL FIELD

[0001] Some embodiments relate to processing resources for performing and facilitating concurrent forward error correction (FEC) and cyclic redundancy check (CRC). BACKGROUND

[0002] A communication system sends signals from a transmitter to a receiver via a communication channel or medium (e.g., a cable, printed circuit board, link, wireless, etc.). For example, a communication system can send signals over a Peripheral Component Interconnect Express (e.g., a PCIe or PCI-e bus). In such examples, data can be transferred between the transmitter and receiver in fixed lengths, e.g., in flit format, where each flit has the same number of bits. In some examples, to ensure that data is reliably transferred through the interconnect, the receiver can perform one or more error correction operations. For example, the receiver can perform a forward error correction (FEC) operation and a cyclic redundancy check (CRC) operation when receiving a flit. Conventional solutions perform one error operation before the other. For example, the receiver can perform the FEC operation before performing the CRC operation. Thus, the receiver can experience additional latency when receiving data due to having to independently and sequentially perform each error operation. BRIEF DESCRIPTION OF DRAWINGS

[0003] Various embodiments according to the present disclosure will be described with reference to the drawings, in which:

[0004] Figure 1 is an example communication system according to some embodiments;

[0005] Figure 2 is an example communication system illustrating concurrent cyclic redundancy check (CRC) and forward error correction (FEC) operations according to some embodiments;

[0006] Figure 3 is an example communication system illustrating a CRC component according to some embodiments;

[0007] Figure 4 is an example communication system illustrating a CRC component according to some embodiments;

[0008] Figure 5 is a flowchart of a method for concurrent CRC and FEC operations according to some embodiments; and

[0009] Figure 6 illustrates an example computer system for concurrent CRC and FEC operations according to some embodiments. DETAILED DESCRIPTION

[0010] Techniques for performing error correction operations (e.g., forward error correction (FEC) and cyclic redundancy check (CRC)) are described in the context of a communication system. In particular, error correction operations can be performed in the context of a high-speed peripheral component interconnect system (e.g., a PCIe or PCI-e system). The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a thorough understanding of several implementations of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in a simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth are merely examples. Particular implementations can vary from these exemplary details and still be considered to be within the scope of the present disclosure.

[0011] As described above, a communication system sends signals from a transmitter to a receiver via a communication channel or medium (e.g., a cable, a printed circuit board, a link, wireless, etc.). The transmitter and receiver can be examples of personal computer components (e.g., a graphics processing unit (GPU), a storage device (e.g., a volatile or non-volatile memory device), a central processing unit (CPU), a data processing unit (DPU), a graphics card, etc. In some examples, the transmitter and receiver can be used in data-centric applications in the Internet of Things (IoT), automotive, medical, etc. In some implementations, the transmitter and receiver can communicate according to a communication protocol. For example, the communication system can send signals over a peripheral component interconnect express link (e.g., a PCIe or PCI-e bus). In such implementations, each receiver and transmitter can include a PCIe controller that can organize data into packets for transmission and perform error correction operations on received data.

[0012] In some embodiments, the communication system can utilize PCIe 6.0 (e.g., the sixth generation of PCIe). In some embodiments, the communication system can utilize pulse amplitude modulation with four levels (e.g., PAM4 signaling), combining two (2) bits per clock cycle to achieve four amplitude levels (e.g., 00, 01, 10, 11). In some implementations, the communication system can organize data packets in fixed length flow control units, e.g., data can be transmitted according to a flit pattern, where data is sent in flits each having a same fixed length. For example, each flit can include 2048 bits. In some embodiments, the system can need multiple cycles to send a single flit. For example, if the internal data path of the system is 512 bits, it can take four (4) cycles to send a flit between a receiver and a transmitter.

[0013] In some embodiments, due to PAM4 signaling, there can be a high bit error rate (BER). Accordingly, a system can use forward error correction (FEC) to mitigate the higher error rate, for example, a system can use FEC to ensure that the data received at a receiver is the same as the data sent by a transmitter. In some embodiments, FEC can be the addition of a number of bits in a flit to reduce the probability of bit errors during transmission. However, FEC alone can not be sufficient to reduce link errors. In some embodiments, a system can also perform a cyclic redundancy check (CRC) operation, for example, an error-detecting code that is used to detect accidental changes in digital data during transmission by appending a short check value within each flit. For example, a flit can include a 242 byte data payload, an eight (8) byte CRC value, and a 6 byte FEC code. In some embodiments, a system can wait until the end of reception of a flit before performing FEC and CRC operations, for example, data within a flit can be used after FEC and CRC checks pass.

[0014] Some solutions can first perform an FEC operation and then perform a CRC operation, for example, the CRC value can rely on the corrected data of the FEC operation. In some implementations, a system can first input data into an FEC component (e.g., an FEC engine) that performs an FEC operation. As described above, a flit can be transmitted in four parts, each part transmitted within one (1) clock cycle. Accordingly, an FEC operation can take four (4) cycles to perform. After the FEC operation, a system can input the modified data into a CRC component (e.g., a CRC engine) to perform a CRC operation. In some embodiments, a CRC operation can also take four (4) cycles. In such embodiments, a system can experience an eight (8) cycle delay due to the FEC and CRC operations, for example, performing these operations independently and sequentially can cause an increase in latency during data transmission.

[0015] Advantageously, aspects of the present disclosure can address the aforementioned deficiencies and other technical problems by concurrently or simultaneously performing a cyclic redundancy check (CRC) operation and a forward error correction (FEC) operation. For example, a system can pre-compute possible CRC values for a data payload included in a flit, and utilize the known values to correct errors detected by the FEC operation. In some embodiments, a first CRC component (e.g., a CRC decoder) can perform a CRC operation on received data, e.g., before the data undergoes an FEC operation. Concurrently, an FEC component (e.g., an FEC decoder) can output errors to a second, simplified CRC component to generate correct CRC data. For example, the second CRC component can use a lookup table and exclusive OR (XOR) logic to determine a CRC value from error bytes (e.g., from error bytes flagged by the FEC engine). That is, the output of the FEC component can be three (3) error byte locations corresponding to errors in the data. Based on a fixed length CRC algorithm, toggling one bit will result in a known fixed change in the CRC value. By pre-computing all CRC values and knowing the error bytes and error parity, the final correct CRC can be computed.

[0016] In some embodiments, a system can use additional XOR logic to logically combine (e.g., XOR) a computed CRC from error bytes and a computed CRC from original data (e.g., XOR the outputs of the first and second CRC components). In such embodiments, the correctness of the CRC can be determined with reduced latency. For example, a system can perform a CRC operation at a first CRC component concurrently with performing an FEC operation at an FEC component. In an example where a flit is transmitted in four (4) cycles, the FEC and CRC operations can occur concurrently in four (4) clock cycles. In other embodiments, a flit can be transmitted in a different number of clock cycles (e.g., one, two, three, five, six, etc.). The system can then take additional clock cycles to compare the CRC values generated by the first and second CRC components to compute a correct CRC value. Thus, this process can require fewer clock cycles than some solutions.

[0017] Utilizing concurrent FEC and CRC operations can reduce latency in a system and shorten the time for data processing at a receiver. That is, by performing error correction operations in a shorter time, a receiver can process received data in fewer clock cycles than some solutions.

[0018] Figure 1An example communication system 100 is illustrated in accordance with some example embodiments. The system 100 includes devices 110 (e.g., device 110-a, device 110-b, device 110-c, and device 110-d) coupled via a link 135 (e.g., a communication network). In some embodiments, the devices 110 are two endpoint devices in a computing system, such as a central processing unit (CPU) or a graphics processing unit (GPU). In some embodiments, the devices 110 are two servers. In one example embodiment, the devices 110 correspond to one or more of a personal computer (PC), a laptop, a tablet, a smartphone, a server, a collection of servers, etc. In some embodiments, the devices 110 can correspond to any appropriate type of device that communicates with other devices connected to the common link 135. In some examples, the devices 110 can be used in data-centric applications as in Internet of Things (IoT), automotive, medical, etc.

[0019] In accordance with embodiments, each device 110 can include a transceiver having a transmitter and a receiver. In some implementations, the receiver of a device 110 can correspond to a GPU, a switch (e.g., a high-speed network switch), a network adapter, a CPU, a memory device, an input / output (I / O) device, other peripheral devices or components on a system-on-a-chip (SoC), or other devices and components that receive or measure signals, etc. As another specific, but non-limiting, example, a device 110 can correspond to a server that provides information resources, services, and / or applications to user devices, client devices, or other hosts in the system 100. In one example, a device 110 can correspond to a network device, such as a switch, a network adapter, or a data processing unit (DPU).

[0020] Examples of the link 135 that can be used to connect the devices 110 include an Internet Protocol (IP) network, Ethernet, an InfiniBand (IB) network, a Fibre Channel network, the Internet, a cellular communication network, a wireless communication network, combinations thereof (e.g., Ethernet Fibre Channel), variations thereof, etc. In one specific, but non-limiting, example, the link 135 is an example of a Peripheral Component Interconnect Express (e.g., a PCIe or PCI-e bus). In some embodiments, the link 135 can communicate via a sixth generation PCIe protocol (e.g., PCIe Generation 6.0).

[0021] Device 110 includes a transceiver for transmitting and receiving signals (e.g., data signals). The data signals can be digital or optical signals modulated with data, or can be other suitable signals for carrying data. The transceiver of device 110 can include a digital data source, a transmitter, a receiver, and processing circuitry that controls the transceiver. The digital data source can include suitable hardware and / or software for outputting data in a digital format (e.g., binary code and / or thermometer code). The digital data output by the digital data source can be retrieved from a memory (not shown) or generated from an input (e.g., user input).

[0022] The transmitter of device 110-a includes suitable software and / or hardware for receiving digital data from the digital data source and outputting a data signal from the digital data for transmission to the receivers of devices 110-b through 110-d over link 135. Other details of the structure of the transmitter are discussed in more detail below with reference to the figures.

[0023] The receiver of device 110 can include suitable hardware and / or software for receiving signals (such as data signals) from link 135. For example, the receiver of device 110 can include components for receiving and processing signals to extract data for storage in a memory, as discussed in more detail below with reference to the Figures 2-5 Detailed Description.

[0024] The processing circuitry included in device 110 can include software, hardware, or a combination thereof. For example, the processing circuitry can include a memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory can correspond to any suitable type or set of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that can be used include flash memory, random access memory (RAM), read only memory (ROM), variations thereof, combinations thereof, and the like. In some embodiments, the memory and the processor can be integrated into a common device (e.g., a microprocessor can include integrated memory). Additionally or alternatively, the processing circuitry can include hardware such as an application specific integrated circuit (ASIC). Other non-limiting examples of processing circuitry include an integrated circuit (IC) chip, a central processing unit (CPU), a general purpose processing unit (GPU), a microprocessor, a field programmable gate array (FPGA), a collection of logic gates, resistors, capacitors, inductors, diodes, etc. Some or all of the processing circuitry can be disposed on a printed circuit board (PCB) or set of PCBs. It should be understood that any suitable type of electrical component or set of electrical components can be suitable for inclusion in the processing circuitry. The processing circuitry can send and / or receive signals to / from other elements of the transceiver to control the overall operation of the transceiver of device 110.

[0025] The transceiver or selected elements of the transceiver can take the form of a pluggable card or controller of the device 110. For example, the transceiver or selected elements of the transceiver can be implemented on a network interface card (NIC).

[0026] Although not explicitly shown, it should be understood that the device 110 can include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks such as sending and receiving data.

[0027] In some implementations, the transceiver of the device 110 can include a controller 115. In some embodiments, the controller 115 is associated with a PCIe protocol, e.g., the controller 115 can send and receive data according to the PCIe protocol. In some embodiments, each device 110 of the system 100 includes a controller 115. In some embodiments, the controller 115 can include an error circuit 120 for processing data received from another device 110. For example, the device 110-b can include an error circuit 120 for processing data received from the device 110-a. In some embodiments, the error circuit 120 can include a CRC component 125 and a CRC component 130. In some embodiments, the CRC component 125 is for performing a cyclic redundancy check (CRC) operation to compute a CRC value associated with data received at a receiver. In some implementations, the CRC component 125 is for performing the CRC operation concurrently with a forward error correction operation (FEC) performed at an FEC component, as described with reference to Figure 2 In some embodiments, the CRC component 130 is for generating a second CRC value that can be used to modify or otherwise correct the CRC value generated by the CRC component 125, as described with reference to Figure 2 For example, the CRC component 130 can receive error data, e.g., receive error byte positions, from the FEC component. In some embodiments, the CRC component 130 can include a lookup table that stores a CRC value associated with each error byte position. Accordingly, the CRC component 130 can output a respective second CRC value associated with the error byte position. In some embodiments, the error circuit 120 can include exclusive OR (XOR) logic and XOR the CRC value generated by the CRC component 125 and the second CRC value generated by the component 130 to determine a correct CRC associated with the data, as described with reference to Figure 2

[0028] Figure 2 FIG. illustrates an example error circuit 200 within a communication system 100 as described with reference to Figure 1 The system 200 includes a controller 215 and an error circuit 220 as described with reference to Figure 1 ​The cyclic redundancy check (CRC) component 125 and CRC component 130 are described above. In some embodiments, the system 200 may further include a forward error correction (FEC) component 210, a delay trigger (DFF) 225, and an XOR logic 230.

[0029] In some embodiments, system 200 may be located as referenced Figure 1 The controller 115 is located, for example, within a PCIe controller or a PCIe 6.0 controller. In some implementations, when the corresponding device 110 (e.g., as referenced) Figure 1 System 200 can be used when devices 110-b through 110-d receive data from a transmitter (e.g., from device 110-a). In some embodiments, system 200 can receive data 205-a, data 205-b, data 205-c, and data 205-d. Generally, data 205 can be referred to as chip 207, for example, the transmitter can send fixed-length data to the receiver by organizing packets into chips. In this example, receiving chip 207 requires four (4) clock cycles. In other embodiments, receiving chip 207 may require more or less than four (4) clock cycles, for example, receiving chip 207 may require one, two, three, five, six, etc., clock cycles. In some embodiments, the number of clock cycles for receiving chip 207 may depend on, as referenced Figure 1 The size of the internal data path or link 135, for example, the larger the internal data path, the fewer clock cycles required to receive the microchip 207. In some embodiments, the microchip 207 can be 2048 bits, where each data 205 consists of 512 bits. In such an embodiment, the microchip 207 may include a 242-byte data payload, 8 bytes corresponding to the CRC value, and 6 bytes corresponding to the FEC code. In other embodiments, the microchip 207 may include different numbers of bytes; for example, the data payload, CRC value, and FEC code may have more or fewer bytes. It should be noted that even if the microchip 207 may include more or fewer bytes, each microchip 207 may maintain a fixed length.

[0030] In some implementations, the FEC component 210 is to receive the flits 207, e.g., data 205-a through data 205-d, within four (4) clock cycles. In some embodiments, the FEC component 210 can perform FEC operations. In some embodiments, the system can utilize block codes for FEC operations, e.g., in block codes, a message or data to be transmitted is divided into fixed-length bits (e.g., into flits 207), and redundant bits are added for error correction. In some embodiments, the FEC component 210 can perform FEC operations using Hamming codes (e.g., block codes capable of detecting two simultaneous error bits and correcting single-bit errors), Reed-Solomon codes (e.g., block codes that can correct burst errors in received data flits 207), and low-density parity-check codes (e.g., block codes specified by a parity-check matrix containing a low density of ones (1)). In some implementations, the FEC component 210 can be capable of utilizing convolutional codes, e.g., the FEC component 210 can utilize binary convolutional codes, where an encoder processes an input bit sequence to generate an output bit sequence of arbitrary length. In some embodiments, the FEC component 210 can determine and correct errors of the flits 207. For example, the FEC component 210 can generate corrected data (e.g., data that has undergone FEC operations) 215-a through 215-d.

[0031] In some embodiments, the data 215-a through 215-d can still contain errors, e.g., the CRC values of data 215-b through 215-d can be incorrect since CRC operations have not been performed on data 215-a through 215-b. In some implementations, the FEC component 210 can also generate error data 220. In some embodiments, the FEC component 210 can determine error bit or error byte locations. In such embodiments, the error data 220 can include the error byte locations and corresponding error data. For example, the FEC component 210 can output three (3) error byte locations, e.g., output a first error byte location, a second error byte location, and a third error byte location. In some implementations, the number of error byte locations output by the FEC component 210 can depend on the number of groups that the data 205-a through 205-d are split into. For example, in some embodiments, the data payload of the flits 207 can be split into three (3) groups, each group having 81 or 82 bytes. Thus, the first error byte location can correspond to the first group, the second error byte location can correspond to the second group, and the third error byte location can correspond to the third group. In some embodiments, the data payload can be split into more or less than three (3) groups. In such embodiments, the FEC component 210 can output more or less than three (3) error byte locations, each error byte location corresponding to a different group.

[0032] In some embodiments, CRC component 130 is configured to perform a CRC operation on error data 220 received from FEC 210, e.g., CRC component 130 can determine a CRC value derived from an error byte or error byte location of flit 207. In some embodiments, the CRC operation is a type of checksum that produces a fixed-length data set based on the received data. In some embodiments, CRC component 130 can perform the CRC operation by finding the remainder of a polynomial division of the transmitted data to evaluate a check value (e.g., a CRC byte included in flit 207). In other embodiments, CRC component 130 can map error data 220 to a fixed length, e.g., a hash function. In some implementations, because the length of the CRC algorithm is fixed, each error (e.g., bit toggle) causes a known fixed change in the generated CRC value. Where system 200 determines an error byte location (e.g., error byte and error parity), system 200 can determine the effect of the error on the final CRC value.

[0033] For example, consider an illustrative case (e.g., a case for illustrative purposes only and not limiting the claims), where there are three (3) bits of input, each input having a value of ‘0’ or ‘1’, e.g., there are inputs (A, B, C), where A, B, and C can be ‘0’ or ‘1’. In some embodiments, based on a known CRC algorithm (e.g., based on the CRC algorithm used by CRC component 130 and CRC component 125), the CRC for inputs (0, 0, 0) is 0. Where the correct CRC for (A, B, C) is equal to CRC(A, 0, 0) ^ CRC(0, B, 0) ^ CRC(0, 0, C). If bit B has an error, then an error CRC value will be calculated. In some embodiments, bit B can initially have a value of ‘0’ and be toggled (e.g., the bit value can change during transmission) to a value of ‘1’. In such embodiments, CRC(0, B, 0) will not be equal to zero, e.g., because CRC(0, 0, 0) is 0, changing bit B from ‘0’ to ‘1’ will change the CRC value. Thus, an error CRC is generated. In one example, the CRC value can be corrected with exclusive OR (XOR) logic and by XORing CRC(0, ~B, 0), e.g., the CRC value can be corrected by performing an XOR operation with (0, ~B, 0). In this example, (0, ~B, 0) will be (0, 1, 0). In a second embodiment, bit B can initially have a value of ‘1’ and be toggled to a value of ‘0’. In such embodiments, the CRC for (0, ~B, 0) will be 0, e.g., changing the bit value to ‘1’ will result in an error CRC value being calculated that is 0 based on the CRC for inputs (0, 0, 0) being 0. In the second embodiment, the correct CRC can be determined by performing an XOR multiplication with CRC(0, B, 0) (i.e., CRC(0, 1, 0)), e.g., the XOR of (0, ~B, 0) and (0, B, 0) results in the corrected CRC value. Thus, in either embodiment (e.g., whether the ‘B’ was toggled from ‘0’ to ‘1’ or from ‘1’ to ‘0’), the correct CRC can be determined by performing the same XOR CRC(0, 1, 0).

[0034] The above example illustrates that a correct CRC can be generated as long as the location of the erroneous byte and erroneous bit is known. For example, FEC component 210 can output the location of the erroneous byte, CRC component 130 can look up a pre-calculated CRC value based on the erroneous location, and XOR logic 230 can receive the pre-calculated CRC value, i.e., the CRC value calculated by CRC component 125, and perform an XOR operation to correct the CRC, as described above. In some embodiments, CRC calculation may be complex and difficult, or performing CRC on 242 bytes in one cycle may not be feasible. Therefore, CRC component 130 may include, as referenced... Figure 4 The aforementioned predefined lookup table. For additional details regarding the internal processes of the CRC component 130, please refer to [link / reference needed]. Figure 4 To describe.

[0035] In some embodiments, CRC component 125 is configured to calculate a CRC value based on chip 207. As described above, because CRC component 125 receives data directly (e.g., before the FEC operation is performed), errors may exist in the chip 207 received at CRC component 125. CRC component 125 can determine the CRC value of "erroneous data" or data that otherwise contains errors. In some implementations, CRC component 125 performs a CRC operation, which is a checksum that generates a fixed-length dataset based on the received data. In some embodiments, CRC component 125 can perform a CRC operation by finding the remainder of a polynomial division of the transmitted data to evaluate the checksum (e.g., the CRC bytes included in chip 207). In other embodiments, CRC component 125 can map chip 207 to a fixed length, such as a hash function.

[0036] In some embodiments, XOR logic 230 is used to receive a CRC calculated based on error data 220 and to receive a CRC value from CRC component 125, for example, a CRC value derived from chip 207. In some embodiments, the CRC calculated based on error data 220 and the CRC value from CRC component 125 may be the same. In such embodiments, there may be no error associated with the CRC value; for example, sending data to system 200 will not produce an error. In other embodiments, XOR logic 230 may receive a CRC value from CRC component 125 that is different from the CRC value received from CRC component 130. In some embodiments, XOR logic 230 may output a correct CRC 245 based on receiving different CRC values ​​from CRC component 125 and CRC component 130, respectively. For example, as described above, if FEC component 210 outputs a second error byte position (e.g., indicating an error in bit "B"), CRC component 130 may output the value CRC(0, 1, 0) and XOR the CRC in data 205 with CRC(0, 1, 0) to obtain a correct CRC 245. In other implementations, CRC components 125 and 130 can utilize more complex algorithms. However, as long as the location of the erroneous byte is known, CRC component 130 can generate a CRC value for correcting potential errors in the CRC based on data 205.

[0037] In some embodiments, the Delay Trigger (DFF) 225 may receive data 215 (e.g., data 205 corrected by the FEC component 210). In some embodiments, the DFF 225 may delay data transmission by one (1) or more cycles. For example, in an embodiment where an error is calculated, one (1) clock cycle may be required to determine the correct CRC after the FEC component 210 and CRC component 125 output values, for example, the FEC component 210 and CRC component 125 may perform their respective error correction operations concurrently. For example, each of the FEC component 210 and CRC component 125 may occupy four (4) clock cycles. In other embodiments, the FEC component 210 and CRC component 125 may require more or less than four (4) clock cycles depending on the number of data 205 portions in the chip 207, for example, if the chip 207 is split into two (2) data 205 portions, the FEC component 210 and CRC component 125 may require two (2) clock cycles to perform the error correction operation. In some implementations, DFF 225 is optional; for example, if waiting to generate a correct CRC 245, DFF 225 can optionally delay data 215.

[0038] Figure 3 An example communication system 300 according to some example embodiments is illustrated. System 300 includes, as referenced... Figure 1and Figure 2 The CRC component 125. In some embodiments, the CRC component 125 may include XOR logic 310.

[0039] In some embodiments, CRC component 125 may receive a CRC value associated with each bit 305 of chip 207. For example, CRC component 125 may receive a first CRC value for a first bit, a second CRC value for a second bit, and so on. n The first bit n CRC values, for example, receiving the CRC value of bit 305-a of the first bit 305-a, the CRC value of bit 305-b of the second bit 305-b, and the CRC value of the third bit 305-a. n The CRC values ​​of bits 305-n. In some embodiments, each CRC value associated with a bit may be a predetermined number of bits, depending on the CRC algorithm used by the CRC component 125. For example, each CRC value associated with bit 305 may be 64 bits. In some embodiments, the number of CRC values ​​associated with bit 305 may be based on the number of bits in chip 207, as referenced. Figure 2 The number of data bits associated with the data payload in chip 207 can be used as a basis, for example. In some implementations, chip 207 may include a 242-byte data payload, or, for example, chip 207 may include 1936 bits associated with the data payload. In such an embodiment, XOR logic 310 can receive 1936 × 64 bits.

[0040] In some embodiments, XOR logic 310 can be configured to XOR the received CRC values ​​to generate a final CRC value 315. In embodiments where each CRC value associated with bit 305 is 64 bits, CRC component 125 can utilize CRC-64, such as a 64-bit Cyclic Redundancy Check algorithm. In some embodiments, XOR logic 310 can generate a CRC value with the same number of bits as the CRC value associated with the corresponding bit 305; for example, if each CRC value is 64 bits, XOR logic 310 can XOR each received CRC value associated with each bit 305 to a final CRC value 315 comprising 64 bits.

[0041] Figure 4 An example communication system 400 according to an example embodiment is illustrated. System 400 includes, as referenced... Figure 1 and Figure 2The CRC component 130. In some embodiments, the CRC component 130 includes lookup table 410 (e.g., lookup table 410-a, lookup table 410-b, and lookup table 410-c), XOR logic 415, and XOR logic 420.

[0042] In some embodiments, the CRC component 130 is used to base its decisions on received error data (e.g., as referenced). Figure 2 The error data 220 is used to generate a CRC value. For example, as referenced... Figure 2 The CRC component 130 can receive error locations from the FEC component 210. In some embodiments, the error location may be three (3) bytes, each byte representing an error location of a portion of the microchip 207, as referenced. Figure 2 As described above. For example, error position 405-a can be associated with the first group of bytes of microchip 207, error position 405-b can be associated with the second group of bytes of microchip 207, and error position 405-c can be associated with the third group of bytes of microchip 207. For example, in an embodiment with a data payload of 242 bytes, error position 405-a can be associated with the first 82 bytes of microchip 207, error position 405-b can be associated with the next 81 bytes of microchip 207, and error position 405-c can be associated with the last 81 bytes of microchip 207. (See reference...) Figure 2 The CRC component 130 can receive any number of error byte positions 405 based on the number of groups into which the chip 207 of the CRC component 130 is divided. For example, if the chip 207 is processed in four groups at the CRC component 130, then the CRC component 130 can receive four error byte positions.

[0043] In some implementations, lookup table 410 can receive the corresponding error position 405 and generate a CRC value based on the received error position 405. For example, see reference [reference]. Figure 2 In the illustrative example described (e.g., using input (A, B, C), where A, B, and C can be '0' or '1'), in one embodiment, error location 405-B can indicate the location of the error associated with the value "B". See reference... Figure 2As stated above, regardless of whether the value "B" is flipped from '0' to '1' or from '1' to '0', the error can be corrected by performing an XOR operation with the CRC value (0, 1, 0). That is, based on the location of the error at the value "B", a known CRC value (0, 1, 0) can be generated to correct the error. For example, when CRC component 130 uses a CRC algorithm with a fixed length, even if it is unknown whether the value "B" is flipped from '0' to '1' or from '1' to '0', knowing the location of the error is sufficient to correct the CRC. In one embodiment, a lookup table can store the CRC value for each corresponding error location 405. For example, lookup table 410-b can store the CRC value (0, 1, 0). When lookup table 410-b receives an error location (e.g., the error has the value "B"), CRC component 130 can use lookup table 410 to determine the corresponding CRC value (e.g., CRC value (0, 1, 0)). See reference... Figure 2 The CRC component 130 can utilize CRC-64, such as a 64-bit cyclic redundancy check algorithm. Therefore, each CRC value stored in the lookup table can consist of 64 bits. That is, since each error byte position 405 consists of eight (8) bits, the lookup table 410 can output a 64×8-bit, for example, a 64-bit CRC value for each bit of the error byte position.

[0044] In some embodiments, XOR logic 415 is used to receive the CRC value and error content 425 stored in lookup table 410. For example, XOR logic 415-b can receive the CRC value associated with error position 405-b from lookup table 410-b. In some embodiments, XOR logic 415 is used to perform an XOR operation on the stored CRC value and error content 425. As described with reference to lookup table 410, XOR logic 415 can receive the CRC value for each byte of error byte position 405, for example, receiving the 64-bit CRC value for each bit of error byte position 405. In some embodiments, lookup table 410 can generate an error-independent CRC value. For example, lookup table 410 generates a CRC value for each bit of the error byte position. In some embodiments, some bits of the error byte position indicate that there is no error at the corresponding position. For example, a generated value '1' may affect the determined CRC value, while a generated value '0' may not affect the CRC. For example, if lookup table 410 generates a CRC value (0, 1, 0), it will indicate an error at "B" but will not affect CRC values ​​that are "A" or "C". In some embodiments, the error byte content 425 may indicate the content of the error accordingly, for example, indicating an error determined by FEC component 210. In some implementations, XOR logic 415 may XOR the CRC value generated by lookup table 410 with the error content 425 to generate a CRC value associated with the error location and error content; for example, each of the CRC bits 430 may consist of 64 bits corresponding to the corresponding error location 405 and error content 425.

[0045] In some embodiments, XOR logic 420 is used to receive CRC bits 430 associated with each corresponding error position 405 and error content 425. In some embodiments, XOR logic 420 is used to XOR the received CRC bits 430 to generate a final CRC bit 440. In some embodiments, the final CRC bit 440 corresponds to as referenced. Figure 2 The CRC calculated based on error data 220. In such an embodiment, CRC component 130 can output the final CRC bits 440 to a reference... Figure 2 The XOR logic 230 is described above. Therefore, the XOR logic 230 can utilize the final CRC bit 440 to correct any errors in the CRC generated by the CRC component 125, as referenced. Figure 2 As described above. By utilizing CRC component 130, as referenced... Figure 2The system 200 can concurrently perform FEC and CRC operations at CRC component 125. In such an embodiment, the system 200 can then use the final CRC bits 440 determined by CRC component 130 to correct the CRC value generated from CRC component 125. The system 200 can also correct the CRC value by determining the error location and error byte content at FEC component 210.

[0046] Figure 5 The illustration shows an example flowchart of a method 500 for concurrently performing forward error correction (FEC) and cyclic redundancy check (CRC) operations, according to some implementation. Method 500 can be executed by processing logic including hardware, software, firmware, or any combination thereof. In some embodiments, method 500 is provided by reference... Figure 1 and Figure 2 Systems 100 and 200 are executed, for example, method 500 may be executed at controller 115 by FEC component 210, CRC component 125, CRC component 130, XOR logic 230, and delay trigger (DFF) 225. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment.

[0047] At operation 505, the receiver (e.g., as referenced) Figure 1 The receiver and / or processing logic of the device 110 can receive data bits corresponding to the first set of data, for example, receiving data bits as shown in the reference. Figure 2 The microchip 207 corresponds to data 205-a to data 205-d. In some embodiments, the receiver will also receive second data bits corresponding to the second set of data, wherein the first set of data and the second set of data have the same length; for example, each received microchip 207 may be the same size. In some embodiments, the receiver may receive data via a link (e.g., as referenced). Figure 1 The link 135 receives data. In some embodiments, the link is an example of a high-speed peripheral component interconnect (PCIe), for example, the link may communicate according to PCIe generation 6 (PCIe 6.0). In some implementations, the data bits may also include a CRC value and an FEC code; for example, each chip 207 may include a data payload and additional bits corresponding to the CRC value and FEC code to ensure reliable transmission of the data payload.

[0048] At operation 510, the processing logic (e.g., as referenced) Figure 2The FEC component 210 can perform forward error correction (FEC) on data bits in response to receiving data bits to generate error locations. See reference... Figure 2 The processing logic can determine the error location and error parity associated with the received data. In some embodiments, the processing logic can correct or modify the received data to correct detected errors. In some embodiments, the processing logic can convert erroneous data (e.g., as referenced) into erroneous data. Figure 4 The error byte position 405 or error content 425 is output to the CRC component, for example, as shown in the reference. Figure 4 The simplified CRC component 130 is described above. In some embodiments, the processing logic may output modified or corrected received bits to a delay trigger (e.g., as referenced). Figure 2 (Referring to the DFF 225). In some embodiments, the processing logic may determine one or more errors, and the DF 225 may delay the received data by one or more clock cycles. In some embodiments, the processing logic may determine that no error exists in response to performing an FEC operation; for example, no error may be associated with transmitting data over the link. In such embodiments, the processing logic may avoid generating a second CRC value in response to determining that no error exists; for example, the processing logic may avoid generating the second CRC value described in reference operation 520.

[0049] At operation 510, the processing logic (e.g., as referenced) Figure 2 The CRC component 125 can also perform a Cyclic Redundancy Check (CRC) operation on the data bits to generate a first CRC value, wherein the CRC operation and the FEC operation are performed concurrently. (See reference...) Figure 2 The system can perform CRC and FEC operations concurrently. In some embodiments, the CRC component 125 may generate incorrect (e.g., faulty) CRC values ​​because the received data has not yet been corrected by the FEC operation (e.g., because the FEC operation is performed concurrently, the CRC component 125 may perform a CRC operation on faulty data or data that has errors due to the transmission process).

[0050] At operation 515, the processing logic (e.g., as referenced) Figure 1 The CRC component 130 can determine a second CRC value after performing the FEC operation, wherein the second CRC value is based on the error location. (See reference...) Figure 2 As stated above, if the error location and error parity are known, the processing logic can correct the CRC error via CRC component 130. For example, CRC component 130 can utilize a fixed-length CRC algorithm, where the bit flip value has a fixed change for the CRC value. In some implementations, the processing logic can receive the error location, for example, as referenced...Figure 4 The received error location is 405. In some embodiments, the processing logic can determine the corresponding CRC value for the error location. For example, the CRC component 130 may include a lookup table storing multiple CRC values, where the multiple CRC values ​​include a second CRC value. Therefore, the processing logic can compare the error location with the table storing multiple CRC values ​​and determine that the second CRC value corresponds to the received error location. In some embodiments, the CRC component 130 may include multiple lookup tables, each storing multiple CRC values ​​associated with a portion of data bits. For example, the CRC component 130 may include multiple lookup tables, each lookup table and a reference... Figure 2 The different portions of the data bits are associated.

[0051] At operation 520, the processing logic can generate a third CRC value corresponding to the first set of data in response to performing a CRC operation and determining the second CRC value, for example, as referenced. Figure 2 The XOR logic 230 can XOR the first CRC value with the second CRC value to generate a third CRC value. In some embodiments, the third CRC is a correct value, for example, it is a CRC value associated with the received data bits. In some embodiments, the processing logic can use the third CRC value to correct any errors present in the data bits, for example, as referenced. Figure 2 Errors in data 215-a to data 215-d are addressed. Therefore, the processing logic can perform CRC and FEC operations concurrently, and correct the CRC once the error location is known, to help reduce overall system latency.

[0052] In some embodiments, the receiver may include a first cyclic redundancy check (CRC) component to perform a first CRC operation and generate a first CRC value on the received data bits, for example, including a reference... Figure 2 The CRC component 125 is described above. In some embodiments, the receiver may further include a forward error correction (FEC) component to perform FEC operations and determine the error location associated with the received data bits, wherein the first CRC operation and the FEC operation are performed concurrently, for example, including a reference... Figure 2 The FEC component 210 is described above. In some implementations, the receiver may further include a second CRC component coupled to the FEC component, and perform a second CRC operation, generating a second CRC value based on the determined error location, for example, including a reference... Figure 2 The CRC component 130 is described above. In some embodiments, the receiver may further include XOR logic to logically combine the first CRC value and the second CRC value, and generate a third CRC value associated with the received data bits, for example, as referenced. Figure 2The XOR logic 230 is described above. In some embodiments, the second CRC component includes a table storing a plurality of CRC values, wherein the plurality of CRC values ​​includes a second CRC value. In some embodiments, the second CRC component can receive an error location, and in response to receiving an error location, compare the error location with the table storing the plurality of CRC values, and in response to comparing the error location with a reference... Figure 2 and Figure 4 The tables are compared to determine that the second CRC value corresponds to the received error location. In some implementations, the FEC component can determine that no error exists in response to performing an FEC operation; for example, data can be transmitted error-free on link 135. In such an implementation, the second CRC component can avoid generating a second CRC value in response to the FEC component determining that no error exists; for example, since no error exists, the CRC generated by the first CRC component 125 can be correct and no additional modification is required.

[0053] Figure 6 This is a block diagram illustrating an exemplary computer system 600 according to some implementations of this disclosure. The computer system 600 executes one or more sets of instructions that cause the machine to perform any or more of the methods discussed herein. Instruction sets, instructions, etc., can refer to instructions that, when executed by the computer system 600, cause the computer system 600 to perform one or more operations on root device 106 and / or target device 120. The machine can operate as a server or client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the actions the machine should take. Furthermore, although only a single machine is illustrated, the term "machine" should also be considered as including any set of machines that individually or jointly execute sets of instructions to perform any or more of the methods discussed herein.

[0054] Computer system 600 includes processing device 602, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage device 616, which communicate with each other via bus 608.

[0055] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 602 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computer (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processing device that implements other instruction sets or combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions of computer system 100 to perform the operations discussed herein.

[0056] Computer system 600 may also include a network interface device 622 that provides communication with other machines via a network 618 (such as a local area network (LAN), intranet, extranet, or Internet). Computer system 600 may also include a display device 610 (e.g., a liquid crystal display (LCD) or cathode ray tube (CRT)), an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), and a signal generation device 620 (e.g., a speaker).

[0057] Data storage device 616 may include a non-transitory computer-readable storage medium 624 storing an instruction set of computer system 100 embodying any one or more of the methods or functions described herein. During execution of the instruction set by computer system 600, the instruction set may also reside wholly or at least partially in main memory 604 and / or processing device 602, which also constitute computer-readable storage media. The instruction set may also be transmitted or received on network 618 via network interface device 622.

[0058] While an example of computer-readable storage medium 624 is shown as a single medium, the term "computer-readable storage medium" can include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store a set of instructions. The term "computer-readable storage medium" can include any medium capable of storing, encoding, or carrying a set of instructions for machine execution and causing a machine to perform any or more methods of this disclosure. The term "computer-readable storage medium" can include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0059] Many details have been set forth in the foregoing description. However, it will be apparent to those skilled in the art who will benefit from this disclosure that this disclosure can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring this disclosure.

[0060] Some parts of the specific implementation are presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that can produce the desired result. These operations require physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for common use.

[0061] However, it can be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specified, it should be understood that throughout the description, discussions using terms such as “authenticate,” “provide,” “receive,” “identify,” “determine,” “send,” and “enable” refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computer system’s memory or registers into other data similarly represented as physical quantities within the computer system’s memory, registers, or other such information storage, transmission, or display devices.

[0062] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, optical disc read-only memory (CD-ROM), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions.

[0063] The terms “example” or “exemplary” as used herein mean as an example, instance, or illustration. Any aspect or design described herein as an “example” or “exemplary” is not necessarily to be construed as superior to other aspects or designs. Rather, the term “example” or “exemplary” is used to present concepts in a specific manner. The term “or” as used in this application is intended to mean inclusive or “not exclusive” or “…”. That is, unless otherwise stated or the context clearly indicates, “X comprises A or B” is intended to mean any natural inclusive arrangement. That is, if X comprises A; X comprises B; or X comprises both A and B, then in any of the foregoing cases, “X comprises A or B” holds true. Furthermore, the articles “a” and “an” as used in this application and the appended claims can generally be interpreted as “one or more” unless otherwise stated or clearly indicated from the context as a single form. In addition, the use of the terms “an implementation” or “a realization” throughout the document does not mean the same implementation unless otherwise described. The terms “first,” “second,” “third,” “fourth,” etc., as used herein are intended as labels to distinguish different elements and do not necessarily have an ordinal meaning based on their numerical names.

[0064] For simplicity, the methods herein are described as a series of actions or operations. However, actions according to this disclosure can occur in various sequences and / or concurrently, and together with other actions not described or illustrated herein. Furthermore, not all actions shown may be required to implement a method according to the disclosed subject matter. Moreover, those skilled in the art will understand and recognize that these methods can also be represented by a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the methods disclosed in this specification can be stored on an article of art to facilitate the transport and transfer of these methods to a computing device. The term "article of art" as used herein is intended to encompass any computer program accessible from any computer-readable device or storage medium.

[0065] In other implementations, one or more processing devices are disclosed for performing the operations described above. Furthermore, in implementations of this disclosure, a non-transitory computer-readable storage medium stores instructions for performing the operations of the described implementations. Similarly, in other implementations, a system for performing the operations of the described implementations is also disclosed.

[0066] It should be understood that the above description is illustrative and not limiting. Other implementations will become apparent to those skilled in the art upon reading and understanding the above description. Therefore, the scope of this disclosure can be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A receiver, coupled to a link and including control logic, is configured to: Receive the data bits corresponding to the first group of data; Based on the received data bits, a forward error correction (FEC) operation is performed on the data bits to generate an error location, and a cyclic redundancy check (CRC) operation is performed on the data bits to generate a first CRC value, wherein the CRC operation and the FEC operation are performed concurrently. After performing the FEC operation, a second CRC value is determined based on the error location; as well as After determining the second CRC value, a third CRC value corresponding to the first set of data is generated based on the second CRC value.

2. The device according to claim 1, wherein, in order to generate the third CRC value, the control logic is configured as follows: Perform an XOR operation using the first CRC value and the second CRC value.

3. The device of claim 1, wherein the second CRC value is determined at a CRC component, the CRC component including a table storing a plurality of CRC values, and wherein the plurality of CRC values ​​includes the second CRC value.

4. The device of claim 3, wherein, in order to determine the second CRC value, the CRC component is configured to: Receive the error location; Based on the received error location, the error location is compared with the table storing the plurality of CRC values; and Based on comparing the error location with the table, it is determined that the second CRC value corresponds to the received error location.

5. The device according to claim 1, wherein the data bits corresponding to the first set of data include a CRC value and an FEC code.

6. The device of claim 1, wherein the link is a high-speed peripheral component interconnect (PCIe).

7. The device according to claim 1, wherein the control logic is configured to: In response to performing the FEC operation, it is determined that no error exists; and Based on the certainty that no error exists, the generation of the second CRC value is avoided.

8. A method comprising: The device receives the data bits corresponding to the first set of data at its receiver. Based on the received data bits, a forward error correction (FEC) operation is performed on the data bits to generate an error location, and a cyclic redundancy check (CRC) operation is performed on the data bits to generate a first CRC value, wherein the CRC operation and the FEC operation are performed concurrently. After performing the FEC operation, a second CRC value is determined based on the error location; as well as After performing the CRC operation and determining the second CRC value, a third CRC value corresponding to the first set of data is generated based on the second CRC value.

9. The method according to claim 8, further comprising: An XOR operation is performed using the first CRC value and the second CRC value, wherein the generation of the third CRC is at least partially based on the performance of the XOR operation.

10. The method of claim 8, wherein the second CRC value is determined at a CRC component, the CRC component comprising a table storing a plurality of CRC values, the plurality of CRC values ​​including the second CRC value.

11. The method of claim 10, further comprising: The error location is received at the CRC component; Based on the received error location, the error location is compared with the table storing the plurality of CRC values; as well as Based on comparing the error location with the table, it is determined that the second CRC value corresponds to the received error location.

12. The method of claim 8, wherein the data bits corresponding to the first set of data include a CRC value and an FEC code.

13. The method of claim 8, wherein the receiver is coupled to a link, and wherein the link is a high-speed peripheral component interconnect (PCIe).

14. The method of claim 8, further comprising: In response to performing the FEC operation, it was determined that no error was present; as well as Based on the certainty that no error exists, the generation of the second CRC value is avoided.

15. A receiver, comprising: The first cyclic redundancy check (CRC) component is used to perform a first CRC operation on the received data bits and generate a first CRC value; A forward error correction (FEC) component is used to perform an FEC operation and determine the error location associated with the received data bits, wherein the first CRC operation and the FEC operation are performed concurrently; A second CRC component is coupled to the FEC component and is used to perform a second CRC operation and generate a second CRC value based on the determined error location; as well as The XOR logic is used to logically combine the first CRC value and the second CRC value, and generate a third CRC value associated with the received data bits.

16. The receiver of claim 15, wherein the second CRC component further includes a table storing a plurality of CRC values, and wherein the plurality of CRC values ​​includes the second CRC value.

17. The receiver of claim 16, wherein the second CRC component is used for: Receive the error location; Based on the received error location, the error location is compared with the table storing the plurality of CRC values; and Based on comparing the error location with the table, it is determined that the second CRC value corresponds to the received error location.

18. The receiver of claim 15, wherein the received data bits correspond to a first set of data including a CRC value and an FEC code.

19. The receiver according to claim 15, wherein: The FEC component is used to determine that no error exists in response to performing the FEC operation; as well as The second CRC component is used to avoid generating the second CRC value based on the determination by the FEC component that no error exists.

20. The receiver of claim 15, wherein the receiver is coupled to a link, and wherein the link is a high-speed peripheral component interconnect (PCIe).

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