Performance analysis method and device for cross-architecture semantic equivalence instruction stream, and storage medium

Abstract

The invention provides a performance analysis method and device for a cross-architecture semantic equivalence instruction stream and a storage medium, and the method comprises the steps: taking a high-level language program as input, aiming at a plurality of target architectures, generating a multi-dimensional semantic equivalence instruction stream set from a high-level language form to an intermediate representation and then to an assembly code through a compiler; based on semantic equivalence instruction streams of code units with different granularities and compiler debugging information, establishing a mapping relationship between a target region in a source code and an intermediate representation and assembly codes, and forming a cross-hierarchy equivalence region fully-connected graph; and based on the semantic equivalence instruction stream set and the cross-level equivalence region fully-connected graph, automatically embedding a performance monitoring code at the boundary of the target region, and carrying out performance test on the elastic region. According to the method, the accurate performance test of the cross-architecture semantic equivalence instruction stream can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer architecture, and in particular to a performance analysis method and device for cross-architecture semantically equivalent instruction streams, and a storage medium and program product. BACKGROUND

[0002] An instruction stream refers to a sequence of instructions followed by a computer when executing a program, which is a basic component of program execution and reflects the running characteristics of a computer architecture. In a computer system, different processor architectures often rely on their unique instruction sets to generate instruction streams. Therefore, the design of an instruction set has a crucial impact on the composition, execution efficiency, and performance optimization of an instruction stream. Different architectures define the basic elements of machine language, and these elements implement various operations of a computer through carefully designed instruction streams. For example, architectures such as X86, RISC-V, and LoongArch each have unique instruction set characteristics, and thus exhibit their respective architectural features and advantages in the generated instruction streams. By comparing and analyzing the instruction streams generated from the same source program under different architectures, it can be found that these instruction streams are semantically equivalent, referred to as semantically equivalent instruction streams. However, in the automatic analysis of semantically equivalent instruction streams, there are still many challenges, and it is difficult to comprehensively and effectively handle cross-architecture instruction stream analysis. SUMMARY

[0003] To address the deficiencies of the prior art, the present application provides a performance analysis method, device, storage medium, and program product for cross-architecture semantically equivalent instruction streams, which can achieve accurate performance analysis of instruction streams of different architectures.

[0004] In one aspect, the present application provides a performance analysis method for cross-architecture semantically equivalent instruction streams, comprising the following steps:

[0005] Taking a high-level language program as input, a multi-dimensional semantically equivalent instruction stream set is generated from the high-level language form to the intermediate representation and then to the assembly code for multiple target architectures through a compiler, wherein the multi-dimensional semantically equivalent instruction stream set contains semantically equivalent instruction streams of different granularity code units, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures;

[0006] Based on the semantically equivalent instruction streams of different granularity code units and the compiler debugging information, a mapping relationship between the target region in the source code and the intermediate representation and the assembly code is established to form a full-connected graph of cross-level equivalent regions.

[0007] Based on the semantic equivalent instruction flow set and the cross-level equivalent region full connectivity graph, performance monitoring code is automatically embedded at the target region boundary, and performance testing and comparison analysis are performed on the elastic region; wherein the elastic region is selected according to the code unit.

[0008] In an embodiment of the present application, the code unit includes an atomic statement, wherein the semantic equivalent instruction flow of the atomic statement is generated, and contains:

[0009] Locate the line number and column number of the atomic statement in the source code;

[0010] Call the compiler to generate an intermediate representation, find the instruction sequence corresponding to the atomic statement in the intermediate representation, and record the position and content;

[0011] Compile the intermediate representation into assembly code, find the instruction sequence corresponding to the atomic statement in the assembly code, and record the position and content;

[0012] Establish the hierarchical mapping relationship of the atomic statement in the source code, the intermediate representation, and the assembly code.

[0013] In an embodiment of the present application, the code unit includes a single compound statement, wherein the semantic equivalent instruction flow of the single compound statement is generated, and contains:

[0014] Parse the syntax structure of the single compound statement, decompose it into multiple atomic statements, and record the position of each atomic statement;

[0015] Build the semantic equivalent instruction flow of each atomic statement respectively;

[0016] Summarize the hierarchical mapping relationship of each atomic statement, and establish the overall mapping relationship of the single compound statement in the source code, the intermediate representation, and the assembly code.

[0017] In an embodiment of the present application, the code unit includes a specific statement region, and the specific statement region is a continuous code block composed of one or more atomic statements or compound statements in the source code; wherein the semantic equivalent instruction flow of the specific statement region is generated, and contains:

[0018] For each atomic statement in the region, determine its semantic equivalent instruction flow and the corresponding hierarchical mapping relationship;

[0019] For each compound statement in the region, build its semantic equivalent instruction flow and the corresponding hierarchical mapping relationship;

[0020] Summarize all hierarchical mapping relationships in the region, and establish the overall mapping relationship of the specific statement region in the source code, the intermediate representation, and the assembly code.

[0021] In an embodiment of the present application, the code unit comprises a whole function body, the function body being a complete code composed of one or more atomic statements and compound statements in the source code; wherein the semantic equivalent instruction stream of the whole function body is generated, containing:

[0022] For each atomic statement in the function body, the semantic equivalent instruction stream and the corresponding hierarchical mapping relationship are determined;

[0023] For each compound statement in the function body, the semantic equivalent instruction stream and the corresponding hierarchical mapping relationship are determined;

[0024] For each specific statement area in the function body, the semantic equivalent instruction stream and the corresponding hierarchical mapping relationship are determined;

[0025] All hierarchical mapping relationships in the function body are summarized to establish the overall mapping relationship of the function body in the source code, the intermediate representation and the assembly code.

[0026] In an embodiment of the present application, the method for generating the full connectivity graph across the hierarchical equivalent areas contains:

[0027] According to the semantic equivalent instruction stream of the code unit of different granularities that has been constructed, the instruction sequence corresponding to the target area of the source code is located in the intermediate representation and the assembly code respectively;

[0028] Combined with the compiler debugging information, the line number of the target area, the position of the intermediate representation and the position of the assembly code are one-to-one bound;

[0029] The complete mapping relationship from the target area to the intermediate representation and then to the assembly code is constructed to form the full connectivity graph across the hierarchical equivalent areas, wherein each node corresponds to a code unit and the edge represents the mapping relationship between different hierarchical levels.

[0030] In an embodiment of the present application, the compiler debugging information specifically refers to enabling the debugging information generation option when calling the LLVM or GCC compiler to obtain the metadata file containing the corresponding relationship between the source code line number and the intermediate representation instruction and the assembly code instruction.

[0031] In an embodiment of the present application, automatically embedding the performance monitoring code at the boundary of the target statement in the source code comprises: inserting a timestamp acquisition function and a clock cycle counter at the starting line and the ending line of the target statement, and obtaining the performance data of the target statement by calculating the timestamp difference and the clock cycle difference between the starting line and the ending line.

[0032] In an embodiment of the present application, for the same target architecture, the semantic equivalent instruction stream under the same architecture is generated by adjusting the optimization stage and the instruction set option of the compiler;

[0033] For cross-architecture scenarios, by switching compilers for different target architectures, semantically equivalent instruction streams across architectures can be generated;

[0034] In one embodiment of the present invention, an initial instruction stream is generated by enabling the compilation configuration of all optional instruction sets; the assembly mnemonics in the initial instruction stream are traversed, and if an instruction belongs to an optional instruction set, the optional instruction set is disabled and a new instruction stream is generated by recompiling; after traversing all optional instruction sets, a set of semantically equivalent instruction streams under the same architecture is finally generated.

[0035] In another aspect, the present invention provides a performance analysis apparatus for cross-architecture semantically equivalent instruction streams, comprising:

[0036] The instruction stream construction module is used to take a high-level language program as input and generate a set of semantically equivalent instruction streams from high-level language form to intermediate representation and then to assembly code through the compiler for multiple target architectures. The set of semantically equivalent instruction streams includes semantically equivalent instruction streams of code units with different granularities, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures.

[0037] The instruction flow localization module is used to establish the mapping relationship between target regions in the source code and intermediate representations and assembly code based on semantically equivalent instruction flows of code units of different granularities and compiler debugging information, forming a fully connected graph of cross-level equivalent regions;

[0038] The performance analysis module is used to automatically embed performance monitoring code at the boundary of the target region based on the semantically equivalent instruction stream set and the fully connected graph of cross-level equivalent regions, to perform performance testing and performance comparison analysis on the elastic region; wherein, the elastic region is selected according to the code unit.

[0039] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the above-described method.

[0040] In another aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the performance analysis method for cross-architecture semantically equivalent instruction streams described above.

[0041] As can be seen from the above solutions, the advantages of the present invention are:

[0042] This invention provides a cross-architecture semantic equivalence instruction flow performance analysis method. For multiple target architectures, it generates a multi-dimensional semantic equivalence instruction flow set from high-level language forms to intermediate representations and then to assembly code, based on different granularity code units of the source program. Based on the semantic equivalence instruction flows of different granularity code units and compiler debugging information, it establishes a mapping relationship between target regions in the source code and intermediate representations and assembly code, forming a fully connected graph of cross-level equivalence regions. Based on the semantic equivalence instruction flow set and the fully connected graph of cross-level equivalence regions, it automatically embeds performance monitoring code at the boundaries of the target regions to perform performance testing on flexible regions. This method accurately locates source code-level semantic equivalence instruction flows and performs precise performance testing by constructing a multi-dimensional semantic equivalence instruction flow graph. It can realize cross-level equivalence region instruction flows, track the transformation process of programs from high-level languages ​​to low-level languages, construct fully connected graphs between architectures, support variable-granularity equivalence instruction flow analysis, automatically reduce performance bottlenecks, and identify key performance difference characteristics. This method provides strong support for chip design and compiler optimization, significantly improving efficiency and accuracy. Attached Figure Description

[0043] Figure 1 A schematic diagram of the overall flow of a performance analysis method for cross-architecture semantically equivalent instruction streams provided by an embodiment of the present invention is shown.

[0044] Figure 2 A schematic diagram of the overall structure of a cross-architecture semantic equivalence instruction stream performance analysis device provided in an embodiment of the present invention is shown.

[0045] The attached figures are labeled as follows:

[0046] 300: A cross-architecture semantically equivalent instruction stream performance analysis device;

[0047] 310: Indicator Stream Building Module;

[0048] 320: Indicator flow positioning module;

[0049] 330: Performance Analysis Module. Detailed Implementation

[0050] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0051] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] Current performance analysis primarily targets the same architectural pattern. However, under the same architecture, existing performance analysis methods cannot automatically generate equivalent comparative data for the same program semantic region. Firstly, under the same architecture, for the same program slice, the instruction flows generated by different compilers have equivalent semantics, but their layouts differ significantly, directly resulting in performance differences. Current performance analysis methods lack flexibility in their analysis targets, failing to flexibly select the scope of target program statements and program regions, thus failing to generate accurate region performance data. Secondly, current performance analysis does not support recursive analysis. When a region contains complex control flow or calls, it cannot automatically narrow down and pinpoint deeper performance differences based on the instruction flow differences within the current region. Thirdly, while current performance analysis can compare differences between assembly codes, it cannot deduce the compiler-side causes leading to the instruction flow layout. These problems often necessitate step-by-step filtering and manual adjustments to focus on the target region during program debugging and optimization, resulting in low efficiency.

[0053] In the field of modern processor design, different architectures each possess unique advantages and characteristics in their instruction sets, providing abundant possibilities for performance optimization and architectural innovation. However, existing performance analysis methods do not support cross-architecture compatibility, making it difficult to conduct performance analysis across different architectures. When performing performance tuning across different architectures, developers face difficulties in manual debugging and data integration, hindering the formation of effective analysis frameworks or standards, further increasing the complexity of development and optimization work. Cross-architecture performance analysis, however, has significant value. It not only exposes differences in instruction flow and processor architecture but also helps uncover the potential for compiler optimization. However, cross-architecture performance analysis first faces the challenge of characterizing program regions that can be analyzed at equal rates; secondly, it requires effectively reducing the scope to a reasonable level to minimize the cost of manual analysis; and more importantly, performance data formats generated within the same architecture are often incompatible, preventing direct exchange and comparison.

[0054] To address this issue, this invention presents a performance analysis method for cross-architecture semantically equivalent instruction flows, supporting both intra-architecture and cross-architecture modes. This method performs in-depth analysis of multi-architecture code to construct a multi-dimensional semantically equivalent instruction flow graph for high-level language code. During the construction process, leveraging compiler features, it can accurately locate the semantically equivalent instruction flow at the source code level and perform precise performance testing on its range. Ultimately, based on detailed analysis data, it achieves automated and precise analysis of cross-architecture semantically equivalent instruction flows, providing strong technical support for performance optimization and architectural innovation in processor design. The following section will detail this performance analysis method for cross-architecture semantically equivalent instruction flows.

[0055] refer to Figure 1 As shown, Figure 1 This diagram illustrates the overall flow of a performance analysis method for cross-architecture semantically equivalent instruction streams provided by an embodiment of the present invention.

[0056] A performance analysis method for cross-architecture semantically equivalent instruction streams includes the following steps:

[0057] Step S1: Taking a high-level language program as input, for multiple target architectures, the compiler generates a multi-dimensional semantically equivalent instruction stream set from high-level language form to intermediate representation and then to assembly code. The multi-dimensional semantically equivalent instruction stream set includes semantically equivalent instruction streams of code units with different granularities, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures.

[0058] Application performance is determined by both the compiler and the processor architecture. Different combinations of compiler and processor architectures will produce different levels of program instruction flows, such as high-level language representations, different intermediate representations, and assembly code. For regions with the same program semantics, the semantics of instruction flows at different levels are equivalent. Therefore, in the process of compiling a program from a high-level language to a processor-specific low-level language, it is necessary to accurately define and track the transformation process of the target program regions, and define the mapping relationship from the specified program regions to the basic block regions of the intermediate representations, and then to the basic block regions of the assembly code.

[0059] In one embodiment, taking a high-level language program as input, a multi-dimensional semantically equivalent instruction stream set is generated by the compiler, ranging from high-level language form to intermediate representation (IR) and then to assembly code, for both intra-architecture and cross-architecture scenarios. For the same target architecture, semantically equivalent instruction streams under the same architecture are generated by adjusting the compiler's optimization stage and instruction set options. Semantically equivalent instruction streams with different optimization stages and instruction set options under the same architecture are fully interconnected, constructing an optimization and performance analysis system. Simultaneously, for different instruction set options within the same architecture, connectivity between various instruction streams is established, forming a comprehensive optimization and performance analysis system. For cross-architecture scenarios, cross-architecture instruction streams semantically equivalent to the original architecture are generated by switching the compiler for the target architecture. Semantically equivalent instruction streams between different architectures are fully interconnected. By comparing and analyzing the instruction streams generated under different architectures, a cross-architecture semantic mapping relationship is established to ensure semantic consistency. Specifically, this includes constructing a cross-level mapping relationship from high-level language to intermediate representation and then to assembly code, supporting peer-to-peer analysis between different architectures. By constructing a fully connected graph of cross-level instruction flows that can be analyzed on an equal footing across different architectures, developers can intuitively compare performance differences between different architectures.

[0060] In one embodiment, semantically equivalent instruction streams are generated based on code units of different granularities. During the compilation process from high-level language to assembly code, the cross-level semantically equivalent instruction stream of a specified granularity region consists of the semantically equivalent instruction streams of all its statements. Specifically, it includes four types of granularity code units: atomic statements, single compound statements, specific statement regions, and the entire function body. An atomic statement is an indivisible statement; a single compound statement region consists of a compound statement in a high-level language, which contains one or more atomic statements; a specific statement region consists of a specified high-level language code region, which contains one or more single statements or compound statements, or a combination of both; a function body consists of one or more basic statements and compound statements. The semantically equivalent instruction stream of an atomic statement consists of its entire representation during the compilation process from high-level language form to assembly code; the semantically equivalent instruction stream of a compound statement consists of the semantically equivalent instruction streams of the atomic statements it contains; the semantically equivalent instruction stream of a specific statement region consists of the semantically equivalent instruction streams of all statements within it. The semantically equivalent instruction stream of a function body consists of the semantically equivalent instruction streams of all basic statements and compound statements within the function body. A function body can contain multiple basic statements and compound statements, each with its corresponding semantically equivalent instruction stream. By constructing a semantically equivalent instruction stream for the function body, it is ensured that the semantics of the function body remain consistent across different compilation stages and architectures, unaffected by compiler optimizations.

[0061] Atomic statements are the most basic units of program execution. Constructing a semantically equivalent instruction stream for an atomic statement requires accurately recording its location in the source code, as well as its corresponding intermediate representation and assembly code region during compilation. First, the source code is read and parsed to locate the atomic statement, recording its line and column numbers. Next, the compiler converts the source code into an intermediate representation (IR), searching for the instruction sequences corresponding to the atomic statements within the IR, and recording the positions and contents of these sequences. The IR is further compiled into assembly code, where the corresponding instruction sequences are found and their positions and contents are recorded. Finally, a hierarchical mapping relationship is established between the atomic statement and the source code, intermediate representation, and assembly code.

[0062] Compound statements consist of multiple atomic statements, such as loops, conditional statements, or function calls. Constructing a semantically equivalent instruction stream for a compound statement requires decomposing it into multiple atomic statements and building a semantically equivalent instruction stream for each atomic statement separately. First, the syntax structure of a single compound statement is read and parsed, decomposing it into multiple atomic statements, and the position of each atomic statement in the source code is recorded. Then, for each atomic statement, its semantically equivalent instruction stream is constructed using the above process, and the position of each atomic statement in the source code, as well as its corresponding IR and assembly code regions, are recorded. Finally, the hierarchical mapping relationships of all atomic statements are summarized to establish the overall mapping relationship of the single compound statement in the source code, intermediate representation, and assembly code, ensuring the semantic equivalence of the compound statement in the source code, IR, and assembly code.

[0063] To ensure that the semantic equivalence of specific statement regions and function bodies remains unchanged during compilation optimization, precise semantic analysis of each statement is required during compilation to ensure semantic consistency across different levels (high-level language, IR, and assembly code). A multi-level mapping relationship is established from high-level language to IR and then to assembly code to ensure the semantic equivalence of each statement across different levels. Through this mapping relationship, semantic equivalence analysis can be performed across different levels, ensuring that the optimized code remains semantically consistent with the original code.

[0064] Specifically, the specific statement region is a continuous code block in the source code consisting of one or more atomic or compound statements. Generating a semantically equivalent instruction stream for the specific statement region includes: reading and parsing the syntactic structure of the specific statement region, decomposing it into multiple atomic and compound statements, and recording the position of each atomic and compound statement in the source code. For each atomic statement within the region, its semantically equivalent instruction stream and corresponding hierarchical mapping relationship are determined using the aforementioned method for constructing semantically equivalent instruction streams for atomic statements; for each compound statement within the region, its semantically equivalent instruction stream and corresponding hierarchical mapping relationship are constructed using the aforementioned method for constructing semantically equivalent instruction streams for single compound statements. Finally, all hierarchical mapping relationships within the region are summarized to establish the overall mapping relationship of the specific statement region in the source code, intermediate representation, and assembly code.

[0065] The function body is a complete piece of code in the source code consisting of one or more atomic statements and compound statements. Generating the semantically equivalent instruction stream of the entire function body specifically includes: reading and parsing the syntax structure of the function body, decomposing it into multiple atomic statements, compound statements, and specific statement regions, and recording the position of each atomic statement, compound statement, and specific statement region in the source code. For each atomic statement in the function body, its semantically equivalent instruction stream and corresponding hierarchical mapping relationship are determined using the method described above for constructing the semantically equivalent instruction stream of a single compound statement; for each compound statement in the function body, its semantically equivalent instruction stream and corresponding hierarchical mapping relationship are determined; for each specific statement region in the function body, its semantically equivalent instruction stream and corresponding hierarchical mapping relationship are determined. Finally, all hierarchical mapping relationships within the function body are summarized to establish the overall mapping relationship of the function body in the source code, intermediate representation, and assembly code.

[0066] Step S2: Based on the semantically equivalent instruction streams of code units of different granularities and compiler debugging information, establish the mapping relationship between target regions and intermediate representations and assembly code in the source code, and form a fully connected graph of cross-level equivalent regions.

[0067] A fully connected graph of cross-level equivalence regions is a network structure used to represent semantic equivalence relationships between different levels (source code, IR, assembly code). Constructing a fully connected graph requires connecting semantic equivalence regions at different levels to form a complete mapping network.

[0068] In one embodiment, based on the semantically equivalent instruction streams of code units at different granularities, instruction sequences that completely correspond to the target region in the source code are located in the intermediate representation and assembly code, respectively. Then, using compiler features, debugging information is obtained. Combined with the compiler debugging information, the line numbers of the target region, the positions of the intermediate representation and the assembly code are bound one-to-one, thereby achieving precise location of semantically equivalent instruction streams at different compilation stages. In one embodiment, when calling the LLVM or GCC compiler, the debugging information generation option is enabled to obtain a metadata file containing the correspondence between source code line numbers and intermediate representation instructions and assembly code instructions. Finally, a complete mapping relationship is constructed from the target region to the instruction sequence of the intermediate representation, and then to the instruction sequence of the assembly code, forming a fully connected graph of cross-level equivalent regions, where each node corresponds to a code unit, and edges represent the mapping relationship between different levels.

[0069] Step S3: Based on the semantically equivalent instruction stream set and the fully connected graph of cross-level equivalent regions, automatically embed performance monitoring code at the boundary of the target region, perform performance testing on the elastic region, and conduct performance comparison analysis; wherein, the elastic region is selected according to the code unit.

[0070] By automatically embedding performance monitoring code at the boundaries of target statements in the source code, precise performance testing of elastic regions is achieved, generating corresponding performance test information. The range of the elastic region can be selected based on code units as needed, supporting multi-granularity performance evaluation from single atomic statements to the entire function body. The range of the elastic region can be defined as needed, including single atomic statements, compound statements, specific statement regions, and the entire function body. This flexibility allows performance evaluation to adapt to different granularity analysis needs, whether it's macro-level function performance analysis or micro-level instruction performance analysis. The semantically equivalent instruction flow at each granularity is constructed through multi-dimensional analysis, ensuring semantic equivalence between different compilation stages (such as source code, intermediate representation, and assembly code), providing end-to-end performance data from source code to assembly code. The final analysis report includes individual statement and overall performance test information. The individual statement report extracts the semantically equivalent instruction streams of atomic or compound statements under the same and cross-architecture conditions, generating a performance comparison table that includes instruction usage (such as whether AVX instructions are called). The overall report summarizes the individual statement report data of all code units within a specific statement region or function body, generating an overview graph containing the overall execution time of the region / function and the performance ratio of each sub-unit. Finally, combined with the cross-level equivalent region connectivity graph, the report marks the source code line number, intermediate representation instructions, and assembly code instructions corresponding to the performance bottleneck, forming a full-link analysis conclusion of "source code - intermediate representation - assembly code - performance data".

[0071] In one embodiment, a timestamp acquisition function (clock function) and a clock cycle counter (rdtsc instruction) are inserted into both the start and end lines of the target statement in the source code. Performance data of the target statement is obtained by calculating the timestamp difference and clock cycle difference between the start and end lines. This method can accurately measure the execution time of the target statement, thereby providing data support for performance analysis.

[0072] Furthermore, by combining the generated multidimensional semantically equivalent instruction flow set with performance test information, a semantically equivalent instruction flow graph with source code-level single statement granularity is iteratively established. This process not only covers the entire link analysis from high-level language to assembly code, ensuring accurate tracking of semantic equivalence across different levels, but also ensures semantic equivalence under different architectures and optimization strategies by constructing cross-level mapping relationships from high-level language to intermediate representation and then to assembly code.

[0073] Furthermore, performance data is collected for cross-architecture performance comparison and analysis. Data collected from different flows is time-base normalized, frequency-normalized, and highlighted for differences. Performance information such as cycle time, instruction count, and IPC is collected on the target platform, and a formatted performance analysis report is output. Specifically, by calling the Hardware Performance Monitoring Unit (PMU) of different target architecture processors, core metrics such as instruction cycle time, instruction count, instructions per clock cycle, cache hit rate, and branch prediction error rate are collected. High-precision timestamps and clock cycle counters are automatically embedded at the boundaries of semantically equivalent instruction flows (such as the start / end lines of atomic statements) to record the start and end times of instruction flow execution and calculate the actual execution time. For the differences in clock frequency between different target architecture processors, a "normalized cycle time" is used as a unified benchmark. If the target platform supports dynamic frequency adjustment, the current core frequency is obtained in real time through the operating system interface to correct for cycle time deviations caused by frequency fluctuations. This study compares the performance metrics of the same semantically equivalent instruction flow across different architectures. By combining this with a multi-dimensional semantically equivalent instruction flow graph, performance differences are correlated with instruction set characteristics. In the fully connected graph of cross-level equivalence regions, nodes (code units) with performance deviation rates exceeding a threshold are color-coded, and critical paths are marked. An abstract interface encapsulates the performance data output formats of compilers for different architectures, unifying the parsing of debugging information in the Intermediate Representation (IR) to ensure consistency in the mapping relationships between source code line numbers, IR instructions, and assembly instructions across architectures. Finally, a performance comparison analysis report for different architectures is output.

[0074] In summary, the cross-architecture semantically equivalent instruction flow performance analysis method provided in this embodiment firstly generates a multi-dimensional semantically equivalent instruction flow set, from high-level language form to intermediate representation and then to assembly code, based on different granularity code units of the source program for multiple target architectures. This process accurately captures all semantically equivalent instruction flows generated by the target function by enabling all instruction sets in multiple target architectures, thus constructing a multi-dimensional semantically equivalent instruction flow system and ensuring full connectivity across different compilation stages, different instruction set options within the same architecture, and different architectures. Then, combining compiler characteristics, after each generation of a new semantically equivalent instruction flow, the source code-level semantically equivalent instruction flow at different stages is normalized and located. Using a single statement at the source code level as the granularity, the semantically equivalent instruction flow at different compilation stages (such as high-level language, intermediate representation, and assembly code) is accurately located. Simultaneously, by automatically embedding performance monitoring code at the boundaries of target statements at the source code level, accurate performance testing of flexible regions is achieved. Finally, by combining multi-level semantically equivalent instruction flows and performance test information, a semantically equivalent instruction flow graph with source code-level single-statement granularity is iteratively constructed. This covers the entire chain analysis from high-level languages ​​to assembly code, and through multi-dimensional full connectivity, it ensures semantic equivalence under different architectures and optimization strategies, achieving automatic analysis of semantically equivalent instruction flows across architectures, multiple levels, multiple dimensions, and source code levels. This method accurately locates source code-level semantically equivalent instruction flows and performs precise performance testing by constructing a multi-dimensional semantically equivalent instruction flow graph. It can realize cross-level equivalent region instruction flows, trace the program's transformation process from high-level to low-level languages, construct a fully connected graph between architectures, support variable-granularity equivalent instruction flow analysis, and automatically reduce performance bottlenecks and identify key performance difference characteristics. This method provides strong support for chip design and compiler optimization, significantly improving efficiency and accuracy.

[0075] The following are method embodiments corresponding to the above method embodiments, such as... Figure 2 As shown, Figure 2 A schematic diagram of a cross-architecture semantically equivalent instruction flow performance analysis device 300 provided in an embodiment of the present invention is shown. This method implementation can be implemented in conjunction with the above-described device implementation. The relevant technical details mentioned in the above method implementation remain valid in this device implementation, and will not be repeated here to avoid repetition.

[0076] A cross-architecture semantically equivalent instruction stream performance analysis device 300 includes:

[0077] The instruction stream construction module 310 is used to take a high-level language program as input and generate a set of semantically equivalent instruction streams from high-level language form to intermediate representation and then to assembly code for multiple target architectures through a compiler. The set of semantically equivalent instruction streams includes semantically equivalent instruction streams of code units with different granularities, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures.

[0078] The instruction flow location module 320 is used to establish the mapping relationship between the target region in the source code and the intermediate representation and assembly code based on the semantically equivalent instruction flow of code units of different granularities and compiler debugging information, forming a fully connected graph of cross-level equivalent regions.

[0079] The performance analysis module 330 is used to automatically embed performance monitoring code at the boundary of the target region based on the semantically equivalent instruction stream set and the fully connected graph of cross-level equivalent regions, and to perform performance testing on the elastic region; wherein the elastic region is selected according to the code unit.

[0080] This device embodiment can be implemented in conjunction with the implementation methods described above. The relevant technical details mentioned in the implementation methods of the above embodiments remain valid in the implementation methods of this device embodiment, and will not be repeated here to avoid repetition.

[0081] In addition, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the performance analysis method for cross-architecture semantically equivalent instruction streams disclosed in the above embodiments.

[0082] In addition, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the performance analysis method for cross-architecture semantically equivalent instruction streams disclosed in the above embodiments.

[0083] Furthermore, it should be understood that the storage medium in the device embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0084] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A performance analysis method for cross-architecture semantically equivalent instruction streams, characterized in that, Includes the following steps: Taking a high-level language program as input, for multiple target architectures, the compiler generates a multi-dimensional semantically equivalent instruction stream set from high-level language form to intermediate representation and then to assembly code. The multi-dimensional semantically equivalent instruction stream set contains semantically equivalent instruction streams of code units with different granularities, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures. Based on the semantically equivalent instruction streams of code units of different granularities and compiler debugging information, a mapping relationship between target regions and intermediate representations and assembly code in the source code is established to form a fully connected graph of cross-level equivalent regions; Based on the semantically equivalent instruction stream set and the fully connected graph of cross-level equivalent regions, performance monitoring code is automatically embedded at the boundary of the target region to perform performance testing and performance comparison analysis on the elastic region; wherein, the elastic region is selected according to the code unit.

2. The method according to claim 1, characterized in that, The code unit includes atomic statements, wherein the semantically equivalent instruction stream that generates the atomic statements includes: Locate the line and column numbers of atomic statements in the source code; The compiler is invoked to generate an intermediate representation, and the instruction sequence corresponding to the atomic statement is found in the intermediate representation and its position and content are recorded. The intermediate representation is compiled into assembly code. The instruction sequence corresponding to the atomic statement is found in the assembly code, and its position and content are recorded. Establish the hierarchical mapping relationship between the atomic statements in the source code, intermediate representation, and assembly code.

3. The method according to claim 2, characterized in that, The code unit includes a single compound statement, wherein the semantically equivalent instruction stream that generates the single compound statement includes: Parse the grammatical structure of a single compound statement, break it down into multiple atomic statements, and record the position of each atomic statement; For each atomic statement, construct its semantically equivalent instruction stream; The hierarchical mapping relationships of each atomic statement are summarized to establish the overall mapping relationship of the single compound statement in the source code, intermediate representation, and assembly code.

4. The method according to claim 3, characterized in that, The code unit includes a specific statement region, which is a continuous code block in the source code consisting of one or more atomic or compound statements; wherein, the semantically equivalent instruction stream that generates the specific statement region includes: For each atomic statement within the region, determine its semantically equivalent instruction stream and the corresponding hierarchical mapping relationship; For each compound statement within the region, construct its semantically equivalent instruction stream and the corresponding hierarchical mapping relationship; Summarize all hierarchical mapping relationships within the region and establish the overall mapping relationship of the specific statement region in the source code, intermediate representation, and assembly code.

5. The method according to claim 3, characterized in that, The code unit includes the entire function body, which is a complete code in the source code consisting of one or more atomic statements and compound statements; wherein, the semantically equivalent instruction stream that generates the entire function body includes: For each atomic statement within a function body, determine its semantically equivalent instruction stream and the corresponding hierarchical mapping relationship; For each compound statement within a function body, determine its semantically equivalent instruction stream and the corresponding hierarchical mapping relationship; For each specific statement region within a function body, determine its semantically equivalent instruction flow and the corresponding hierarchical mapping relationship; Summarize all hierarchical mapping relationships within the function body and establish the overall mapping relationship of the function body in the source code, intermediate representation, and assembly code.

6. The method according to claim 1, characterized in that, The method for generating the fully connected graph of the cross-level equivalent regions includes: Based on the semantically equivalent instruction streams of code units of different granularities that have been constructed, the instruction sequences that completely correspond to the target regions of the source code are located in the intermediate representation and assembly code, respectively. By combining the compiler debugging information, the line number, the position of the intermediate representation, and the position of the assembly code in the target area are bound one by one; Construct a complete mapping relationship from the target region to the intermediate representation and then to the assembly code, forming a fully connected graph of cross-level equivalent regions, where each node corresponds to a code unit and the edges represent the mapping relationship between different levels.

7. The method according to claim 6, characterized in that, When the compiler is invoked, enable the debug information generation option to obtain a metadata file containing the correspondence between source code line numbers and intermediate representation instructions and assembly code instructions.

8. The method according to claim 1, characterized in that, Automatically embedding performance monitoring code at the boundary of the target statement in the source code includes: inserting a timestamp acquisition function and a clock cycle counter at both the start and end lines of the target statement, and obtaining the performance data of the target statement by calculating the timestamp difference and clock cycle difference between the start and end lines.

9. The method according to claim 1, characterized in that, For the same target architecture, by adjusting the compiler's optimization stage and instruction set options, semantically equivalent instruction streams under the same architecture can be generated; For cross-architecture scenarios, by switching compilers for different target architectures, semantically equivalent instruction streams can be generated across architectures.

10. The method according to claim 9, characterized in that, For the target architecture, enable the compilation configuration of all optional instruction sets to generate the initial instruction stream; Traverse the assembly mnemonics in the initial instruction stream; if an instruction belongs to an optional instruction set... The optional instruction set is disabled and a new instruction stream is generated after recompiling. After traversing all optional instruction sets, a semantically equivalent instruction stream under the target architecture is finally generated.

11. A performance analysis device for cross-architecture semantically equivalent instruction streams, characterized in that, include: The instruction stream construction module is used to take a high-level language program as input and generate a set of semantically equivalent instruction streams from high-level language form to intermediate representation and then to assembly code through the compiler for multiple target architectures. The set of semantically equivalent instruction streams includes semantically equivalent instruction streams of code units with different granularities, and covers semantically equivalent instruction streams of different optimization stages and instruction set options under the same architecture, as well as semantically equivalent instruction streams between different architectures. The instruction flow localization module is used to establish the mapping relationship between target regions in the source code and intermediate representations and assembly code based on semantically equivalent instruction flows of code units of different granularities and compiler debugging information, forming a fully connected graph of cross-level equivalent regions; The performance analysis module is used to automatically embed performance monitoring code at the boundary of the target region based on the semantically equivalent instruction stream set and the fully connected graph of cross-level equivalent regions, to perform performance testing and performance comparison analysis on the elastic region; wherein, the elastic region is selected according to the code unit.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any one of claims 1-10.

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