Unified probabilistic graph computation architecture power consumption optimization method, system, medium and device

Abstract

The application relates to the field of signal processing and discloses a unified probability graph computing architecture power consumption optimization method, system, medium and equipment, which comprises the following steps: a unified probability graph for multiple tasks is used to perform sparse optimization on message passing data flow by dynamically regulating the message passing data flow in a probability iteration calculation process; and based on the optimized message passing data flow, the activation state of a memory-computing integrated array node is dynamically selected by a computing circuit of a memory-computing integrated characteristic device to improve the adaptability of the computing architecture and hardware resources. The application reduces the calculation-storage scale by deleting probability messages with low reasoning contribution and dynamically regulating the message passing data flow in the probability iteration calculation process, and the adaptability of the computing architecture and hardware resources is improved by dynamically selecting the activation state of the memory-computing integrated array node, so that the power consumption is further reduced.

Description

Technical Field

[0001] This invention relates to the field of ultra-low power signal processing sparsity optimization technology, and in particular to a power optimization method, system, medium and device for a unified probabilistic graph computing architecture. Background Technology

[0002] In recent years, probabilistic graphical computation has shown great potential in processing complex signals (such as communication, radar, and sensing signals) due to its powerful uncertainty reasoning and joint probabilistic modeling capabilities, especially in scenarios involving large-scale signal sources, noise interference, and hidden state estimation. However, it also suffers from excessively high computational complexity when facing large-scale signal processing applications. Summary of the Invention

[0003] To address the aforementioned issues, the present invention aims to provide a unified probabilistic graph computing architecture power consumption optimization method, system, medium, and device. This method dynamically adjusts the message passing data flow during probabilistic iterative computation to reduce the computation-storage scale by eliminating probabilistic messages with low inference contributions; it also dynamically selects the activation state of the in-memory computing array nodes to improve the adaptability of the computing architecture to hardware resources, thereby further reducing power consumption.

[0004] To achieve the above objectives, in a first aspect, the technical solution adopted by the present invention is: a power consumption optimization method for a unified probabilistic graph computing architecture, comprising: acquiring a unified probabilistic graph oriented to multiple tasks; optimizing the message passing data stream by dynamically controlling the message passing data stream during the probability iteration calculation process; and, based on the optimized message passing data stream, dynamically selecting the activation state of the array nodes in the in-memory computing device through the computing circuit of the in-memory computing device to improve the adaptability of the computing architecture to hardware resources.

[0005] Furthermore, the unified probabilistic graph for multi-task applications and the computing circuitry of in-memory computing devices constitute a unified probabilistic graph computing circuit architecture enabled by in-memory computing, including:

[0006] Based on the common characteristics of baseband signal processing tasks, a unified signal model is established and represented as a unified probability graph.

[0007] Based on the unified probabilistic graph, the message passing from the verification node to all variable nodes connected by undirected edges is described as a unified signal processor architecture. The unified signal processor architecture includes the node state matrix, driving vector and state value probability vector corresponding to several undirected edges.

[0008] The node state matrix corresponding to each undirected edge is pre-stored in the in-memory computing characteristic device to form the in-memory operator array corresponding to the undirected edge. The driving vector corresponding to the undirected edge is used as the input analog quantity of the in-memory operator array, and the state value probability vector corresponding to the undirected edge is used as the output analog quantity of the in-memory operator array.

[0009] The analog outputs of all memory operator arrays are iteratively updated to obtain the message from the variable node to the verification node, which is then used as the input of the memory computing integrated device. Based on the set iteration conditions, iterative calculations are performed to complete the baseband signal processing task.

[0010] Furthermore, the unified probabilistic graph for multi-task applications includes: variable nodes, verification nodes, and undirected edges;

[0011] Variable nodes represent unknown variables;

[0012] Verification nodes represent the coupling relationships between unknown variables, observed variables, and the correlation mapping matrix;

[0013] Undirected edges are used to connect variable nodes and check nodes that have a connection relationship;

[0014] In this context, variable nodes correspond to column vectors in the association mapping matrix, and verification nodes correspond to row vectors in the association mapping matrix.

[0015] Furthermore, the message passing data stream includes message passing from the verification node to all variable nodes connected by undirected edges:

[0016]

[0017] in, Representing variables The included states, For verification nodes To variable node Passed variables The state value is The news, for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, Indicates and verifies nodes Connected and variable nodes Values The combination of all variable node states, express From the verification node i A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, Represents variable nodes To the verification node The message conveyed about The news.

[0018] Furthermore, by dynamically controlling the message passing data flow during the probability iteration calculation process, including:

[0019] When a message is passed to a variable node, the verification node only selects the messages corresponding to the D states with the highest probability values ​​on that variable node for transmission; this reduces the scale of message transmission from... Reduce to ;

[0020] in, represent The messages corresponding to the D states with the highest probability are: the messages corresponding to the D states with the highest probability values, and the messages corresponding to the D states with probability values ​​greater than a set threshold.

[0021] Furthermore, the message passing data stream includes iterative updates of messages from variable nodes to verification nodes:

[0022]

[0023] in, Represents variable nodes To the verification node Passing information about variable nodes between nodes The state value is The news, Represents variable nodes To the verification node The message is from the verification node. Other than variable nodes Connected verification nodes Provide message generation, For verification nodes To variable node Passing information about variables The state value is The news.

[0024] Furthermore, the message passing data flow is dynamically controlled during the probability iteration calculation process, including:

[0025] Select Z variable nodes and fix their values ​​to the state with the highest probability.

[0026] For the remaining variable nodes, only those corresponding to the highest probability in their state set are passed. W The number of messages transmitted will be increased from J to a single state. W Reduce to .

[0027] Secondly, the technical solution adopted by the present invention is as follows: a power consumption optimization system for a unified probabilistic graph computing architecture, comprising: a data flow optimization module, which acquires a unified probabilistic graph oriented to multiple tasks and optimizes the message passing data flow by dynamically controlling the message passing data flow during the probability iteration calculation process; and a data flow transmission module, which, based on the optimized message passing data flow, dynamically selects the activation state of the array nodes in the in-memory computing characteristic device through the computing circuit of the in-memory computing characteristic device to improve the adaptability of the computing architecture and hardware resources.

[0028] Thirdly, the technical solution adopted by the present invention is: a computer-readable storage medium for storing one or more programs, wherein the one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform any of the methods described above.

[0029] Fourthly, the technical solution adopted by the present invention is: a computing device comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the methods described above.

[0030] The present invention has the following advantages due to the adoption of the above technical solutions:

[0031] This invention addresses the problem of excessive complexity in probabilistic graph computation for processing large-scale signals. Based on a unified baseband signal processing method, it employs a unified probabilistic graph computation architecture power optimization technique. By dynamically adjusting the message passing data flow during probabilistic iteration computation, it reduces the computation-storage scale by eliminating probabilistic messages with low inference contributions. It also dynamically selects the activation state of the in-memory computing array nodes, improving the adaptability of the computing architecture to hardware resources and further reducing power consumption. Attached Figure Description

[0032] Figure 1 This is a flowchart of the power consumption optimization method for the unified probabilistic graph computing architecture in an embodiment of the present invention;

[0033] Figure 2a This is a schematic diagram of message passing data flow during the probability iterative calculation process without sparse optimization in this embodiment of the invention;

[0034] Figure 2b This is a schematic diagram of the message passing data flow during the probabilistic iterative calculation process for sparse optimization in an embodiment of the present invention. Detailed Implementation

[0035] To address the issue of excessive computational complexity in existing unified probabilistic graph computing architectures for large-scale signal processing applications, this invention proposes a power consumption optimization method, system, medium, and device for unified probabilistic graph computing architectures. At the mathematical level, it dynamically adjusts the message passing data flow during probabilistic iteration calculations, reducing probabilistic messages with low inference contributions to decrease the computation-storage scale. At the hardware level, it dynamically selects the activation state of in-memory computing array nodes, improving the adaptability of the computing architecture to hardware resources and further reducing power consumption.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0038] In one embodiment of the present invention, a power consumption optimization method for a unified probabilistic graph computation architecture is provided, belonging to the field of signal processing, specifically a sparsity optimization technique for in-memory computing-enabled probabilistic graph computation circuits. In a unified probabilistic graph computation (UPGC) without sparsity optimization, message passing between check nodes and variable nodes involves all possible node states. This requires activating all row voltage inputs to the RRAM array and reading all column currents from the RRAM array. To further reduce the computational overhead of unified probabilistic graph computation (PGC), the present invention proposes a sparse optimization method specifically designed for it. Its core optimization principle lies in eliminating states with low contribution in the variable node state space, whose impact on probability calculation is negligible due to their extremely low probability. Mathematically, this method prunes the transmitted messages to reduce the computational scale and optimizes the data flow of message passing; from a hardware perspective, it can dynamically activate the row inputs of the RRAM array and selectively read columns, thereby minimizing power consumption. In this embodiment, as shown... Figures 1 to 2b As shown, the method includes the following steps:

[0039] 1) A unified probabilistic graph for multi-task applications, which optimizes the sparsity of message passing data flow by dynamically adjusting the message passing data flow during probability iteration calculation.

[0040] 2) Based on the optimized message passing data stream, the activation state of the in-memory computing array node is dynamically selected through the unified probabilistic graph computing circuit enabled by in-memory computing, so as to improve the adaptability of computing architecture and hardware resources.

[0041] The sparse optimization employed in this invention is primarily used to eliminate variable states with relatively low probabilities in the node state space, thereby reducing computational complexity. The contribution of these low-probability variable states to the computation of the probabilistic graph is negligible.

[0042] In step 1) above, the unified probabilistic graph for multi-task applications and the computing circuit of in-memory computing devices constitute a unified probabilistic graph computing circuit architecture enabled by in-memory computing, including:

[0043] Based on the common characteristics of baseband signal processing tasks, a unified signal model is established and represented as a unified probability graph.

[0044] Based on the unified probabilistic graph, the message passing from any verification node to all variable nodes connected by undirected edges is described as a unified signal processor architecture. The unified signal processor architecture includes node state matrices, driving vectors, and state value probability vectors corresponding to several undirected edges.

[0045] The node state matrix corresponding to each undirected edge is pre-stored in the in-memory computing characteristic device to form the in-memory operator array corresponding to the undirected edge. The driving vector corresponding to the undirected edge is used as the input analog quantity of the in-memory operator array, and the state value probability vector corresponding to the undirected edge is used as the output analog quantity of the in-memory operator array.

[0046] The analog outputs of all memory operator arrays are iteratively updated to obtain the message from the variable node to the verification node, which is then used as the input of the memory computing integrated device. Based on the set iteration conditions, iterative calculations are performed to complete the baseband signal processing task.

[0047] Specifically, the baseband signal processing tasks in this embodiment include: Task 1: multi-antenna detection task; Task 2: channel decoding task; Task 3: channel estimation task; Task 4: multi-user identification task.

[0048] like Figure 2a As shown, based on the common characteristics of baseband signal processing tasks, a unified signal model is established as follows: ,in, These are unknown variables (variables to be estimated). For given and The correlation mapping matrix between them For observed variables, This is unknown disturbance noise. Each is a certain unknown variable. Each of these represents a specific observed variable.

[0049] When faced with different tasks in baseband signal processing, the parameters of the unified signal model represent different meanings, for example:

[0050] In multi-antenna detection tasks: This is the characteristic matrix of a multi-antenna channel. For the transmitted symbol to be estimated, For the mixed signal observed by the receiver from multiple antennas, continuous, continuous, For unknown discrete variables;

[0051] In channel decoding tasks: This is the codeword verification matrix. For the transmitted bits to be estimated, The bit sequence received by the receiving end. It is known that Discrete, continuous, For unknown discrete variables;

[0052] In channel estimation tasks: For pilot structure matrix, For the communication channel to be estimated, The pilot signal observed at the receiving end. It is known that continuous, Discrete, Unknown continuous variable;

[0053] In multi-user detection tasks, For the perception matrix, The device is in an active state. The signal observed by the receiver is a superimposed signal from multiple users. It is known that continuous, continuous, It is an unknown continuous variable.

[0054] In step 1) above, the unified probabilistic graph for multi-task applications includes: variable nodes, verification nodes, and undirected edges; variable nodes represent unknown variables; verification nodes represent the coupling relationship between unknown variables, observed variables, and the correlation mapping matrix; undirected edges are used to connect variable nodes and verification nodes that have a connection relationship; wherein, the variable node corresponds to the correlation mapping matrix between the unknown variable and the observed variable. The column vectors in the matrix, and the corresponding association mapping matrix for each verification node. Row vectors in a matrix. For example, the incidence matrix. The Middle Row vector representation , for No. Line number Column elements, representing validation nodes. With variable nodes The relationship between them, if the association mapping matrix middle If the element is 1, then the variable node With verification node If there is a connection relationship, such as an association mapping matrix of If the element is 0, then the variable node... With verification node No connection exists.

[0055] In this embodiment, a probability configuration function is constructed. This characterizes the differences in probabilistic iterative messages from the verification node to the variable node across different tasks in baseband signal processing. Based on different tasks, a probabilistic configuration function is constructed. They are all different; the following describes the probability allocation function. This is an example, but not limited to:

[0056] In multi-user identification tasks Represented as:

[0057] ;

[0058] in, Indicates the noise variance. Indicates the received symbol. Channel matrix The first in Row vectors.

[0059] In this embodiment, the message passing data stream includes message passing from the verification node to all variable nodes connected by undirected edges:

[0060]

[0061] in, Representing variables The included states, For verification nodes To variable node Passed variables The state value is The message (essentially representing the verification node) To variable node The message about the first Variables about The confidence level is the posterior probability. for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, Indicates and verifies nodes There are connections, except for variable nodes. The combination of all variable node states except for It is a set The number of candidate vectors is . M There are 1 candidate vectors, and the candidate vectors are unknown variables. One of the elements, Indicates and verifies nodes Connected and variable nodes Values The combination of all variable node states, express From the verification node A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, the specific calculation method includes but is not limited to , Represents variable nodes To the verification node The message conveyed about The news.

[0062] In this embodiment, as Figure 2b As shown, when performing message passing from the verification node to all variable nodes connected by undirected edges, the message passing data flow during the probability iteration calculation is dynamically controlled, specifically including:

[0063] When a message is passed to a variable node, the verification node only selects the variable node with the highest probability value. D The message corresponding to each state is transmitted; in order to reduce the scale of message transmission from Reduce to ;in, K Indicates the original size of the message.

[0064] in, represent The highest probability D The message corresponding to each state; the one with the highest probability value. D The message corresponding to each state has a probability value greater than a set threshold. D The message corresponding to each state.

[0065] In this embodiment, the message passing data stream also includes iterative updates to obtain messages from the variable node to the verification node:

[0066]

[0067] in, Represents variable nodes To the verification node Passing information about variable nodes between nodes The state value is The news, Represents variable nodes To the verification node The message is from the verification node. Other than variable nodes Connected verification nodes Provide message generation, For verification nodes To variable node Passing information about variables The state value is The news.

[0068] For example, This is just one example, and not limited to this.

[0069] In this embodiment, as Figure 2b As shown, when iteratively updating to obtain messages from variable nodes to verification nodes, the message transmission data flow during the probability iterative calculation process is dynamically adjusted, specifically including:

[0070] Select Z variable nodes and fix their values ​​to the state with the highest probability.

[0071] For the remaining variable nodes, only those corresponding to the highest probability in their state set are passed.W A message in a specific state;

[0072] The number of messages transmitted is reduced from J. W Reduce to in, J Indicates the number of variable nodes.

[0073] In step 2) above, the in-memory computing characteristic device is implemented using a memristor.

[0074] In step 2) above, the original array row input was voltage, which needed to be converted into voltage by the ADC and applied to all rows. The column output was obtained by sampling the current by the DAC. After sparse optimization, only a portion of the voltage needs to be input and a portion of the current needs to be read.

[0075] Figure 2a P(x) in t () indicates that messages are passed from the variable node to the verification node. The function; that is:

[0076]

[0077] In the above formula This item. Because... The calculation is a vector-matrix multiplication operation, G i The value of (x) will be written into the array, that is, to represent the matrix, from P(x1) to P(x). T Each number is a real number, and the whole thing is a vector. This is directly converted into a voltage input and fed into an array with storage and computational functions, including but not limited to memristors and resistors. The result is read from the columns of the matrix in the form of current. P(x1) to P(x... T There are a total of T probabilities, each probability representing a combination of variables x. t The joint probability distribution is formed, and after sparse optimization, it is equivalent to using only a portion.

[0078] In the above embodiments, when the multiplication and accumulation operations involved in the unified probability graph calculation process use a cross array composed of memristors, the row voltage input and column current readout of the array are dynamically activated.

[0079] In one embodiment of the present invention, a power optimization system for a unified probabilistic graphical computing architecture is provided, comprising:

[0080] The data flow optimization module, a unified probabilistic graph for multiple tasks, optimizes the message passing data flow by dynamically adjusting the message passing data flow during the probability iteration calculation process.

[0081] The data flow transmission module, based on the optimized message transmission data flow, dynamically selects the activation state of the in-memory computing array nodes through the computing circuit of the in-memory computing characteristic device, so as to improve the adaptability of computing architecture and hardware resources.

[0082] In the above embodiments, the unified probabilistic graph for multi-task applications and the computing circuit of the in-memory computing device constitute an in-memory computing-enabled unified probabilistic graph computing circuit architecture, including:

[0083] Based on the common characteristics of baseband signal processing tasks, a unified signal model is established and represented as a unified probability graph.

[0084] Based on the unified probabilistic graph, the message passing from the verification node to all variable nodes connected by undirected edges is described as a unified signal processor architecture. The unified signal processor architecture includes the node state matrix, driving vector and state value probability vector corresponding to several undirected edges.

[0085] The node state matrix corresponding to each undirected edge is pre-stored in the in-memory computing characteristic device to form the in-memory operator array corresponding to the undirected edge. The driving vector corresponding to the undirected edge is used as the input analog quantity of the in-memory operator array, and the state value probability vector corresponding to the undirected edge is used as the output analog quantity of the in-memory operator array.

[0086] The analog outputs of all memory operator arrays are iteratively updated to obtain the message from the variable node to the verification node, which is then used as the input of the memory computing integrated device. Based on the set iteration conditions, iterative calculations are performed to complete the baseband signal processing task.

[0087] In the above embodiments, the unified probabilistic graph for multi-task applications includes: variable nodes, verification nodes, and undirected edges;

[0088] Variable nodes represent unknown variables;

[0089] Verification nodes represent the coupling relationships between unknown variables, observed variables, and the correlation mapping matrix;

[0090] Undirected edges are used to connect variable nodes and check nodes that have a connection relationship;

[0091] Wherein, the variable nodes correspond to the association mapping matrix. The column vectors in the matrix, and the corresponding association mapping matrix for each verification node. Row vectors in the array.

[0092] Representing variables x j The included states, For verification nodes i To variable node j Passed variables xj The state value is In the above embodiments, the message passing data stream includes message passing from the verification node to all variable nodes connected by undirected edges:

[0093]

[0094] in, Representing variables x j The included states, For verification nodes i To variable node j Passed variables x j The state value is The news, for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, Indicates and verifies nodes i Connected and variable nodes j Values The combination of all variable node states, express From the verification node i A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, Represents variable nodes To the verification node The message conveyed about The news.

[0095] In this embodiment, the message passing data flow during the probability iteration calculation process is dynamically controlled, including:

[0096] When a message is passed to a variable node, the verification node only selects the messages corresponding to the D states with the highest probability values ​​on that variable node for transmission; this reduces the scale of message transmission from... Reduce to ;

[0097] in, represent The messages corresponding to the D states with the highest probability are: the messages corresponding to the D states with the highest probability values, and the messages corresponding to the D states with probability values ​​greater than a set threshold.

[0098] In the above embodiments, the message passing data stream includes iterative updates of messages from variable nodes to verification nodes:

[0099]

[0100] in, Represents variable nodes j To the verification node Passing information about variable nodes between nodes The state value is The news, Represents variable nodes j To the verification node i The message is from the verification node. i Other than variable nodes j Connected verification nodes Provide message generation, For verification nodes To variable node j Passing information about variables x j The state value is The news.

[0101] In this embodiment, the message passing data flow during the probability iteration calculation process is dynamically controlled, including:

[0102] Select Z variable nodes and fix their values ​​to the state with the highest probability.

[0103] For the remaining variable nodes, only those corresponding to the highest probability in their state set are passed. W A message in a specific state;

[0104] The number of messages transmitted is reduced from J. W Reduce to .

[0105] The system provided in this embodiment is used to execute the above-described method embodiments. For specific processes and details, please refer to the above embodiments, which will not be repeated here.

[0106] In one embodiment of the present invention, a computing device is provided. This computing device can be a terminal and may include a processor, a communication interface, memory, a display screen, and an input device. The processor, communication interface, and memory communicate with each other via a communication bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. When the computer programs are executed by the processor, they implement the methods described in the above embodiments. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wi-Fi, a management network, NFC (Near Field Communication), or other technologies. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the casing of the computing device, or an external keyboard, touchpad, or mouse. The processor can call logical instructions stored in the memory.

[0107] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] In one embodiment of the present invention, a computer program product is provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to perform the methods provided in the above-described method embodiments.

[0109] In one embodiment of the present invention, a non-transitory computer-readable storage medium is provided, which stores server instructions that cause a computer to perform the methods provided in the above embodiments.

[0110] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0111] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power consumption optimization method for a unified probabilistic graphical computing architecture, characterized in that, include: Obtain a unified probability graph for multi-task applications, and optimize the message passing data flow by dynamically adjusting the message passing data flow during the probability iteration calculation process. Based on the optimized message passing data stream, the activation state of the array nodes in the in-memory computing device is dynamically selected by the computing circuit of the in-memory computing device to improve the adaptability of the computing architecture and hardware resources. A unified probabilistic graph computing circuit architecture with in-memory computing capabilities, comprising a unified probabilistic graph computing circuit architecture for multi-task applications and computing circuits with in-memory computing characteristics, includes: Based on the common characteristics of baseband signal processing tasks, a unified signal model is established and represented as a unified probability graph. Based on the unified probabilistic graph, the message passing from the verification node to all variable nodes connected by undirected edges is described as a unified signal processor architecture. The unified signal processor architecture includes the node state matrix, driving vector and state value probability vector corresponding to several undirected edges. The node state matrix corresponding to each undirected edge is pre-stored in the in-memory computing characteristic device to form the in-memory operator array corresponding to the undirected edge. The driving vector corresponding to the undirected edge is used as the input analog quantity of the in-memory operator array, and the state value probability vector corresponding to the undirected edge is used as the output analog quantity of the in-memory operator array. The analog outputs of all memory operator arrays are iteratively updated to obtain the message from the variable node to the verification node, which is then used as the input of the memory computing integrated device. Based on the set iteration conditions, iterative calculations are performed to complete the baseband signal processing task.

2. The power consumption optimization method for the unified probabilistic graphical computing architecture as described in claim 1, characterized in that, A unified probabilistic graph for multi-task applications includes: variable nodes, check nodes, and undirected edges; Variable nodes represent unknown variables; Verification nodes represent the coupling relationships between unknown variables, observed variables, and the correlation mapping matrix; Undirected edges are used to connect variable nodes and check nodes that have a connection relationship; Wherein, the variable nodes correspond to the association mapping matrix. The column vectors in the matrix, and the corresponding association mapping matrix for each verification node. Row vectors in the array.

3. The power consumption optimization method for the unified probabilistic graphical computing architecture as described in claim 2, characterized in that, The message passing data stream includes message passing from the validation node to all variable nodes connected by undirected edges: in, Representing variables The included states, For verification nodes i To variable node j Passed variables x j The state value is The news for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, Indicates and verifies the node i Connected and variable nodes j Values The combination of all variable node states, express From the verification node i A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, Represents variable nodes To the verification node The message conveyed about The news.

4. The power consumption optimization method for the unified probabilistic graphical computing architecture as described in claim 3, characterized in that, By dynamically controlling the message passing data flow during the probability iteration calculation process, including: When a message is passed to a variable node, the verification node only selects the messages corresponding to the D states with the highest probability values ​​on that variable node for transmission; this reduces the scale of message transmission from... Reduce to ; in, represent The messages corresponding to the D states with the highest probability are the messages corresponding to the D states with probability values ​​greater than a set threshold.

5. The power consumption optimization method for the unified probabilistic graphical computing architecture as described in claim 3, characterized in that, The message passing data stream includes messages from variable nodes to verification nodes obtained through iterative updates: in, Represents variable nodes j To the verification node i Passing information about variable nodes between nodes The state value is The news Represents variable nodes j To the verification node i The message is from the verification node. i Other than variable nodes j Connected verification nodes l Provide message generation, For verification nodes l To variable node j Passing information about variables x j The state value is The news.

6. The power consumption optimization method for the unified probabilistic graphical computing architecture as described in claim 5, characterized in that, The message passing data flow during the dynamic control of probability iteration calculation includes: Select Z variable nodes and fix their values ​​to the state with the highest probability. For the remaining variable nodes, only those corresponding to the highest probability in their state set are passed. W The number of messages transmitted will be increased from J to a single state. W Reduce to , J Indicates the number of variable nodes.

7. A power optimization system for a unified probabilistic graphical computing architecture, used to implement the power optimization method for a unified probabilistic graphical computing architecture as described in any one of claims 1 to 6, characterized in that, include: The data flow optimization module acquires a unified probability graph for multiple tasks and performs sparsity optimization on the message passing data flow by dynamically adjusting the message passing data flow during the probability iteration calculation process. The data flow transmission module, based on the optimized message transmission data flow, dynamically selects the activation state of the array nodes in the in-memory computing device through the computing circuit of the in-memory computing device, so as to improve the adaptability of the computing architecture and hardware resources.

8. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the methods described in claims 1 to 6.

9. A computing device, characterized in that, include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods described in claims 1 to 6.

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