Chip storage area testing methods, apparatus, equipment, and computer storage media

Abstract

This application proposes a chip storage area testing method, apparatus, device, and computer storage medium. The chip storage area testing method includes: obtaining the address of a target area in the DRAM chip under test used to store a target test program; loading an initial test program into the SRAM chip in the test system SoC, and calling the initial test program to test the target area according to the address; if the target area test passes, testing the areas of the DRAM chip under test other than the target area according to the target test program and the target area. Through the above chip storage area testing method, the detection blind spot of the DRAM chip under test is eliminated, and reliable testing of the entire physical memory space, i.e., all storage areas, of the DRAM chip under test is achieved.

Description

Technical Field

[0001] This application relates to the field of chip storage area testing, and in particular to a chip storage area testing method, apparatus, device, and computer storage medium. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a core storage component of electronic devices, and its storage reliability directly determines the operational stability of the entire system. Therefore, testing DRAM chips is particularly important. Existing testing systems require a portion of the DRAM chip's physical memory space to store test-related programs to ensure the continuous execution of test steps.

[0003] DRAM chip memory area testing relies on destructive read / write operations: data must be written to the memory cells of the DRAM chip, and then defects are identified through data consistency verification. However, performing destructive read / write tests on the memory space occupied by the program being tested within the DRAM chip will directly lead to instruction corruption, operating system kernel crashes, or test code execution interruptions, thereby terminating the entire DRAM chip memory area testing process or resulting in inaccurate test results. Therefore, existing DRAM chip memory area testing designs must exclude the memory space occupied by the program being tested from the testing scope, creating an undetectable blind spot.

[0004] Therefore, how to eliminate the detection blind spots in DRAM chip storage area testing and achieve reliable testing of the entire physical memory space of DRAM chips has become a key technical problem that urgently needs to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a chip storage area testing method, apparatus, device, and computer storage medium.

[0006] To address the aforementioned technical problems, this application proposes a chip memory region testing method, which includes:

[0007] Obtain the address of the target region in the DRAM chip under test used to store the target test program;

[0008] Load the initial test program into the SRAM chip in the test system SOC, and call the initial test program to test the target area according to the address;

[0009] If the target area test is passed, the regions of the DRAM chip under test other than the target area are tested according to the target test program and the target area.

[0010] The target test program is a bootloader, which is used to test a first area where the kernel program is stored, and the kernel program is used to test a second area. The first area, the second area, and the target area constitute the storage area of ​​the DRAM chip to be tested.

[0011] The test is performed on the regions of the DRAM chip under test other than the target region according to the target test program and the target region, including:

[0012] Load the bootloader into the target region and execute the bootloader to test the first region;

[0013] After the first region test is passed, the kernel program is loaded into the first region and executed to test the second region.

[0014] The initial test program, the bootloader, and the kernel program are embedded in the non-volatile memory of the test system SOC.

[0015] The step of calling the initial test program to test the target area based on the address includes:

[0016] The target controller is invoked to write a first data value to each storage unit in the target region;

[0017] The target controller is invoked to read the data values ​​in each storage unit of the target region sequentially from the first address to the last address;

[0018] If the data value read from the current storage unit is not the first data value, the current storage unit is determined to be a faulty storage unit.

[0019] The chip storage area testing method further includes:

[0020] When the data value read from the current storage unit is the first data value, the target controller is invoked to write the second data value into the current storage unit and then read the data value from the next storage unit.

[0021] When all the data values ​​read from the storage units are the first data value, the data values ​​in each storage unit of the target area are read in descending order from the last address to the first address.

[0022] When all the data values ​​read from the storage units are the second data value, the target area test is deemed to have passed.

[0023] The chip storage area testing method further includes:

[0024] If at least one memory cell in the target area is faulty, the testing of the DRAM chip under test shall be stopped.

[0025] The fault address in the target area is determined based on the address of the faulty storage unit.

[0026] The chip storage area testing method further includes:

[0027] If a faulty memory cell exists in the target area, the redundant memory cells in the DRAM chip under test are obtained.

[0028] If the redundant storage unit is not faulty, the faulty storage unit in the target area is mapped to the redundant storage unit;

[0029] The target test program is loaded into the target area, excluding the faulty storage unit and the redundant storage unit.

[0030] To address the aforementioned technical problems, this application proposes a chip memory region testing apparatus, which includes:

[0031] The acquisition module is used to acquire the address of the target region in the DRAM chip under test, which is used to store the target test program;

[0032] The loading module is used to load the initial test program into the SRAM chip in the test system SOC, and call the initial test program to test the target area according to the address;

[0033] The testing module is used to test areas other than the target area in the DRAM chip under test, according to the target test program and the target area, if the target area test passes.

[0034] To address the aforementioned technical problems, this application also proposes a chip storage area testing device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the chip storage area testing method described above.

[0035] To address the aforementioned technical problems, this application also proposes a computer storage medium for storing program data, which, when executed by a computer, is used to implement the aforementioned chip storage area testing method.

[0036] Compared with the prior art, the beneficial effects of this application are: it provides a brand-new test program, namely the initial test program. At the start of the test, the initial test program is loaded into the SRAM inside the SOC for startup. Before the target test program occupies the target area, the target area is tested in advance by the initial test program. The target area of ​​the program to be tested during the test has been tested. If the target area test is passed, the target test program is then loaded into the target area, which can realize the testing of the remaining areas of the DRAM chip under test except for the target area. This eliminates the detection blind spot of the DRAM chip under test and realizes reliable testing of the entire physical memory space, i.e., all storage areas of the DRAM chip under test. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0038] Figure 1 This is a flowchart illustrating the first embodiment of the chip storage area testing method provided in this application;

[0039] Figure 2 This is an architecture diagram of the chip storage area test provided in this application;

[0040] Figure 3 This is a flowchart illustrating the phased testing process provided in this application;

[0041] Figure 4 This is a flowchart illustrating the process of testing the target area provided in this application;

[0042] Figure 5 This is a schematic diagram of an embodiment of the chip storage area testing device provided in this application;

[0043] Figure 6 This is a schematic diagram of the structure of an embodiment of the chip storage area testing device provided in this application;

[0044] Figure 7 This is a schematic diagram of the structure of an embodiment of the computer storage medium provided in this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] Please see Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip storage area testing method provided in this application.

[0048] The chip storage area testing method of this application is applied to a chip storage area testing device, which can be a server, a terminal device, or a system in which the server and the terminal device cooperate with each other. Accordingly, the various parts of the chip storage area testing device, such as each unit, subunit, module, and submodule, can all be set in the server, all in the terminal device, or separately in the server and the terminal device.

[0049] Furthermore, the aforementioned server can be either hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it can be implemented as multiple software programs or software modules, such as software or software modules used to provide distributed server functionality, or as a single software program or software module; no specific limitations are made here.

[0050] The chip memory area testing method described in this application is applied to a testing system; please refer to [link / reference needed]. Figure 2 , Figure 2 This is an architecture diagram of the chip memory area test provided in this application, such as... Figure 2The test architecture shown includes a host computer, a control board, and a test system. The host computer is the control center for the chip storage area test tasks. It includes a result analysis and report manager and a test process manager. It is responsible for editing the test process, issuing test commands and configuration parameters, and receiving and analyzing the final test results returned by the lower-level computer (control board and test system) to generate bad block reports.

[0051] The control board acts as a bridge between the host computer and the test system. It includes an instruction relay processor, a power / timing controller, and a firmware downloader / data collector. The control board receives test commands from the host computer, performs precise power management and timing control of the test system, and downloads the necessary firmware from the host computer or local server to the designated test system. Furthermore, the control board collects real-time test data from the test system and sends it back to the host computer.

[0052] The testing system is the core platform for testing DRAM chips, and its specific components include:

[0053] SOC (System on a Chip): Internally integrates CPU (Central Processing Unit), SRAM (Static Random Access Memory), controller, etc.

[0054] The test system also includes non-volatile memory for storing firmware images issued by the control board.

[0055] The DRAM chip under test is connected to the test system via a slot or probe.

[0056] like Figure 1 As shown, the specific steps are as follows:

[0057] Step S11: Obtain the address of the target region in the DRAM chip under test used to store the target test program.

[0058] In related technologies, when testing DRAM chips, the testing system needs to occupy a portion of the physical memory space of the DRAM chip to store the test-related programs. In the embodiments of this application, the target test program is the test-related program, and the physical memory space occupied by the test-related program is recorded as the target area.

[0059] The total physical memory space of the DRAM chip under test is the storage area of ​​the DRAM chip under test.

[0060] The test steps are performed by the SOC to test the DRAM chip under test. During the test, the SOC first determines the address of the target area through the preset configuration information, which includes the starting address and size of the target area.

[0061] Step S12: Load the initial test program into the SRAM chip in the test system SOC, and call the initial test program to test the target area according to the address.

[0062] In this embodiment of the application, the initial test program is a lightweight initial boot program used for the test target area in the DRAM chip under test. The memory space occupied by the initial test program is much smaller than that of the target test program.

[0063] The initial test program is loaded into the SRAM chip, which is embedded in the SOC. The SRAM chip has a small capacity, usually in the KB range, such as tens to hundreds of KB. It cannot store the entire program used for comprehensive testing of the DRAM chip under test. Since the initial test program is a lightweight program, it occupies less memory space and can be loaded into the SRAM chip.

[0064] CPUs cannot directly read and execute programs stored in external devices; they can only access programs in memory (i.e., DRAM or SRAM). Therefore, during testing, the program to be executed must first be loaded into DRAM or SRAM, and the CPU reads and executes the various instructions included in the program in DRAM or SRAM.

[0065] After the initial test program is loaded into the SRAM chip, the CPU calls the initial test program to test the target region based on the address of the target region and obtain the test results of the target region.

[0066] Step S13: If the target area test passes, test the areas of the DRAM chip under test other than the target area according to the target test program and the target area.

[0067] In this embodiment of the application, when the test result of the target area is that the target area test is passed, the remaining areas of the DRAM chip to be tested, excluding the target area, are tested according to the target test program and the target area.

[0068] When the target area test passes, the target test program is loaded into the target area and executed to begin testing the remaining areas.

[0069] Through the above embodiments, a novel test program, namely the initial test program, is provided. At the start of the test, the initial test program is loaded into the SRAM inside the SOC for startup. Before the target test program occupies the target area, the target area is tested in advance through the initial test program. The target area of ​​the relevant program to be tested during the test has been tested. If the target area test passes, the target test program is then loaded into the target area. This enables the testing of the remaining areas of the DRAM chip under test, excluding the target area, thus eliminating the detection blind spot of the DRAM chip under test and realizing reliable testing of the entire physical memory space, i.e., all storage areas, of the DRAM chip under test.

[0070] In an optional embodiment, the target test program is a bootloader, which is used to test a first region storing a kernel program, and the kernel program is used to test a second region. The first region, the second region, and the target region constitute the storage region of the DRAM chip under test. Testing the regions of the DRAM chip under test other than the target region according to the target test program and the target region includes: loading the bootloader into the target region and executing the bootloader to test the first region; after the first region passes the test, loading the kernel program into the first region and executing the kernel program to test the second region.

[0071] In this embodiment of the application, the DRAM chip to be tested is divided into three parts: a target area, a first area, and a second area; wherein, the target area is tested by an initial test program, the first area is tested by a bootloader, and the second area is tested by a kernel program.

[0072] The system startup process is divided into three stages (SRAM stage, Bootloader stage, and Kernel stage), among which:

[0073] The SRAM stage completes the most basic hardware initialization, only initializing the hardware necessary for subsequent startup, without performing redundant operations; it initializes the clock system, key pins, and DRAM controller, with the DRAM controller being initialized to prepare the Bootloader loading environment.

[0074] The bootloader is the program that connects the hardware and the kernel. It performs more comprehensive hardware initialization based on the SRAM stage, loads and starts the operating system kernel, and covers all the hardware required for kernel startup.

[0075] The goal of the Kernel (operating system kernel) stage is to initialize the basic services of the operating system, establish the user space runtime environment, and ultimately enable the system to run applications.

[0076] The complete DRAM testing task is broken down into three test phases that are strictly tied to multiple stages of the system boot process. Each preceding phase is responsible for verifying and ensuring the memory reliability of the program's runtime environment in the next phase, thus constructing a chain-like testing process.

[0077] Based on this, the testing process of the test system for the DRAM chip under test is divided into three stages:

[0078] Phase 1: The initial test program is loaded onto the SRAM chip outside the DRAM chip under test. The initial test program does not rely on the DRAM chip under test as running memory. It can be started using only the limited SRAM chip inside the SOC and completes the initialization of the core hardware to obtain the low-level read and write control of the DRAM chip under test. The initial test program is executed by a single CPU core to perform low-level read and write control on the target area to test the target area.

[0079] Phase Two: After the target region test is passed, the bootloader is loaded into the target region, and the first region is tested based on the bootloader;

[0080] The bootloader is executed by a single CPU core. The test module embedded in the bootloader uses hardware acceleration units such as DMA (Direct Memory Access) controllers to perform more complex memory test algorithms on the predetermined loading area of ​​the subsequent kernel program. The DMA controller can quickly move and compare data, which greatly improves the test efficiency.

[0081] Phase 3: After the first region test is passed, the kernel program is loaded into the first region, and the second region is tested based on the bootloader.

[0082] In the third stage, all CPU cores are used to execute the kernel program, and multimedia instruction sets such as NEON (ARM Advanced SIMD Extensions) are used to generate complex pseudo-random test streams to perform high-intensity stress tests on the DRAM chips under test.

[0083] The initial test program is an extremely lightweight program that runs on the SOC's internal SRAM. It does not rely on the DRAM chip under test as running memory. It completes the most basic hardware initialization of the test system and performs pre-testing on the DRAM area, i.e. the target area, that will be occupied by the subsequent bootloader.

[0084] The initial test program, the bootloader, and the kernel program are embedded in the non-volatile memory of the test system SOC.

[0085] Please see Figure 3 , Figure 3 This is a flowchart illustrating the phased testing process provided in this application, such as... Figure 3 As shown, it includes:

[0086] Step S301: Power on the SOC and load the initial test program into the SRAM chip;

[0087] Step S302: Test the target area according to the initial test procedure;

[0088] Step S303: Determine if a fault exists in the target area. If yes, proceed to step S304; otherwise, proceed to step S305.

[0089] Step S304: Report the error address through the data interface and test the system to shut down;

[0090] Step S305: Load the bootloader to the target area;

[0091] Step S306: Test the first region according to the bootloader;

[0092] Step S307: Determine if there is a fault in the first area. If yes, proceed to step S308; if no, proceed to step S309.

[0093] Step S308: Report the error address through the data interface and test the system to shut down;

[0094] Step S309: Load the kernel program into the first region;

[0095] Step S310: Test the second region according to the kernel program;

[0096] Step S311: Determine if there is a fault in the second area. If yes, proceed to step S312; if no, proceed to step S313.

[0097] Step S312: Report the error address through the data interface and test the system to shut down;

[0098] Step S313: Report the test pass information through the data interface.

[0099] In an optional embodiment, the step of calling the initial test program to test the target area according to the address includes: calling the target controller to write a first data value to each storage unit in the target area; calling the target controller to read the data values ​​in each storage unit in the target area sequentially from the first address to the last address; and determining the current storage unit as a faulty storage unit when the data value read in the current storage unit is not the first data value.

[0100] The chip storage area testing method further includes: when the data value of the current storage unit is the first data value, calling the target controller to write the second data value into the current storage unit, and reading the data value of the next storage unit; when the data values ​​of all storage units are the first data value, reading the data values ​​in each storage unit of the target area in descending order from the last address to the first address; when the data values ​​of all storage units are the second data value, determining that the target area test has passed.

[0101] In this application embodiment, common faults in DRAM chips are classified as follows:

[0102] Fixed failure: The memory cell is permanently fixed at 0 or 1 and cannot be rewritten.

[0103] Transitional failure: The storage cell is unable to complete a normal state transition from 0 to 1 or from 1 to 0.

[0104] Partial address decoding failure: When accessing one address, another address was incorrectly accessed.

[0105] Please see Figure 4 , Figure 4 This is a flowchart illustrating the process of testing the target area provided in this application, such as... Figure 4 As shown, it includes:

[0106] Step S41: Write initialization data into the target area.

[0107] This involves traversing all addresses (i.e., all memory units) in the target region and writing the first data value to each address, which is equivalent to writing initialization data in the target region, such as writing "0" to all addresses.

[0108] Step S42: Read the data value of each address in the target area sequentially from the first address to the last address, and write the reverse value of the initialization data to each address.

[0109] The operation is performed on each address in ascending order, meaning that two consecutive operations are performed on each address from the first address to the last address: Operation a: Read the data value of the current address and compare the read data value with the written data value (first data value "0"). If the read value is not the first data value, it indicates that the current address may have a fault where the data value is fixed as the second data value, and the test fails; Operation b: If the read value is the first data value, immediately write the inverted value of the first data value (second data value "1") to the current address to test whether the current address can convert from the first data value to the second data value.

[0110] Step S43: Read the data value of each address in the target area sequentially from the end address to the beginning address, and write the reversed value of the data written in step S42 to each address.

[0111] The operation is performed on each address in descending order, that is, two consecutive operations are performed on each address from the last address to the first address: Operation a: Read the data value of the current address and compare the read data value with the written data value (second data value "1"). If the read value is not the second data value, it means that the conversion from the first data value to the second data value is incorrect. The current address may have a fault of being fixed as the first data value or a partial address decoding fault. At this time, the test fails; Operation b: If the read value is the second data value, immediately write the reversed value of the data written in step S42 (first data value "0") to the current address.

[0112] The chip storage area testing method further includes: stopping the testing of the DRAM chip under test when at least one storage cell in the target area is faulty; and determining the fault address in the target area based on the address of the faulty storage cell.

[0113] In this embodiment of the application, if any data mismatch is found during the test, i.e., at least one storage unit is faulty, a failure message containing the incorrect physical address is immediately sent to the control board via the serial port, and the system stops the detection of the target area.

[0114] The error-stopping mechanism during testing can accurately report the erroneous physical address, avoiding invalid testing.

[0115] In an optional embodiment, the chip storage region testing method further includes:

[0116] If a faulty memory cell exists in the target area, a redundant memory cell in the DRAM chip under test is obtained; if the redundant memory cell does not have a fault, the faulty memory cell in the target area is mapped to the redundant memory cell; the target test program is loaded into the other memory cells in the target area except for the faulty memory cell and the redundant memory cell.

[0117] In this embodiment of the application, instead of using a stop-on-error mechanism, all addresses are tested. When an address is found to be a faulty storage unit, it is marked. After marking, the next address is tested, and all faulty storage units in all target areas are tested.

[0118] If there is a faulty memory cell in the target area, obtain the redundant memory cell in the DRAM chip under test. The redundant memory cell is a spare memory cell reserved during the design process of the DRAM chip under test to replace the faulty memory cell. Test the redundant memory cell to confirm whether the redundant memory cell is intact. If the redundant memory cell is also faulty, it cannot be used for replacement. If the redundant memory cell is not faulty, the redundant memory cell can be used to replace the faulty memory cell in the target area.

[0119] Specifically, when a redundant storage unit replaces a faulty storage unit in a target area, the address that originally pointed to the faulty storage unit is redirected to the address of the redundant storage unit through circuit or logic configuration, that is, the faulty storage unit is mapped to the redundant storage unit.

[0120] When the target area is completely intact, the target test program will be loaded into the target area. However, if there is a faulty storage unit in the target area, the target test program will be loaded into the other storage units in the target area, as well as the redundant storage units. That is, the target test program still follows the original instructions to load the target test program into the target area and write the corresponding data into all storage units in the target area one by one. When performing the write operation corresponding to the faulty storage unit in the target area, the address of the faulty storage unit is mapped to the redundant storage unit, and the corresponding data is written into the redundant storage unit.

[0121] The above embodiments avoid the target test program from failing to load completely due to local faults.

[0122] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0123] To implement the above-mentioned chip memory area testing method, this application also proposes a chip memory area testing apparatus, for details please refer to [link / reference needed]. Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the chip storage area testing device provided in this application.

[0124] The chip storage area testing apparatus 500 in this embodiment includes:

[0125] The acquisition module 51 is used to acquire the address of the target region in the DRAM chip under test that is used to store the target test program;

[0126] The loading module 52 is used to load the initial test program into the SRAM chip in the test system SOC, and call the initial test program to test the target area according to the address;

[0127] The test module 53 is used to test the areas of the DRAM chip under test other than the target area according to the target test program and the target area, provided that the target area test is passed.

[0128] The target test program is a bootloader, which is used to test a first area where the kernel program is stored, and the kernel program is used to test a second area. The first area, the second area, and the target area constitute the storage area of ​​the DRAM chip to be tested.

[0129] The aforementioned testing module is further configured to load the bootloader into the target region and execute the bootloader to test the first region; after the first region passes the test, load the kernel program into the first region and execute the kernel program to test the second region.

[0130] The initial test program, the bootloader, and the kernel program are embedded in the non-volatile memory of the test system SOC.

[0131] The loading module described above is also used to call the target controller to write a first data value to each storage unit in the target area; call the target controller to read the data values ​​in each storage unit in the target area in order from the first address to the last address; and determine that the current storage unit is a faulty storage unit when the data value read in the current storage unit is not the first data value.

[0132] The loading module is further configured to, when the data value of the current storage unit is the first data value, call the target controller to write the second data value into the current storage unit and read the data value of the next storage unit; when the data values ​​of all the storage units are the first data value, read the data values ​​in each storage unit of the target region in descending order from the last address to the first address; and when the data values ​​of all the storage units are the second data value, determine that the target region has passed the test.

[0133] The aforementioned chip storage area testing device further includes a determination module, used to stop testing the DRAM chip under test when at least one storage cell in the target area is faulty; and to determine the fault address in the target area based on the address of the faulty storage cell.

[0134] The aforementioned chip storage area testing device further includes: a mapping module, used to acquire redundant storage units in the DRAM chip under test when there are faulty storage units in the target area; to map the faulty storage units in the target area to the redundant storage units when there are no faulty redundant storage units; and to load the target test program to the other storage units in the target area other than the faulty storage units and the redundant storage units.

[0135] To implement the above-mentioned chip memory area testing method, this application also proposes a chip memory area testing device, for details please refer to [link / reference needed]. Figure 6 , Figure 6 This is a schematic diagram of an embodiment of the chip storage area testing device provided in this application.

[0136] The chip storage area testing device 400 of this embodiment includes a processor 41, a memory 42, an input / output device 43, and a bus 44.

[0137] The processor 41, memory 42, and input / output device 43 are respectively connected to the bus 44. The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the chip storage area testing method described in the above embodiment.

[0138] In this embodiment, processor 41 can also be referred to as a CPU (Central Processing Unit). Processor 41 may be an integrated circuit chip with signal processing capabilities. Processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 41 can be any conventional processor.

[0139] This application also provides a computer storage medium; please refer to the following: Figure 7 , Figure 7 This is a schematic diagram of a computer storage medium according to an embodiment of the present application. The computer storage medium 600 stores a computer program 61, which, when executed by a processor, is used to implement the chip storage area testing method of the above embodiment.

[0140] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0141] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for testing chip storage areas, characterized in that, The chip storage area testing method includes: Obtain the address of the target region in the DRAM chip under test, wherein the target region is the physical memory space occupied by the target test program in the DRAM chip under test, wherein the target test program is a bootloader, the bootloader is used to test the first region where the kernel program is stored, the kernel program is used to test the second region, and the first region, the second region and the target region constitute the storage region of the DRAM chip under test; The initial test program is loaded into the SRAM chip outside the DRAM chip to be tested in the test system SOC. Before the target test program occupies the target area, the initial test program is called to test the target area according to the address. If the target area test is passed, the regions of the DRAM chip under test other than the target area are tested according to the target test program and the target area; The testing of regions other than the target region in the DRAM chip under test, based on the target test program and the target region, includes: loading the bootloader into the target region and executing the bootloader to test the first region; after the first region passes the test, loading the kernel program into the first region and executing the kernel program to test the second region.

2. The chip storage area testing method according to claim 1, characterized in that, The initial test program, the bootloader, and the kernel program are embedded in the non-volatile memory of the test system SOC.

3. The chip storage area testing method according to claim 1, characterized in that, The step of calling the initial test program to test the target area based on the address includes: The target controller is invoked to write a first data value to each storage unit in the target region; The target controller is invoked to read the data values ​​in each storage unit of the target region sequentially from the first address to the last address; If the data value read from the current storage unit is not the first data value, the current storage unit is determined to be a faulty storage unit.

4. The chip storage area testing method according to claim 3, characterized in that, The chip storage area testing method also includes: When the data value read from the current storage unit is the first data value, the target controller is invoked to write the second data value into the current storage unit and then read the data value from the next storage unit. When all the data values ​​read from the storage units are the first data value, the data values ​​in each storage unit of the target area are read in descending order from the last address to the first address. When all the data values ​​read from the storage units are the second data value, the target area test is deemed to have passed.

5. The chip storage area testing method according to claim 3, characterized in that, The chip storage area testing method also includes: If at least one memory cell in the target area is faulty, the testing of the DRAM chip under test shall be stopped. The fault address in the target area is determined based on the address of the faulty storage unit.

6. The chip storage area testing method according to claim 1, characterized in that, The chip storage area testing method also includes: If a faulty memory cell exists in the target area, the redundant memory cells in the DRAM chip under test are obtained. If the redundant storage unit is not faulty, the faulty storage unit in the target area is mapped to the redundant storage unit; The target test program is loaded into the target area, excluding the faulty storage unit and the redundant storage unit.

7. A chip storage area testing device, characterized in that, The chip storage area testing device includes: The acquisition module is used to acquire the address of a target region in the DRAM chip under test, wherein the target region is the physical memory space occupied by the target test program in the DRAM chip under test, wherein the target test program is a bootloader, the bootloader is used to test a first region where the kernel program is stored, the kernel program is used to test a second region, and the first region, the second region and the target region constitute the storage region of the DRAM chip under test; The loading module is used to load the initial test program into the SRAM chip outside the DRAM chip to be tested in the test system SOC. Before the target test program occupies the target area, the initial test program is called to test the target area according to the address. The testing module is used to test areas of the DRAM chip under test other than the target area, according to the target test program and the target area, provided that the target area has passed the test. The method is further configured to test regions other than the target region in the DRAM chip under test according to the target test program and the target region in the following manner: loading the bootloader to the target region and executing the bootloader to test the first region; after the first region passes the test, loading the kernel program to the first region and executing the kernel program to test the second region.

8. A chip storage area testing device, characterized in that, The chip storage area testing equipment includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the chip memory area testing method as described in any one of claims 1 to 6.

9. A computer storage medium, characterized in that, The computer storage medium is used to store program data, which, when executed by the computer, is used to implement the chip storage area testing method as described in any one of claims 1 to 6.

Images