Simple gate oxide integrity test device and test method thereof

Abstract

The application provides a simple gate oxide integrity testing device, which comprises a test sample and a test structure; the test sample comprises a substrate, a dielectric layer (gate oxide layer) on the substrate, a gate replacement layer used for replacing a gate layer or being located above the gate layer, so that the test sample forms a three-layer structure comprising the substrate-dielectric layer-gate replacement layer, and the gate oxide integrity of the dielectric layer is tested by combining a thermal desorption technology; the test structure is used for accommodating the test sample, providing a test temperature, and recording released elements; the application also provides a simple gate oxide integrity testing method, which has the technical effects of low cost, simple operation, and rapid feedback of test results, and does not need to prepare a transistor device, adopts the gate replacement layer arranged on the substrate-dielectric layer (gate oxide layer) to combine the thermal desorption technology, and directly tests the stacked layer material contained in a MOS stacked layer structure.

Description

Technical Field

[0001] This invention relates to the technical field of testing or testing methods or equipment specifically applicable to the manufacturing or handling of semiconductor or solid-state devices or their components, and in particular to a simplified testing apparatus and testing method that replaces the traditional gate oxide integrity test TDDB. Background Technology

[0002] In the semiconductor manufacturing field, gate oxide integrity (GOI) is used to evaluate the quality of the gate dielectric / oxide layer. As the physical thickness of the dielectric / oxide layer continues to decrease, it faces severe problems such as leakage and easy breakdown. Evaluating the dielectric / oxide layer's resistance to electrical breakdown has become a key indicator for measuring the lifespan of semiconductor devices.

[0003] Traditional gate oxide integrity tests include Time-Dependent Dielectrics Breakdown (TDDB), V-ramp, and J-ramp, all of which test the dielectric / oxide layer's breakdown resistance / lifetime by applying voltage / current across the gate dielectric / oxide layer. Figure 1 As shown in b, the TDDB test requires a top electrode 101 and a low electrode 102 to be provided on both sides of the dielectric layer 12 of the semiconductor device 1 (e.g., MOS) to apply a gradually decreasing or increasing voltage until the dielectric layer 12 is broken down or damaged, thereby achieving the purpose of testing the gate oxide integrity.

[0004] Traditional gate oxide integrity testing has the following drawbacks:

[0005] First, it has poor timeliness. It requires setting physical electrodes on standard devices to apply long-term stress current or voltage. Therefore, the entire process must be completed to prepare the sample to be tested after the standard device manufacturing is completed. It cannot be detected online in real time, which seriously restricts the efficiency of the production line. The dual time consumption problem in the preparation and long-term stress loading process has become the efficiency bottleneck of the mass production line. When the gate oxide reliability degrades due to process changes, the traditional GOI test method cannot provide timely feedback information, which can easily lead to a decrease in yield.

[0006] Secondly, the cost is high. Additional testing equipment needs to be designed, and the device needs to undergo thousands of hours of accelerated stress testing in a high temperature and high electric field environment, which consumes a lot of time and financial costs.

[0007] Third, it belongs to the standard device (finished product) testing, which is not compatible with semiconductor manufacturing processes, cannot meet the needs of rapid and high-quality production, and is inefficient. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a simple testing device and method for thermal desorption spectroscopy (TDS) or equivalent technology to replace traditional gate oxide integrity testing, in order to solve the problems of poor timeliness, high cost and incompatibility with the process of the prior art.

[0009] To achieve the above and other related objectives, the present invention provides a simple gate oxide integrity testing device, comprising a test sample and a test structure:

[0010] The test specimen includes a substrate and a dielectric layer located on the substrate; it also includes,

[0011] A substitute gate layer is used to replace the gate layer of the test specimen or is located above the gate layer of the test specimen, so that the test specimen forms a stacked structure including at least the substrate-the dielectric layer-the substitute gate layer to test the gate oxide integrity of the dielectric layer.

[0012] The test structure is used to contain the test sample, provide a test temperature, and record the release of at least one element with a mass-to-charge ratio of 2 or 18 by the test sample during the process of reaching the test temperature.

[0013] The test sample is at least one of the following: untreated by photolithography, undoped, without electrodes, treated by photolithography, doped, or with electrodes.

[0014] Preferably, the dielectric layer comprises an oxide layer, and the gate electrode layer comprises polysilicon, TiN, TaN, W, Mo, Ru, Co, N, or a metal silicide.

[0015] Preferably, the test structure is heated or illuminated to provide the test temperature.

[0016] Preferably, the test structure is a thermal desorption mass spectrometer.

[0017] Preferably, the test temperature is room temperature to 1200 degrees Celsius, above 900 degrees Celsius, above 1100 degrees Celsius, or above 1200 degrees Celsius.

[0018] The present invention also provides a simple method for testing gate oxide integrity, using the testing apparatus described above, and further comprising:

[0019] Place the test sample into the test structure;

[0020] The test structure provides the test temperature and records the elements released by the test sample during the process of reaching the test temperature;

[0021] Analyze the changes in the elements with temperature or time to determine the gate oxide integrity.

[0022] Preferably, the variation features include at least one of element type, element quantity, mass-to-charge ratio, or thermal desorption mass spectrum.

[0023] Preferably, it includes thermal desorption mass spectra with a mass-to-charge ratio ranging from 1 to 200.

[0024] Preferably, the integrity of the gate oxide is determined by the peak characteristics of the thermal desorption mass spectrum.

[0025] To enable the semiconductor manufacturing process to use the above-described testing apparatus and methods in real time, the present invention also proposes a manufacturing method for real-time detection of gate oxide integrity, which uses any of the above-described testing methods before photolithography, before doping, before electrode placement, after photolithography, after doping, or after electrode placement.

[0026] As described above, the simplified gate oxide integrity testing device and method of the present invention can use a substitute gate layer to replace the gate layer, and can test the gate oxide integrity of the dielectric layer without completing the complete manufacturing process of the semiconductor standard device. Alternatively, a substitute gate layer can be set above the gate layer of the standard device (standard transistor), and there is no need to set electrodes on the test sample. The gate oxide integrity of the device can be tested after the main structure of the device substrate-dielectric layer-substitute gate layer is completed. It has high efficiency, low cost and is compatible with semiconductor manufacturing processes. The method is flexible and can be performed offline or in real time on the production line to detect the gate oxide integrity of semiconductor devices. Attached Figure Description

[0027] Figure 1 a is a test sample (transistor) with a substitute gate layer used in the simplified GOI test apparatus of this invention.

[0028] Figure 1 b is the standard device used in the traditional GOI test method with a gate layer, compared with 1a.

[0029] Figure 2 This is a flowchart of the preparation of test specimens (transistors) A and B with different Qt durations and gate layers.

[0030] Figure 3 These are the TDDB curves obtained from testing samples A and B using the traditional GOI test method (TDDB).

[0031] Figure 4 a is the thermal desorption mass spectrum of H2O (mass charge ratio m / z is 18) obtained by testing samples A and B using the simplified GOI test method of this invention.

[0032] Figure 4b is the H2 (mass charge ratio m / z is 2) thermal desorption mass spectrum obtained by testing samples A and B using the simplified GOI test method of this invention.

[0033] Figure 5 This is a thermal desorption mass spectrum of H2O (mass charge ratio m / z is 18) obtained by testing samples in three states using the simplified GOI test method of this invention.

[0034] Figure 6 a is the thermal desorption mass spectrum of H2O (mass charge ratio m / z is 18) obtained by the simplified GOI test method of this invention.

[0035] Figure 6 b is the H2O (mass charge ratio m / z is 18) thermal desorption mass spectrum obtained by testing a transistor without a deposited gate layer using the simplified GOI test method of this invention.

[0036] Figure 7 a is Figure 2 The transmission electron microscope (TEM) cross-sectional image of the prepared sample A shows a high-angle annular dark field (HAADF) image of the top part of the gate layer surface and the bottom part of the gate oxide region on the left side, and an oxygen distribution map (red represents oxygen) on the right side.

[0037] Figure 7 b is Figure 2 The transmission electron microscope (TEM) cross-sectional image of the prepared sample B shows a high-angle annular dark field (HAADF) image of the gate oxide layer surface (upper part) and gate oxide region (lower part) on the left half, and an oxygen element (red represents oxygen) distribution map on the right half.

[0038] Figure 8 yes Figure 2 The oxygen content distribution of each part of the transistor obtained by energy dispersive spectroscopy (EDS) analysis of the prepared samples A and B.

[0039] Figure 9 This is a schematic diagram of the test structure in the simplified GOI test device of the present invention.

[0040] Figure 10 This is a flowchart of the simplified gate oxide integrity test method of the present invention.

[0041] Figure 11 This is the thermal desorption mass spectrum of H2 (mass-to-charge ratio m / z = 2) obtained by testing a simplified MOS device after extending the waiting time Qt using the test method of this invention.

[0042] Figure 12 The test method of this invention is used to test the thermal desorption mass spectrum of H2O (mass charge ratio m / z is 18) obtained by a simple MOS device after extending the waiting time Qt.

[0043] Component designation explanation

[0044] Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0047] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0048] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0049] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0050] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] This invention provides a simple gate oxide integrity testing device, such as... Figure 9 and Figure 1 As shown in Figure a, the test sample 1 and the test structure 2 are included. The test sample 1 includes a substrate 13 and a dielectric layer 12 located on the substrate 13. The substrate 13 includes silicon and can be a silicon substrate, a silicon-containing substrate such as a silicon carbide substrate, or an epitaxial wafer of other silicon-containing substrates. The dielectric layer 12 can be an oxide layer, a nitride layer, a silicate layer, an aluminate layer, an oxygen-containing low-k dielectric layer, or a high-k dielectric layer, such as SiO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2, LaAlO3, SiAlO, Si3N4, SiON, Y2O3, Sc2O3, Gd2O3, ZrSiO, HfAlO, AlON, TiO2, SrTiO3, BaTiO3, and BST, etc.

[0053] The test structure 2 is used to accommodate the test sample 1, provide a test temperature, and record the elements released by the test sample 1 during the process of reaching the test temperature. The test structure 2 includes a heating unit 21 to provide the test temperature, a vacuum unit 22 to provide the vacuum environment required for the test, a temperature control unit 23 to adjust the test temperature, and a mass spectrometer 24 to record the elements released by the test sample 1. It should be noted that in other embodiments, the heating unit 23 can adjust the test temperature without the need for a temperature control unit 23. The mass spectrometer 24 records the elements in real time as the temperature changes within the test structure 2, including their type and quantity, and processes the data to form a mass spectrum. Figure 9 As shown, test structure 2 is a thermal desorption mass spectrometer (TDS), including a load lock sample inlet chamber and an ultra-high vacuum test chamber. The background vacuum of the test chamber is < 1E-7 Pa, such as the common ESCO TDS1200II system. Heating unit 21 is an infrared heating module, vacuum unit 22 is an ultra-high vacuum (UHV) chamber, temperature control unit 23 is a thermocouple, and mass spectrometer 24 is a quadrupole mass spectrometer and sample stage (not shown). The background pressure within vacuum unit 22 is better than 1 × 10⁻⁶ Pa. -7Pa, the mass range of which is 1~200 amu, the infrared heating module provides the test temperature by irradiating the sample with far-infrared filament, and the thermocouple is installed under the sample stage (not shown) to provide real-time temperature feedback; during the test, the heating rate of the TDS1200II system is fixed at 1~180℃ / min, and the heating rate can be fixedly set to 60℃ / min.

[0054] The test sample 1 is formed with at least the substrate 13, the dielectric layer 12, and the substitute gate layer 11 to test the gate oxide integrity of the dielectric layer 12. It should be noted that the stacked structure is only described as having a dielectric layer 12 formed on the substrate 13 and a substitute gate layer 11 formed on the dielectric layer 12. Other layer structures may exist between the substrate 13 and the dielectric layer 12, and other layer structures may also exist between the dielectric layer 12 and the substitute gate layer 11.

[0055] The applicant will further elaborate on the effectiveness of the simple gate oxide integrity testing device (method) achieved by combining the gate layer 11 in the test sample 1 with the thermally desorbed test structure 2.

[0056] Test sample 1 has a "substrate 13-dielectric layer 12-substitute gate layer 11" structure. The substitute gate layer 11 can either replace the gate layer of the standard transistor (i.e., replace the gate layer) to test the gate oxide integrity of the dielectric layer 12, or it can be placed above the gate layer of the standard transistor to test the gate oxide integrity of the dielectric layer 12. That is, it forms two structures: "substrate 13-dielectric layer 12-substitute gate layer 11" or "substrate 13-dielectric layer 12-gate layer (not shown)-substitute gate layer 11". It can also be other structures with the following characteristics: it consists of at least three thin films, namely a substrate, a gate oxide film, and an electrode layer. The material and stacking order of each thin film layer are the same as those of the MOS transistor that functions as the gate oxide. The stack structure is the same; the test sample 1 with the structure "substrate 13-dielectric layer 12-substitute gate layer 11" can be embedded in the process and can be fabricated from a transistor that has not undergone photolithography, doping, and electrode placement; the test sample 1 with the structure "substrate 13-dielectric layer 12-gate layer (not shown)-substitute gate layer 11" can be fabricated by covering a standard transistor with a substitute gate layer 11 on top of a standard transistor that has undergone photolithography, doping, and electrode placement. The substitute gate layer 11 is polycrystalline silicon or other gate electrode materials such as TiN, TaN, W, Mo, Ru, Co, Ni, and metal silicides; therefore, based on the substitute gate layer 11, the test sample 1 can be a full-wafer simple transistor or a standard transistor. The thickness of the substitute gate layer 11 is 900~1200 Å, preferably 1050 Å.

[0057] The following section will further introduce the concept using a full wafer-level (FULL WAFER) simplified transistor as an example. The applicant will not elaborate further on the full wafer-level (FULL WAFER) standard transistor.

[0058] like Figure 2 As shown, after the formation of dielectric layer 12 and before the deposition of gate layer 11, different waiting times (Queue time, Qt) are set to form different samples. The waiting time QtA for sample A is 12 hours, and the waiting time QtB for sample B is 32 hours. Sample A and sample B are formed after the deposition of gate layer 11. Figure 3 As shown, the horizontal axis represents the cumulative injected charge (Qbd) at breakdown, and the vertical axis represents the cumulative failure probability obtained by the Weibull distribution model. Samples A and B were tested using the traditional TDDB test GOI. Samples A and B showed significant differences in TDDB behavior. As the waiting time Qt during the deposition of the polysilicon gate layer 11 increased, the cumulative injected charge (Qbd) of sample B was significantly higher than that of sample A, indicating that sample B has a longer device lifetime under the same stress conditions. This trend is also reflected in the increase of the Weibull distribution slope and the increase of the characteristic breakdown charge (Qbd@63%). The relevant data are summarized in Table 1, showing that sample B, which was placed in the production line environment for a longer natural oxidation time, has better gate oxide integrity. Figure 4 As shown, the mass spectra of the elements released after heating in this test structure 1 for samples A and B exhibit characteristic γ peaks. Compared to sample A, sample B, which was placed in the production line environment for a longer period, also shows better gate oxide integrity. Figure 3 The TDDB (method) verified Figure 4 The characteristic γ peak of the simplified testing device (method) of the present invention is effective, and its consistency confirms the preliminary effectiveness of the test structure and test sample in detecting the integrity of the gate oxide.

[0059] Table 1

[0060]

[0061] To further verify the effectiveness of this simplified GOI test device in detecting the gate oxide integrity of the dielectric layer 12 before depositing the gate layer 11, such as... Figure 5 As shown, the applicant will select Figure 2The prepared samples were sequentially subjected to three states: State 1 (placed in test structure 2 for heating and desorption, i.e., the original deposition); State 2 (sample placed in test structure 2 after State 1, cooled, and then heated and desorbed again, i.e., the original deposition without air exposure); and State 3 (sample removed from test structure 2 after State 1 or State 2, exposed to ambient air in the production line for a period of time, and then placed back into test structure 2 for heating and desorption, i.e., the original deposition exposed to air). It is evident that the State 2 sample without ambient air exposure did not exhibit a characteristic γ peak, indicating that the waiting time Qt in the ambient air is positively correlated with gate oxide integrity. Simultaneously... Figure 4 and Figure 5 The non-characteristic nature of the α and β peaks in testing gate oxide integrity in this invention was verified. Specifically, the physical origin of the high-temperature γ peak was investigated. The adsorption behavior of the sample was studied using TDS. First, the deposited sample underwent its first TDS measurement, termed "as-deposited". After the first State 1 test, the sample was kept in the TDS chamber until the system returned to its initial temperature and vacuum conditions, at which point a second test was performed, termed "without air-exposure". Once the desorption peak signal disappeared, the sample was removed from the chamber and exposed to ambient air for 8 hours, followed by a third TDS test, termed "with air-exposure". Figure 5 The TDS results for the same sample at states 1 through 3 are presented. In state 1, “as-deposited” (blue curve), a significant desorption peak appears at m / z=18. In contrast, in state 2, “without air-exposure” (orange curve), these peaks almost disappear, leaving only a baseline signal, indicating that most of the desorbed material was released during the first heating process. Notably, after 8 hours of air exposure, state 3 again shows significant desorption peaks in the TDS spectrum, especially the reappearance of the high-temperature γ peak, suggesting that this desorption behavior originates from the surface and is influenced by air exposure. This finding indicates that some of the gas released during heating originates from surface-adsorbed material, and this adsorption can be recovered through atmospheric exposure. Therefore, we infer... Figure 4 The high-temperature γ peaks observed are mainly related to surface adsorbed species, and the corresponding adsorption-desorption processes are reversible.

[0062] To further verify the effectiveness of the simplified GOI testing device of the present invention in detecting the gate oxide integrity of the dielectric layer 12 by setting a substitute gate layer 11 on the test sample 1, as follows: Figure 6 As shown in Figure a, the applicant placed a substrate 13 made of monocrystalline silicon (a pre-cleaned monocrystalline silicon substrate can be used directly) in the ambient air of the production line for time T, and then placed it in the test structure 2. After thermal desorption, a characteristic γ peak was observed; as shown in Figure a. Figure 6 As shown in b, the applicant will Figure 6In test structure 2, a bilayer structure of "substrate 13-dielectric layer 12" (i.e., without a polysilicon gate layer 11) with a 7.1nm silicon dioxide layer (gate oxide layer) formed on a single-crystal silicon substrate through ISSG, DPN, and PNA processes was placed in the ambient air of the production line for time T. After thermal desorption, no characteristic γ peak was observed. This indicates that the element released by thermal desorption corresponding to the characteristic γ peak originated from the ambient air of the production line, and the polysilicon gate layer 11 on the dielectric layer 12 (silicon dioxide layer) could not adsorb the element corresponding to the characteristic γ peak. This shows the effectiveness of the polysilicon gate layer 11 in testing the gate oxide integrity of the dielectric layer 12 in this simple GOI test device. At the same time, the shift of the high-temperature TDS peak related to TDDB behavior is not directly reflected in the oxide dielectric layer 12 itself, but only appears after the growth of the polysilicon gate layer 11. This observation suggests that the polysilicon gate layer 11 may play a key role in amplifying the structural differences caused by process differences.

[0063] Combination Figure 7 and Figure 8 To further investigate the structural and compositional differences between the samples, the applicant conducted transmission electron microscopy (TEM) analysis on samples A and B. Figure 7 The results show that there are significant differences in oxygen distribution on the surface of the polysilicon gate layer 11 between the two samples. Figure 8The energy dispersive spectroscopy (EDS) analysis shows the oxygen content distribution at 12 points along the polysilicon gate-substitute layer 11 surface, through the dielectric layer (gate oxide region), to the substrate. The results indicate that the oxygen concentration in the native oxide layer (i.e., the primary oxide layer) on the surface of the polysilicon gate-substitute layer 11 of sample B is significantly higher than that of sample A, while the difference in oxygen content between the two is not significant in other regions. Furthermore, D-SIMS and TOF-SIMS analyses were performed on samples A and B. The depth distribution curves for nitrogen, hydrogen, and oxygen (not shown) show no significant difference in the content of these elements between the two samples. This further supports the finding that thermal desorption techniques such as TDS are effective in detecting GOI, indicating that the main difference between samples A and B is concentrated on the surface of the polysilicon gate-substitute layer 11. Extending the waiting time (Qt) allows a thicker, more oxygen-rich native oxide layer to form on the polysilicon surface of sample B. This surface characteristic leads to the shift of the high-temperature γ peak in the TDS spectrum. Based on the TDDB results, it can be inferred that the native oxide layer on the surface of the polysilicon gate layer 11 is one of the key factors affecting the TDDB failure distribution of the dielectric layer 12. The surface layer of the polysilicon gate layer 11 acts as a barrier against hydrogen impurity penetration, and its shielding effectiveness is affected by the surface composition (such as oxygen content). As is well known, hydrogen impurities diffuse into the gate oxide and participate in the breakdown process, significantly affecting the TDDB lifetime distribution. The extended latency Qt may first change the microstate of the gate oxide (dielectric layer 12) surface, thereby affecting the nucleation and growth behavior of the polysilicon gate layer 11 and leading to differences in the polysilicon surface composition. In the subsequent BEOL process, impurities may diffuse from the surface of the polysilicon gate layer 11 into the device, such as the MOS stack. Differences in the surface composition of the polysilicon gate layer 11 result in different impurity blocking capabilities, ultimately affecting device reliability. TDS shows extremely high sensitivity to small changes caused by the process, demonstrating its effectiveness as a fast and low-cost GOI assessment tool.

[0064] The test temperature in the above thermal desorption is room temperature to 1200 degrees Celsius, above 900 degrees Celsius, above 1100 degrees Celsius, or above 1200 degrees Celsius; the heating unit 21 provides the test temperature by heating or light.

[0065] The simplified gate oxide integrity testing device of the present invention can use a substitute gate layer 11 to replace the gate layer (not shown). It can test the gate oxide integrity of the dielectric layer 12 without completing the complete manufacturing process of the semiconductor standard device. Alternatively, the substitute gate layer 11 can be set above the gate layer (not shown) of the standard device (standard transistor). There is no need to set electrodes on the test sample 1. The gate oxide integrity of the sample can be tested after completing the three-layer main structure of the device substrate 13-dielectric layer 12-substitute gate layer 11. It is highly efficient, low cost and compatible with semiconductor manufacturing processes. The method is flexible and can be used for post-production testing or real-time detection of the gate oxide integrity of transistors on the production line.

[0066] This invention also provides a simple method for testing gate oxide integrity, using the testing apparatus described above, such as... Figure 10 As shown, it also includes the following steps:

[0067] S1. Prepare test sample 1 to form a three-layer structure of substrate-dielectric layer-gate layer;

[0068] S2. Place the test sample 1 into the test structure 2;

[0069] S3. The test structure 2 provides the test temperature and records the elements released by the test sample 1 during the process of reaching the test temperature;

[0070] S4. Analyze the characteristics of elemental changes with temperature or time to determine the integrity of the gate oxide.

[0071] To form the "simple transistor" described above, such as Figure 2 As shown, the dielectric layer 12 of the actual design of the test sample semiconductor device / transistor product is only an example. S1 also includes steps S10-S131 / S132:

[0072] S10, Pre-cleaning of silicon wafers or substrates 13

[0073] The silicon wafer or substrate 13 has a diameter of at least about 20 mm, and more typically between about 20 mm and about 500 mm. In some embodiments, the diameter is at least about 20 mm, at least about 45 mm, at least about 90 mm, at least about 100 mm, at least about 150 mm, at least about 200 mm, at least about 250 mm, at least about 300 mm, at least about 350 mm, or even at least about 450 mm. The thickness of the silicon wafer or substrate 13 may be between about 100 micrometers and about 5000 micrometers, such as between about 100 micrometers and about 1500 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers.

[0074] When present as an impurity in the starting silicon wafer or substrate 13, substituted carbon has the ability to catalyze the formation of oxygen precipitate nucleation centers. Therefore, it is preferable that the starting silicon wafer or substrate 13 has a low carbon concentration. That is, the carbon concentration of the starting silicon wafer or substrate 13 is preferably less than about 5 × 10⁻⁶. 16 atoms per cubic centimeter, preferably less than 1 × 10⁻⁶ 16 One atom per cubic centimeter, and more preferably less than 5 × 10⁻⁶ atoms per cubic centi 15 One atom per cubic centimeter.

[0075] The resistivity of the silicon wafer or substrate 13 is not critical to the method of the present invention and varies depending on the end-use requirements. The silicon wafer or substrate 13 may be heavily doped, semi-insulating, or have an intermediate doping profile. In some embodiments, the silicon wafer or substrate 13 contains p-type or n-type dopants. Suitable dopants include boron (p-type), gallium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The dopant concentration is selected based on the desired wafer resistivity. In some embodiments, the wafer type may have a resistivity such that it can be characterized as any one of N++, N+, N, N-, and N--. Typical N+ resistivity ranges down to 10 milliohms-cm for Sb doping, down to 2 milliohms-cm for As doped N++, and down to 1 milliohm-cm for P doped N++++. In some embodiments, the resistivity can be in the range of about 0.1 milliohm-cm to about 1 kilohm-cm, such as 0.1 milliohm-cm to about 100 ohm-cm, such as 0.1 milliohm-cm to about 10 ohm-cm, or about 0.1 milliohm-cm to about 1 ohm-cm. In some embodiments, the resistivity can be in the range of about 0.01 ohm-cm to about 1 kilohm-cm, such as 0.01 ohm-cm to about 100 ohm-cm, such as 0.01 ohm-cm to about 10 ohm-cm, or about 0.01 ohm-cm to about 1 ohm-cm. Substrates in lightly doped forms, such as N-type (phosphorus) and P-type (boron), are also available, rated at 1 ohm-cm, 10 ohm-cm, or 100 ohm-cm. The choice of substrate resistivity depends on the application (e.g., if the substrate is used as a back gate, then a lower resistivity is preferred).

[0076] Clean the silicon wafer or substrate 13 before rapid thermal annealing to remove, for example, organic matter or other impurities. A piranha solution can be used, which contains concentrated H2SO4 and H2O2 (30% solution), usually in a 3:1 ratio, but other ratios such as 4:1 or 7:1 may be used as appropriate. The cleaning time should be between about 15 minutes and about 2 hours.

[0077] Preferably, substrate 13 is a 300mm p-type (100) silicon wafer.

[0078] S11, In-situ vapor growth of ISSG to form dielectric layer 12 (oxide film):

[0079] Regarding the formation of the silicon dioxide dielectric layer 12, an in-situ steam generation (ISSG) process can be used, employing ISSG oxidation with dichloroisocyanurate at a preferred temperature of 800-1100°C. The resulting ultrathin dielectric layer 12 is silicon dioxide. In practical applications, rapid thermal oxidation (RTO) or ISSG oxidation (using oxygen and hydrogen as the reaction gases) can also be used. Other existing technologies for forming the silicon dioxide dielectric layer 12 will not be elaborated upon here.

[0080] Due to the different types of test samples, the above-mentioned dielectric layer 12 material may vary, such as high-K dielectric layer, and the existing ISSG process, thin film process, or other processes may be adopted. The applicant will not elaborate on these details here.

[0081] S12, Decoupled plasma nitriding of the DPN dielectric layer to dope nitrogen, followed by nitriding annealing of the PNA to form a high-quality dielectric layer 12 (oxide film):

[0082] To form a high-quality silicon dioxide dielectric layer 12, high-temperature pure N is used to bake and eliminate the positive charge on the surface of the substrate 13, a high-quality oxide layer is generated by decoupled plasma nitriding (DPN) plasma nitriding, and a post nitriding annealing (PNA) process is used to improve nitrogen fixation efficiency, thus forming a silicon dioxide dielectric layer 12 with a thickness of 7.1 nm.

[0083] After a waiting time QtA of 12 hours, the gate replacement layer 11 of sample A is processed in step S131; after a waiting time QtA of 32 hours, the gate replacement layer 11 of sample B is processed in step S132.

[0084] Step 131 / Step 132: Deposit a polycrystalline silicon or monocrystalline silicon gate layer 11 on the dielectric layer; Depositing polycrystalline silicon and monocrystalline silicon are existing technologies, and the applicant will not elaborate on them here; Full wafer-level simple transistors can continue to steps S2~S4 without photolithography, and can be embedded in the production line for real-time detection.

[0085] To form the "standard transistor" mentioned above, between steps S10-S12 and steps S131 / S132, there are also process steps such as photolithography to form a normal gate layer. These process steps vary depending on the type of transistor and are existing technology, so the applicant will not elaborate on them here.

[0086] Step S2: Place the test sample 1 into the test structure 2, such as the thermal desorption mass spectrometer;

[0087] After the wafer is cleaved into fragments of 0.5*0.5cm to 2*2cm, the test sample is obtained. Preferably, the wafer is cleaved into fragments of 1*1cm and then placed into a thermal desorption mass spectrometer.

[0088] Step S3: The test structure 2 provides the test temperature using a thermal desorption mass spectrometer. The programmed temperature range is set to RT-900℃ / 1100℃ / 1200℃, i.e., the test temperature is 900℃ / 1100℃ / 1200℃. The heating rate is set to 1~180℃ / min, preferably 60℃ / min. The QMS acquisition program of the thermal desorption mass spectrometer is opened, and the desorption spectrum of the sample is acquired using the thermal desorption mass spectrometer. The elements released by the test sample 1 during the process of reaching the test temperature are recorded.

[0089] Step S4: Analyze the changes in elements with temperature or time to determine the gate oxide integrity; determine the device reliability based on the thermal desorption spectrum of the test sample.

[0090] like Figures 4-6 As shown, the variation characteristics include at least one of element type, element quantity, mass-charge ratio, or thermal desorption mass spectrum, including thermal desorption mass spectra with a mass-charge ratio range of 1 to 100, preferably including thermal desorption mass spectra with mass-charge ratios of 2, 18, 28, and 44.

[0091] like Figure 1 a, Figure 1 b、 Figure 11 , Figure 12 As shown, several silicon wafer substrates with a diameter of 300 mm were prepared, and more than 90 processes, including oxidation, deposition, etching, and photolithography, were combined to fabricate the following: Figure 1 The standard MOS device shown in b is a standard transistor and... Figure 1 The simplified MOS device shown in a is a simplified transistor. The standard MOS device can be fabricated with 136 dies per silicon wafer substrate 13. Each die contains a polycrystalline silicon layer with different shapes and sizes (referred to as different "patterns") of various standard devices, with at least 50 of each type of device. The simplified MOS device is full wafer-level and does not involve photolithography.

[0092] By extending the waiting time Qt for the deposition of the polysilicon gate layer 11 in the process, i.e., the atmospheric exposure time, two different sets of samples were obtained. The first set contains two types of devices: a standard MOS device and a simplified MOS device fabricated using the standard waiting time Qt process, denoted as A1 and A2. The second set contains a standard MOS device and a simplified MOS device fabricated using the extended waiting time Qt process, denoted as B1 and B2.

[0093] The obtained A1 and B1 devices were placed on a CM300 probe station. Twenty-five dies were selected, and one pattern for each die was subjected to TDDB testing using the CM300 probe station. The test results were obtained as follows: Figure 3 The results shown are those obtained using the traditional GOI evaluation method. Test results indicate that extending the latency Qt improves the device's Qbd to some extent.

[0094] Devices A2 and B2 were cleaved to a size of 1*1cm to obtain test samples, which were then transferred to a thermal desorption mass spectrometer.

[0095] The program temperature range is set to RT-1200℃, and the heating rate is set to 60℃ / min.

[0096] Open the QMS acquisition program of the thermal desorption mass spectrometer, and use the thermal desorption mass spectrometer to acquire the desorption spectrum of the test sample to obtain the test results, such as... Figure 10 and Figure 11 The figure shows the results obtained by using TDS instead of GOI for evaluation in this invention. It shows that after extending the waiting time Qt, the TDS peak of the simplified MOS device shifts, which is reflected in the desorption curves of B2 at different charge-to-mass ratios. For example, the double peak in the 900-1000℃ range when m / z=2 shifts towards lower temperatures after extending the waiting time Qt, and the peak around 950℃ when m / z=18 shifts towards lower temperatures after extending the waiting time Qt.

[0097] This invention also proposes a manufacturing method for real-time detection of gate oxide integrity. The testing method described above can be used before photolithography, before doping, before electrode setup, after photolithography, after doping, or after electrode setup. This method can be embedded in the production line to detect gate oxide integrity in real time, provide timely feedback, improve process improvement efficiency, and effectively improve product yield.

[0098] This invention provides a simple gate oxide integrity testing device and method. A substitute gate layer 11 can be used to replace the gate layer, and the gate oxide integrity of the dielectric layer 12 can be tested without completing the complete manufacturing process of a standard semiconductor device. Alternatively, a substitute gate layer 11 can be placed above the gate layer (not shown) of a standard device (standard transistor), eliminating the need to place electrodes on the test sample 1. The gate oxide integrity of the sample can be tested after completing the three-layer main structure of the device substrate 13-dielectric layer 12-substitute gate layer 11. The method is highly efficient, low-cost, compatible with semiconductor manufacturing processes, and flexible. It can be used for post-production testing or for real-time detection of the gate oxide integrity of transistors on the production line.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A simple gate oxide integrity testing device, characterized in that, Including test specimens and test structures: The test specimen includes a substrate and a dielectric layer located on the substrate; it also includes, A substitute gate layer is used to replace the gate layer of the test specimen or is located above the gate layer of the test specimen, so that the test specimen forms a stacked structure including at least the substrate-the dielectric layer-the substitute gate layer to test the gate oxide integrity of the dielectric layer. The test structure is used to contain the test sample, provide a test temperature, and record the release of at least one element with a mass-to-charge ratio of 2 or 18 from the test sample during the process of reaching the test temperature from room temperature. The test sample is one of the following: untreated by photolithography, undoped, without electrodes, treated by photolithography, doped, or with electrodes.

2. The testing apparatus according to claim 1, characterized in that, The dielectric layer comprises an oxide layer, and the gate layer comprises polysilicon, TiN, TaN, W, Mo, Ru, Co, or a metal silicide.

3. The testing apparatus according to claim 1, characterized in that, The test structure is heated or illuminated to provide the test temperature.

4. The testing apparatus according to claim 1, characterized in that, The test setup is a thermal desorption mass spectrometer.

5. The testing apparatus according to claim 1, characterized in that, The test temperature is above 900 degrees Celsius.

6. A simplified method for testing gate oxide integrity, characterized in that, The test apparatus as described in any one of claims 1 to 5 further includes, Place the test sample into the test structure; The test structure provides the test temperature and records the elements released by the test sample during the process of reaching the test temperature from room temperature; Analyze the changes in the elements with temperature or time to determine the gate oxide integrity.

7. The test method according to claim 6, characterized in that, The variation characteristics include at least one of the following: element type, element quantity, mass-to-charge ratio, or thermal desorption mass spectrum.

8. The test method according to claim 7, characterized in that, Includes thermal desorption mass spectra with a mass-to-charge ratio range of 1-200.

9. The test method according to claim 7, characterized in that, Gate oxide integrity is determined by the peak characteristics of the thermal desorption mass spectrum.

10. A manufacturing method for real-time detection of gate oxide integrity, characterized in that, The test method described in any one of claims 6 to 9 is used before photolithography, before doping, before electrode setup, after photolithography, after doping, or after electrode setup.

Images