A low-power ruggedized module with controllable clock edge timing

Abstract

This application relates to a low-power ruggedized module with controllable clock edge timing. The module includes a clock gating circuit, a ruggedized unit, and a clock and power supply module. In the clock gating circuit, the substrates of two PMOS transistors are connected to a variable DC power supply to achieve controllable clock edge timing. The ruggedized unit uses a cross-coupled CMOS bistable structure through a bistable latch module to store the synchronous data after clock gating in nodes X0 to X3, and inputs the data to nodes X0 to X3 through an input path via an input control module. In the clock and power supply module, the voltage VDD is set to 1V, reducing overall power consumption and saving energy. This module has the function of resisting six-node flip-flops, making it more robust and safer.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a low-power ruggedized module with controllable clock edge timing. Background Technology

[0002] Polar hardening, also known as radiation hardening or single-event hardening, aims to improve the reliability and stability of integrated circuits under radiation or high-energy particle bombardment. Polar hardening is primarily used in fields with extremely high reliability requirements, such as aerospace, avionics in commercial flights at high altitudes, medical electronics, and high-reliability industrial and automotive applications.

[0003] When high-energy particles (such as protons and heavy ions in space, or alpha particles and neutrons on the ground) penetrate a semiconductor chip, they generate a brief, localized electron-hole pair in the silicon material through ionization. If this charge packet is collected by sensitive circuit nodes, it may lead to the following consequences: (1) Soft error: The circuit logic state flips unexpectedly (such as 0 to 1, or 1 to 0), but the hardware itself is not permanently damaged. This is the most common single-event effect. (2) Latch-up: Triggers parasitic thyristor structures, resulting in a low-resistance path between the power supply and ground, causing a large current, which may burn out the chip. (3) Gate oxide breakdown: High-energy particles directly cause permanent damage to the ultrathin gate oxide layer. Polar hardening technology was developed to suppress these effects.

[0004] In circuit design, NMOS or PMOS transistors can be used to completely surround a node. When bombarded by particles, the node voltage will only change in a single direction; this transistor characteristic is called polarity. Specifically, when a node is surrounded entirely by NMOS transistors, the node voltage will only transition to a low level (logic value changes from 1 to 0), and will not transition to a high level (logic value changes from 0 to 1). Similarly, when a node is surrounded entirely by PMOS transistors, the node voltage will only transition to a high level (logic value changes from 0 to 1), and will not transition to a low level (logic value changes from 1 to 0). Therefore, the design approach of placing a node in a state where it is completely surrounded by a certain type of transistor is called polarity hardening technology.

[0005] To mitigate the susceptibility of PMOS transistors, radiation hardening technology has been extensively researched and developed, with several hardening techniques emerging. Currently, shallow trench isolation (STI) is a commonly used transistor isolation technique to reduce interference and crosstalk between transistors. STI helps reduce the impact of radiation on PMOS transistors, thereby improving their radiation resistance. In circuit design, combining circuit design with isolation techniques in a source-isolated layout hardening approach can effectively reduce the drain voltage of sensitive PMOS transistors and mitigate the effects of single-event effects.

[0006] Existing SEI hardening modules designed using polarity hardening technology have the following drawbacks:

[0007] (1) such as Figure 1 As shown, when the input signal of X1 changes from low level to high level, the voltage of X1 does not change to VDD (power supply voltage) (1.2V). Instead, it rises rapidly to about 0.81V and then continues to rise at a very slow speed. This will lead to logic level confusion and misjudgment, a sharp drop in noise margin, and an increase in static power consumption.

[0008] (2) The clock edge timing is uncontrollable. The clock edge timing of this module depends almost entirely on the clock edge timing of CLK (clock) and D (input), and from Figure 1 In summary, the clock edge time of this SEI module is extremely short and almost unadjustable, which can lead to overshoot and undershoot, ground bounce and power supply noise, electromagnetic compatibility issues, and greater sensitivity to crosstalk. Summary of the Invention

[0009] To address the problems existing in the above-mentioned traditional methods, this invention proposes a low-power hardened module with controllable clock edge time.

[0010] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0011] On the one hand, a low-power ruggedized module with controllable clock edge timing is provided, comprising:

[0012] The clock gating circuit is used to transmit the input data D and negative input data DN to nodes X1 and X2 through two PMOS transistors, and to transmit the input data D and negative input data DN to nodes X3 and X0 through two NMOS transistors.

[0013] The hardening unit includes a bistable latch module and an input control module. The bistable latch module uses a cross-coupled CMOS bistable structure to store the clock-gated synchronization data in nodes X0 to X3. The input control module receives the clock-gated synchronization data through nodes X0 to X3 and drives the clock-gated synchronization data through the input path.

[0014] The clock and power module provides the clock CLK and inverted clock to the clock gating circuit; it also provides a variable DC voltage to the substrates of the two PMOS transistors in the clock gating circuit to adjust the clock edge timing; and it provides the operating voltage to the low-power ruggedized module.

[0015] In one embodiment, the clock gating circuit includes two PMOS transistors P7 and P8, and two NMOS transistors N7 and N8.

[0016] The substrates of P7 and P8 are both connected to the variable DC voltage output terminal VDD1 of the clock and power module. The gates of P7 and P8 are both connected to the inverted clock output terminal of the clock and power module. The drains of P7 and P8 receive input data D and negative input data DN, respectively. The sources of P7 and P8 are connected to nodes X1 and X2, respectively.

[0017] The substrates of N7 and N8 are both connected to ground (GND). The gates of N7 and N8 are both connected to the clock CLK output of the clock and power modules. The drains of N7 and N8 receive input data D and negative input data DN, respectively. The sources of N7 and N8 are connected to node X3 and node X0, respectively.

[0018] In one embodiment, the bistable latch module includes two PMOS transistors P2 and P3, and four NMOS transistors N1, N2, N4, and N5.

[0019] The gates of N1 and N5 are connected, the gate of N2 is connected to the gate of N4, the drain of N4 and the source of N1 are both connected to node X1, and the drain of N5 and the source of N2 are both connected to node X2; the sources of N4 and N5 are both connected to ground GND.

[0020] The drains of N1 and P2 are both connected to node a, the gate of P2 is connected to node X0, the sources of P2 and P3 are both connected to VDD, the drains of N2 and P3 are both connected to node b, the gate of P3 is connected to node X3, node a is connected to the double exponential current source I1, and node b and VSS are connected to the double exponential current source I2.

[0021] In one embodiment, the input control module includes four PMOS transistors P1, P4, P5, and P6, and two NMOS transistors N3 and N6.

[0022] The source of P1 is connected to VDD, the gate of P1 and the gate of N3 are both connected to node X1, the drain of P1 is connected to the source of P5, the gate of P5 is connected to node X3, the drains of P5 and N3 are both connected to node X0, and the source of N3 is connected to ground GND.

[0023] The source of P4 is connected to VDD, the gate of P4 and the gate of N6 are both connected to node X1, the drain of P4 is connected to the source of P6, the gate of P6 is connected to node X0, the drains of P6 and N6 are both connected to node X3, and the source of N6 is connected to ground GND.

[0024] In one embodiment, the clock and power module includes: a clock CLK source, an inverting clock source, a DC power supply, and a variable DC power supply.

[0025] The outputs of the clock CLK source and the inverting clock source are connected to the clock gating circuit.

[0026] The DC power supply is used to provide the operating voltage for this low-power ruggedized module, and the DC power supply output voltage is 1V.

[0027] The output of the variable DC power supply is connected to the substrate of the PMOS transistor in the clock gating circuit.

[0028] One of the above technical solutions has the following advantages and beneficial effects:

[0029] The aforementioned low-power ruggedized module with controllable clock edge timing includes: a clock gating circuit, a ruggedized unit, and a clock and power supply module. In the clock gating circuit, the substrates of two PMOS transistors are connected to a variable DC power supply to achieve controllable clock edge timing. The ruggedized unit uses a cross-coupled CMOS bistable structure through a bistable latch module to store the clock-gated synchronous data in nodes X0 to X3, and inputs the data to nodes X0 to X3 through an input path via an input control module. In the clock and power supply module, the voltage VDD is set to 1V, reducing overall power consumption and saving energy. This module has anti-six-node flip-flop capability, making it more robust and safer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 Operating curves of SEI hardening modules in existing technologies;

[0032] Figure 2 This is a schematic diagram of a low-power hardened module with controllable clock edge timing in one embodiment;

[0033] Figure 3 This is a schematic diagram of the simulation results of Cadence software in one embodiment;

[0034] Figure 4 This is a schematic diagram illustrating the effect of VDD1=0.4V on the clock edge in one embodiment;

[0035] Figure 5 This is a schematic diagram illustrating the effect of VDD1=0.6V on the clock edge in one embodiment;

[0036] Figure 6 This is a schematic diagram illustrating the effect of VDD1=0.8V on the clock edge in one embodiment;

[0037] Figure 7 This is a Monte Carlo simulation waveform of six nodes flipped in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, and includes such combinations.

[0041] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0042] In one embodiment, such as Figure 2 As shown, a low-power ruggedized module with controllable clock edge timing is provided, comprising:

[0043] The clock gating circuit 10 is used to transmit the input data D and the negative input data DN to nodes X1 and X2 through two PMOS transistors, and to transmit the input data D and the negative input data DN to nodes X3 and X0 through two NMOS transistors.

[0044] Specifically, the MOS transistor in the clock gating circuit is a transmission transistor, responsible for transmitting the input data D and the negative input data DN to nodes X0 to X3.

[0045] The input data D and the negative input data DN are inversely related; that is, when D is high, DN is low, and when D is low, DN is high.

[0046] The hardening unit 20 includes a bistable latch module and an input control module. The bistable latch module is used to store the clock-gated synchronization data in nodes X0 to X3 using a cross-coupled CMOS bistable structure. The input control module is used to receive the clock-gated synchronization data through nodes X0 to X3 and drive the clock-gated synchronization data through the input path.

[0047] Specifically, in the hardening unit, nodes XI and X2 employ N-type polarity hardening technology, while nodes X0 and X3 are hardened using PMOS transistor stacking source isolation technology. When CLK is high, Figure 2 When the transmission transistors P7, P8, N7, and N8 of nodes X0 to X3 are turned on, the input data D and the negative input data DN are written to the storage unit through the transmission transistors, and the signals are stored in nodes X0 and X3. When CLK is low, the transmission transistors are turned off, the storage nodes (X0, X3) retain their original values, and the data is retained in the SEI module through the feedback loop (composed of two cross-coupled inverters P2, N4, P3, and N5).

[0048] The radiation resistance principle of the hardened unit is as follows: When node X1 is bombarded by heavy ions, its node voltage logic value changes from 1 to 0. At this time, PMOS transistor P1 turns on, and NMOS transistor N3 turns off. However, since PMOS transistor P5 remains off, node X0 is in a high-impedance state, so the voltage of node X0 remains low and unchanged. Nodes X2 and X3 are unaffected and remain unchanged. The pull-up path (P2 and N1) of node X1 opens, and the pull-down path (N4) closes. Finally, node X1 returns to its initial high level under the pull-up action of P2 and N1; the same applies to other nodes.

[0049] The clock and power module 30 is used to provide the clock CLK and inverted clock to the clock gating circuit; it is also used to provide a variable DC voltage to the substrate of the two PMOS transistors in the clock gating circuit to adjust the clock edge time; and it is also used to provide the operating voltage to the low-power ruggedized module.

[0050] Specifically, the clock and power supply modules add a variable DC voltage source VDD1, which is a variable DC power supply connected to the substrate voltage of the PMOS transistors transmitting signals to nodes X1 and X2, responsible for adjusting the clock edge timing; an inverting clock is added. This is the inversion of the clock CLK, meaning when CLK is high. It is a low level.

[0051] Figure 1 The intermediate clock and power supply modules provide clock CLK and inverting clock. A dual exponential current source I1 and I2 (used to detect whether node self-reversal can be achieved), a DC power supply VDD, and a variable DC power supply VDD1.

[0052] The aforementioned low-power ruggedized module with controllable clock edge timing includes: a clock gating circuit, a ruggedized unit, and a clock and power supply module. In the clock gating circuit, the substrates of two PMOS transistors are connected to a variable DC power supply to achieve controllable clock edge timing. The ruggedized unit uses a cross-coupled CMOS bistable structure through a bistable latch module to store the clock-gated synchronous data in nodes X0 to X3, and inputs the data to nodes X0 to X3 through an input path via an input control module. In the clock and power supply module, the voltage VDD is set to 1V, reducing overall power consumption and saving energy. This module has anti-six-node flip-flop capability, making it more robust and safer.

[0053] In one embodiment, the clock gating circuit 10 includes two PMOS transistors P7 and P8, and two NMOS transistors N7 and N8.

[0054] The substrates of P7 and P8 are both connected to the variable DC voltage output terminal VDD1 of the clock and power module. The gates of P7 and P8 are both connected to the inverted clock output terminal of the clock and power module. The drains of P7 and P8 receive input data D and negative input data DN, respectively. The sources of P7 and P8 are connected to nodes X1 and X2, respectively.

[0055] The substrates of N7 and N8 are both connected to ground (GND). The gates of N7 and N8 are both connected to the clock CLK output of the clock and power modules. The drains of N7 and N8 receive input data D and negative input data DN, respectively. The sources of N7 and N8 are connected to node X3 and node X0, respectively.

[0056] Specifically, the transmission gates of nodes X1 and X2 are replaced with PMOS transistors, so that the voltage of nodes X1 and X2 can rise smoothly to VDD when the level is raised.

[0057] The substrates of the two PMOS transistors are connected to a variable DC power supply VDD1, enabling controllable clock edge timing.

[0058] In one embodiment, the bistable latch module includes two PMOS transistors P2 and P3, and four NMOS transistors N1, N2, N4, and N5.

[0059] The gates of N1 and N5 are connected, the gate of N2 is connected to the gate of N4, the drain of N4 and the source of N1 are both connected to node X1, and the drain of N5 and the source of N2 are both connected to node X2; the sources of N4 and N5 are both connected to ground GND.

[0060] The drains of N1 and P2 are both connected to node a, the gate of P2 is connected to node X0, the sources of P2 and P3 are both connected to VDD, the drains of N2 and P3 are both connected to node b, the gate of P3 is connected to node X3, node a is connected to the double exponential current source I1, and node b and VSS are connected to the double exponential current source I2.

[0061] In one embodiment, the input control module includes four PMOS transistors P1, P4, P5, and P6, and two NMOS transistors N3 and N6.

[0062] The source of P1 is connected to VDD, the gate of P1 and the gate of N3 are both connected to node X1, the drain of P1 is connected to the source of P5, the gate of P5 is connected to node X3, the drains of P5 and N3 are both connected to node X0, and the source of N3 is connected to ground GND.

[0063] The source of P4 is connected to VDD, the gate of P4 and the gate of N6 are both connected to node X1, the drain of P4 is connected to the source of P6, the gate of P6 is connected to node X0, the drains of P6 and N6 are both connected to node X3, and the source of N6 is connected to ground GND.

[0064] In one embodiment, the clock and power module includes: a clock CLK source, an inverting clock source, a DC power supply, and a variable DC power supply.

[0065] The outputs of the clock CLK source and the inverting clock source are connected to the clock gating circuit.

[0066] The DC power supply provides the operating voltage for this low-power ruggedized module, and its output voltage is 1V. Specifically, changing VDD to 1V further reduces overall power consumption and saves energy.

[0067] The output of the variable DC power supply is connected to the substrate of the PMOS transistor in the clock gating circuit.

[0068] In a verification embodiment, Figure 2 The low-power hardened module with controllable clock edge timing shown was simulated using Cadence software. The simulation results from Cadence software (net36 and net015 are respectively) are... Figure 2 (nodes a and b in the text) Figure 3 As shown, it can be observed that the high level of nodes X1 and X2 can now reach a position very close to VDD, which greatly improves the noise margin and reduces the probability of level misjudgment and static power consumption.

[0069] Compared to existing hardened modules, this invention has the advantages of greater noise tolerance and lower probability of level misjudgment. Specifically, when nodes X1 and X2 in the circuit module transition from low to high level, the voltage can smoothly rise to VDD, instead of rising to 0.7VDD in a short time and then rising very slowly, which greatly improves noise tolerance and reduces the probability of misjudgment.

[0070] The effect of changing the substrate voltage VDD1 on the clock edge is as follows: Figures 4 to 6 As shown (the rising and falling edges of CLK and D inputs are both 1ns). Figure 4 This is a schematic diagram illustrating the effect of VDD1 = 0.4V on the clock edge. Figure 5 This is a schematic diagram illustrating the effect of VDD1=0.6V on the clock edge. Figure 6 This is a schematic diagram illustrating the effect of VDD1 = 0.8V on the clock edge; from Figures 4 to 6 It can be seen that: when VDD1=0.4V, the fall time is 1.17ns; when VDD1=0.6V, the fall time is 1.288ns; and when VDD1=0.8V, the fall time is 1.564ns. Compared with the original ruggedized module, this invention has the advantages of higher device safety, lower noise, and better electromagnetic compatibility. Specifically, by adjusting the substrate voltage of the transmission gates P7 and P8 of nodes X1 and X2, the rise / fall time of the circuit signal can be increased or decreased when the subthreshold current of the device is negligible, thereby improving circuit safety.

[0071] The low-power ruggedized module with controllable clock edge timing proposed in this application has the advantage of resisting six-node flips, compared to the original module's resistance to four-node flips, thus offering greater robustness. Figure 7 Flip the six nodes (node ​​X0 to node X3, and...) Figure 2 The Monte Carlo simulation waveforms of the two nodes a and b) connecting the double exponential current source are shown in the figure. Figure 7As can be seen, in all 100 simulations, all nodes successfully returned to their original levels, which proves that this module can withstand six-node flips and is more secure.

[0072] The low-power hardened module with controllable clock edge timing proposed in this application has a VDD of 1V, which is 83.33% of the original VDD, while the dynamic power consumption in digital circuits is... The static power consumption is proportional to VDD, and the change in substrate voltage has a negligible effect on the change in subthreshold leakage current of this circuit module. The power consumption of the improved circuit module is reduced by 17% to 30%.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A low power hardened module of controllable clock edge time, characterized in that, The application relates to a low-power consumption and reinforced clock gating circuit. The clock gating circuit comprises two PMOS tubes P7 and P8 and two NMOS tubes N7 and N8. The substrates of the PMOS tubes P7 and P8 are connected with a variable DC voltage output terminal VDD1 of a clock and power module, the gates of the PMOS tubes P7 and P8 are connected with an inverse clock output terminal of the clock and power module, the drains of the PMOS tubes P7 and P8 receive input data D and negative input data DN respectively, and the sources of the PMOS tubes P7 and P8 are connected with a node X1 and a node X2 respectively. The substrates of the NMOS tubes N7 and N8 are connected with a ground GND, the gates of the NMOS tubes N7 and N8 are connected with a clock CLK output terminal of the clock and power module, the drains of the NMOS tubes N7 and N8 receive the input data D and the negative input data DN respectively, and the sources of the NMOS tubes N7 and N8 are connected with a node X3 and a node X0 respectively.

2. The low-power clock edge time hardening module of claim 1, wherein, The bistable latch module comprises two PMOS tubes P2 and P3 and four NMOS tubes N1, N2, N4 and N5. The gate of the NMOS tube N1 is connected with the gate of the NMOS tube N5, the gate of the NMOS tube N2 is connected with the gate of the NMOS tube N4, the drain of the NMOS tube N4 is connected with the source of the NMOS tube N1, the drain of the NMOS tube N5 is connected with the source of the NMOS tube N2, and the sources of the NMOS tubes N4 and N5 are connected with the ground GND. The drain of the NMOS tube N1 is connected with the drain of the PMOS tube P2, the gate of the PMOS tube P2 is connected with the node X0, the sources of the PMOS tubes P2 and P3 are connected with VDD, the drain of the NMOS tube N2 is connected with the drain of the PMOS tube P3, the gate of the PMOS tube P3 is connected with the node X3, the node a is connected with a double exponential current source I1, and the node b is connected with VSS and a double exponential current source I2.

3. The low power clock edge time hardening module of claim 1, wherein, The input control module comprises four PMOS tubes P1, P4, P5 and P6 and two NMOS tubes N3 and N6. The source of the PMOS tube P1 is connected with VDD, the gate of the PMOS tube P1 and the gate of the NMOS tube N3 are connected with the node X1, the drain of the PMOS tube P1 is connected with the source of the PMOS tube P5, the gate of the PMOS tube P5 is connected with the node X3, the drain of the PMOS tube P5 and the drain of the NMOS tube N3 are connected with the node X0, and the source of the NMOS tube N3 is connected with the ground GND. ​ 4. The low power clock edge time hardening module of claim 1, wherein, ​ ​ The source of P4 is connected with VDD, the gate of P4 and the gate of N6 are connected with node X1, the drain of P4 is connected with the source of P6, the gate of P6 is connected with node X0, the drain of P6 and the drain of N6 are connected with node X3, and the source of N6 is connected with ground GND.

5. The low power consumption clock edge time hardening module of claim 1, wherein, The clock and power module comprises a clock source, an inverted clock source, a direct current power supply and a variable direct current power supply. The output ends of the clock source and the inverted clock source are connected with the clock gating circuit. The direct current power supply is used for providing working voltage for the low-power ruggedized module, and the output voltage of the direct current power supply is 1V. The output end of the variable direct current power supply is connected with the substrate of the PMOS tube in the clock gating circuit.

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