A RISC-V style 8-bit reduced instruction set customization method

Abstract

The application discloses a RISC-V style 8-bit reduced instruction set customization method, comprising the following steps: S1, based on the function and demand of the target application scene, a target instruction set is selected from a RISC-V32I instruction set, the data bit width, PC width, memory space and register group size of the processor are selected; S2, according to the interruption and exception types supported by the instruction set, the processing flow of the interruption and exception is determined; S3, the encoding space is reduced and the register grouping is optimized through a register coding multiplexing strategy, and the customization of the register addressing mode of the instruction set is realized; S4, each instruction is classified according to the instruction format; S5, each instruction is coded based on the format of each instruction. The customization method has a simple and efficient process, is easy to implement and deploy, does not need to be designed from zero, significantly shortens the research and development cycle, can adapt to multiple scene demands, and realizes the miniaturization of the instruction set, minimization of hardware resources and efficient design process.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a method for customizing a RISC-V style 8-bit reduced instruction set. Background Technology

[0002] In the field of embedded systems and microprocessor design, the instruction set architecture (ISA) is the foundation of hardware-software interaction, significantly impacting system performance, power consumption, hardware complexity, and software ecosystem. The RISC-V instruction set is an open-source, modular modern instruction set architecture designed based on RISC (Reduced Instruction Set Computing) principles. RISC-V adheres to design principles such as reduced instructions, regularized coding, fixed-length instructions (e.g., 32-bit or 64-bit), and a load / store architecture, providing a clear and concise instruction format and efficient hardware decoding logic. It supports modular extensions (e.g., integer, multiplication, division, floating-point, atomic operations). Its instruction execution is typically single-cycle, with a regularized pipelining-friendly architecture, high code density and execution efficiency, and excellent portability and scalability, making it suitable for a wide range of applications from embedded microcontrollers to high-performance computing. RISC-V's open-source nature and modern design philosophy make it an important choice for academic research, chip design innovation, and embedded development.

[0003] The RISC-V standard architecture (such as RV32I) uses 32-bit fixed-length instructions. While it boasts excellent scalability and general-purpose computing capabilities, its large instruction width (32 bits per instruction) and large register set (typically 32 general-purpose registers, each 32 bits) result in a large program code size (for example, a simple addition instruction requires 4 bytes of storage, while an 8-bit instruction only requires 1 byte), drastically increasing the demand for ROM / RAM capacity. High power consumption is also a concern: wider instructions require longer fetch cycles, more complex instruction decoding logic, and wider data buses, leading to a significant increase in dynamic power consumption (especially with frequent instruction fetches and instruction cache access). Furthermore, the large-scale register file (32×32 bits), high-width ALU, and complex pipeline control logic impose stringent requirements on chip area and manufacturing cost.

[0004] Therefore, it exhibits significant "performance overkill" in demanding scenarios such as the Internet of Things (IoT), wearable devices, and sensor nodes, and is also unsuitable for resource-constrained embedded systems (such as sensors, controllers, and simple home appliances).

[0005] Most current RISC instruction sets are 32-bit or 64-bit. Some instruction sets (such as the C extension of RISC-V, i.e., compressed instruction sets) provide 16-bit compressed instructions, but their instruction widths are still too large, resulting in large program code sizes and a sharp increase in ROM / RAM capacity requirements. The register sets are large, the data bit widths are high, and the areas of computational and processing units such as the ALU are large, leading to a high processor area cost. Wide instructions require longer fetch cycles, more complex instruction decoding logic, and wider data buses, resulting in a significant increase in dynamic power consumption, making it difficult to meet the practical needs of ultra-low resource, ultra-low power, and ultra-small size scenarios. Summary of the Invention

[0006] One object of the present invention is to provide a method for customizing a RISC-V style 8-bit reduced instruction set, comprising the following steps:

[0007] S1. Based on the functions and requirements of the target application scenario, the target instruction set is selected from the RISC-V32I instruction set, and the processor's data bit width, PC width, memory access space and register group size are selected.

[0008] S2. Determine the interrupt and exception handling process based on the interrupt and exception types supported by the instruction set;

[0009] S3. By reducing the encoding space and optimizing register grouping through register encoding reuse strategy, the instruction set register addressing mode can be customized;

[0010] S4. Categorize each instruction according to its format;

[0011] S5. Encode each instruction based on its format.

[0012] Preferably, in S1, the data bit width is set to 8 bits, the memory access address space bit width is selected as 8 bits, the register group bit width is consistent with the data bit width, the number of registers is 8, the value of register 0 is always zero, and the PC width selection range is 8-16 bits.

[0013] Preferably, in S3, the register encoding multiplexing strategy simplifies a three-operand instruction into a two-operand instruction.

[0014] Preferably, in step S3, optimizing register grouping controls the encoding space of the register number to two bits. The method for optimizing register grouping includes the following steps:

[0015] First, divide the register set into two or four consecutive groups;

[0016] Then, the instructions are categorized according to the type of operation they perform;

[0017] Next, the categorized instructions are assigned to the corresponding register groups.

[0018] Preferably, in S4, the classification types include: R-type instructions for inter-register operations, I-type instructions for load operations for short immediate values ​​and memory access, S-type instructions for memory access operations, B-type instructions for conditional jumps, U-type instructions for long immediate values, and J-type instructions for unconditional jumps.

[0019] Preferably, in step S5, when encoding the opcode and function of an instruction, instructions of the same structure or type are made to have the same or similar opcode and function.

[0020] Preferably, in step S5, the function of adjacent executed instructions is the same, while the opcode differs only in a few bits; or the opcode of adjacent executed instructions is the same, while the function differs only in a few bits. This reduces the state switching overhead of the decoder during the decoding stage, and minimizes hardware signal transitions, power consumption, and timing issues.

[0021] The present invention has the following beneficial effects:

[0022] This invention provides a RISC-V-style 8-bit reduced instruction set customization method. This method is concise, efficient, easy to implement and deploy, eliminates the need for design from scratch, significantly shortens the development cycle, and provides clear customization steps. The customization method is flexible and adaptable to various scenarios. It achieves instruction set miniaturization, hardware resource minimization, and design flow efficiency. This method retains the efficient and mature memory access modes, jump / transfer modes, basic operation types, general-purpose register usage specifications, and interrupt and exception handling mechanisms of RISC-V, and adopts the RISC-V instruction format classification system to ensure a clear and regular instruction structure. Through optimization strategies such as reasonable grouping of the general-purpose register set and setting default registers, the customized 8-bit fixed-length reduced instruction set has a smaller instruction width, smaller program code size, and significantly reduced ROM / RAM capacity. Simultaneously, the register set area and ALU data bit width are reduced, thereby lowering the processor's area cost. The fewer instructions in the 8-bit fixed-length reduced instruction set simplify processor design and implementation, achieving higher coding efficiency within a limited 8-bit width. Ultimately, a fixed-length reduced instruction set suitable for 8-bit hardware platforms was formed.

[0023] The instruction set customized using this 8-bit reduced instruction set customization method not only possesses the simplicity and modularity of RISC-V, but also significantly reduces hardware resource requirements, has fewer instructions, is simpler to implement, and is more in line with the actual needs of ultra-low power embedded application scenarios such as the Internet of Things, wearable devices, and sensor nodes. Attached Figure Description

[0024] Figure 1 These are the register specifications provided in the implementation examples.

[0025] Figure 2 These are the exception types and exception codes provided in the implementation examples.

[0026] Figure 3 These are the register groups corresponding to each instruction provided in the implementation example.

[0027] Figure 4 This is a classification of instruction formats provided in the embodiments.

[0028] Figure 5 This is the instruction set encoding scheme provided in the embodiment.

[0029] Figure 6 It is an extended form of the pseudo-instruction provided in the embodiment.

[0030] Figure 7 This is a flowchart illustrating the customization process of the RISC-V style 8-bit reduced instruction set customization method of this invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] Reference Figure 7 This invention discloses a method for customizing a RISC-V style 8-bit reduced instruction set, which specifically includes the following steps:

[0033] S1. Based on the application scenario and design requirements, select and count the instructions with the target function from the RISC-V32I instruction set, and clarify the processor's data bit width, PC width, memory access space and register group size.

[0034] The instruction length is set to 8 bits; the data width can be selected as 8 bits or 16 bits, with 8 bits being preferred; the program counter (PC) width can be selected between 8 bits and 16 bits, and can be appropriately expanded according to the application scenario; the memory access address space (i.e., the address bus width) can be selected as 8 bits or 16 bits, with 8-bit address being preferred; the register set size can be selected as 8×8 bits or 8×16 bits, and the register set width must be consistent with the data width.

[0035] For example:

[0036] In this embodiment, the instruction set is designed with an instruction length and data width of 8 bits, a PC width of 8 bits, and a memory access space of 256 bytes. The general-purpose register set is designed with eight 8-bit registers, where register 0 has a constant value of 0. The status control register (CSR) retains only the mtvec, mepc, mcause, and mstatus registers from RISC-V, and all are 8 bits. This reduces the area of ​​the register set and allows the access width to be compressed to 2 bits.

[0037] In RISC-V, the access width of the CSR is 12 bits. However, when designing this instruction set, based on usage requirements, no additional expansion of the CSR register is needed, and only the mtvec, mepc, mcause, and mstatus registers are required. This is equivalent to trimming the CSR in RISC-V and recoding the above four registers, so that only a two-bit access width is needed to cover the above four registers.

[0038] S2. Determine the interrupt and exception handling process based on the interrupt and exception types supported by the instruction set.

[0039] Interrupt types can be selected as single-level or multi-level, with options for interrupt priority and nesting. Exception types are based on possible exceptions in the instruction set, and exception codes are designed for each. Internal processor exceptions include address access exceptions, illegal instruction exceptions, breakpoint exceptions, and unaligned address exceptions.

[0040] Interrupt exception handling procedures can be implemented custom-made or adapted to suit the current instruction set architecture by referencing existing mature instruction set architectures.

[0041] In this embodiment, the instruction set only supports single-level interrupts and does not support interrupt nesting or preemption. The interrupt exception handling process will adopt the same method as RISC-V. The interrupt exception types and their exception codes in the instruction set are as follows: Figure 2 As shown.

[0042] S3, Register addressing mode for custom instruction sets.

[0043] For RISC-V three-operand arithmetic instructions (e.g., rd = rs1 + rs2), it is typically necessary to allocate independent encoding bits for each register operand, requiring a total bit length of 4 (opcode) + 3 (rd) + 3 (rs1) + 3 (rs2) = 13 bits. However, 13 bits exceeds the capacity of an 8-bit instruction, thus requiring significant compression of the encoding space. To adapt to the 8-bit instruction width, we will adopt a register encoding multiplexing scheme to simplify the traditional three-operand instruction into a two-operand instruction (e.g., rd = rd + rs1).

[0044] Since 8-bit instructions directly encode 3-bit register numbers (i.e., 2^3=8, supporting 8 registers), each operand requires at least 3 bits × 2 operands = 6 bits. The remaining 2 bits cannot carry complex opcodes or addressing modes. Therefore, we need to adopt a register grouping design to control the encoding space of register numbers to two bits.

[0045] To implement the register grouping design, the register group is first divided into several groups; then, the instructions are classified according to the type of operation they are to perform; finally, the classified instructions are assigned to the corresponding register groups.

[0046] Register grouping is designed to address the problem of insufficient instruction encoding space, making it impossible to encode all registers. Therefore, registers are grouped, which involves splitting the register into two or four consecutive parts.

[0047] Instructions are classified based on the operations they perform and their characteristics. Specifically, instructions of similar types that are suitable for using the same register group are grouped into one category.

[0048] In this embodiment, the instructions are categorized and grouped, and the final grouping result is as follows: Figure 3 As shown. Group 1 includes data operation instructions, and Group 2 includes data load, memory access, data set, jump, bubble, breakpoint exception, and CSR (Status Control Register) instructions. In Group 1, the vast majority of instructions use register sets x0 to x3. Specifically, the 2-bit register number in the instruction is padded with 0 in the highest bit to obtain the 3-bit register number, which is the actual register number. In Group 2, registers x4 to x7, or x2 to x5, are used. The 2-bit register number in the instruction is padded with 1 or added with 2 to determine the final register number.

[0049] S4. Next, classify each instruction according to its format. Specifically, they are divided into the following types: R-type instructions are used for register operations; I-type instructions are used for short immediate values ​​and memory load operations; S-type instructions are used for memory access operations; B-type instructions are used for conditional jumps; U-type instructions are used for long immediate values; and J-type instructions are used for unconditional jumps. The classification results are as follows: Figure 4 As shown.

[0050] S5. Finally, each instruction is encoded based on its format.

[0051] In this embodiment, the final encoding scheme is as follows: Figure 5 As shown.

[0052] To design and encode instructions, we need to analyze the implementation of each instruction one by one.

[0053] Taking the data-operating `add` instruction as an example, in the RISC-V instruction set, the `add` instruction implements the register selection (MV) pseudo-instruction in the form of `addi rd, rs1, 0` or `add rd, x0, rs2`. In this case, since the `addi` instruction, besides the opcode, `Funct2`, and the two-bit immediate value `imm`, cannot directly perform register transfers using the remaining two bits of register space, the `add` instruction is chosen to implement the MV pseudo-instruction. The `add` instruction is an R-type instruction; it can only operate on two registers, and its register selection space is only two bits.

[0054] First, consider a full transfer between register set 1 (x0-x3), using the `addl` instruction. Before using this instruction, `rd` needs to be cleared using the `and` instruction. Next, consider a full transfer between register set 2 (x4-x7), using the `addh` instruction. Before using this instruction, `rd` needs to be cleared using the `slt` instruction. Finally, consider a transfer between register set 1 and register set 2, using the `addm` instruction. Depending on the transfer direction, there are two cases: before transferring from register set 1 to register set 2, `rd` needs to be cleared using the `and` instruction; before transferring from register set 2 to register set 1, `rd` needs to be cleared using the `slt` instruction. Ultimately, the extended form of the MV pseudo-instruction is as follows: Figure 6 As shown.

[0055] The implementation of the nop pseudo-instruction is the same as in RISC-V, with the extended form being addi x0 0, such as... Figure 6 As shown.

[0056] Let's look at the subtraction instruction (sub) for data operations. In this embodiment, considering the register and data width are 8 bits, and to support more application scenarios, this instruction set needs to provide 16-bit addition and subtraction operations. For addition instructions, the carry operation of the adder was already preserved in the processor design; therefore, 16-bit addition can be performed sequentially by adding the low-order and high-order bits. Subtraction is usually implemented based on adders, and the subtraction operation is achieved by inverting the subtrahend and adding 1. However, this implementation cannot obtain the borrow from the previous subtraction. Therefore, it is necessary to distinguish between high-order and low-order subtraction: low-order subtraction (sub) inverts the subtrahend, adds 1, and then performs the addition; while high-order subtraction (subcarry) inverts the subtrahend, adds the carry from the low-order subtraction, and then performs the addition.

[0057] The remaining data operation instructions are mainly logical operations, performing operations on two source registers and writing the result back to the rd register. Data load and memory access instructions are inherited from the RISC-V instructions lui, lw, and sw. Since the memory access width of this instruction set is byte-wide, only single-byte memory access instructions are needed, and issues such as address misalignment are not considered. Considering the limited encoding space of the 8-bit instruction set, the four-bit encoding space can only accommodate the base address and immediate value imm for memory access; therefore, the source or destination register for data load and memory access instructions is set to x4 by default.

[0058] The data set instruction `slt` compares the values ​​of source register 1 (rs1) and source register 2 (rd). If `rs1` is less than `rd`, `rd` is set to 1; otherwise, it is set to 0. Based on the `slt` instruction, pseudo-instructions `slti` (set when less than 0) and `sgti` (set when greater than 0) can be implemented, with extensions as follows: Figure 6 As shown.

[0059] The lui instruction is a U-type instruction used to load long immediate values. Therefore, it is necessary to maximize the use of the encoding space of the immediate value and use the x5 register by default.

[0060] In PC-based jump instructions, `beqr` is used for register jumps when equal to a value. Additionally, the pseudo-instruction `beqzr` can be used for register jumps when equal to 0. `bnezr` is used for register jumps when not equal to 0. `jal` and `jalr` are unconditional relative jumps and unconditional register jumps, respectively. The `sPC` instruction is a replacement for the `auiPC` instruction in RISC-V. Due to limited instruction encoding space, `sPC` saves encoding space and can be used in conjunction with `addi` instructions to implement `auiPC` functionality. Due to the limitation of the 8-bit fixed-length instruction set encoding space, all PC-based jump instructions use the x5 register as the default PC jump register, thus efficiently saving encoding space and increasing the number of implementable instructions.

[0061] Breakpoint exception instructions are special operations that can be implemented using 8-bit fixed encoding.

[0062] The csrrw instruction in the csr type is used to perform read-write operations on the CSR register. To save coding space, the x5 register is used as the CSR read-write register by default.

[0063] Finally, when encoding the opcode and function2 of instructions, we need to optimize the instruction encoding so that instructions of the same structure or type have the same or similar opcode and function2. This helps optimize the processor's decoding module. At the same time, we should strive to make the encodings of adjacent instructions similar (e.g., changing only a few bits), ensuring that the function of adjacent instructions is the same, while the opcode differs by only a few bits, or that the opcode of adjacent instructions is the same, while the function differs by only a few bits. This reduces the state switching overhead of the decoder during the decoding stage, minimizing hardware signal transitions, power consumption, and timing issues.

[0064] Encoding similarity means that the opcode and function parts of several instructions differ by only a few bits. For example, in this embodiment, the opcode and function parts of the and instruction are 0110, and those of the addl instruction are 0111, with only one bit different.

[0065] To reduce decoding complexity, this embodiment encodes instructions based on the instruction structure and register number range, ensuring that instructions with the same register number range share the same opcode and Funct2 encoding as much as possible. Furthermore, since the `mv` pseudo-instruction is frequently used, and its extended form contains two instructions, sequences such as `and-addl`, `and-addm`, `slt-addh`, and `slt-addm` frequently appear in the instruction sequence. Therefore, in the encoding design, the `addl` and `addm` instructions differ from the `and` instruction by only one bit, and the `addh` and `addm` instructions also differ from the `slt` instruction by only one bit. This reduces bit flipping during the processor's value fetching and decoding stages, further reducing power consumption.

[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A RISC-V style 8-bit reduced instruction set customization method, characterized in that, It comprises the following steps: S1, based on the function and requirement of the target application scene, a target instruction set is selected from the RISC-V32I instruction set, the data bit width, PC width, memory space and register group size of the processor are selected; S2, according to the interruption and exception type supported by the instruction set, the processing flow of interruption and exception is determined; S3, the encoding space is reduced and the register grouping is optimized through the register encoding multiplexing strategy, and the customization of the register addressing mode of the instruction set is realized; S4, each instruction is classified according to the instruction format; S5, each instruction is encoded based on the format of each instruction; In the S1, the data bit width is set to 8 bits, the bit width of the memory address space is selected to be 8 bits, the bit width of the register group is consistent with the data bit width, the number of registers is 8, the value of the 0th register is always zero, and the PC width is selected in the range of 8-16 bits; In the S3, the register encoding multiplexing strategy is to simplify three-operand instructions into two-operand instructions; In the S3, the optimization of the register grouping controls the encoding space of the register number to be two bits, and the method of optimizing the register grouping comprises the following steps: Firstly, the register group is equally divided into two or four continuous groups; Then, the instructions are classified according to the operation type they perform; Next, the classified instructions are allocated to the corresponding register group.

2. The customization method of claim 1, wherein, In the S4, the classification types include: R-type instructions for inter-register operations, I-type instructions for short immediate number and load operation, S-type instructions for memory storage operation, B-type instructions for conditional jump, U-type instructions for long immediate number, and J-type instructions for unconditional jump.

3. The customization method of claim 1, wherein, In the S5, when the opcode and Funct of the instruction are encoded, the instructions of the same structure or type have the same or similar opcode and Funct.

4. The customization method of claim 1, wherein, In the S5, the Funct of the instructions executed adjacently is the same, and the opcode only has individual bits difference, or the opcode of the instructions executed adjacently is the same, and the Funct only has individual bits difference.

Images