Liquid crystal display driving circuit dynamic adjustment system for low power consumption requirement

Abstract

The present application relates to the technical field of liquid crystal display driving, and discloses a dynamic adjustment system of a liquid crystal display driving circuit for low-power consumption demand. The system comprises a power consumption feature extraction module, a power consumption dynamic allocation module, a scanning strategy optimization module, a timing control reconstruction module and a driving signal conversion module. The power consumption feature extraction module collects real-time power consumption parameters of each region and establishes a regional power consumption feature map; the power consumption dynamic allocation module analyzes power consumption fluctuation differences and generates a partition power consumption quota matrix in combination with a preset threshold; the scanning strategy optimization module adjusts a row scanning sequence and a column scanning frequency accordingly and generates an adaptive scanning strategy table; the timing control reconstruction module reconstructs a synchronous signal timing logic and outputs a dynamic timing control waveform; and the driving signal conversion module converts to generate a control signal and feeds back actual driving power consumption data. The system realizes dynamic adjustment of the liquid crystal display driving circuit and adapts to low-power consumption demand.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display driving technology, specifically to a dynamic adjustment system for liquid crystal display driving circuits designed for low power consumption. Background Technology

[0002] With the rapid popularization of portable electronic products such as mobile terminals and wearable devices, low power consumption has become one of the core requirements for LCD display design. Traditional LCD display driving circuits mostly use fixed scanning strategies and timing control methods. Regardless of how the displayed content changes, the driving circuit always operates at a constant frequency and voltage, which largely results in unnecessary energy consumption.

[0003] In practical applications, the content displayed on an LCD screen often exhibits significant regional differences. For example, when displaying static text, most pixels remain stable, while only a small portion shows dynamic changes; when playing video, the motion amplitude and color changes vary across different areas of the screen. However, existing driving circuits cannot adjust power consumption accordingly based on these regional differences, resulting in high-power and low-power areas using the same driving parameters, leading to energy waste.

[0004] Existing power consumption control methods mostly focus on adjusting the overall voltage or frequency, lacking fine-grained management of individual areas of the display panel. When the displayed content changes locally, the driving circuit still needs to scan and drive the entire panel, which not only increases unnecessary power consumption but may also affect the stability of the display effect due to overall parameter adjustments. In addition, the timing control logic of traditional driving circuits is relatively fixed, making it difficult to dynamically adapt to real-time power consumption characteristics. This limits the flexibility and response speed of power consumption adjustment, failing to meet the dual requirements of low power consumption and display performance in different scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide a dynamic adjustment system for liquid crystal display driving circuits that meets low power consumption requirements, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides a dynamic adjustment system for a liquid crystal display driving circuit designed for low power consumption, the system comprising:

[0007] The module includes a power consumption feature extraction module, a power consumption dynamic allocation module, a scanning strategy optimization module, a timing control reconstruction module, and a drive signal conversion module.

[0008] The power consumption feature extraction module is used to continuously collect real-time power consumption parameters of each area of ​​the display panel and establish a regional power consumption feature map based on the analysis results of the display content.

[0009] The power dynamic allocation module analyzes the power fluctuation difference between the current frame and historical frames based on the regional power consumption feature map, generates a partition power consumption quota matrix in combination with the preset power consumption threshold, and synchronizes the partition power consumption quota matrix to the scanning strategy optimization module.

[0010] The scanning strategy optimization module receives the partition power consumption quota matrix, dynamically adjusts the row scanning sequence and column scanning frequency according to the power consumption quota weight of each region, generates an adaptive scanning strategy table, and transmits it to the timing control reconstruction module.

[0011] The timing control reconstruction module parses the scanning timing parameters in the adaptive scanning strategy table, reconstructs the timing logic relationship between the vertical synchronization signal and the horizontal synchronization signal, and outputs the dynamic timing control waveform to the drive signal conversion module.

[0012] The drive signal conversion module generates grayscale voltage control signals and gate turn-on voltage signals based on the dynamic timing control waveform, and simultaneously feeds back the actual drive power consumption data to the power consumption feature extraction module.

[0013] Preferably, the power consumption feature extraction module includes:

[0014] Collect the brightness values ​​of the three primary colors (red, green, and blue) and refresh rate parameters of each pixel unit on the display panel, and map them to generate a pixel-level power consumption distribution heatmap;

[0015] The display panel is divided into M×N power consumption monitoring blocks, and the average brightness and refresh rate change frequency of each block are statistically analyzed.

[0016] The real-time power consumption coefficient of each block is calculated based on the average brightness and refresh rate change frequency of each block, and then integrated to form a regional power consumption characteristic map.

[0017] Preferably, the power consumption dynamic allocation module performs the following operations:

[0018] Extract the block power consumption coefficients of K consecutive frames in the regional power consumption feature map, and calculate the power consumption fluctuation variance of each block;

[0019] Compare the power consumption fluctuation variance of the blocks with the preset fluctuation tolerance threshold, and mark the blocks that exceed the threshold as high fluctuation areas;

[0020] The global power consumption allocation weight coefficient is adjusted based on the proportion of high-fluctuation areas, and a partitioned power consumption quota matrix containing the maximum allowable power consumption value of each block is generated by combining the preset power consumption threshold.

[0021] Preferably, the scanning strategy optimization module is specifically implemented as follows:

[0022] Analyze the power quota weight of each block in the partitioned power quota matrix, and classify the blocks with weights lower than the set value as low priority areas;

[0023] For low-priority areas, a row scan merging strategy is used to merge three adjacent row scan signals into a single scan operation;

[0024] The column scan frequency of high-weight regions is dynamically reduced based on the block power consumption quota weight, generating an adaptive scan strategy table that includes row merging identifiers and column frequency adjustment parameters.

[0025] Preferably, the timing control reconstruction module includes:

[0026] Read the row merging identifier in the adaptive scanning strategy table and recalculate the effective pulse width of the vertical synchronization signal;

[0027] Analyze the column frequency adjustment parameters and reconstruct the rising edge trigger interval of the horizontal synchronization signal;

[0028] A dynamic timing control waveform with a variable blanking period is generated based on the reconstructed vertical synchronization signal and horizontal synchronization signal.

[0029] Preferably, the drive signal conversion module includes:

[0030] Receive the blanking period parameter in the dynamic timing control waveform and turn off the grayscale voltage output of inactive areas during the blanking period;

[0031] The duration of the gate turn-on voltage is dynamically adjusted based on the horizontal synchronous trigger interval of the dynamic timing control waveform.

[0032] The drive current value of each block is monitored in real time and converted into actual drive power consumption data, which is then fed back to the power consumption feature extraction module.

[0033] Preferably, the system further includes a power consumption threshold adaptive module:

[0034] Receive the regional power consumption feature map output by the power consumption feature extraction module, and extract the difference between the average power consumption and the peak power consumption of the whole screen;

[0035] When the peak power consumption difference exceeds the preset warning value, the preset power consumption threshold is dynamically increased based on historical power consumption data.

[0036] When the average power consumption of the full screen is lower than the set threshold for multiple consecutive frames, the preset power consumption threshold is reduced by a preset step value.

[0037] Preferably, the power consumption threshold adaptive module further includes:

[0038] Establish a connection channel between the ambient light intensity sensor and the display content complexity detection unit;

[0039] The baseline value for adjusting the preset power consumption threshold is adjusted based on the change in ambient light intensity.

[0040] The preset power consumption threshold fluctuation range is adjusted based on the graphic edge density parameter output by the display content complexity detection unit.

[0041] Preferably, the drive signal conversion module includes a signal spectrum analysis unit:

[0042] The frequency distribution characteristics of the grayscale voltage control signal are collected, and the energy values ​​of the main harmonic components are extracted.

[0043] When the energy value of the main harmonic component exceeds the set threshold, a waveform smoothing request is sent to the timing control reconfiguration module.

[0044] After the timing control reconfiguration module responds to the request, it adds a rising edge buffer time for the horizontal synchronization signal.

[0045] Preferably, the signal spectrum analysis unit performs the following operations:

[0046] Within the complete cycle of the vertical synchronization signal, multiple consecutive time-domain sampling windows are divided at equal intervals;

[0047] The actual waveform of the grayscale voltage control signal within each time domain sampling window is captured by a high-speed analog-to-digital converter.

[0048] Perform a Fast Fourier Transform operation on the actual waveform of each captured time-domain sampling window to extract the corresponding spectral distribution feature data;

[0049] The extracted spectral distribution feature data is compared with the pre-stored benchmark energy distribution template to identify abnormal frequency points where the spectral energy is significantly higher than the benchmark energy.

[0050] The time-domain sampling window containing abnormal frequency points is marked as the electromagnetic interference window, and its start and end positions are recorded throughout the entire vertical synchronization cycle.

[0051] Summarize the location information of all marked electromagnetic interference windows and generate an electromagnetic interference window location information table;

[0052] The electromagnetic interference window position information table is transmitted to the scanning strategy optimization module in real time.

[0053] After receiving the electromagnetic interference window position information table, the scanning strategy optimization module skips the row scanning operation of the corresponding display area based on the position identified in the electromagnetic interference window position information table when generating the adaptive scanning strategy table.

[0054] Compared with the prior art, the beneficial effects of the present invention are:

[0055] By continuously collecting real-time power consumption parameters from various areas of the display panel through a power consumption feature extraction module and combining this with the results of display content analysis to establish regional power consumption feature maps, the system can accurately capture the power consumption variation patterns of each area, providing detailed regional basis for subsequent power consumption adjustment. This region-based power consumption feature analysis breaks through the limitations of traditional drive circuits that make general judgments about the overall power consumption of the panel, enabling the system to gain a deeper understanding of the power consumption characteristics of different areas.

[0056] The dynamic power allocation module analyzes the power fluctuation differences between the current frame and historical frames based on regional power consumption feature maps, and generates a partitioned power quota matrix by combining it with preset power consumption thresholds, thus achieving reasonable power allocation for each region. In this way, the system can allocate corresponding power quotas to different regions according to their power consumption fluctuations, avoiding unreasonable occupation of power resources and making power allocation more in line with the actual needs of each region.

[0057] The scanning strategy optimization module dynamically adjusts the row scanning sequence and column scanning frequency based on the power consumption quota weight of each region in the partitioned power consumption quota matrix, generating an adaptive scanning strategy table. This allows the scanning process to be adjusted specifically according to the power consumption quota of each region. For regions with low power consumption quotas, the scanning frequency can be appropriately reduced or the scanning sequence optimized to reduce unnecessary scanning operations; for regions with high power consumption quotas, appropriate scanning parameters are maintained to ensure display quality, thereby reducing overall unnecessary power consumption.

[0058] The timing control reconfiguration module parses the scanning timing parameters in the adaptive scanning strategy table, reconstructs the timing logic relationship between the vertical and horizontal synchronization signals, and outputs a dynamic timing control waveform. This dynamic reconstruction of timing logic enables the synchronization signals to match the scanning strategies of each region, making the timing of the driving process more closely aligned with actual power consumption requirements and scanning methods, thus improving the adaptability of timing control.

[0059] The drive signal conversion module generates grayscale voltage control signals and gate turn-on voltage signals based on the dynamic timing control waveform, and feeds back the actual drive power consumption data to the power consumption feature extraction module, forming a closed-loop adjustment mechanism. Through this closed-loop feedback, the system can obtain power consumption data in the actual drive process in a timely manner, compare it with the preset quotas and strategies, making subsequent power consumption adjustment more accurate and forming a continuous optimization cycle. Attached Figure Description

[0060] Figure 1 This is a schematic diagram illustrating the working principle of the dynamic adjustment system for liquid crystal display driving circuits designed for low power consumption, as described in this invention.

[0061] Figure 2 A flowchart illustrating the operation of the power consumption feature extraction module;

[0062] Figure 3 A flowchart illustrating the operation of the scanning strategy optimization module;

[0063] Figure 4 A flowchart illustrating how the signal conversion module operates;

[0064] Figure 5 This is a flowchart for the spectrum analysis of the drive signal conversion module. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Please see Figure 1 This invention provides a dynamic adjustment system for liquid crystal display driving circuits designed for low power consumption. The system includes: a power consumption feature extraction module, a power consumption dynamic allocation module, a scanning strategy optimization module, a timing control reconstruction module, and a driving signal conversion module. Specific implementation details are as follows:

[0067] The power consumption feature extraction module continuously collects real-time power consumption parameters of each area of ​​the display panel, including the brightness values ​​of the three primary colors (red, green, and blue) and refresh rate parameters of the pixel units. It generates a pixel-level power consumption distribution heat map by mapping and divides the display panel into M×N power consumption monitoring blocks. It statistically analyzes the average brightness and refresh rate change frequency of each block and finally calculates the real-time power consumption coefficient of the block and integrates them to form a regional power consumption feature map.

[0068] The power dynamic allocation module analyzes the power fluctuation difference between the current frame and historical frames based on the regional power consumption feature map, extracts the block power consumption coefficient of K consecutive frames to calculate the fluctuation variance value, marks the high fluctuation area that exceeds the preset fluctuation tolerance threshold, and generates a partitioned power consumption quota matrix in combination with the preset power consumption threshold.

[0069] After receiving the partition power consumption quota matrix, the scanning strategy optimization module dynamically adjusts the row scanning sequence and column scanning frequency according to the power consumption quota weight of each block. For low-priority areas, a row scanning merging strategy is adopted to merge three adjacent row scanning signals into a single scanning operation. At the same time, the column scanning frequency of high-weight areas is reduced to generate an adaptive scanning strategy table.

[0070] The timing control reconstruction module parses the scanning timing parameters in the adaptive scanning strategy table, recalculates the effective pulse width of the vertical synchronization signal, reconstructs the rising edge trigger interval of the horizontal synchronization signal, and outputs a dynamic timing control waveform containing a variable blanking period.

[0071] The drive signal conversion module generates grayscale voltage control signals and gate enable voltage signals based on the dynamic timing control waveform. During the blanking period, it turns off the grayscale voltage output of inactive regions and feeds back the actual drive power consumption data to the power consumption feature extraction module to form a closed-loop control.

[0072] Example 1: See Figure 2 The detailed workflow of the power consumption feature extraction module and the power consumption dynamic allocation module is as follows: The power consumption feature extraction module acquires the red, green, and blue primary color brightness data of each pixel unit on the display panel in real time through a high-precision analog-to-digital converter array. This data comes from the color data buffer inside the display driver chip. Simultaneously, the module reads the refresh rate parameters of the current frame from the timing controller register, including the vertical refresh cycle and horizontal scan frequency. After preprocessing, the acquired raw data is used to generate a pixel-level power consumption distribution heatmap using a spatial interpolation algorithm. This heatmap is stored in the form of a two-dimensional matrix, where each element corresponds to the real-time power consumption feature value of a specific pixel on the display panel.

[0073] The display panel is divided into multiple rectangular monitoring blocks, each containing a fixed number of pixel units. The blocks are divided using an equal-area principle, ensuring that each monitoring block maintains a consistent physical size. For each monitoring block, the module calculates the arithmetic mean of the brightness values ​​of all pixels within it, serving as the average brightness index for that block. The refresh rate change frequency is statistically analyzed by comparing the time interval between refresh commands between two adjacent frames, specifically by calculating the number of refresh commands occurring per unit time. These statistical parameters are fed into a feature calculation unit, and after weighted calculations, a real-time power consumption coefficient for each block is output. This coefficient reflects the relative power consumption level of the block in the current display state; a higher value indicates higher power consumption in that area.

[0074] The regional power consumption feature map is constructed using a dynamic update mechanism, and the map data structure adopts a hierarchical storage architecture. The bottom layer stores the raw collected data, the middle layer stores the block statistical parameters, and the top layer stores the finally calculated power consumption coefficients. The map update cycle is synchronized with the display refresh rate, and a global update operation is performed after each frame is displayed. During the update process, the system compares the changes in the map between two consecutive frames and records the changing trend of the power consumption coefficients of each block.

[0075] The dynamic power allocation module operates based on a sliding window analysis mechanism, which maintains a fixed-length historical data queue. This queue stores regional power consumption characteristic maps from multiple consecutive frames. The system analyzes this historical data to calculate the fluctuation of power consumption coefficients for each block. Specifically, the calculation involves statistically analyzing the power consumption value sequence of each block over time, outputting a quantitative indicator representing the degree of fluctuation. This indicator is compared with a preset fluctuation tolerance threshold; blocks exceeding the threshold are marked as high-fluctuation regions.

[0076] The calculation of the global power consumption allocation weight coefficient takes into account the proportion of high-fluctuation areas in the overall display area. This coefficient adopts a dynamic adjustment strategy, updating in real time according to the actual situation of the current frame. The system maintains a baseline weight value; when the proportion of high-fluctuation areas is small, the actual weight is close to the baseline value; when the proportion of high-fluctuation areas increases, the weight value increases accordingly. This adjustment method allows the system to prioritize the display quality of high-fluctuation areas while appropriately reducing resource allocation to stable areas.

[0077] The generation process of the partitioned power consumption quota matrix adopts a hierarchical decision-making mechanism. The system first determines the overall power consumption budget based on the global strategy, and then allocates this budget to each block according to weighted coefficients. The maximum allowable power consumption value obtained by each block depends not only on its current power consumption coefficient but also on its historical power consumption performance. Blocks with significant power consumption fluctuations in recent times will receive higher power consumption quota limits, while blocks with stable operation will be appropriately restricted. The matrix data is stored in a compressed format to reduce bandwidth consumption during data transmission.

[0078] The matrix synchronization mechanism employs a double-buffered structure to ensure that data updates do not affect ongoing power allocation operations. The currently active matrix is ​​stored in the active buffer, while newly generated matrices are stored in the prepared buffer. Once the new matrix is ​​constructed, the system atomically switches the buffer pointers, achieving seamless matrix data updates. This design avoids data inconsistencies during the update process.

[0079] The calculation of the block power consumption coefficient takes into account a variety of influencing factors. In addition to basic parameters such as average brightness and refresh rate, the system also refers to auxiliary information such as the operating voltage of the pixel unit and the ambient temperature. This auxiliary information comes from the sensor array built into the display panel and is transmitted to the computing module through a dedicated interface circuit. The computing unit adopts a pipelined architecture, which can process data from multiple blocks in parallel, ensuring that all computing tasks are completed within a limited time.

[0080] The power consumption fluctuation analysis algorithm employs multi-stage filtering technology to effectively eliminate interference from measurement noise. The raw acquired data is first low-pass filtered to remove high-frequency noise components. Then, a moving average is applied to smooth short-term random fluctuations. Finally, statistical methods are used to identify the true power consumption change trend, avoiding misinterpreting instantaneous fluctuations as actual changes. This processing method improves the system's accuracy in identifying true power consumption changes.

[0081] The high-volatility region labeling strategy employs a dynamic threshold mechanism. The system not only compares the current volatility value with a fixed threshold but also considers the block's historical volatility characteristics. For blocks that have remained stable over a long period, the system appropriately relaxes the criteria; while for blocks with frequent fluctuations, a stricter standard is applied. This differentiated approach allows the system to more accurately identify truly high-volatility regions that require special attention.

[0082] The dynamic adjustment process of the weight coefficients incorporates a smooth transition mechanism. When a weight value needs to be changed, the system does not immediately jump to the new value, but adjusts gradually according to a preset transition curve. This gradual change method avoids display quality fluctuations caused by sudden weight changes, making the adjustment process smoother and more natural. The shape of the transition curve can be configured according to actual needs, supporting linear changes and various non-linear change modes.

[0083] The algorithm for generating the partitioned power consumption quota matrix supports multiple allocation strategies. The system has built-in preset modes such as equal allocation, on-demand allocation, and hybrid allocation, allowing the selection of the most suitable strategy based on the characteristics of the displayed content. In hybrid allocation mode, the system divides the display area into multiple functional partitions, applying different allocation principles to each partition. This flexible allocation method better adapts to the needs of various application scenarios.

[0084] Differential signaling technology is used for the transmission of matrix data to improve anti-interference capabilities. Data is encoded before transmission, with error correction and verification information added. The receiving end checks the data integrity during decoding and can request retransmission if errors are detected. This mechanism ensures the reliability of critical control data during transmission, preventing system malfunctions due to communication errors.

[0085] Example 2: See Figure 3 The scanning strategy optimization module and the timing control reconfiguration module work collaboratively. After receiving the partitioned power quota matrix from the power dynamic allocation module, the scanning strategy optimization module first parses the matrix data. The parsing process uses a layered decoding method, first reading the matrix header information to obtain the block division parameters, and then extracting the power quota weight value of each block row by row. The weight values ​​are stored in fixed-point notation, with a value range between 0 and 1, and a precision of three decimal places. The system maintains a weight classification threshold table and dynamically adjusts the classification criteria according to the current display mode. For static display mode, the threshold setting is relatively lenient; while for dynamic display mode, a stricter classification standard is used.

[0086] Low-priority regions are determined by comparing their block weight values ​​with a set threshold. When the weight value is below the threshold, the block is classified as a low-priority region. The system employs a special scanning strategy for these regions, the core idea being to reduce power consumption by minimizing the number of scan operations. The specific implementation of the row scan merging strategy involves reconstructing the traditional scan sequence; the scan enable signals, which originally needed to be sent row by row, are rearranged. The merging operation uses three rows as a basic unit, combining the scan enable signals of three consecutive rows into a single enable pulse. This merging not only reduces the number of scan signal transmissions but also lowers the switching frequency of the row driver circuitry. The merged row scan signal carries composite address information, requiring the row address decoder to support extended address mapping functionality.

[0087] The column scan frequency adjustment strategy has a non-linear relationship with the block weight value. The system uses the following formula to calculate the column scan frequency division coefficient:

[0088]

[0089] Among them, C adj W represents the adjusted column scan frequency division coefficient. b The value represents the block weight, and e is the base of the natural logarithm. The frequency division coefficient generated by this formula approaches its maximum value when the weight value is low, gradually decreases as the weight value increases, and rapidly converges to its minimum value after the weight value exceeds a critical point. This variation curve ensures that important display areas receive sufficient scanning resources while effectively limiting the scanning overhead of non-critical areas. The frequency division coefficient is implemented using a programmable frequency divider array, with each monitoring block configured with an independent frequency divider instance.

[0090] The adaptive scanning strategy table is constructed using an incremental update mechanism. The system maintains a copy of the currently effective strategy table, and when a new partition power consumption quota matrix is ​​received, the strategy is recalculated only for the affected blocks. The table data structure uses an index-based organization, including multiple fields such as block coordinate index, row merge flag, and column scan frequency division coefficient. The row merge flag uses bitmap encoding, with each bit corresponding to a specific row merge group. The column scan frequency division coefficient field stores the configuration values ​​actually applied to the hardware frequency divider. The table update operation uses a transaction processing mode to ensure that if an exception occurs during the update process, it can be rolled back to a previous consistent state.

[0091] The timing control reconstruction module begins by parsing the adaptive scan strategy table. The module has a dedicated table parsing engine that efficiently extracts timing control parameters from the table. The key to reconstructing the vertical synchronization signal lies in adjusting its effective pulse width, which requires precise calculation of the timing changes caused by the row merging operation. The system has a built-in pulse width calculation unit that dynamically determines the duration of each stage of the vertical synchronization signal based on the number of row merging groups and basic timing parameters. The calculation process takes into account the setup and hold time requirements of the row driver circuit to avoid signal sampling errors caused by inappropriate pulse width.

[0092] The reconstruction of the horizontal synchronization signal is more complex, involving dynamic adjustment of the rising edge trigger interval. The timing control reconstruction module integrates a digital phase-locked loop (PLL) circuit to generate a precisely adjustable scan clock signal. A programmable frequency divider is inserted into the PLL's feedback loop, with the division ratio determined by the column scan division coefficient. Clock signal jitter control is implemented using dedicated circuitry to ensure sufficient signal integrity during frequency changes. The calculation of the rising edge trigger time needs to consider the actual end time of the previous scan cycle; the system uses a predictive algorithm to pre-determine the optimal trigger point.

[0093] The generation process of the dynamic timing control waveform employs mixed-signal processing technology. The digital section is responsible for the precise calculation of timing parameters and logic control, while the analog section handles signal shaping and drive enhancement. The control of the blanking interval is particularly critical; the system dynamically adjusts the blanking period length based on the block activity parameter. Activity calculation is based on the actual number of scans and power consumption of the block in the most recent frames. The blanking interval counter adopts a reloadable design, supporting dynamic modification of the count value during scanning. This design enables the system to respond in real-time to changes in the displayed content and adjust timing parameters accordingly.

[0094] The waveform generation module's output stage employs a differential drive structure, enhancing signal transmission's anti-interference capability. Each output channel is equipped with an independent impedance matching network, automatically adjusting output characteristics according to actual load conditions. Signal overshoot and ringing are suppressed through built-in pre-emphasis and de-emphasis circuits. Output level calibration is completed during system initialization, with calibration data stored in non-volatile memory.

[0095] The row address generator employs a multi-stage pipelined architecture, enabling parallel processing of address calculations for multiple merged row groups. The address mapping table is implemented using content-addressable memory, supporting fast lookups and updates. For merged row groups, the address generator produces composite address codes, requiring the row driver to work with special decoding logic for correct parsing. The address transmission protocol utilizes a redundancy check mechanism to ensure that address information is transmitted without errors.

[0096] The column scan control circuit is designed to balance flexibility and efficiency. Each monitoring block is equipped with an independent column scan sequence generator, and the sequence generation algorithm is dynamically adjusted based on the frequency division coefficient. The timing of column data loading is carefully calculated to ensure precise synchronization with the row scan operation. The data latch signal is generated by a dedicated timing calibration circuit to compensate for transmission delay differences between different blocks. The power supply voltage of the column driver can be finely adjusted according to the actual scan frequency to minimize power consumption while ensuring signal quality.

[0097] The adaptive adjustment process of timing parameters incorporates a feedback control mechanism. The system monitors the deviation between the actual scan timing and the expected target in real time, and gradually eliminates the error through closed-loop adjustment. The feedback signal comes from timing detection circuits at the edge of the display panel, which can accurately measure the actual arrival time of key control signals. The adjustment algorithm adopts a gradual approximation strategy to avoid system instability caused by over-adjustment.

[0098] Example 3: See Figure 4 This document details the workflow of the drive signal conversion module and the power consumption threshold adaptive module. The core function of the drive signal conversion module is to convert the dynamic timing control waveform generated by the timing control reconstruction module into actual drive signals, while simultaneously monitoring system power consumption and forming a feedback loop. This module employs a multi-channel parallel processing architecture, with each display area corresponding to an independent signal conversion channel. The number of channels is consistent with the display panel's partitioning scheme. The signal conversion process begins with receiving the dynamic timing control waveform. The waveform data is transmitted via a high-speed serial interface, employing differential signal transmission technology to improve anti-interference capabilities. The receiving end uses a clock data recovery circuit to accurately extract the clock signal, ensuring the accuracy of the data sampling timing.

[0099] The grayscale voltage control signal is generated using a piecewise linear approximation technique. The module integrates a high-precision digital-to-analog converter (DAC) array, with each DAC responsible for the grayscale voltage output of a specific display area. The blanking cycle detection circuit analyzes the dynamic timing control waveform in real time. When a blanking interval is detected, it immediately triggers the low-power mode of the corresponding DAC. This mode is achieved by cutting off the reference voltage source, and a ramp-start method is used to avoid voltage surges when resuming operation. The grayscale voltage output buffer uses an adjustable drive strength design, with the drive strength parameter D... str With block weight value W b The relationship is as follows:

[0100] D str =0.5+2 3Wb-1

[0101] Among them, D str W represents the normalized driving intensity coefficient. bThe block weight values ​​are derived from the partitioned power consumption quota matrix. This formula ensures that important display areas receive stronger driving capabilities, while the driving strength of secondary areas is appropriately reduced. The output stage of the buffer adopts a Class AB amplifier structure, ensuring both linearity and energy efficiency.

[0102] The generation process of the gate turn-on voltage signal has strict timing requirements. The module incorporates a dedicated timing calibration circuit to compensate for inherent delays in the signal path. The turn-on duration is dynamically adjusted based on block activity, with carefully designed adjustment steps to avoid noticeable brightness jumps. The gate driver's charging current is programmable, allowing flexible switching between fast turn-on and low-power modes. The rise and fall slopes of the drive signal are independently adjustable to adapt to different display scenarios. An overshoot suppression circuit monitors the output waveform in real time and eliminates ringing by dynamically adjusting the drive current.

[0103] The actual power consumption monitoring system employs a distributed architecture. Each display block is equipped with an independent current sensor, which is implemented using a precision sampling resistor and instrumentation amplifier. The current measurement value is digitized by a 24-bit Σ-Δ analog-to-digital converter, with the sampling rate synchronized with the display refresh rate. The digitized current data is sent to the data processing unit to calculate statistical parameters such as average current and peak current. The data processing unit uses a sliding window algorithm, and the window size can be dynamically configured according to monitoring requirements. The statistical results are fed back to the power consumption feature extraction module through a dedicated communication interface, forming the basis for closed-loop control.

[0104] The power consumption threshold adaptive module operates based on historical power consumption data stored in a circular buffer. The buffer employs a first-in, first-out (FIFO) management strategy, with configurable storage depth; typically, it stores power consumption information for the most recent 256 frames. The full-screen average power consumption is calculated using a weighted moving average algorithm, with recent frame data having a higher weighting coefficient. The peak power consumption difference is obtained by comparing the current frame's power consumption with the historical average in real time, and the comparison result is sent to the threshold adjustment decision unit. The decision unit is implemented using a state machine, which determines whether the power consumption threshold needs adjustment based on preset rules.

[0105] The adjustment process for the preset power consumption threshold incorporates an inertial damping mechanism. When the system determines that the threshold needs to be increased, the adjustment magnitude is proportional to the degree to which the current power consumption exceeds the threshold, but does not exceed the preset upper limit. Threshold reduction employs a gradual strategy, with each adjustment being a fixed and relatively small increment. Adjustment commands are broadcast to all modules in the system via a digital bus, and the receiving modules update their parameters within a specified time window. Historical records of threshold changes are stored in non-volatile memory for system initialization and fault recovery.

[0106] The ambient light intensity sensor's data acquisition cycle is asynchronous with the display refresh rate to avoid mutual interference. Sensor data undergoes digital filtering to eliminate false positives caused by transient interference. The display content complexity detection unit runs on a dedicated core of the graphics processor, employing parallel algorithms to accelerate the edge detection process. The detection result is quantified as a complexity coefficient between 0 and 1, which, along with the ambient light intensity data, influences the calculation of the power consumption threshold baseline.

[0107] The signal spectrum analysis unit's workflow begins with high-speed sampling. The analog-to-digital converter's sampling clock is strictly synchronized with the display timing, but the phase is programmably adjusted to capture key signal features. Sampled data is stored in ping-pong buffers; one set of buffers is used for data acquisition while another is used by the spectrum analysis engine. The Fast Fourier Transform processor is implemented using a radix-4 algorithm, supporting real-time spectrum calculation. The spectrum analysis results are compared frequency-by-frequency with a pre-stored reference template; frequency points with differences exceeding a threshold are marked as potential interference sources.

[0108] The generation of waveform smoothing requests follows a cautious principle. An adjustment request is only issued when significant spectral anomalies are detected in multiple consecutive sampling windows. The request information contains detailed spectral anomaly characteristics, allowing the timing control and reconstruction module to precisely adjust waveform parameters. The rising edge buffer time of the horizontal synchronization signal is adjusted using a small-step, gradual approach, with spectral characteristics reassessed after each adjustment until satisfactory interference suppression is achieved.

[0109] Example 4: See Figure 5 The impact mechanism of ambient light intensity and display content complexity on power consumption threshold adjustment, and the workflow of the signal spectrum analysis unit are explained. The system collects ambient light conditions in real time through an ambient light sensor, which uses an I... 2 The digital illuminance chip with a C-interface measures light intensity from 1 to 100,000 lux, outputting 16-bit precision light intensity data. The sensor samples at 200-millisecond intervals, with each sample consisting of five rapid measurements, and the median value is taken as the valid output. The light intensity data is then processed by a moving average filter before being fed into a threshold calculation unit. Display content complexity detection runs on a dedicated computing unit of the graphics processor, using the Sobel edge detection algorithm to analyze the image data in the current frame buffer and calculate the percentage of edge pixels out of the total number of pixels as a complexity indicator.

[0110] The impact of ambient light intensity and displayed content on power consumption thresholds is implemented through a lookup table mechanism. The system maintains a two-dimensional parameter table, which represents light intensity and complexity as discrete levels, with each intersection storing the corresponding threshold adjustment coefficient. When the ambient light intensity changes or new display content complexity is detected, the system queries the table to obtain the adjustment coefficient and updates the preset power consumption threshold accordingly. The table below shows a typical parameter representation example:

[0111]

[0112] The signal spectrum analysis unit begins its operation with high-speed sampling, employing an 8-bit resolution, 4GS / s sampling rate analog-to-digital converter to capture the grayscale voltage control signal. The sampling process is strictly synchronized with the vertical synchronization signal to ensure consistent sampling window positions within each frame period. Sampled data is stored in a double-buffered memory; one buffer stores newly acquired data while the data in the other buffer undergoes spectrum analysis. Spectrum analysis utilizes a 128-point Fast Fourier Transform algorithm, employing a Hanning window function to reduce spectral leakage. The analysis results are compared with a pre-stored reference spectrum template, dynamically selected based on different display modes, encompassing typical spectral characteristics under normal operating conditions.

[0113] Abnormal frequency identification employs a multi-condition judgment mechanism. The system not only compares the absolute difference between the current spectral components and the reference value, but also analyzes the changing trends of adjacent frequency points. When the energy value of a certain frequency point consistently exceeds the reference level by more than 10 dB, and the three surrounding frequency points also show a similar trend, the area is marked as an electromagnetic interference risk zone. Interference window location information is recorded in bitmap format, with each bit corresponding to a 32.6 microsecond sampling window. Setting a bit indicates that the window has an interference risk. Bitmap data is transmitted to the scanning strategy optimization module through a dedicated channel, and cyclic redundancy check is used during transmission to ensure data integrity.

[0114] The calibration process for the ambient light sensor is completed during the system initialization phase. During calibration, the sensor performs multi-point measurements under standard light source conditions to establish a calibration curve between the raw readings and the actual light intensity. Calibration parameters, including offset and gain coefficients, are stored in non-volatile memory. During operation, the sensor periodically executes a self-test procedure, verifying its operating status by measuring the internal reference voltage. When an anomaly is detected, the system automatically switches to a backup sensor or continues operation using default parameters.

[0115] The display content complexity detection employs a parallel processing architecture. The graphics processor divides the display area into multiple processing blocks, each analyzed by a dedicated thread. The edge detection algorithm optimizes memory access patterns and fully utilizes cache to improve data throughput. The complexity calculation results undergo spatial filtering to eliminate the impact of local abrupt changes. The final output complexity value is a weighted average of the complexity of each region, with the weights dynamically adjusted based on the region's location, and the central region having a higher weight than the edge regions.

[0116] The dynamic adjustment process of the power consumption threshold incorporates a rate limiting mechanism. The system limits the rate of threshold change to avoid fluctuations in display quality caused by large adjustments in a short period. Adjustment commands are broadcast via the system bus. Upon receiving the command, each functional module first verifies the rationality of the new threshold before executing the actual parameter update. The system records the timestamp and adjustment amount of each threshold adjustment. This historical data is used to analyze power consumption trends and optimize adjustment strategies.

[0117] Subsequent processing of the spectrum analysis results includes interference mode classification. Based on the distribution characteristics of anomalous frequency points, the system categorizes interference into narrowband interference, wideband interference, and resonant interference. For each type of interference, the waveform smoothing request includes processing suggestions. Upon receiving the request, the timing control and reconstruction module selects the most suitable adjustment strategy based on the interference type. Narrowband interference primarily requires increasing the rise-edge buffer time, wideband interference necessitates adjusting the overall signal shape, and resonant interference may require altering the timing of the scan sequence.

[0118] The system maintains a knowledge base of interference patterns, recording various interference characteristics and their treatment effects throughout history. When a new interference pattern is detected, the system first searches the knowledge base for similar cases and refers to historical treatment solutions. The knowledge base is updated regularly to include validated and effective treatment solutions. This case-based reasoning approach improves the system's ability to cope with new types of interference and reduces the time spent on trial and error adjustments.

[0119] Example 5: Focusing on Precise Detection and Dynamic Avoidance Mechanisms for Electromagnetic Interference Windows. The system uses the vertical synchronization signal as a reference, dividing each frame period into 512 equally spaced time-domain sampling windows, each lasting 32.6 microseconds. A high-speed analog-to-digital converter employs time interleaving technology, completing 8 waveform captures within a single sampling window, with sampling points evenly distributed across the window's time range. The captured analog signal is processed by an anti-aliasing filter, whose cutoff frequency is dynamically adjusted according to the current display mode to adapt to signal characteristics at different resolutions. Sampling data is temporarily stored in ping-pong buffers; while one buffer is used to store newly acquired waveform data, data from the other buffer is fed into the spectrum analysis pipeline.

[0120] The spectral feature extraction process employs windowed Fourier transform technology, with the window function type dynamically selected based on interference characteristics. The system pre-sets three window functions: Hanning window, flat-top window, and Kaiser window, each suitable for signal analysis with different spectral characteristics. A reference energy distribution template is stored in non-volatile memory, containing the spectral characteristics of grayscale voltage control signals under various typical operating conditions. The template matching algorithm not only compares the absolute energy values ​​of each frequency point but also analyzes the similarity of the spectral envelope shape. Abnormal frequency point identification employs a multi-level screening strategy: first, it identifies frequency points with energy significantly higher than the average level; then, it checks the persistence of these frequency points within the continuous sampling window; and finally, it evaluates the geometric characteristics of frequency point clusters.

[0121] The marking process for electromagnetic interference windows incorporates a confidence assessment mechanism. Each marked window is accompanied by a confidence score, reflecting the reliability of interference detection. The score is calculated based on a combination of factors, including the number of anomalous frequency points, the degree of energy exceeding limits, and the duration. The system maintains a dynamic threshold; only windows with confidence scores exceeding this threshold are included in the final interference window location information table. The threshold itself is adaptively adjusted based on the statistical characteristics of historical detection results, maintaining a balance between detection sensitivity and false alarm rate.

[0122] The interference window location information table is stored in a compressed format, using run-length encoding to represent continuous interference window intervals. The table update mechanism employs incremental processing, modifying only the changed portions. Table data is transmitted to the scanning strategy optimization module via a dedicated data channel. The transmission protocol includes error detection and automatic retransmission functions to ensure reliable delivery of critical information. The receiving end decompresses and verifies the table data before fusing it with the current scanning strategy.

[0123] The scanning strategy adjustment follows the principle of minimal intervention. The system first analyzes the distribution pattern of interference windows within the frame period to identify concentrated interference periods. For isolated interference windows, the scanning sequence is fine-tuned to avoid them; for continuous groups of interference windows, the scanning sequence is replanned, advancing or delaying the scanning operation of the affected areas. The line address generator, in conjunction with the adjusted scanning strategy, dynamically modifies the line scanning order to ensure that skipping the display area corresponding to the interference window does not cause obvious screen tearing or flickering.

[0124] The compensation scan mechanism ensures display integrity while maintaining a stable refresh rate. When the system decides to skip certain interference windows, a compensation scan operation is inserted during a safe period of the frame cycle. The compensation scan uses a dedicated line buffer to store the data to be displayed. This buffer has a dual-port design, supporting simultaneous data writing and reading. Timing calibration circuitry precisely controls the start timing of the compensation scan, ensuring seamless integration with normal scan operations. The power management unit provides additional power budget for the compensation scan, preventing excessive instantaneous power consumption due to concentrated scanning.

[0125] The interference pattern learning system continuously analyzes the occurrence patterns of electromagnetic interference. The system records the temporal distribution characteristics, spectral properties, and environmental parameters of interference windows, establishing an interference event database. Periodically running machine learning algorithms extract interference patterns from historical data, identifying potential periodicity or correlation. The learning results are used to optimize detection parameters and adjust strategies, such as predicting potential interference periods and adjusting scanning plans in advance. The knowledge base update process employs a version control mechanism, allowing for rollback to previous stable configurations when necessary.

[0126] The real-time monitoring interface displays the current interference detection status and the execution of avoidance strategies. Engineers can observe spectrum analysis results, interference window distribution diagrams, and the effects of scan sequence adjustments. The debugging interface supports injecting test signals to simulate various interference scenarios to verify the system response. The performance statistics function records the accuracy of interference detection, the success rate of avoidance strategies, and system resource usage; this data is used for continuous optimization of algorithm parameters.

[0127] Hardware accelerators enhance the real-time performance of spectrum analysis. A dedicated digital signal processor performs Fast Fourier Transform and template matching operations in parallel, with processing latency controlled within five sampling windows. The memory subsystem employs a hierarchical design, with high-frequency access data cached in on-chip memory and large-capacity templates stored in external low-power memory. The power management unit provides an independent voltage domain for signal acquisition and analysis circuits, reducing the interference of digital noise on analog signals.

[0128] The system initialization process includes comprehensive self-tests and calibration procedures. The gain and offset parameters of the analog-to-digital converter are calibrated at the factory, and self-calibration is performed periodically during operation to compensate for temperature drift. The reference energy template is dynamically updated based on the actual display content, avoiding template aging issues caused by long-term use. The startup sequence of each functional module is carefully designed to ensure that critical subsystems complete initialization before functions that rely on them.

[0129] The anomaly handling mechanism covers the entire process from signal acquisition to scan adjustment. When a hardware fault or data anomaly is detected, the system takes tiered response measures based on the severity. Minor anomalies trigger a local recovery process, resetting only the affected functional modules; severe errors activate a system-level protection mechanism, switching to a simplified safe operating mode. Dynamic parameter adjustment allows the system to adapt to different operating environments. In complex electromagnetic environments, the system automatically increases detection sensitivity and enhances the conservatism of the scanning strategy; in environments with less interference, the detection criteria are appropriately relaxed to reduce computational overhead. The environmental parameter monitoring unit collects data such as temperature, humidity, and power supply noise in real time; this information is used to fine-tune the interference detection threshold.

[0130] The user interface provides configuration options related to interference management. It allows adjustment of detection sensitivity, the aggressiveness of evasion strategies, and the priority of compensatory scans. The advanced settings interface supports professional users in fine-tuning spectrum analysis parameters and scan timing parameters. All configuration changes undergo validity checks to avoid contradictory settings that could lead to system instability. Configuration data is stored in non-volatile memory and supports import / export functions for easy batch deployment.

[0131] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0132] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A dynamic adjustment system for a liquid crystal display driving circuit designed for low power consumption, characterized in that, It includes a power consumption feature extraction module, a power consumption dynamic allocation module, a scanning strategy optimization module, a timing control reconstruction module, and a drive signal conversion module; The power consumption feature extraction module is used to continuously collect real-time power consumption parameters of each area of ​​the display panel and establish a regional power consumption feature map based on the analysis results of the display content. The power dynamic allocation module analyzes the power fluctuation difference between the current frame and historical frames based on the regional power consumption feature map, generates a partition power consumption quota matrix in combination with the preset power consumption threshold, and synchronizes the partition power consumption quota matrix to the scanning strategy optimization module. The scanning strategy optimization module receives the partition power consumption quota matrix, dynamically adjusts the row scanning sequence and column scanning frequency according to the power consumption quota weight of each region, generates an adaptive scanning strategy table, and transmits it to the timing control reconstruction module. The timing control reconstruction module parses the scanning timing parameters in the adaptive scanning strategy table, reconstructs the timing logic relationship between the vertical synchronization signal and the horizontal synchronization signal, and outputs the dynamic timing control waveform to the drive signal conversion module. The drive signal conversion module generates grayscale voltage control signals and gate turn-on voltage signals based on the dynamic timing control waveform, and simultaneously feeds back the actual drive power consumption data to the power consumption feature extraction module.

2. The dynamic adjustment system for liquid crystal display driving circuits designed for low power consumption as described in claim 1, characterized in that, The power consumption feature extraction module includes: Collect the brightness values ​​of the three primary colors (red, green, and blue) and refresh rate parameters of each pixel unit on the display panel, and map them to generate a pixel-level power consumption distribution heatmap; The display panel is divided into M×N power consumption monitoring blocks, and the average brightness and refresh rate change frequency of each block are statistically analyzed. The real-time power consumption coefficient of each block is calculated based on the average brightness and refresh rate change frequency of each block, and then integrated to form a regional power consumption characteristic map.

3. The dynamic adjustment system for liquid crystal display driving circuits designed for low power consumption as described in claim 2, characterized in that, The power dynamic allocation module performs the following operations: Extract the block power consumption coefficients of K consecutive frames in the regional power consumption feature map, and calculate the power consumption fluctuation variance of each block; Compare the power consumption fluctuation variance of the blocks with the preset fluctuation tolerance threshold, and mark the blocks that exceed the threshold as high fluctuation areas; The global power consumption allocation weight coefficient is adjusted based on the proportion of high-fluctuation areas, and a partitioned power consumption quota matrix containing the maximum allowable power consumption value of each block is generated by combining the preset power consumption threshold.

4. The dynamic adjustment system for liquid crystal display driving circuits according to claim 1, characterized in that, The scanning strategy optimization module is specifically implemented as follows: Analyze the power quota weight of each block in the partitioned power quota matrix, and classify the blocks with weights lower than the set value as low priority areas; For low-priority areas, a row scan merging strategy is used to merge three adjacent row scan signals into a single scan operation; The column scan frequency of high-weight regions is dynamically reduced based on the block power consumption quota weight, generating an adaptive scan strategy table that includes row merging identifiers and column frequency adjustment parameters.

5. The dynamic adjustment system for liquid crystal display driving circuits according to claim 4, characterized in that, The timing control reconstruction module includes: Read the row merging identifier in the adaptive scanning strategy table and recalculate the effective pulse width of the vertical synchronization signal; Analyze the column frequency adjustment parameters and reconstruct the rising edge trigger interval of the horizontal synchronization signal; A dynamic timing control waveform with a variable blanking period is generated based on the reconstructed vertical synchronization signal and horizontal synchronization signal.

6. The dynamic adjustment system for liquid crystal display driving circuits according to claim 5, characterized in that, The drive signal conversion module includes: Receive the blanking period parameter in the dynamic timing control waveform and turn off the grayscale voltage output of inactive areas during the blanking period; The duration of the gate turn-on voltage is dynamically adjusted based on the horizontal synchronous trigger interval of the dynamic timing control waveform. The drive current value of each block is monitored in real time and converted into actual drive power consumption data, which is then fed back to the power consumption feature extraction module.

7. The dynamic adjustment system for liquid crystal display driving circuits according to claim 1, characterized in that, It also includes a power consumption threshold adaptive module: Receive the regional power consumption feature map output by the power consumption feature extraction module, and extract the difference between the average power consumption and the peak power consumption of the whole screen; When the peak power consumption difference exceeds the preset warning value, the preset power consumption threshold is dynamically increased based on historical power consumption data. When the average power consumption of the full screen is lower than the set threshold for multiple consecutive frames, the preset power consumption threshold is reduced by a preset step value.

8. The dynamic adjustment system for liquid crystal display driving circuits according to claim 7, characterized in that, The power consumption threshold adaptive module further includes: Establish a connection channel between the ambient light intensity sensor and the display content complexity detection unit; The baseline value for adjusting the preset power consumption threshold is adjusted based on the change in ambient light intensity. The preset power consumption threshold fluctuation range is adjusted based on the graphic edge density parameter output by the display content complexity detection unit.

9. The dynamic adjustment system for liquid crystal display driving circuits according to claim 1, characterized in that, The drive signal conversion module includes a signal spectrum analysis unit: The frequency distribution characteristics of the grayscale voltage control signal are collected, and the energy values ​​of the main harmonic components are extracted. When the energy value of the main harmonic component exceeds the set threshold, a waveform smoothing request is sent to the timing control reconfiguration module. After the timing control reconfiguration module responds to the request, it adds a rising edge buffer time for the horizontal synchronization signal.

10. The dynamic adjustment system for liquid crystal display driving circuits according to claim 9, characterized in that, The signal spectrum analysis unit performs the following operations: Within the complete cycle of the vertical synchronization signal, multiple consecutive time-domain sampling windows are divided at equal intervals; The actual waveform of the grayscale voltage control signal within each time domain sampling window is captured by a high-speed analog-to-digital converter. Perform a Fast Fourier Transform operation on the actual waveform of each captured time-domain sampling window to extract the corresponding spectral distribution feature data; The extracted spectral distribution feature data is compared with the pre-stored benchmark energy distribution template to identify abnormal frequency points where the spectral energy is significantly higher than the benchmark energy. The time-domain sampling window containing abnormal frequency points is marked as the electromagnetic interference window, and its start and end positions are recorded throughout the entire vertical synchronization cycle. Summarize the location information of all marked electromagnetic interference windows and generate an electromagnetic interference window location information table; The electromagnetic interference window position information table is transmitted to the scanning strategy optimization module in real time. After receiving the electromagnetic interference window position information table, the scanning strategy optimization module skips the row scanning operation of the corresponding display area based on the position identified in the electromagnetic interference window position information table when generating the adaptive scanning strategy table.

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