Periodic information buffer space equalization and flow control method and system

Abstract

The application provides a periodic information cache space balancing and flow control method and system, the method realizes the ordered delivery of messages by establishing the mapping relationship between the message identifier and the load length and combining the DMA polling delivery mechanism. By calculating the cache number occupied by each message, the total cache number and the balancing factor, the cache space is dynamically allocated according to the load length and the balancing factor, so that the cache resources are reasonably allocated according to the message demand, and the problems of resource waste or shortage caused by uneven allocation of cache space are avoided. By judging whether the total cache space meets the preset condition and dynamically adjusting the load length or the cache unit space, the cache utilization efficiency is further optimized, the adaptability of the cache demand of all messages to the total cache space of the board in a scheduling period is improved, the stability of the periodic information transmission and the efficiency of the resource utilization are improved, so as to solve the problems of DMA congestion, scheduling failure or low bandwidth that cannot meet the bandwidth demand in the communication process.

Description

Technical Field

[0001] This invention relates to the field of GLink high-speed fiber optic communication bus node communication technology, and in particular to a periodic information buffer space balancing and flow control method and system. Background Technology

[0002] GLink (Generic Link) high-speed fiber optic communication bus is a new generation of high-speed fiber optic communication bus that integrates air and ground. It features high bandwidth, strong real-time performance, high reliability, and command-response serial communication. It also supports bus, star, and ring network topologies. Systems, devices, and boards can all be connected using a single GLink bus, and the bus standard is unified.

[0003] In the GLink network topology, communication nodes, such as the network controller (NC) and the network terminal (NT), may experience DMA congestion, scheduling failures, or insufficient bandwidth to meet bandwidth requirements and achieve system performance during communication using traditional send / receive mechanisms. Therefore, a message buffer space balancing and flow control algorithm is needed to further improve performance, stability, and reliability. Summary of the Invention

[0004] This invention provides a method and system for periodic information buffer space balancing and flow control to solve the problems of DMA congestion, scheduling failure, or insufficient bandwidth to meet bandwidth requirements during communication.

[0005] On the one hand, the present invention provides a periodic information cache space balancing and flow control method, including: determining the total number of messages to be sent, message identifiers and load lengths, determining the space of a single DMA cache unit, establishing a mapping relationship between the message identifiers and the load lengths, and sequentially sending the messages to be sent according to the polling mechanism using a DMA polling method;

[0006] Based on the mapping relationship, combined with the load length and the space of a single cache unit in the DMA, the number of caches occupied by the message to be sent is calculated, and the number of caches occupied is accumulated to obtain the total number of message caches required by the message to be sent in one scheduling cycle;

[0007] Obtain the total cache space of the board, and combine the total cache space with the space of a single cache unit of the DMA to calculate the total cache count of the board;

[0008] Calculate the ratio of the total number of caches on the board to the total number of message caches to obtain the balance factor;

[0009] Based on the mapping relationship, for each message to be sent, the number of cached messages to be sent is calculated by combining the balancing factor and the load length; the cache space of the message to be sent is calculated by combining the number of cached messages with the space of a single cache unit in the DMA; and the cache spaces are accumulated to obtain the total cache space of the message to be sent.

[0010] Determine whether the total cache space meets the preset conditions. If the total cache space does not meet the preset conditions, adjust the load length of the message to be sent or adjust the space of a single cache unit of the DMA, and repeat the process until the total cache space of the message to be sent meets the preset conditions.

[0011] Optionally, establishing the mapping relationship between the message identifier and the payload length includes:

[0012] The message identifier is converted into a RAM address, and the message identifier and the read / write pointer of the message to be sent are stored in the RAM address;

[0013] If different message identifiers result in the same RAM address after conversion, then the RAM address calculated later is incremented by one.

[0014] When a message needs to be read, the corresponding RAM address is calculated based on the message identifier, and the message identifier stored in the RAM address is matched with the identifier of the message to be read. If the match is consistent, the message data is read based on the read / write pointer.

[0015] Optionally, it also includes:

[0016] For each message to be sent, which has a different message identifier, multiple data blocks of the same size are allocated;

[0017] The DDR address and number of data blocks of the message to be sent are stored in RAM.

[0018] Optionally, before calculating the balancing factor based on the total number of caches on the board and the total number of message caches, the method further includes:

[0019] Set a basic scheduling period and calculate the total load length of the messages to be sent within the basic scheduling period;

[0020] The minimum processing speed is calculated by combining the basic scheduling period and the total load length, whereby the minimum processing speed is the total load length divided by the basic scheduling period.

[0021] Optionally, the method of sequentially sending the messages to be sent using a DMA polling approach further includes:

[0022] Determine the maximum cache space from the cache space of the messages to be sent, and calculate the maximum time required to process the messages to be sent corresponding to the maximum cache space in combination with the minimum processing speed;

[0023] Set the maximum time as the minimum polling time;

[0024] Set the board balance query polling time to an integer multiple K of the minimum polling time, and set the minimum number of polling, the maximum and minimum board balance values, and satisfy the condition that the integer multiple K < (maximum board balance - minimum board balance) / (maximum cache space × minimum number of polling).

[0025] The board remaining capacity query polling time is determined based on the integer multiple K.

[0026] Optionally, it also includes:

[0027] Determine the load length of each message in the messages to be sent, and calculate the total load length of the messages to be sent;

[0028] Obtain the basic data processing rate;

[0029] Divide the total load length by the basic data processing rate to obtain the minimum processing time;

[0030] The minimum processing time is multiplied by a preset time redundancy coefficient to generate a polling time slice, which is used for sleep waiting time in flow control operations.

[0031] Optionally, after determining whether the total cache space meets the preset conditions, the method further includes:

[0032] Set the minimum and maximum percentage of remaining cache space on the board;

[0033] The minimum and maximum cache space sizes are calculated based on the minimum and maximum percentages of the board's cache remaining capacity, and the total number of messages cached.

[0034] Obtain the number of free cache spaces for the message to be sent;

[0035] If the number of free cache spaces is less than or equal to the minimum number of cache spaces, then sleep and wait until the polling time slice ends;

[0036] If the minimum cache space number is greater than the free cache space number and the free cache space number is less than or equal to the maximum cache space number, then after sending the data to be sent, the system will sleep and wait until the polling time slice ends.

[0037] If the number of free cache spaces is greater than the number of maximum cache spaces, data will continue to be sent and the remaining cache space of the board will be obtained until the number of free cache spaces falls between the number of minimum cache spaces and the number of maximum cache spaces.

[0038] Optionally, it also includes:

[0039] The load percentage of the message to be sent is obtained by the ratio of the load length of the message to be sent to the total load length of the message to be sent.

[0040] Multiply the load percentage by the total cache size of the board to obtain the initial cache size of the message to be sent;

[0041] If the cache space corresponding to the initial cache number is less than the maximum load length of the message to be sent, then the cache number of the message to be sent is adjusted according to the minimum cache number required for the maximum load length.

[0042] Optionally, if the total cache space does not meet the preset conditions, the method further includes:

[0043] The fluctuation range of the remaining buffer space on the board after data is sent during the scheduling period is statistically analyzed.

[0044] If the fluctuation amplitude of multiple consecutive scheduling cycles exceeds the preset fluctuation threshold, the equilibrium factor is recalculated to obtain a corrected equilibrium factor.

[0045] The cache size of the messages to be sent is adjusted based on the aforementioned adjustment balance factor.

[0046] On the other hand, this application also provides a periodic information cache space balancing and flow control system, including:

[0047] The message parameter and mapping relationship establishment module is used to determine the total number of messages to be sent, message identifiers and load lengths, determine the space of a single DMA cache unit, and establish a mapping relationship between the message identifiers and the load lengths.

[0048] The DMA polling delivery module is used to sequentially deliver the messages to be delivered according to the polling mechanism using the DMA polling delivery method.

[0049] The cache acquisition module is used to calculate the number of caches occupied by the message to be sent based on the mapping relationship, combined with the load length and the DMA single cache unit space, and to accumulate the number of caches occupied to obtain the total number of message caches required by the message to be sent within a scheduling cycle; to acquire the total cache space of the board, and to calculate the total cache number of the board by combining the total cache space with the DMA single cache unit space.

[0050] The balance factor calculation module calculates the ratio of the total number of caches on the board to the total number of message caches to obtain the balance factor.

[0051] The statistics module is used to calculate the cache number of each message to be sent based on the mapping relationship, combined with the balancing factor and the load length; calculate the cache space of the message to be sent by combining the cache number with the DMA single cache unit space; and accumulate the cache spaces to obtain the total cache space of the message to be sent.

[0052] A judgment and parameter adjustment module is added to determine whether the total cache space meets the preset conditions. If the total cache space does not meet the preset conditions, the load length of the message to be sent or the space of a single cache unit of the DMA is adjusted, and the process is repeated until the total cache space of the message to be sent meets the preset conditions.

[0053] On the other hand, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the periodic information cache space balancing and flow control method as described above.

[0054] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the periodic information cache space balancing and flow control method as described above.

[0055] On the other hand, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the periodic information cache space balancing and flow control method as described above.

[0056] This invention provides a method and system for balancing and controlling the periodic information cache space. The method establishes a mapping relationship between message identifiers and load lengths, combined with a DMA polling mechanism, to achieve orderly message delivery and precise management. By calculating the cache size occupied by each message, the total cache size, and the balancing factor, cache space is dynamically allocated based on the load length and balancing factor, ensuring that cache resources are rationally allocated according to message needs and avoiding resource waste or insufficiency caused by uneven cache space allocation. Simultaneously, by determining whether the total cache space meets preset conditions and dynamically adjusting the load length or cache unit space, cache utilization efficiency is further optimized. This ensures the adaptability of the cache requirements of all messages within a scheduling cycle to the total cache space of the board, improving the stability of periodic information transmission and the efficiency of resource utilization. This addresses issues such as DMA congestion, scheduling failures, or insufficient bandwidth during communication. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of the periodic information cache space balancing and flow control method provided in an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of the data storage process for messages to be sent, provided in an embodiment of the present invention.

[0060] Figure 3 This is a flowchart of the periodic message cache space balancing processing provided in an embodiment of the present invention;

[0061] Figure 4 This is a schematic diagram of the periodic information cache space balancing and flow control system structure provided in an embodiment of the present invention;

[0062] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0064] Figure 1 This is a flowchart illustrating the periodic information cache space balancing and flow control method provided in this embodiment of the invention.

[0065] like Figure 1 As shown, the periodic information cache space balancing and flow control method provided in this embodiment of the invention mainly includes the following steps:

[0066] 101. Determine the total number of messages to be sent, message identifiers, and payload lengths; determine the space of a single cache unit in DMA (Direct Memory Access); establish a mapping relationship between message identifiers and payload lengths; and use the DMA polling method to send the messages to be sent sequentially according to the polling mechanism.

[0067] The total number of messages to be sent can be determined by using a preset counter or by querying the message queue length. The message identifier can be a unique number or tag to identify each message, ensuring accurate identification and differentiation of different messages during transmission. The payload length is determined based on the actual content of the messages to be sent, reflecting the size of the data carried by the messages.

[0068] The space of a single DMA cache unit needs to be set reasonably according to the system's hardware configuration and performance requirements, so as to ensure that it can accommodate a certain amount of message load while avoiding space waste.

[0069] Establishing a mapping relationship between message identifiers and payload lengths is to enable the message to be quickly and accurately located based on the message identifier during message transmission and reception, thereby correctly parsing and processing the message.

[0070] By employing a DMA polling delivery method, messages are sequentially delivered according to a polling mechanism, ensuring that every message has a chance to be sent and avoiding delays or loss of some messages due to long waiting times. By establishing a mapping relationship between identifiers and payloads, precise message indexing and management are achieved, preventing message confusion. The DMA polling delivery mechanism guarantees the orderly delivery of messages, reduces concurrency conflicts, and provides a processing order basis for subsequent cache space calculations.

[0071] In addition, a mapping relationship is established between message identifiers and payload lengths, specifically including:

[0072] The message identifier is translated into a RAM (Random Access Memory) address, and the message identifier and the read / write pointer of the message to be sent are stored in the RAM address.

[0073] If different message identifiers result in the same RAM address after conversion, then increment the RAM address calculated later.

[0074] When a message needs to be read, the corresponding RAM address is calculated based on the message identifier, and the message identifier stored in the RAM address is matched with the identifier of the message to be read. If the match is found, the message data is read based on the read / write pointer.

[0075] When establishing the mapping relationship between message identifiers and payload lengths, a preset algorithm, such as a hash algorithm, is used to convert the identifier of each message to be sent into a corresponding RAM address. Then, the message identifier and its corresponding read / write pointer are written into the RAM address to complete the basic mapping storage. If different message identifiers result in the same RAM address after conversion, it indicates that an address conflict has occurred. In this case, the conflict address calculated later is incremented by one to generate a new unique RAM address and store the corresponding information, thereby avoiding mapping confusion caused by address duplication.

[0076] When a message needs to be read, the corresponding RAM address is first calculated using the same algorithm based on the identifier of the message to be read. Then, the message identifier stored in the RAM address is retrieved and compared with the identifier of the message to be read. If the match is successful, the message data is located and read based on the read / write pointer stored in the RAM address, ensuring the accuracy and efficiency of message reading.

[0077] In some embodiments, the periodic information cache space balancing and flow control method provided in this application further includes:

[0078] For each message to be sent, allocate multiple data blocks of the same size;

[0079] Store the DDR (Double Data Rate) address and number of data blocks of the message to be sent into RAM.

[0080] In the process of cache management for messages to be sent with different message identifiers, multiple data blocks of uniform size are first allocated in DDR for each message to be sent with a unique identifier. The storage space of the data blocks must meet the storage requirements of the maximum load length of the message to be sent. The uniform size design simplifies the management logic of cache allocation and release. Subsequently, the DDR address corresponding to each message to be sent, that is, the physical storage start position of the data block in DDR and the number of data blocks allocated for the message to be sent, are stored in RAM. The DDR address is used to quickly locate the storage location of the message data, and the number of data blocks is used to record the cache resource quota of the message to be sent. By storing the DDR address and the number of data blocks in RAM, efficient query and update of message cache status can be achieved, providing fast index support for subsequent read and write operations based on message identifiers and improving the overall response speed of cache management.

[0081] For example, such as Figure 2 As shown, for each message to be sent with a different message identifier, multiple data blocks of the same size are allocated in DDR for storage. Each data block is 4K in size and can accommodate the maximum message length. The size of the data block for each message to be sent is represented by BMS (Block Memory Size).

[0082] A unique identifier for multiple messages to be sent, such as MSG0 ID, MSG1 ID, ..., MSGn ID, serves to distinguish different messages. The message identifier MSGx ID is converted to its corresponding RAM address (ram addr), providing an index for accessing message management information in RAM.

[0083] If a conflict occurs where different identifiers are mapped to the same address, a unique address will be generated by incrementing the address to ensure the uniqueness of the mapping.

[0084] The RAM is located in the middle and stores management information blocks that correspond one-to-one with each message to be sent, such as MSG0 INFO, MSG1 INFO, ..., MSGn INFO. Each INFO block contains the starting storage address of the message to be sent in DDR, read / write pointers, and the number of allocated cache blocks. The RAM is the bridge connecting the message identifier and physical storage.

[0085] Represented by MSG0 BMS and MSG1 BMS, these connect RAM and DDR. The function of MSG0 BMS and MSG1 BMS is to control the storage, retrieval, and cache allocation of message data to be sent in DDR based on the information in the RAINFO block, ensuring the linkage between management information and physical storage.

[0086] Located on the far right, DDR is the physical space for storing message data. It is divided into multiple fixed-size storage blocks, such as the 4k block, which represents the capacity of a single storage block. Each message to be sent is associated with several storage blocks in DDR through control logic. These storage blocks together constitute the cache space for the message to be sent, used to store the payload data.

[0087] Understandably, when multiple data frames of a message to be sent are buffered in DDR, to facilitate the management of information such as DDR addresses and frame counts, this information is stored in RAM. The mapping algorithm then maps the message identifier to the RAM address; specifically, the 67-bit message identifier is converted into a 10-bit RAM address. The message identifier and read / write pointers are then stored in RAM. This allows for fast message management for both receiving and sending. The mapping algorithm is a discrete polynomial computation process. Each generated RAM address occupies 1 bit for marking. If a given address is used in a calculation, it is incremented by 1. During reverse addressing, the RAM address is calculated based on the message identifier and matched against the message identifier in that address, thus achieving efficient DDR storage and retrieval operations.

[0088] Furthermore, before using the DMA polling method to sequentially send messages according to the polling mechanism, the following steps are also included:

[0089] Set a basic scheduling period and calculate the total load length of messages to be sent within the basic scheduling period;

[0090] The minimum processing speed is calculated by combining the basic scheduling cycle and the total load length.

[0091] The minimum processing speed is calculated by dividing the total load length by the basic scheduling cycle. Based on the system's real-time requirements for periodic message transmission, such as the communication latency requirements of the GLink bus and the time constraints for message processing, a basic scheduling cycle is set. This cycle defines the time range within which all messages to be sent must complete a full transmission.

[0092] Subsequently, the mapping relationship between message identifiers and load lengths is established. All messages planned to be sent within a basic scheduling cycle are traversed and filtered out. The load length of each message to be sent is extracted one by one. The total load length of messages to be sent within the basic scheduling cycle is obtained through cumulative calculation. This ensures that the statistical range is completely matched with the scheduling cycle and avoids data deviations due to message omissions or over-calculation.

[0093] Finally, the minimum processing speed is calculated by combining the determined basic scheduling period and the total load length. The minimum processing speed is obtained by dividing the total load length by the basic scheduling period. The minimum processing speed is the minimum rate standard to ensure that messages to be sent can be processed and sent on time within the basic scheduling period. This provides a basis for judging whether the processing capacity of the processor and DMA meets the requirements, and also lays the foundation for optimizing polling time and avoiding message backlog or resource idleness.

[0094] In some embodiments, the method of sequentially sending messages to be sent using a DMA polling approach further includes:

[0095] Determine the maximum cache space from the cache space of messages to be sent, and calculate the maximum time required to process the messages to be sent corresponding to the maximum cache space based on the minimum processing speed;

[0096] Set the maximum time to the minimum polling time;

[0097] Set the board balance query polling time to an integer multiple K of the minimum polling time, and set the minimum number of polling, the maximum and minimum board balance values, and satisfy the condition that the integer multiple K < (maximum board balance - minimum board balance) / (maximum cache space × minimum number of polling).

[0098] The polling time for board remaining capacity is determined based on integer multiples of K.

[0099] When using the DMA polling method to send messages sequentially according to the polling mechanism, it is necessary to first select the cache space with the largest value from all the cache spaces of the messages to be sent, and then combine it with the minimum processing speed. By dividing the maximum cache space by the minimum processing speed, the maximum time required to process the message to be sent corresponding to the maximum cache space is obtained. This ensures that the polling interval can cover the processing requirements of the most time-consuming message.

[0100] Subsequently, the maximum time is set as the minimum polling time, serving as the baseline value for the polling interval. This avoids excessive resource consumption due to overly frequent polling or message processing delays due to overly infrequent polling. Then, the board balance query polling time is set to an integer multiple K of the minimum polling time, while configuring the minimum number of polling iterations. This ensures sufficient monitoring frequency, maximum and minimum board balance values ​​within the balance fluctuation range, and strictly satisfies the constraint K < (maximum board balance - minimum board balance) / (maximum cache space × minimum number of polling iterations). This constraint quantifies the relationship between the board balance fluctuation range, message cache requirements, and the number of polling iterations, ensuring that changes in balance can be captured promptly through K polling iterations as the balance decreases from its maximum to its minimum. Finally, based on the determined integer multiple K and the minimum polling time, the minimum polling time × K is used to obtain the board balance query polling time. This achieves a match between the polling frequency, message processing time, and board balance fluctuations, ensuring both timely balance monitoring and avoiding excessive querying that consumes system resources.

[0101] Furthermore, in some embodiments, the periodic information cache space balancing and flow control method further includes:

[0102] Determine the load length of each message in the pending messages and calculate the total load length of the pending messages;

[0103] Obtain the basic data processing rate;

[0104] Divide the total load length by the basic data processing rate to obtain the minimum processing time.

[0105] Multiply the minimum processing time by a preset time redundancy coefficient to generate a polling time slice.

[0106] The polling time slice is used for sleep waiting time in flow control operations. When generating the polling time slice, the load length of each message to be sent is extracted one by one based on the mapping relationship between the message identifier and the load length of the message to be sent. The total load length of all messages to be sent is obtained by accumulation calculation, thereby quantifying the total amount of data to be processed in a scheduling cycle.

[0107] Next, the basic data processing rate is obtained through a preset parameter file. The basic data processing rate is the baseline processing capability of the processor or DMA controller, usually measured in MB / s, reflecting the amount of data that can be processed per unit time.

[0108] After obtaining the basic data processing rate, divide the total load length by the basic data processing rate to obtain the minimum processing time theoretically required to process all messages to be sent. The minimum processing time is the shortest processing time without any redundancy, ensuring that the data can be processed within the cycle.

[0109] Finally, the minimum processing time is multiplied by a preset time redundancy coefficient to calculate the specific duration of the polling time slice. The polling time slice serves as the timing standard for sleep waiting during flow control operations. It ensures that the sleep duration is sufficient to cover data processing needs while avoiding frequent wake-ups that waste resources due to excessively short durations or delayed flow control responses due to excessively long durations, thus guaranteeing the efficient and stable operation of the flow control mechanism. The time redundancy coefficient is set according to the system's tolerance for latency, typically between 1.2 and 2.0, to reserve buffer time for handling sudden delays and data fluctuations.

[0110] 102. Based on the mapping relationship, combined with the load length and the space of a single DMA cache unit, calculate the number of caches occupied by the messages to be sent, and sum up the number of caches occupied to obtain the total number of message caches required for messages to be sent within a scheduling cycle.

[0111] Specifically, based on the established mapping relationship between message identifiers and payload lengths, the payload length of each message to be sent is obtained by traversing each message in the mapping relationship. For each message to be sent, the payload length of the message to be sent is calculated with the space of a single DMA cache unit. If the payload length is divisible by the space of a single DMA cache unit, the calculated quotient is the number of cache units occupied by the message to be sent. If there is a remainder, the quotient is incremented by 1 to obtain the number of cache units occupied, ensuring that the payload can be stored completely.

[0112] After calculating the cache usage of each message to be sent, the cache usage of all messages to be sent is accumulated sequentially using an accumulator. Finally, the total cache usage of all messages to be sent within a scheduling cycle is obtained. This quantifies the total cache resource demand of messages within the entire cycle, providing basic data for subsequent matching with the actual cache capacity of the board and the calculation of the balancing factor.

[0113] 103. Obtain the total cache space of the board, and calculate the total number of caches on the board by combining the total cache space with the space of a single cache unit in DMA.

[0114] The total cache space of the board can be obtained through the board's hardware configuration interface, such as the PCIe configuration register or the onboard management chip communication interface. The total cache space parameter is in MB and represents the total storage capacity of the board that can be used to cache message data.

[0115] Subsequently, the total cache space of the board is divided by the space of a single cache unit in the DMA, and the quotient is the total cache number of the board. The total cache number of the board indicates how many independent cache units, each the same size as a single cache unit in the DMA, can be divided into the total cache space of the board. By calculating the total cache number of the board, the total storage resources of the board are quantified into the number of cache units of the same dimension as the number of cache units occupied. This provides a unified measurement benchmark for the subsequent calculation of the balance factor based on the actual cache capacity of the board and the total message demand, ensuring the accuracy of resource matching and allocation.

[0116] 104. Calculate the ratio of the total number of caches on the board to the total number of message caches to obtain the balance factor.

[0117] The balancing factor is calculated by dividing the total cache count of the board by the total cache count of messages and dividing the total cache count of the messages by the total cache count of the board. The balancing factor quantifies the matching ratio between the actual cache capacity of the board and the total cache demand of the messages: if the factor is greater than 1, it indicates that the board's cache resources are sufficient, and more cache can be allocated proportionally to the messages to be sent; if the factor is less than 1, it indicates that resources are scarce, and the balancing factor is used to limit the cache allocation of individual messages to avoid the total demand exceeding the board's capacity. By calculating the balancing factor, a proportional basis is provided for dynamically allocating cache counts for each message to be sent, ensuring a balanced distribution of cache resources among all messages, meeting the basic storage needs of each message without exceeding the actual carrying capacity of the board.

[0118] 105. Based on the mapping relationship, for each message to be sent, calculate the number of cached messages to be sent by combining the balancing factor and the load length; combine the number of cached messages with the DMA single cache unit space to calculate the cache space of the message to be sent; and sum the cache spaces to obtain the total cache space of the message to be sent.

[0119] First, based on the mapping relationship between message identifiers and load lengths, the load length of each message to be sent is obtained by traversing each message in the mapping relationship. For each message, the load length is calculated by combining the load factor and the load length of the message to be sent. The theoretical cache requirement is obtained by multiplying the load length by the load factor. Then, the actual cache size required for the message to be sent is obtained by rounding up, taking into account the space of a single cache unit in the DMA, ensuring that the cache size can fully accommodate the load of the message to be sent. Next, the cache size of each message to be sent is multiplied by the space of a single cache unit in the DMA to obtain the actual cache space occupied by the message to be sent.

[0120] Finally, the cache space of all messages to be sent is accumulated sequentially using an accumulator to obtain the total cache space of all messages to be sent within a scheduling cycle. A load balancing factor is used to proportionally allocate cache resources among the messages, ensuring both the storage integrity of individual messages and, through the statistics of the total cache space, ensuring the matching of cache space allocation with system constraints.

[0121] 106. Determine whether the total cache space meets the preset conditions. If the total cache space does not meet the preset conditions, adjust the load length of the message to be sent or adjust the space of a single cache unit of DMA, and repeat the process until the total cache space of the message to be sent meets the preset conditions.

[0122] The process involves comparing the total cache space of messages to be sent with preset conditions to determine if it is within a reasonable range. These preset conditions are based on the total cache space of the board; for example, the total cache space must not exceed 90% of the board's total cache space to retain redundancy, or it must not be lower than a certain minimum threshold to avoid resource waste.

[0123] If the total cache space does not meet the preset conditions and exceeds the upper limit of the total cache space of the board, the adjustment mechanism will be activated. On the one hand, the load length of some messages to be sent will be adjusted by message splitting or compression, such as splitting long messages into multiple short messages or compressing non-critical data to reduce the load. On the other hand, the space of a single cache unit of DMA can be adjusted by hardware configuration tools, such as increasing the granularity of a single cache unit of DMA to reduce the number of caches required for a single message to be sent.

[0124] After the adjustment is completed, steps 102 to 105 are executed again, and the results are compared with the preset conditions again. This process is repeated until the total cache space falls within the preset condition range, ultimately ensuring that the cache requirements of the messages to be sent are matched with the actual cache capacity of the board. This avoids data loss caused by cache overflow and prevents waste caused by idle resources, thus ensuring the rationality and stability of the system cache space allocation.

[0125] After determining whether the total cache space meets the preset conditions, the process also includes:

[0126] Set the minimum and maximum percentage of remaining cache space on the board;

[0127] Calculate the minimum and maximum cache space based on the minimum and maximum percentages of the board's cache remaining capacity and the total number of messages cached.

[0128] Get the number of free cache spaces for messages to be sent;

[0129] If the number of free cache spaces is less than or equal to the minimum number of cache spaces, then sleep and wait until the polling time slice ends;

[0130] If the minimum cache size is greater than the number of free cache spaces and the number of free cache spaces is less than or equal to the maximum cache size, then after sending the data to be sent, the system will sleep and wait until the polling time slice ends.

[0131] If the number of free cache spaces is greater than the maximum number of cache spaces, data will continue to be sent and the remaining cache space of the board will be obtained until the number of free cache spaces falls between the minimum number of cache spaces and the maximum number of cache spaces.

[0132] Based on the carrying capacity of the board's cache resources and the system stability requirements, a minimum and a maximum percentage of the board's cache remaining capacity are set. The minimum percentage of the board's cache remaining capacity is the threshold for determining insufficient cache, and the maximum percentage of the cache remaining capacity is the threshold for determining sufficient cache, thereby dividing different control ranges for cache remaining capacity.

[0133] Next, based on the minimum and maximum percentages of remaining board cache space and the total number of message caches, the minimum and maximum number of cache spaces are calculated by multiplication, respectively, transforming the abstract percentages into the specific number of cache units, which serves as the quantitative benchmark for flow control judgment.

[0134] Subsequently, the number of currently free cache spaces for messages to be sent is obtained in real time through the board status monitoring interface, reflecting the current availability of cache resources; then, differentiated operations are performed based on the comparison results of the number of free cache spaces with the minimum and maximum number of cache spaces.

[0135] If the number of free cache spaces is less than or equal to the minimum number of cache spaces, it indicates that cache resources are scarce. The process needs to be controlled to sleep and wait until the preset polling time slice ends to avoid continuing to send data and causing cache overflow.

[0136] If the number of free cache spaces is between the minimum and maximum number of cache spaces, it indicates that the resources are in a balanced state. Data to be processed can be sent first, and after completion, the cache will sleep until the polling time slice ends, thus maintaining dynamic cache balance.

[0137] If the number of free cache spaces is greater than the number of maximum cache spaces, it means that resources are sufficient. Data needs to be continuously sent and the remaining cache space of the board needs to be refreshed in real time until the number of free cache spaces falls between the minimum and maximum cache spaces. Then, the flow control logic of the corresponding range is switched to achieve efficient utilization of cache resources and dual guarantee of system stability.

[0138] For example, such as Figure 3 As shown, the algorithm flow for balancing the cache space of periodic messages is as follows:

[0139] The number of messages to be sent is set to n, the message payload data length is Ln (in bytes), and the DMA single cache unit space Dm is 4KB, which is equivalent to Dm = 4 / 1024MB.

[0140] Set the maximum padding load of the message, which is the amount of data sent to the DMA each time, to Fn, in bytes.

[0141] The number of packets to be split is calculated as Cn, and the calculation formula is Cn=Ln / Fn, where Cn is the amount of buffer space required for the message.

[0142] The total amount of cache space required for n messages, C, is calculated using the formula: C = C1 + C2 + ... + Cn.

[0143] The total cache space of the board is obtained as A, in MB, and the total cache size is Num, calculated using the formula Num = A / Dm. The initial value of the load balancing factor is B, calculated using the formula: B = Num / C.

[0144] The cache size for each message is Sn, calculated using the formula Sn = Cn * B. The cache space occupied by each message is Mn, calculated using the formula Mn = Sn * Dm, with the unit being MB.

[0145] The total cache space A1 for all messages is calculated using the formula: A1 = M1 + M2 + ... + Mn, with the unit being MB;

[0146] When A1 is less than A, the equilibrium factor B satisfies the condition; otherwise, the equilibrium factor B = B + 1, and the process is repeated until A1 is less than A.

[0147] In some embodiments, if the total cache space does not meet a preset condition, the method further includes:

[0148] The fluctuation range of the remaining buffer on the board after data is distributed within the statistical scheduling period;

[0149] If the fluctuation amplitude of multiple consecutive scheduling cycles exceeds the preset fluctuation threshold, the equilibrium factor is recalculated to obtain the corrected equilibrium factor.

[0150] The number of cached messages to be sent is adjusted based on the corrected balance factor.

[0151] Specifically, if the total cache space does not meet the preset conditions, further dynamic correction of cache balancing needs to be performed. First, in each scheduling cycle, after the data is distributed, the current cache balance value of the board is recorded and compared with the cache balance of adjacent cycles to calculate the fluctuation range in each cycle. The fluctuation range is quantified by the difference or standard deviation between the maximum and minimum values ​​of the remaining balance, and the fluctuation range reflects the stability of the cache resources.

[0152] Next, a preset fluctuation threshold can be set based on the system's requirements for cache stability. If the fluctuation amplitude exceeds the threshold for multiple consecutive scheduling cycles, it indicates that the cache allocation caused by the current balance factor is at risk of imbalance, and the balance factor correction mechanism needs to be triggered. The balance factor correction mechanism can re-execute the calculation logic of step 104 based on the latest total number of board caches and total number of message caches to obtain the corrected balance factor. Finally, based on the corrected balance factor, the operation of calculating the cache count of a single message in step 105, combining the balance factor and load length, is re-executed to adjust the cache allocation ratio of each message to be sent, making the allocation of cache resources among messages more closely match the actual fluctuation situation, thereby reducing the fluctuation of cache remaining space in subsequent cycles and improving the stability and balance of the system's cache space.

[0153] In some embodiments, the periodic information cache space balancing and flow control method provided in this application further includes:

[0154] The load percentage of the messages to be sent is obtained by the ratio of the load length of the messages to be sent to the total load length of the messages to be sent.

[0155] Multiply the load percentage by the total number of caches on the board to obtain the initial number of caches for messages to be sent.

[0156] If the cache space corresponding to the initial cache size is less than the maximum load length of the message to be sent, then the cache size of the message to be sent is adjusted according to the minimum cache size required for the maximum load length.

[0157] In the process of evenly distributing cache resources, the first step is to calculate the load percentage for each message to be sent. The ratio obtained by dividing the load length of the message to be sent by the total load length of all messages to be sent reflects the weight of the message to be sent in the overall data volume. Then, based on the load percentage, the initial cache number is multiplied by the total cache number of the board to obtain the initial cache number allocated to the messages to be sent, thus realizing the basic logic of allocating cache resources according to the data volume ratio.

[0158] Next, the validity of the initial cache count is verified, and the initial cache space corresponding to the initial cache count is calculated. That is, the initial cache space is the initial cache count × the space of a single DMA cache unit. The initial cache space is then compared with the maximum load length of the message to be sent. If the initial cache space is less than the maximum load length, it means that the initially allocated cache cannot accommodate the maximum possible load of the message to be sent. In this case, the minimum cache count required needs to be calculated based on the maximum load length. For example, the maximum load length is divided by the space of a single DMA cache unit. If there is a remainder, it is rounded up to obtain the minimum cache count. The minimum cache count is then used as the corrected cache count to ensure that the cache allocation for each message can reflect the overall balance and meet its maximum storage requirements, avoiding message truncation or loss due to insufficient cache.

[0159] Based on the same general inventive concept, this invention also protects a periodic information cache space balancing and flow control system. The periodic information cache space balancing and flow control system provided by this invention will be described below. The periodic information cache space balancing and flow control system described below can be referred to in correspondence with the periodic information cache space balancing and flow control method described above.

[0160] Figure 4 As shown in the figure, this application provides a periodic information cache space balancing and flow control system, including:

[0161] The message parameter and mapping relationship establishment module 410 is used to determine the total number of messages to be sent, message identifiers and load lengths, determine the space of a single DMA cache unit, and establish a mapping relationship between message identifiers and load lengths.

[0162] The DMA polling delivery module 420 is used to sequentially deliver messages to be delivered according to the polling mechanism using the DMA polling delivery method.

[0163] The cache acquisition module 430 is used to calculate the number of caches occupied by the messages to be sent based on the mapping relationship, combined with the load length and the space of a single cache unit of DMA, and to accumulate the number of caches occupied to obtain the total number of message caches required for the messages to be sent within a scheduling cycle; to obtain the total cache space of the board, and to calculate the total number of caches of the board by combining the total cache space with the space of a single cache unit of DMA.

[0164] The balance factor calculation module 440 is used to calculate the ratio of the total number of caches on the board to the total number of message caches to obtain the balance factor.

[0165] The statistics module 450 is used to calculate the number of cached messages to be sent for each message to be sent based on the mapping relationship, combined with the balancing factor and the load length; to calculate the cache space of the message to be sent by combining the number of cached messages with the space of a single cache unit in DMA; and to accumulate the cache spaces to obtain the total cache space of the message to be sent.

[0166] Add a judgment and parameter adjustment module 460 to determine whether the total cache space meets the preset conditions. If the total cache space does not meet the preset conditions, adjust the load length of the message to be sent or adjust the space of a single cache unit of DMA, and repeat the process until the total cache space of the message to be sent meets the preset conditions.

[0167] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention.

[0168] like Figure 5As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540. The processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions from the memory 530 to execute periodic information cache space balancing and flow control methods.

[0169] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0170] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the periodic information cache space balancing and flow control methods provided by the above methods.

[0171] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the periodic information cache space balancing and flow control methods provided by the above methods.

[0172] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0173] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for periodic information cache space balancing and flow control, characterized in that, The method comprises the following steps: determining the total number of messages to be sent, the message identifier and the load length, determining the DMA single cache unit space, establishing the mapping relationship between the message identifier and the load length, and sequentially sending the messages to be sent in the polling mechanism by using the DMA polling sending mode; based on the mapping relationship, combining the load length and the DMA single cache unit space, calculating the occupied cache number of the messages to be sent, and accumulating the occupied cache number to obtain the total cache number required by the messages to be sent in a scheduling period; obtaining the total cache space of the board card, combining the total cache space and the DMA single cache unit space, and calculating the total cache number of the board card; calculating the ratio of the total cache number of the board card and the total cache number of the messages to obtain an equalization factor; based on the mapping relationship, combining the equalization factor and the load length, and calculating the cache number of each message to be sent; combining the cache number and the DMA single cache unit space, and calculating the cache space of the messages to be sent; and accumulating the cache space to obtain the total cache space of the messages to be sent; determining whether the total cache space meets the preset condition, if the total cache space does not meet the preset condition, adjusting the load length of the messages to be sent or adjusting the DMA single cache unit space, and repeating the execution until the total cache space of the messages to be sent meets the preset condition.

2. The method of claim 1, wherein, The method for establishing the mapping relationship between the message identifier and the load length comprises: convert the message identifier into a RAM address, and store the message identifier and the read-write pointer of the message to be sent to the RAM address; if different message identifiers are converted to obtain the same RAM address, perform an add-one operation on the RAM address calculated later; when the message needs to be read, calculate the corresponding RAM address according to the message identifier, and match the message identifier stored in the RAM address with the identifier of the message to be read, and if the match is consistent, read the message data based on the read-write pointer.

3. The method of claim 1, wherein, The method further comprises: opening multiple data blocks of the same size for each message to be sent; storing the DDR address of the message to be sent and the number of data blocks in the RAM.

4. The method of claim 1, wherein, Before sequentially sending the messages to be sent by using the DMA polling sending mode in the polling mechanism, the method further comprises: setting a basic scheduling period, and counting the total load length of the messages to be sent in the basic scheduling period; combining the basic scheduling period and the total load length to calculate the minimum processing speed, which is the total load length divided by the basic scheduling period.

5. The method of claim 4, wherein, The method for sequentially sending the messages to be sent by using the DMA polling sending mode in the polling mechanism further comprises: determining the maximum cache space from the cache space of the messages to be sent, combining the minimum processing speed to calculate the maximum time required to process the messages to be sent corresponding to the maximum cache space; setting the maximum time as the minimum polling time; The board card margin query polling time is set as an integer multiple K of the minimum polling time, and the minimum polling times, the maximum and minimum board card margin values are set, and the integer multiple K satisfies K < (the maximum board card margin value-the minimum board card margin value) / (the maximum cache space*the minimum polling times); The board card margin query polling time is determined based on the integer multiple K.

6. The method of claim 1, wherein, Further comprising: Determine the load length of each message in the to-be-delivered message, and count the total load length of the to-be-delivered message; Obtain the basic data processing rate; Divide the total load length by the basic data processing rate to obtain the minimum processing time; Multiply the minimum processing time by a preset time redundancy coefficient to generate a polling time slice, which is used for sleep waiting timing in flow control operation.

7. The method of claim 6, wherein, After judging whether the total cache space meets the preset condition, further comprising: Set the minimum and maximum board card cache margin percentage values; Calculate the minimum and maximum cache space numbers according to the minimum and maximum board card cache margin percentage values and the total number of messages; Obtain the idle cache space number of the to-be-delivered message; If the idle cache space number is less than or equal to the minimum cache space number, sleep and wait until the polling time slice ends; If the minimum cache space number is greater than the idle cache space number and the idle cache space number is less than or equal to the maximum cache space number, deliver the to-be-delivered message and then sleep and wait until the polling time slice ends; If the idle cache space number is greater than the maximum cache space number, continuously deliver data and obtain the board card cache margin until the idle cache space number falls between the minimum and maximum cache space numbers.

8. The method of claim 1, wherein, Further comprising: Obtain the load proportion of the to-be-delivered message according to the ratio of the load length of the to-be-delivered message to the total load length of the to-be-delivered message; Multiply the total board card cache number by the load proportion to obtain the initial cache number of the to-be-delivered message; If the cache space corresponding to the initial cache number is less than the maximum load length of the to-be-delivered message, correct the cache number of the to-be-delivered message according to the minimum cache number required by the maximum load length.

9. The method of claim 1, wherein, If the total cache space does not meet the preset condition, further comprising: Count the fluctuation amplitude of the board card cache margin after delivering data within the scheduling period; If the fluctuation amplitudes of a plurality of consecutive scheduling periods exceed a preset fluctuation threshold, recalculate the balancing factor to obtain a corrected balancing factor; Adjust the cache number of the to-be-delivered message based on the corrected balancing factor.

10. A periodic information buffer space equalization and flow control system, characterized by, Comprising: A message parameter and mapping relationship establishing module for determining the total number of to-be-delivered messages, message identifiers and load lengths, determining a DMA single cache unit space, and establishing a mapping relationship between the message identifiers and the load lengths; A DMA polling delivery module for delivering the to-be-delivered messages in turn according to a polling mechanism by using a DMA polling delivery mode. The cache obtaining module is configured to calculate the occupied cache number of the to-be-delivered message based on the mapping relationship, in combination with the load length and the DMA single cache unit space, and accumulate the occupied cache number to obtain the total cache number required by the to-be-delivered message in a scheduling period. The total cache space of the board card is obtained, and the total cache number of the board card is calculated in combination with the total cache space and the DMA single cache unit space. The balance factor calculating module is configured to calculate a ratio of the total cache number of the board card and the total cache number of the message to obtain a balance factor. The statistical module is configured to calculate the cache number of each to-be-delivered message in combination with the balance factor and the load length based on the mapping relationship. The cache space of the to-be-delivered message is calculated in combination with the cache number and the DMA single cache unit space. The cache space is accumulated to obtain the total cache space of the to-be-delivered message. The adding judgment and parameter adjusting module is configured to judge whether the total cache space meets a preset condition, and if the total cache space does not meet the preset condition, adjust the load length of the to-be-delivered message or adjust the DMA single cache unit space, and then repeat the execution until the total cache space of the to-be-delivered message meets the preset condition.

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