Method, device and system for chip leakage current power consumption analysis

Abstract

The invention discloses a method, a device and a system for chip leakage current power consumption analysis, and relates to the technical field of chip development. The method comprises the following steps: configuring a chip database for storing chip design data including an input file for chip power consumption analysis; collecting chip leakage current power consumption analysis demand information, wherein the information comprises a chip item to which a target chip module to be analyzed belongs and target process corner scene information; after a total path of data storage is obtained from the database according to requirements, an input file related to chip power consumption analysis of the target chip module is extracted and stored in a specified path; a power consumption analysis tool is triggered and called to read the file from the specified path and then carry out power consumption analysis, and leakage current power consumption data is extracted based on a power consumption analysis result and then a leakage current power consumption analysis report is generated. Manual operation in chip leakage current power consumption analysis is reduced, the chip power consumption analysis efficiency is improved, and the chip development period is shortened.

Description

Technical Field

[0001] This invention relates to the field of chip development technology, and in particular to a method, apparatus and system for analyzing chip leakage current and power consumption. Background Technology

[0002] As integrated circuits become increasingly larger and manufacturing processes shrink, chip power consumption becomes a more prominent issue, with leakage power accounting for a significantly higher proportion, sometimes even exceeding dynamic power consumption. Leakage power is the electrical consumption caused by leakage current, which leads to energy loss and heat generation, thus affecting chip stability and power management.

[0003] The Liberty library, a common toolkit for electronic design automation (EDA), is used to describe the timing and power consumption characteristics of digital integrated circuits (ICs). During chip design, engineers can use the models and data provided in the Liberty library to evaluate and optimize key performance indicators such as chip performance, power consumption, and area. Regarding leakage current, it is generally affected by three factors: process, voltage, and temperature, collectively known as the PVT parameter. The process is divided into different process corners, such as typical N-type P (TT), fast N-fast P (FF), slow N-slow P (SS), fast N-slow P (FS), and slow N-fast P (SF), where N represents NMOS and P represents PMOS. The voltage threshold (VT) types typically include low voltage threshold (LVT), standard voltage threshold (SVT), and high voltage threshold (HVT). Among them, LVT has fast switching speed and low delay, but large leakage current, and is often used in critical paths and units that require high performance; SVT has a more balanced performance and leakage current, and is often used as the default unit; HVT has low leakage current and low static power consumption, but slow speed, and is often used in non-critical paths and low power consumption scenarios.

[0004] In the early stages of every chip design project, it is necessary to analyze and optimize the leakage current of the chip as it varies with process corners. This reduces the risk of later modifications and improves chip development efficiency and success rate. Chips using different process technologies have different leakage current parameters. Generally speaking, the more advanced the process, the smaller the leakage; for example, the leakage of a 12nm process is smaller than that of a 22nm process. Furthermore, a single process technology can contain multiple different process corners (such as the aforementioned process corner types), and different corners can contain different voltages and temperatures. Moreover, library files under the same corner can be configured with different threshold voltage process options (such as the aforementioned voltage threshold types).

[0005] In traditional on-chip design, engineers use the Liberty library for power consumption design. However, because the Liberty library provides power consumption values ​​under given conditions (or scenarios), its data volume is limited and cannot fully reflect the overall picture of delay and leakage current under different process corners. If engineers need parameters under other conditions, they need to perform simulation tests based on the chip project's place and route netlist (PRnetlist, which contains all standard cells, their connections, and physical information generated by the place and route tools, such as parasitic parameters), and collect leakage current data of the place and route netlist under specific conditions at different process corners. The above tests are automatically completed by professional power analysis tools—such as the power analysis tool PTPX (Prime Time Power Extension, an industry-standard power analysis tool). PTPX input data typically includes a chip netlist, timing library files (.lib format), SPEF files (SPEF stands for Standard Parasitic Exchange Format, a file format defined by the IEEE 1481 standard, mainly used to store and exchange wiring parasitic parameters, such as resistance (R), capacitance (C), coupling capacitance (Cc), etc.), and chip post-simulation waveform files (used to determine circuit states and chip operating modes). PTPX output data typically includes Total Power, Dynamic Power, Static Power (i.e., leakage current power consumption), module-level power distribution, and power consumption peaks and troughs. If engineers are interested in the leakage current power consumption of a specific chip module under one or more specific conditions, they need to extract the Static Power of the relevant chip module under various conditions from the aforementioned output data for analysis.

[0006] Since different chip projects typically contain different chip modules, when using PTPX to analyze the power consumption data of a chip project's PRnetlist under specific conditions (or scenarios) of different process corners, engineers need to organize the input and output data according to the chip module to be analyzed. This requires manually searching and organizing the corresponding input and output data for each process corner scenario. For example, to analyze the power consumption of a specific chip module in a TSMC22 process chip under specific scenarios such as FF0P99V125 / 0 / -40C (representing fast process corner FF, 0.99V voltage, high temperature 125°C, typical temperature 0°C, low temperature -40°C), TT0P9V25 / 85C (representing typical process corner TT, 0.9V voltage, low temperature 25°C, high temperature 85°C), and SS0P81V125 / 0 / -40C (representing slow process corner SS, 0.81V voltage, high temperature 125°C, typical temperature 0°C, low temperature -40°C), engineers need to collect the PR netlist of the chip module and then use the PTPX tool to perform data processing and simulation tests for the above process corner scenarios. The testing and data processing processes require a lot of manual operation, resulting in a significant time commitment for collecting leakage current and power consumption data for each project, which is costly and extends the chip design cycle. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method, apparatus, and system for chip leakage current and power consumption analysis. The chip leakage current and power consumption analysis scheme provided by this invention effectively reduces manual operations in chip leakage current and power consumption analysis, improves chip power consumption analysis efficiency, and helps shorten the chip development cycle.

[0008] To achieve the above objectives, the present invention provides the following technical solution: A method for analyzing chip leakage current and power consumption includes the following steps: Configure a chip database, which stores chip design data for chip projects. The chip design data for a chip project is stored in a single master path. The chip design data includes input files for chip power consumption analysis, and the input files conform to preset data format requirements. Collect user-initiated chip leakage current and power consumption analysis request information, which includes the chip project to which the target chip module to be analyzed belongs and the target process corner scenario information; Based on the required information, after obtaining the total data storage path of the chip project from the chip database, the input file related to the chip power consumption analysis of the target chip module is extracted from the storage area corresponding to the total path, and the input file is stored in the specified path. Based on user triggers, the pre-configured power analysis tool is invoked to read all files from the aforementioned specified path and use them as input files for power analysis; and based on the power analysis results, the leakage current power consumption data of the target module under the aforementioned target process corner scenario is extracted and a leakage current power consumption analysis report is generated according to a preset data structure.

[0009] Furthermore, the input files include netlist files for each chip module in the chip project, standard parasitic parameter exchange format SPEF files, timing library (lib) file sets, and post-simulation waveform files. The lib file sets cover various pre-configured specific scenarios for different process corners. At this point, based on the chip project to which the target chip module to be analyzed belongs, the netlist file, spef file, and post-simulation waveform file of the target chip module are extracted from the aforementioned chip database; and the lib files corresponding to each scenario are extracted based on the target process corner scenario information.

[0010] Furthermore, the waveform file is an fsdb file; The power consumption analysis tool is the PTPX tool. The output data of the PTPX tool includes the total power consumption, dynamic power consumption and leakage current power consumption of the chip module. The leakage current power consumption is extracted from the aforementioned output data to generate a leakage current power consumption analysis report.

[0011] Furthermore, the data structure of the leakage current power consumption analysis report includes at least the following fields: module name field, unit type field, threshold voltage field, number of units field, unit ratio field, leakage current power consumption value field, and leakage current power consumption percentage field. Output the target module name and / or number under the module name field; The process angle type, voltage, and temperature configured for the process angle scenario are output under the cell type field. The threshold voltage type configured for the process corner scenario is output under the threshold voltage field, including low threshold voltage LVT, standard threshold voltage SVT, and high threshold voltage HVT; The number of units designed under the process corner scenario is output under the unit quantity field; The unit ratio designed under the process angle scenario is output under the unit ratio field; The leakage current power consumption value for the process corner scenario is output under the leakage current power consumption value field. The leakage current power consumption ratio field outputs the proportion of leakage current power consumption to total power consumption in the process corner scenario.

[0012] Furthermore, it also includes a user graphical interface, which includes a design data acquisition component and a design data publishing component. The design data acquisition component is used for designers to input or import chip design data; when inputting or importing chip design data, the corresponding chip project name and / or number should also be entered. The design data publishing component is used by designers to publish data after inputting or importing data; when the publishing component corresponding to the data is triggered, the data is published to a preset online platform; in the online platform, each data is classified and stored according to its chip project.

[0013] Furthermore, the user graphical interface also includes a power consumption analysis setting component, which allows users to set the name and / or number of the chip project to be analyzed, the target chip module information, and the process corner type, voltage value, temperature value, and threshold voltage options for the target process corner scenario.

[0014] Furthermore, the user graphical interface also includes a file path reading component and a leakage current power consumption analysis trigger component. When the file path reading component is triggered, it can read files under the specified path. When the target process corner scene information to be analyzed is multiple process corner scenes, the specified path includes multiple sub-paths. At this time, for different process corner scenes, according to the sorting of the sub-paths under the specified path, files are read from multiple sub-paths of the specified path for testing in sequence until the files under all sub-paths are tested. Once the leakage current power consumption analysis trigger component is triggered, it can call a pre-configured power consumption analysis tool to perform simulation testing on the currently read file for power consumption analysis.

[0015] The present invention also provides a chip leakage current and power consumption analysis device, the device comprising the following structure: The chip database configuration unit is used to configure the chip database, which stores the chip design data of a chip project. The chip design data of a chip project is stored in a single master path. The chip design data includes input files for chip power consumption analysis, and the input files conform to preset data format requirements. The power consumption analysis setting unit is used to collect the user's chip leakage current power consumption analysis requirements; it includes the chip project to which the target chip module to be analyzed belongs and the target process corner scenario information. The input file preparation unit is used to obtain the total data storage path of the chip project from the chip database according to the aforementioned requirement information, extract the input file related to the chip power consumption analysis of the target chip module from the storage area corresponding to the total path, and store the input file in the specified path. The leakage current analysis and processing unit is used to call the pre-configured power consumption analysis tool to read all files from the aforementioned specified path as input files for power consumption analysis based on the user's trigger; and, based on the power consumption analysis results, extract the leakage current power consumption data of the target module in the aforementioned target process corner scenario and generate a leakage current power consumption analysis report according to the preset data structure.

[0016] Furthermore, the input files include netlist files for each chip module in the chip project, standard parasitic parameter exchange format SPEF files, timing library (lib) file sets, and post-simulation waveform files. The lib file sets cover various pre-configured specific scenarios for different process corners. At this point, based on the chip project to which the target chip module to be analyzed belongs, the netlist file, spef file, and post-simulation waveform file of the target chip module are extracted from the aforementioned chip database; and the lib files corresponding to each scenario are extracted based on the target process corner scenario information.

[0017] The present invention also provides a chip power consumption analysis system, the system comprising, The aforementioned chip leakage current and power consumption analysis device; A visualization and report generation device is used to present the analysis results graphically based on the analysis report from the aforementioned leakage current power consumption analysis device.

[0018] Compared with the prior art, the present invention, by adopting the above technical solution, has the following advantages and positive effects: The chip leakage current power consumption analysis scheme provided by the present invention effectively reduces manual operation in chip leakage current power consumption analysis, improves chip power consumption analysis efficiency, and helps to shorten the chip development cycle. Attached Figure Description

[0019] Figure 1 A flowchart of a method for analyzing chip leakage current and power consumption provided in an embodiment of the present invention.

[0020] Figure 2 The power analysis tool provided in this embodiment of the invention reads an input file from a specified path to perform power analysis. This is an information transmission diagram.

[0021] Figure 3 This is a schematic diagram showing the arrangement of operation components in the GUI interface provided in an embodiment of the present invention.

[0022] Figure 4 This is an example diagram of the preferred data structure for the leakage current and power consumption analysis report of the vdu_sys module provided in an embodiment of the present invention. Detailed Implementation

[0023] The method, apparatus, and system for chip leakage current and power consumption analysis disclosed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated; they can be combined with each other to achieve better technical effects. In the accompanying drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0024] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes and to aid those skilled in the art in understanding and reading the invention. They are not intended to limit the conditions under which the invention can be implemented. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of the invention, should fall within the scope of the technical content disclosed in the invention. The scope of the preferred embodiments of the present invention includes other implementations, wherein functions may be performed not in the order stated or discussed, including substantially simultaneously or in reverse order, depending on the functions involved. This should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0025] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. Example

[0026] See Figure 1 As shown in this embodiment, a method for analyzing chip leakage current and power consumption is provided. The method includes the following steps: S100, Configure the chip database. The chip database stores chip design data for chip projects, with the chip design data for one chip project stored under a single master path; the chip design data includes input files for chip power consumption analysis, and the input files conform to preset data format requirements.

[0027] S200 collects user-initiated chip leakage current and power consumption analysis requests, which include the chip project to which the target chip module belongs and the target process corner scenario information.

[0028] S300: Based on the required information, after obtaining the total data storage path of the chip project from the chip database, extract the input file related to the chip power consumption analysis of the target chip module from the storage area corresponding to the total path, and store the input file in the specified path.

[0029] S400, triggered by the user, calls a pre-configured power analysis tool to read all files from the aforementioned specified path and uses them as input files for power analysis; and, based on the power analysis results, extracts the leakage current power consumption data of the target module under the aforementioned target process corner scenario and generates a leakage current power consumption analysis report according to a preset data structure.

[0030] In this embodiment, the input file may specifically include the netlist files of each chip module in the chip project, the standard parasitic parameter exchange format SFE file, the timing library .lib file set (or timing library file, which is a .lib format file set), and the post-simulation waveform file, see [link to documentation]. Figure 2 As shown.

[0031] The timing library file set includes multiple lib files, covering various pre-configured Corner scenarios for different process corners. Different process corner scenarios correspond to different lib files.

[0032] The simulated waveform file can be, for example, a waveform file in fsdb format.

[0033] At this point, based on the chip project to which the target chip module belongs, the netlist file, SFE file, and post-simulation waveform file (FSDB file) of the target chip module are first extracted from the aforementioned chip database. Then, based on one or more Corner scenes in the Corner scene information of the target process corner to be analyzed, the corresponding .lib files for each scene are extracted from the chip database. The extraction of these files can be specifically implemented using a Python script.

[0034] Preferably, when the target process corner scene information consists of multiple process corner scenes, there are multiple lib files. In this case, for different process corner scenes, multiple sub-paths can be set under the aforementioned specified path to store the lib files of different process corner scenes respectively.

[0035] The power consumption analysis tool is preferably PTPX (Prime Time Power Extension, an industry-standard power consumption analysis tool). In this embodiment, the input data of the PTPX tool includes at least the chip module netlist, timing library file (.lib format), spef file, and chip post-simulation waveform file. The waveform file is used to determine the circuit state and chip operating mode, and may also include other parameter files as needed. The output data of the PTPX includes at least Total Power, Dynamic Power, and Static Power (i.e., leakage current power consumption). This invention focuses on leakage current power consumption, therefore, leakage current power consumption needs to be extracted from the aforementioned output data to generate a leakage current power consumption analysis report.

[0036] In this embodiment, the data structure of the leakage current power consumption analysis report is configured to include at least the module name field, the unit type field, the threshold voltage field, the number of units field, the unit ratio field, the leakage current power consumption value field, and the leakage current power consumption percentage field.

[0037] Output the target module name and / or number under the module name field.

[0038] The process corner type, voltage, and temperature configured in the process corner scene are output under the cell type field.

[0039] The threshold voltage type configured in the process corner Corner scenario is output under the threshold voltage field, including low threshold voltage (LVT), standard threshold voltage (SVT), and high threshold voltage (HVT).

[0040] The cell quantity field outputs the number of cells designed in the Corner scenario with process angle.

[0041] The cell proportion (the proportion of a cell to the total number of cells) designed in the Corner scenario is output under the cell proportion field.

[0042] The leakage current power consumption value for the Corner scenario in the process corner is output under the leakage current power consumption value field.

[0043] The leakage current power consumption ratio field outputs the percentage of leakage current power consumption to total power consumption in the Corner scenario of the process corner.

[0044] In this embodiment, a graphical user interface (GUI) may also be included to facilitate user operation.

[0045] The user graphical interface preferably includes a design data acquisition component, a design data publishing component, a power consumption analysis setting component, a file path reading component, and a leakage current power consumption analysis triggering component.

[0046] The design data acquisition component is used for designers to input or import chip design data; when inputting or importing chip design data, the corresponding chip project name and / or number are also entered.

[0047] The design data publishing component is used by designers to publish data after inputting or importing data; when the publishing component corresponding to the data is triggered, the data is published to a preset online platform; in the online platform, each data is classified and stored according to its chip project.

[0048] The power consumption analysis setting component allows users to set the name and / or number of the chip project to be analyzed, the target chip module information, and the process corner type, voltage value, temperature value, and threshold voltage options for the target process corner scenario.

[0049] Once the file path reading component is triggered, it can read files under the specified path.

[0050] Once the leakage current power consumption analysis trigger component is triggered, it can call a pre-configured power consumption analysis tool to perform simulation testing on the currently read file for power consumption analysis.

[0051] See Figure 3 As shown, as a typical example, this example illustrates how to set the "open" button as a file path reading component and the "gen" button as a leakage current power consumption analysis trigger component in the GUI interface. When the user triggers (e.g., clicks) the "open" button, the specified path of the target chip module can be opened, and all files under that path can be obtained; then, the user can trigger the "gen" button to start leakage power consumption analysis of the target chip module and generate an analysis report with a preset data structure.

[0052] In this embodiment, when the target process corner scene information to be analyzed consists of multiple process corner scenes, the aforementioned specified path can include multiple subpaths—for example, setting up multiple subfolders under the aforementioned vdu_sys_leakage folder to store the lib files for different scenes respectively. As an example, for the process corner scenes ff0p99v125 / 0 / -40c, tt0p9v25 / 85c, and ss0p81v125 / 0 / -40c, each can have its own corresponding subfolder. These subfolders can be sorted by name within the folder. Based on the order of the subfolders (subpaths), during power consumption analysis, the lib file (along with the netlist file, SFE file, and post-simulation waveform file) is retrieved from the first subfolder for power consumption analysis. After the power consumption analysis for this process corner scenario is completed, the lib file (along with the netlist file, SFE file, and post-simulation waveform file) is retrieved from the second-ranked subfolder for power consumption analysis. After the power consumption analysis for this process corner scenario is completed, the lib file (along with the netlist file, SFE file, and post-simulation waveform file) is retrieved from the next-ranked subfolder for power consumption analysis. This process continues until all files under all subpaths have been tested.

[0053] The following is combined Figure 4 This embodiment will be described in detail.

[0054] First, based on the chip module vdu_sys in the chip project p001 that needs to be analyzed, which is configured by the user in the chip leakage current and power consumption analysis requirement information, and the Corner scenario information (multiple) that needs to be analyzed, relevant files are extracted from the chip database. Specifically, this may include the waveform file vdu_sys.fsdb of the target chip module vdu_sys, the netlist file vdu_sys_netlist.v of vdu_sys, the spef file vdu_sys.spef of vdu_sys, and multiple lib files that vdu_sys needs to be tested.

[0055] Specifically, for various Corner scenarios of the vdu_sys module that need to be analyzed according to user configuration, the extracted lib files include time library files corresponding to specific scenarios of various process corners. For example, for process corner scenarios of ff0p99v125 / 0 / -40c, tt0p9v25 / 85c, and ss0p81v125 / 0 / -40c, the corresponding ff0p99v125 / 0 / -40c lib files, tt0p9v25 / 85c lib files, and ss0p81v125 / 0 / -40c lib files are extracted from the chip database.

[0056] Then, store the above files in a specified path—for example, a local folder. The name of the folder is associated with the name / number of the chip module; for example, the folder name can be automatically configured as vdu_sys_leakage.

[0057] When a user triggers power consumption analysis, the PTPX tool can be invoked to read all files from the aforementioned folder `vdu_sys_leakage` and use them as input files for power consumption analysis, obtaining power consumption analysis results including various power consumption data. Subsequently, the power consumption analysis results need to be processed. After collecting the leakage power consumption data of the `vdu_sys` module under the aforementioned process corner scenarios, a leakage current power consumption analysis report is generated according to a preset data structure. See [link to relevant documentation]. Figure 4 As shown.

[0058] This is an example, not a limitation. Figure 4 The module name is represented as "Sys_name", the cell type as "Cell_type", the threshold voltage as "Pvt_corner", the number of cells as "Cell_num", the cell ratio as "Cell_num_ratio", the leakage current power consumption value as "Leakage_pwr", and the leakage current power consumption ratio as "Leakage pwr ratio".

[0059] The above leakage current and power consumption analysis report allows users to quickly and efficiently understand the leakage current and power consumption data of the target chip module vdu_sys under different process corners.

[0060] Another embodiment of the present invention provides a chip leakage current power consumption analysis device, the device including a chip database configuration unit, a power consumption analysis setting unit, an input file preparation unit, and a leakage current analysis processing unit.

[0061] The chip database configuration unit is used to configure the chip database, which stores chip design data for a chip project. The chip design data for one chip project is stored under a single master path. The chip design data includes input files for chip power consumption analysis, and these input files conform to preset data format requirements.

[0062] The power consumption analysis setting unit is used to collect the user's chip leakage current power consumption analysis requirements. These requirements include the chip project to which the target chip module belongs and the target process corner scenario information.

[0063] The input file preparation unit is used to obtain the total data storage path of the chip project from the chip database according to the aforementioned requirement information, extract the input file related to the chip power consumption analysis of the target chip module from the storage area corresponding to the total path, and store the input file in the specified path.

[0064] The leakage current analysis and processing unit is used to call a pre-configured power consumption analysis tool to read all files from the aforementioned specified path and use them as input files for power consumption analysis based on the user's trigger; and, based on the power consumption analysis results, extract the leakage current power consumption data of the target module in the aforementioned target process corner scenario and generate a leakage current power consumption analysis report according to a preset data structure.

[0065] In this embodiment, the input files include netlist files for each chip module in the chip project, standard parasitic parameter exchange format (SPEF) files, timing library (lib) file sets, and post-simulation waveform files. The lib file sets cover various pre-configured process corner specific scenarios.

[0066] At this point, based on the chip project to which the target chip module to be analyzed belongs, the netlist file, spef file, and post-simulation waveform file of the target chip module are extracted from the aforementioned chip database; and the lib files corresponding to each scenario are extracted based on the target process corner scenario information.

[0067] When the target process corner scene information includes multiple process corner scenes, there are multiple corresponding lib files. For different process corner scenes, multiple sub-paths are set under the aforementioned specified path to store the lib files of each process corner scene respectively.

[0068] Other technical features are described in the previous embodiments and will not be repeated here.

[0069] Another embodiment of the present invention provides a chip power consumption analysis system, the system including the aforementioned chip leakage current power consumption analysis device and visualization and report generation device.

[0070] The visualization and report generation device is used to present the analysis results in a graphical manner based on the analysis report of the aforementioned leakage current power consumption analysis device.

[0071] Other technical features are described in the previous embodiments and will not be repeated here.

[0072] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted in the context of the relevant technical documents in an overly idealistic or impractical manner, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.

Claims

1. A method for analyzing chip leakage current and power consumption, characterized in that... Including the following steps: Configure a chip database, which stores chip design data for chip projects. The chip design data for a chip project is stored in a single master path. The chip design data includes input files for chip power consumption analysis, and the input files conform to preset data format requirements. Collect user-initiated chip leakage current and power consumption analysis request information, which includes the chip project to which the target chip module to be analyzed belongs and the target process corner scenario information; Based on the required information, after obtaining the total data storage path of the chip project from the chip database, the input file related to the chip power consumption analysis of the target chip module is extracted from the storage area corresponding to the total path, and the input file is stored in the specified path. Based on the user's trigger, the pre-configured power analysis tool is invoked to read all files from the aforementioned specified path and use them as input files for power analysis; Furthermore, based on the power consumption analysis results, the leakage current power consumption data of the target module under the aforementioned target process corner scenario is extracted and a leakage current power consumption analysis report is generated according to a preset data structure.

2. The method according to claim 1, characterized in that, The input files include netlist files of each chip module in the chip project, standard parasitic parameter exchange format spef files, timing library lib file set and post-simulation waveform files. The lib file set covers various pre-configured specific scenarios of various process corners. At this point, based on the chip project to which the target chip module to be analyzed belongs, the netlist file, spef file, and post-simulation waveform file of the target chip module are extracted from the aforementioned chip database. Additionally, extract the corresponding lib files for each scenario based on the target process corner scenario information.

3. The method according to claim 1 or 2, characterized in that, The waveform file is an fsdb file; The power consumption analysis tool is the PTPX tool. The output data of the PTPX tool includes the total power consumption, dynamic power consumption and leakage current power consumption of the chip module. The leakage current power consumption is extracted from the aforementioned output data to generate a leakage current power consumption analysis report.

4. The method according to claim 3, characterized in that, The data structure of the leakage current power consumption analysis report includes at least the following fields: module name field, unit type field, threshold voltage field, number of units field, unit ratio field, leakage current power consumption value field, and leakage current power consumption percentage field. Output the target module name and / or number under the module name field; The process angle type, voltage, and temperature configured for the process angle scenario are output under the cell type field. The threshold voltage type configured for the process corner scenario is output under the threshold voltage field, including low threshold voltage LVT, standard threshold voltage SVT, and high threshold voltage HVT; The number of units designed under the process corner scenario is output under the unit quantity field; The unit ratio designed under the process angle scenario is output under the unit ratio field; The leakage current power consumption value for the process corner scenario is output under the leakage current power consumption value field. The leakage current power consumption ratio field outputs the proportion of leakage current power consumption to total power consumption in the process corner scenario.

5. The method according to claim 1 or 2, characterized in that, It also includes a user graphical interface, which includes a design data acquisition component and a design data publishing component. The design data acquisition component is used for designers to input or import chip design data; when inputting or importing chip design data, the corresponding chip project name and / or number should also be entered. The design data publishing component is used by designers to publish data after inputting or importing it; when the publishing component corresponding to the data is triggered, the data is published to a preset online platform. In the online platform, each piece of data is categorized and stored according to the chip project to which it belongs.

6. The method according to claim 5, characterized in that, The user graphical interface also includes a power consumption analysis setting component, which allows users to set the name and / or number of the chip project to be analyzed, the target chip module information, and the process corner type, voltage value, temperature value, and threshold voltage options for the target process corner scenario.

7. The method according to claim 5, characterized in that, The user graphical interface also includes a file path reading component and a leakage current power consumption analysis trigger component. When the file path reading component is triggered, it can read files under the specified path. When the target process corner scene information to be analyzed is multiple process corner scenes, the specified path includes multiple sub-paths. At this time, for different process corner scenes, according to the sorting of the sub-paths under the specified path, files are read from multiple sub-paths of the specified path for testing in sequence until the files under all sub-paths are tested. Once the leakage current power consumption analysis trigger component is triggered, it can call a pre-configured power consumption analysis tool to perform simulation testing on the currently read file for power consumption analysis.

8. A chip leakage current and power consumption analysis device, characterized in that... include: The chip database configuration unit is used to configure the chip database, which stores the chip design data of a chip project. The chip design data of a chip project is stored in a single master path. The chip design data includes input files for chip power consumption analysis, and the input files conform to preset data format requirements. The power consumption analysis setting unit is used to collect the user's chip leakage current power consumption analysis requirements; it includes the chip project to which the target chip module to be analyzed belongs and the target process corner scenario information. The input file preparation unit is used to obtain the total data storage path of the chip project from the chip database according to the aforementioned requirement information, extract the input file related to the chip power consumption analysis of the target chip module from the storage area corresponding to the total path, and store the input file in the specified path. The leakage current analysis processing unit is used to call the pre-configured power consumption analysis tool to read all files from the aforementioned specified path and use them as input files for power consumption analysis based on the user's trigger. Furthermore, based on the power consumption analysis results, the leakage current power consumption data of the target module under the aforementioned target process corner scenario is extracted and a leakage current power consumption analysis report is generated according to a preset data structure.

9. The apparatus according to claim 8, characterized in that, The input files include netlist files of each chip module in the chip project, standard parasitic parameter exchange format spef files, timing library lib file set and post-simulation waveform files. The lib file set covers various pre-configured specific scenarios of various process corners. At this point, based on the chip project to which the target chip module to be analyzed belongs, the netlist file, spef file, and post-simulation waveform file of the target chip module are extracted from the aforementioned chip database. Additionally, extract the corresponding lib files for each scenario based on the target process corner scenario information.

10. A chip power consumption analysis system, characterized in that... include, A leakage current power consumption analysis device, employing the device described in claim 9; A visualization and report generation device is used to present the analysis results graphically based on the analysis report from the aforementioned leakage current power consumption analysis device.

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