Via etching method

Abstract

The application provides a through hole etching method, by forming a gray scale mask layer with a specific inclination angle alpha, bottom width and thickness, the problems of angle regulation inflexibility, narrow process window, large angle tolerance and poor wafer level etching uniformity in the prior art are solved. By adjusting the inclination angle alpha of the mask layer, continuous adjustment and accurate control of the through hole inclination angle beta are realized, thereby significantly improving the flexibility and process window of the through hole etching; by designing the thickness of the mask layer, the excessive consumption of the gray scale mask layer is avoided; by optimizing the inclined surface of the gray scale mask layer to be ladder-shaped, the gray scale exposure time during the formation of the gray scale mask layer is greatly shortened, thereby improving the efficiency, and forming a through hole ladder with the same number of steps as the gray scale mask layer; by designing the bottom width of the gray scale mask layer according to the bottom width of the to-be-formed through hole, flexible adjustment of the through hole width is realized.

Description

Through-hole etching method Technical Field

[0001] This invention relates to the field of photolithography, and in particular to a through-hole etching method. Background Technology

[0002] Currently, inverted trapezoidal via etching technology mainly achieves structural control at specific angles by optimizing photolithography and etching process parameters. For example, in double-layer aluminum interconnect processes, by adjusting the photoresist thickness and hard baking temperature, and combining this with the synergistic optimization of etching gas flow rate, chamber pressure, and electrode power, inverted trapezoidal vias with a fixed slope can be formed, significantly improving the step coverage of the metal layer at the via to over 90%. This technology has been applied to devices such as digital-to-analog converters (D / A converters), effectively improving yield.

[0003] However, existing technologies primarily optimize for single, fixed angles, relying heavily on empirical parameter adjustments and failing to achieve flexible control of arbitrary angles. Control methods are concentrated on mechanical adjustments of gas ratios and power, lacking dynamic closed-loop control capabilities regarding the angle formation mechanism. Slope adjustments require re-optimization of the entire parameter set, resulting in a narrow process window and angle tolerances typically exceeding ±5°. Furthermore, wafer-level etching uniformity is poor, with significant differences in via angles between the edge and center regions, hindering mass production stability.

[0004] As advanced packaging evolves towards high aspect ratio structures such as 3D NAND, the etching technology for inverted trapezoidal vias faces physical limitations. Existing wet or plasma etching methods lack sufficient control over the sidewall morphology of high aspect ratio structures, easily leading to hole bottom residue or uncontrolled sidewall tilt. While laser-induced etching can achieve high aspect ratios, it struggles to accommodate arbitrary angle forming requirements. In summary, inverted trapezoidal via etching technology needs to overcome core bottlenecks such as flexible angle control, surface quality control, and high aspect ratio compatibility to meet the multi-dimensional integration needs of next-generation semiconductor devices. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a through-hole etching method to solve the problems of inflexible through-hole angle control, narrow process window, large through-hole angle tolerance, poor wafer-level etching uniformity, and insufficient control over the sidewall morphology of through-holes with high aspect ratio structures.

[0006] To achieve the above and other related objectives, the present invention provides a through-hole etching method, the through-hole etching method comprising:

[0007] S1 provides a substrate for which through-holes are to be formed;

[0008] S2, a mask layer is formed on the substrate;

[0009] S3, based on the tilt angle β of the via to be formed, the depth H of the via to be formed, and the etching rate of the mask layer... The etching rate of the substrate and etching rate selectivity According to the formula and The tilt angle α and etching time t of the grayscale mask layer are designed, and the bottom width of the grayscale mask layer is designed to be equal to the bottom width of the via to be formed; and the thickness h of the mask layer formed in step S2 is not less than ;

[0010] S4, the mask layer is subjected to grayscale exposure and development based on the tilt angle α and the bottom width to form the grayscale mask layer having the tilt angle α and the bottom width, and the grayscale mask layer has a plurality of grayscale mask layer steps on the inclined surface with the tilt angle α.

[0011] S5, the substrate is etched based on the grayscale mask layer with an inclination angle α and the etching time t to form the stepped via with an inclination angle β and a depth H, and the inclined surface of the stepped via has via steps equal to the number of steps in the grayscale mask layer.

[0012] S6, Remove the grayscale mask layer.

[0013] Further, the grayscale mask layer formed in step S4 has three grayscale mask layer steps on its inclined surface with an angle α: a first step adjacent to the substrate, a second step above the first step, and a third step above the second step, wherein the height of the first step is... The height of the second step is The height of the third step is According to the formula and In step S5, the through hole formed has an inclination angle β on its inclined surface, with steps sequentially formed from the bottom of the through hole upwards, with a height of... , and The three through-hole steps.

[0014] Optionally, the mask layer is a photoresist layer, and the substrate is a hard mask layer.

[0015] Optionally, the mask layer is a first hard mask layer, and the substrate is a second hard mask layer.

[0016] Optionally, in step S5, based on the grayscale mask layer with an angle α and the etching time t, the substrate is etched using high-energy plasma to form the via with an angle β and a depth H.

[0017] Optionally, in step S5, based on the grayscale mask layer with an angle α and the etching time t, the substrate is etched by reactive ion etching or laser-induced wet etching to form the via with an angle β and a depth H.

[0018] Optionally, the shape of the through hole to be formed includes an inverted trapezoid, an inverted frustum, or an inverted triangular truncated pyramid.

[0019] As described above, the via etching method of the present invention has the following beneficial effects: By utilizing grayscale exposure technology to precisely design and form a grayscale mask layer with a specific tilt angle α, bottom width, and thickness, the problems of inflexible angle control, narrow process window, large angle tolerance, and poor wafer-level etching uniformity in traditional via etching methods are solved. This method, by adjusting the tilt angle α of the mask layer, can achieve continuous adjustment and precise control of the via tilt angle β, thereby significantly improving the flexibility and process window of via etching; by designing the mask layer thickness h to be not less than... To avoid excessive consumption of the grayscale mask layer during substrate etching, ensuring that the grayscale mask layer is not prematurely and completely etched away before the vias are formed; by setting the inclined surface of the grayscale mask layer to be stepped, the grayscale exposure time during grayscale mask formation is greatly shortened, thereby improving efficiency, and the number of via steps is equal to the number of grayscale mask layer steps; by designing the bottom width of the grayscale mask layer to be equal to the bottom width of the via to be formed, the via width can be flexibly adjusted; in addition, this method only requires the stability of the vertical etching rate. During the etching process, the grayscale mask structure changes continuously, and the area of ​​lateral etching also changes continuously, effectively avoiding the accumulation of lateral etching in a certain area under the mask in existing methods, greatly reducing the impact of lateral etching on the via structure, and making the process conditions simpler and more controllable. Meanwhile, this method is compatible with a wider range of mask and substrate materials. For different etching selectivity ratios of various materials, the etching rate ratio can be adapted to variations by adjusting the tilt angle α of the grayscale mask. This makes it suitable for flexible control of via structures with various material selectivity ratios. Therefore, the via etching method of this embodiment has significant advantages in improving etching accuracy, enhancing process stability, and adapting to the etching requirements of high aspect ratio structures, thus meeting the stringent technical requirements of multidimensional integration in next-generation semiconductor devices. Attached Figure Description

[0020] Figure 1 shows a schematic flowchart of the through-hole etching method of the present invention.

[0021] Figures 2 to 5 show schematic cross-sectional structures of each step in the through-hole etching method of the present invention.

[0022] Figure 6 shows a coordinate schematic diagram of the etching process in the through-hole etching method of the present invention.

[0023] Figures 7 to 9 show schematic cross-sectional structures of each step in the stepped via etching method of the present invention.

[0024] Figure 10 shows a schematic diagram of the three-dimensional structure of the present invention, which is based on a grayscale mask layer with an inclination angle α and an etching time t to etch the substrate to form an inverted frustum-shaped through hole with an inclination angle β and a depth H.

[0025] Figure 11 shows a schematic diagram of the three-dimensional structure of the present invention, which is based on a grayscale mask layer with an angle α and an etching time t to etch the substrate to form an inverted triangular frustum through-hole with an angle β and a depth H.

[0026] Component labeling explanation: 1 Substrate, 11 Via, 211 First step, 212 Second step, 213 Third step, 12 Upper surface of substrate, 2 Mask layer, 21 Grayscale mask layer, 111 Fourth step, 112 Fifth step, 113 Sixth step, 22 Upper surface of grayscale mask layer, S1~S6 Steps. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please refer to Figures 1 to 11. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] This embodiment provides a through-hole etching method, as shown in Figure 1. The through-hole etching method includes:

[0030] S1 provides a substrate for which through-holes are to be formed;

[0031] S2, a mask layer is formed on the substrate;

[0032] S3, based on the tilt angle β of the via to be formed, the depth H of the via to be formed, and the etching rate of the mask layer... The etching rate of the substrate and etching rate selectivity According to the formula and The tilt angle α and etching time t of the grayscale mask layer are designed, and the bottom width of the grayscale mask layer is designed to be equal to the bottom width of the via to be formed; and the thickness h of the mask layer formed in step S2 is not less than ;

[0033] S4, the mask layer is subjected to grayscale exposure and development based on the tilt angle α and the bottom width to form the grayscale mask layer having the tilt angle α and the bottom width, and the grayscale mask layer has a plurality of grayscale mask layer steps on the inclined surface with the tilt angle α.

[0034] S5, the substrate is etched based on the grayscale mask layer with an inclination angle α and the etching time t to form the stepped via with an inclination angle β and a depth H, and the inclined surface of the stepped via has via steps equal to the number of steps in the grayscale mask layer.

[0035] S6, Remove the grayscale mask layer.

[0036] This embodiment of the via etching method solves the problems of inflexible angle control, narrow process window, large angle tolerance, and poor wafer-level etching uniformity in traditional via etching methods by precisely designing and forming a grayscale mask layer with a specific tilt angle α, bottom width, and thickness using grayscale exposure technology. By adjusting the tilt angle α of the mask layer, this method enables continuous adjustment and precise control of the via tilt angle β, thereby significantly improving the flexibility and process window of via etching; and by designing the mask layer thickness h to be not less than... To avoid excessive consumption of the grayscale mask layer during substrate etching, ensuring that the grayscale mask layer is not prematurely and completely etched away before the vias are formed; by setting the inclined surface of the grayscale mask layer to be stepped, the grayscale exposure time during grayscale mask formation is greatly shortened, thereby improving efficiency, and the number of via steps is equal to the number of grayscale mask layer steps; by designing the bottom width of the grayscale mask layer to be equal to the bottom width of the via to be formed, the via width can be flexibly adjusted; in addition, this method only requires the stability of the vertical etching rate. During the etching process, the grayscale mask structure changes continuously, and the area of ​​lateral etching also changes continuously, effectively avoiding the accumulation of lateral etching in a certain area under the mask in existing methods, greatly reducing the impact of lateral etching on the via structure, and making the process conditions simpler and more controllable. Meanwhile, this method is compatible with a wider range of mask and substrate materials. For different etching selectivity ratios of various materials, the etching rate ratio can be adapted to variations by adjusting the tilt angle α of the grayscale mask. This makes it suitable for flexible control of via structures with various material selectivity ratios. Therefore, the via etching method of this embodiment has significant advantages in improving etching accuracy, enhancing process stability, and adapting to the etching requirements of high aspect ratio structures, thus meeting the stringent technical requirements of multidimensional integration in next-generation semiconductor devices.

[0037] The via etching method of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0038] As shown in Figure 2, step S1 is performed first, providing a substrate 1 for which the via 11 is to be formed.

[0039] As shown in Figure 2, step S2 is then performed to form a mask layer 2 on the substrate 1.

[0040] Next, step S3 is performed, based on the tilt angle β of the via 11 to be formed, the depth H of the via 11 to be formed, and the etching rate of the mask layer 2. The etching rate of the substrate 1 and etching rate selectivity According to the formula and The tilt angle α and etching time t of the grayscale mask layer 21 are designed, and the bottom width of the grayscale mask layer 21 is designed to be equal to the bottom width of the via 11 to be formed; and the thickness h of the mask layer 2 formed in step S2 is not less than .

[0041] As shown in Figure 3, step S4 is then performed, where the mask layer 2 is subjected to grayscale exposure and development based on the tilt angle α and the bottom width to form the grayscale mask layer 21 with the tilt angle α and the bottom width, and the grayscale mask layer 21 has a plurality of grayscale mask layer steps on the inclined surface with the tilt angle α.

[0042] As shown in Figures 3 to 5, step S5 is then performed, where the substrate 1 is etched based on the grayscale mask layer 21 with an angle α and the etching time t to form the stepped via 11 with an angle β and a depth H. The inclined surface of the stepped via has via steps equal in number to the steps of the grayscale mask layer. Figure 3 shows a schematic diagram of the etching start point, and Figure 4 shows a schematic diagram of the etching process.

[0043] Next, step S6 is performed to remove the grayscale mask layer 21. Figure 5 shows a schematic diagram after etching is completed and the grayscale mask layer 21 is removed.

[0044] Specifically, as shown in Figure 6, the top center position of the through hole 11 to be formed is defined as the origin of the coordinate system, the y-axis is perpendicular to the surface of the substrate 1, and the x-axis is parallel to the surface of the substrate 1. The positive direction of the y-axis is from the through hole 11 to the mask layer 2. The coordinates of the endpoint A of the grayscale mask layer formed in step S4 where the inclined edge with the tilt angle α contacts the substrate 1 are (x1, 0), and the coordinates of the other endpoint B are (x2, h).

[0045] In step S5, during the process of etching the substrate 1 based on the grayscale mask layer 21 with an angle α and the etching time t to form the via 11 with an angle β and a depth H, that is, when the intersection of the etching front and the x-axis is between When the etching time is t1, the points on the inclined edge CD with an angle β during the etching process of the through hole 11 satisfy the following relationship: From this, we can deduce that The specific derivation process is as follows:

[0046] Referring to Figure 6, assuming the etching time is t1, the cross section of the etching front is located on the surface where point ECDFG is located. At this time, the intersection point D of the etching front and the x-axis is between x1 and x2.

[0047] In this etched state, when The relationship between y and x satisfies:

[0048]

[0049] when When, the coordinates of point C are known to be ( , The coordinates of point D are ( According to the two-point equation, the equation for the inclined edge CD with an angle β during the etching process of the through hole 11 is:

[0050]

[0051] Therefore, the slope of line segment CD is... Furthermore, given the inclination angle β of the inclined side of the through hole 11 to be etched, the slope of line segment CD can be determined to be... Therefore, we can conclude that:

[0052]

[0053] And because Therefore, we can conclude that:

[0054]

[0055] when When, the coordinates of point D are known to be ( The slope of line segment DF is 0. According to the point-slope equation, the equation for the inclined edge DF with an angle α during the etching process of the grayscale mask layer 21 is:

[0056]

[0057] when At that time, the equation for the etching front FG is:

[0058]

[0059] As a specific example, as shown in Figure 7, the grayscale mask layer 21 formed in step S4 has three grayscale mask layer steps on its inclined surface with an angle α. These are a first step 211 adjacent to the substrate 1, a second step 212 above the first step 211, and a third step 213 above the second step 212. The height of the first step 211 is... The heights of the first step 211 and the second step 212 are The heights of the first step 211, the second step 212, and the third step 213 are: That is, the height of the second step 212 is The height of the third step 213 is According to the formula and As shown in Figure 9, the through hole 11 formed in step S5 has steps formed sequentially from the bottom of the through hole 11 upwards on an inclined surface with an angle β. The height of the steps is... , and The three via steps are specifically the fourth step 111, the fifth step 112, and the sixth step 113, respectively. Figure 8 shows a schematic diagram of the etching process for forming the stepped via 11.

[0060] As an example, the mask layer 2 is a photoresist layer, and the substrate 1 is a hard mask layer, or the mask layer 2 is a first hard mask layer, and the substrate is a second hard mask layer. This is because the grayscale mask layer 21 is not limited to a photoresist mask layer directly formed by grayscale exposure, but can also be used in hard mask etching and multilayer hard mask etching. In hard mask etching technology, the grayscale pattern of the grayscale mask layer 21 can be transferred onto the hard mask layer by using the hard mask layer as the substrate 1 and the photoresist layer as the mask layer 2. Subsequently, the hard mask layer (specifically the first hard mask layer) can be used again as the mask layer 2 to etch the substrate 1. At this time, the substrate 1 can be the second hard mask layer, ultimately achieving flexible control of the tilt angle α of the via 11 using the hard mask etching process.

[0061] In this embodiment, in step S5, based on the grayscale mask layer 21 with tilt angle α and the etching time t, the substrate 1 is etched with high-energy plasma to form the stepped via 11 with tilt angle β and depth H. The etching process of the substrate 1 is not limited to this embodiment.

[0062] In other embodiments, in step S5, based on the grayscale mask layer 21 with an angle α and the etching time t, reactive ion etching (RIE) or laser-induced wet etching (LIWE) is used on the substrate 1 to form the stepped via 11 with an angle β and a depth H. Reactive ion etching combines plasma ion bombardment with free radical reactions, enabling high anisotropic etching. Laser-induced wet etching combines femtosecond laser modification with hydrofluoric acid (HF) wet etching, enabling the via 11 to achieve a 100:1 aspect ratio and supporting sidewall angle adjustment.

[0063] As an example, the via etching method of this embodiment can achieve via shapes 11 to be formed, including but not limited to inverted trapezoidal or inverted frustum shape (refer to FIG. 10) or inverted triangular frustum shape (refer to FIG. 11). Specifically, FIG. 10 is a three-dimensional structural diagram of an inverted frustum-shaped via 11 with an inclination angle β and depth H formed by etching the substrate 1 based on the grayscale mask layer 21 with an inclination angle α and an etching time t. FIG. 11 is a three-dimensional structural diagram of an inverted triangular frustum-shaped via 11 with an inclination angle β and depth H formed by etching the substrate 1 based on the grayscale mask layer 21 with an inclination angle α and an etching time t. Only the upper surface 22 of the grayscale mask layer and the upper surface 12 of the substrate are shown. This diverse via shape control capability greatly expands the application range of the via etching method of this embodiment to meet the design needs of more types of semiconductor devices.

[0064] In summary, the via etching method of the present invention solves the problems of inflexible angle control, narrow process window, large angle tolerance, and poor wafer-level etching uniformity in traditional via etching methods by precisely designing and forming a grayscale mask layer with a specific tilt angle α, bottom width, and thickness using grayscale exposure technology. This method achieves continuous adjustment and precise control of the via tilt angle β by adjusting the tilt angle α of the mask layer, thereby significantly improving the flexibility and process window of via etching; and by designing the mask layer thickness h to be not less than... To avoid excessive consumption of the grayscale mask layer during substrate etching, ensuring that the grayscale mask layer is not prematurely and completely etched away before the vias are formed; by setting the inclined surface of the grayscale mask layer to be stepped, the grayscale exposure time during grayscale mask formation is greatly shortened, thereby improving efficiency, and the number of via steps is equal to the number of grayscale mask layer steps; by designing the bottom width of the grayscale mask layer to be equal to the bottom width of the via to be formed, the via width can be flexibly adjusted; in addition, this method only requires the stability of the vertical etching rate. During the etching process, the grayscale mask structure changes continuously, and the area of ​​lateral etching also changes continuously, effectively avoiding the accumulation of lateral etching in a certain area under the mask in existing methods, greatly reducing the impact of lateral etching on the via structure, and making the process conditions simpler and more controllable. Meanwhile, this method is compatible with a wider range of mask and substrate materials. For different etching selectivity ratios of various materials, the etching rate ratio can be adapted to variations by adjusting the tilt angle α of the grayscale mask, making it suitable for flexible control of via structures with multiple materials and different selectivity ratios. Therefore, the via etching method of this embodiment has significant advantages in improving etching accuracy, enhancing process stability, and adapting to the etching requirements of high aspect ratio structures, meeting the stringent technical requirements of multidimensional integration in next-generation semiconductor devices. Thus, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for etching through-holes, characterized in that, The via etching method includes: S1, providing a substrate for forming vias; S2, forming a mask layer on the substrate; S3, etching according to the tilt angle β of the via to be formed, the depth H of the via to be formed, and the etching rate of the mask layer. The etching rate of the substrate and etching rate selectivity According to the formula and The tilt angle α and etching time t of the grayscale mask layer are designed, and the bottom width of the grayscale mask layer is designed to be equal to the bottom width of the via to be formed; and the thickness h of the mask layer formed in step S2 is not less than S4, perform grayscale exposure and development on the mask layer based on the tilt angle α and the bottom width to form the grayscale mask layer with the tilt angle α and the bottom width. The grayscale mask layer has a plurality of grayscale mask layer steps on the inclined surface with the tilt angle α. The height of each grayscale mask layer step is set according to the etching rate selection ratio k, such that after the etching time t, the height of each grayscale mask layer step multiplied by the etching rate selection ratio k corresponds to the height of the via step. S5, etch the substrate based on the grayscale mask layer with the tilt angle α and the etching time t to form the stepped via with the tilt angle β and the depth H. The inclined surface of the stepped via has the same number of via steps as the grayscale mask layer steps. S6, remove the grayscale mask layer.

2. The through-hole etching method according to claim 1, characterized in that: The grayscale mask layer formed in step S4 has three grayscale mask layer steps on its inclined surface with an angle α. These are a first step adjacent to the substrate, a second step above the first step, and a third step above the second step. The height of the first step is... The height of the second step is The height of the third step is According to the formula and In step S5, the through hole formed has an inclination angle β on its inclined surface, with steps sequentially formed from the bottom of the through hole upwards, with a height of... 、 and The three through-hole steps.

3. The through-hole etching method according to claim 1, characterized in that: The mask layer is a photoresist layer, and the substrate is a hard mask layer.

4. The through-hole etching method according to claim 1, characterized in that: The mask layer is a first hard mask layer, and the substrate is a second hard mask layer.

5. The through-hole etching method according to claim 1, characterized in that: In step S5, based on the grayscale mask layer with tilt angle α and the etching time t, the substrate is etched using high-energy plasma to form the via with a stepped shape having tilt angle β and depth H.

6. The through-hole etching method according to claim 1, characterized in that: In step S5, based on the grayscale mask layer with an angle α and the etching time t, the substrate is etched by reactive ion etching or laser-induced wet etching to form the via with an angle β and a depth H.

7. The through-hole etching method according to claim 1, characterized in that: The shape of the through hole to be formed includes an inverted trapezoid, an inverted frustum, or an inverted triangular frustum.

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