W-band self-adaptive gain CMOS (complementary metal oxide semiconductor) low-noise amplifier

Abstract

The invention discloses a W-band self-adaptive gain CMOS low-noise amplifier which comprises a low-noise amplifier stage, a current steering stage, an output stage and a self-adaptive biasing circuit. The low-noise amplification stage adopts a differential common source structure with a source degeneration inductor LS, so that noise matching and linearity optimization are realized; the current steering stage is of a differential cascode structure, a current switching mechanism of the current steering stage is controlled by a self-adaptive bias circuit, and dynamic gain adjustment is achieved; the output stage adopts a differential common-source structure and is positioned behind the current steering stage to ensure output isolation; the self-adaptive circuit is of a four-level cascade common source structure and can adjust system gain in a self-adaptive mode according to input signal power, and linearity maintenance and dynamic range expansion under the condition of high input power are achieved. Center-tapped transformers are adopted among the stages to carry out stage matching and provide direct-current bias.

Description

Technical Field

[0001] This invention relates to the field of battery equalization management technology, and specifically to a W-band adaptive gain CMOS low-noise amplifier. Background Technology

[0002] With the rapid development of the millimeter-wave band, W-band radar systems, due to their high spatial resolution and wide bandwidth advantages, are widely used in automotive radar, high-resolution imaging, and high-speed wireless communication. However, W-band receiving systems face challenges such as an extremely wide dynamic range of input signal power and complex spectral interference. In practical applications, the receiver front-end must strike a balance between high sensitivity and tolerance to strong interference signals. Traditional fixed-gain low-noise amplifiers often struggle to achieve both performance goals, easily leading to saturation distortion and intermodulation interference due to strong signals, severely affecting the system's dynamic range and signal quality.

[0003] Chinese patent (CN119210365A) discloses a millimeter-wave low-noise amplifier, whose structure is based on a three-stage common-source cascode amplification structure. It employs a transformer combined with transmission line inductance and capacitance for matching, achieving wideband high gain and low noise characteristics. However, this invention is a fixed-gain structure and cannot be dynamically adjusted according to the input signal strength. In practical applications, fixed-gain low-noise amplifiers are prone to amplification saturation and intermodulation distortion under strong signal environments, limiting the system's dynamic range and linear performance.

[0004] Therefore, this application provides a structure that can adaptively adjust the gain, which can adjust the amplification factor in real time according to the changes in the input signal, effectively improving the linearity and dynamic range of the system, enhancing the anti-interference capability, and meeting the needs of more complex millimeter-wave applications. Summary of the Invention

[0005] Based on the above-mentioned technical problems, this application discloses a W-band adaptive gain CMOS low-noise amplifier, including a low-noise amplification stage, a current steering stage, an output stage, and an adaptive bias circuit, with inter-stage matching achieved through transformers.

[0006] The low-noise amplifier stage is provided with ports a and a' on the left side and ports b and b' on the right side.

[0007] The current steering stage has ports c and c' on the left side, ports d and d' on the right side, and port g at the center node.

[0008] The output stage has ports e and e' on the left and ports f and f' on the right.

[0009] The input terminal of the adaptive bias circuit is ADB. in The output terminal is V ADB ;

[0010] The left ports a and a' of the low-noise amplifier stage are connected to the secondary coil of the input transformer XF1; the right ports b and b' of the low-noise amplifier stage are connected to the primary coil of the interstage matching transformer XF2; the secondary coil of the interstage matching transformer XF2 is connected to the left ports c and c' of the current steering stage; the right ports d and d' of the current steering stage are connected to the primary coil of the interstage matching transformer XF3; the secondary coil of the interstage matching transformer XF3 is connected to the left ports e and e' of the output stage; the right ports f and f' of the output stage are connected to the primary coil of the output transformer XF4; the coupler port integrated in the output transformer is connected to the input terminal ADB of the adaptive bias circuit. in Connection; the output terminal V of the adaptive bias circuit ADB It is connected to the center port g of the current steering stage; the above structure forms an adaptive gain CMOS low-noise amplifier structure;

[0011] The low-noise amplification stage employs a degenerate inductor L with a source. S Differential common-source structure;

[0012] The current steering stage adopts a differential common source common gate structure;

[0013] The output stage adopts a differential common-source structure;

[0014] The adaptive bias circuit adopts a four-stage cascaded common-source structure;

[0015] All transformers employ a center-tapped structure to provide DC bias, with the output transformer integrating a power detection coupler to provide feedback signals to the adaptive bias circuit.

[0016] Preferably, the low-noise amplification stage employs a differential common-source structure with a source degradation inductor, wherein the source degradation inductor L... S Used to optimize noise matching and improve linearity; the low-noise amplification stage includes NMOS transistor M1, NMOS transistor M2, and bias voltage V. G1 Inductor L S Capacitor C C1 Capacitor C C2 Power supply voltage V DD ;

[0017] Port a of the low-noise amplifier stage is formed by connecting the gate of NMOS transistor M1 to one end of the secondary coil of input transformer XF1; port a' is formed by connecting the gate of NMOS transistor M2 to the other end of the secondary coil of input transformer XF1; port b of the low-noise amplifier stage is formed by connecting the drain of NMOS transistor M1 to one end of the primary coil of interstage matching transformer XF2; port b' is formed by connecting the drain of NMOS transistor M2 to the other end of the primary coil of interstage matching transformer XF2; the secondary coil of input transformer XF1 is connected to the center with a bias voltage V. G1 The primary coil of the interstage matching transformer XF2 is connected to the power supply voltage V. DD The gate connection capacitor C of the NMOS transistor M1 C1 One end; the source of the NMOS transistor M1 is connected to the inductor L. S One end; the drain of the NMOS transistor M1 is connected to the capacitor C. C2 One end; the gate of the NMOS transistor M2 is connected to capacitor C. C2 At the other end; the source of the NMOS transistor M2 is connected to the inductor L. S At the other end; the drain of the NMOS transistor M2 is connected to capacitor C. C1 The other end; the inductor L S Center grounding.

[0018] Preferably, the current control stage adopts a differential common-source common-gate structure, and current shunting is achieved by controlling the gate voltages of transistors M6 and M7, thereby achieving variable gain; the current control stage includes NMOS transistors M3, M4, M5, M6, M7, and M8, and a bias voltage V. G2 Bias voltage V G3 Power supply voltage V DD Resistor R1, Resistor R2, Capacitor C C3 Capacitor C C4 ;

[0019] The current steering stage port c is formed by connecting the gate of NMOS transistor M3 to one end of the secondary coil of interstage matching transformer XF2; the port c' is formed by connecting the gate of NMOS transistor M4 to the other end of the secondary coil of interstage matching transformer XF2; the current steering stage port d is formed by connecting the drain of NMOS transistor M5 to one end of the primary coil of interstage matching transformer XF3; the port d' is formed by connecting the drain of NMOS transistor M8 to the other end of the primary coil of interstage matching transformer XF3; the center of the secondary coil of interstage matching transformer XF2 is connected to a bias voltage V. G2 The primary coil of the interstage matching transformer XF3 is connected to the power supply voltage V. DD The gate connection capacitor C of the NMOS transistor M3C3 One end; the source of the NMOS transistor M3 is grounded; the drain of the NMOS transistor M3 is connected to capacitor C. C4 One end of the NMOS transistor M5 is connected to the source of NMOS transistor M6; the gate of NMOS transistor M4 is connected to capacitor C. C4 At the other end; the source of the NMOS transistor M4 is grounded; the drain of the NMOS transistor M4 is connected to capacitor C. C3 The other end is connected to the source of NMOS transistor M7 and the source of NMOS transistor M8; the gate of NMOS transistor M5 is connected to the bias voltage V. G3 The gate of the NMOS transistor M8 is connected to a bias voltage V. G3 The gate of the NMOS transistor M6 is connected to resistor R1; the drain of the NMOS transistor M6 is connected to the power supply voltage V. DD The gate of the NMOS transistor M7 is connected to resistor R2; the drain of the NMOS transistor M7 is connected to the power supply voltage V. DD .

[0020] Preferably, the output stage is based on a differential common-source structure, and the output stage includes NMOS transistor M9 and NMOS transistor M... 10 Bias voltage V G4 Capacitor C C5 Capacitor C C6 Power supply voltage V DD ;

[0021] The output stage port e is formed by connecting the gate of NMOS transistor M9 to one end of the secondary coil of interstage matching transformer XF3; the output stage port e' is formed by NMOS transistor M 10 The gate of the NMOS transistor is connected to the other end of the secondary coil of the interstage matching transformer XF3; the output stage port f is formed by connecting the drain of the NMOS transistor M9 to one end of the primary coil of the output transformer XF4; the output stage port f' is formed by connecting the drain of the NMOS transistor M9 to one end of the primary coil of the output transformer XF4. 10 The drain of the transformer is connected to the other end of the primary coil of the output transformer XF4; the center of the secondary coil of the interstage matching transformer XF3 is connected to a bias voltage V. G4 The primary coil of the output transformer XF4 is connected to the power supply voltage V. DD The gate connection capacitor C of the NMOS transistor M9 C5 One end; the source of the NMOS transistor M9 is grounded; the drain of the NMOS transistor M9 is connected to capacitor C. C6 One end; the NMOS transistor M 10 Gate connection capacitor C C6 The other end; the NMOS transistor M 10 The source of the NMOS transistor is grounded; 10 Drain connection capacitor C C5 The other end.

[0022] Preferably, the adaptive bias circuit is based on a four-stage cascaded common-source structure, and the adaptive bias circuit includes an NMOS transistor M. 11 PMOS transistor M 12 NMOS transistor M 13 PMOS transistor M 14 Bias voltage V Gadb Capacitors C1, C2, C3, C4, and C5; resistors R3, R4, R5, R6, and R7; ground potential V. SSadb Power supply voltage V DDadb ;

[0023] The input terminal ADB of the adaptive bias circuit in Connected to the coupler integrated with the output transformer XF4; the output terminal V ADB Connect to node g of resistors R1 and R2; one end of capacitor C1 serves as input terminal ADB. in One end of resistor R3 is connected to the other end of capacitor C1, and the other end is connected to the bias voltage V. Gadb The NMOS transistor M 11 The gate of the NMOS transistor is connected to the connection node of resistor R3 and capacitor C1; 11 The drain of the NMOS transistor is connected to one end of the resistor R4; 11 The source is connected to ground potential V. SSadb The other end of resistor R4 is connected to the power supply voltage V. DDadb The capacitor C2 is connected in parallel with the resistor R4; the PMOS transistor M 12 The gate of the NMOS transistor is connected to resistor R4 and NMOS transistor M. 11 The drain connection node; the PMOS transistor M 12 The source is connected to the power supply voltage V. DDadb The PMOS transistor M 12 The drain of the resistor is connected to one end of the resistor R5; the other end of the resistor R5 is connected to the ground potential V. SSadb The capacitor C3 is connected in parallel with the resistor R5; the NMOS transistor M 13 The gate of the PMOS transistor is connected to the M. 12 The connection node between the drain and resistor R5; the NMOS transistor M 13 The source is connected to ground potential V. SSadb The NMOS transistor M 13 The drain of the resistor is connected to one end of the resistor R6; the other end of the resistor R6 is connected to the power supply voltage V. DDadb The capacitor C4 is connected in parallel with the resistor R6; the PMOS transistor M 14 The gate is connected to the NMOS transistor M.13 The connection node between the drain and resistor R6; the PMOS transistor M 14 The source is connected to the power supply voltage V. DDadb The PMOS transistor M 14 The drain of the resistor is connected to one end of the resistor R7; the other end of the resistor R7 is connected to the ground potential V. SSadb The capacitor C5 is connected in parallel with the resistor R7; the output terminal V ADB By PMOS transistor M 14 The connection node between the drain and resistor R7 is formed.

[0024] Compared with the prior art, the technical solution of this application has the following technical effects:

[0025] This invention employs a current-rudder structure combined with an adaptive bias circuit to achieve a dynamic gain adjustment range of 12.7dB. When the input signal power changes, the adaptive bias circuit automatically adjusts the bias current, achieving dynamic control of the low-noise amplifier gain. This ensures high gain under weak signal conditions, enhancing receiver sensitivity, while effectively reducing gain under strong signal conditions to prevent device saturation.

[0026] This invention, verified through two-tone simulation testing, significantly improves the suppression capability of third-order intermodulation distortion by approximately 10 dB compared to the traditional fixed-gain mode after enabling adaptive gain control. It also effectively enhances the linearity of the low-noise amplifier and extends its dynamic range.

[0027] This invention effectively optimizes the transmission efficiency of radio frequency signals and reduces signal loss by using center-tapped transformers for inter-stage matching and providing DC bias. At the same time, it ensures the stability of the operating points of each stage of the circuit, improves the signal processing capability of the amplifier in the W-band, and enhances the overall reliability of the circuit. This allows the amplifier to maintain stable performance in complex electromagnetic environments and meets the stringent requirements for signal transmission quality in millimeter-wave applications.

[0028] The output stage of this invention adopts a differential common-source structure and is located after the current rudder stage, which significantly improves the output isolation performance, reduces the adverse effects of the subsequent circuit on the preceding amplifier circuit, enables the amplifier to work better with subsequent modules, reduces interference between different circuit modules, improves the integration and operational stability of the entire receiving system, and provides more reliable front-end signal processing support for applications such as W-band radar systems.

[0029] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0030] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0032] Based on the description of the figures and their corresponding technical content in the document, the titles of the figures are as follows:

[0033] Figure 1 This is a block diagram of the W-band receiver front-end of the present invention;

[0034] Figure 2 This is a circuit diagram of the adaptive gain low-noise amplifier of the present invention;

[0035] Figure 3 This is a schematic diagram of the adaptive bias circuit structure of the present invention;

[0036] Figure 4 This is a schematic plan view of the integrated coupler for the output transformer XF4 of this invention;

[0037] Figure 5 For the present invention in different V ADB S under condition 21 (dB) parameter diagram;

[0038] Figure 6 For the present invention in different V Gadb V under the condition ADB Schematic diagram showing the relationship between input power;

[0039] Figure 7 This is a schematic diagram showing the relationship between the output power of the fundamental frequency and the third-order intermodulation product (IM3) of the present invention and the input power. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0041] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0042] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0043] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0044] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0045] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0046] Example 1

[0047] This embodiment mainly describes a W-band adaptive gain CMOS low-noise amplifier, such as... Figure 1 As shown, the input signal P in First, the module enters the adaptive gain low-noise amplifier module based on a current-controlled current rudder structure, with an output power of P. out1 The signal is then transmitted to the coupler, which extracts a certain percentage (approximately -12dB) of power P from the output. coupled Used to drive the adaptive bias circuit, the remaining output power P out2 This is passed to the subsequent circuitry. The adaptive bias circuit automatically adjusts the control voltage V based on the coupling power. ADB The current is fed back to the current control node of the low-noise amplifier, dynamically adjusting the internal current shunting, thereby achieving adaptive gain adjustment.

[0048] With the adaptive bias circuit enabled, the amplitude of the third-order intermodulation distortion (IM3) component is significantly reduced, and the IM3C suppression degree Δ1 is significantly greater than Δ2 with the adaptive bias circuit disabled, effectively improving the linearity and anti-interference capability of the system.

[0049] like Figure 2 As shown, the W-band adaptive gain CMOS low-noise amplifier includes a low-noise amplification stage, a current-controlled stage, an output stage, and an adaptive bias circuit. Transformers are used for inter-stage matching to ensure efficient transmission of RF signals and effectively improve the linearity and stability of the circuit. All transformers used have a center-tapped structure to couple the RF signals and provide a DC bias path.

[0050] The low-noise amplifier stage uses NMOS transistors M1 and M2 to form a differential common-source structure, with a transistor width of 15μm and a source series inductor L. S Source degradation is implemented to improve noise figure and linearity. Input signal RF in The voltage applied to one end of the primary coil of the input transformer XF1 is coupled to the gates of NMOS transistors M1 and M2 through the transformer's magnetic coupling. The center tap of the secondary coil is connected to the bias voltage V. G1 This achieves the superposition of AC RF signals and DC bias. The drains of NMOS transistors M1 and M2 are connected to the primary winding of interstage matching transformer XF2. The secondary winding of the transformer is connected to the gates of current-steering NMOS transistors M3 and M4, respectively, to achieve interstage coupling and impedance matching of the signal. Capacitor C C1 and C C2 It forms a capacitor neutralization network, reduces the influence of parasitic capacitance, and improves bandwidth and phase characteristics.

[0051] The current-driving stage consists of NMOS transistors M3, M4, M5, M6, M7, and M8 forming a differential cascode structure. M3 and M4 have a width of 10μm, M5 and M8 have a width of 19.6μm, and M6 and M7 have a width of 26μm. The secondary winding of the interstage matching transformer XF2 is connected to the gates of NMOS transistors M3 and M4, respectively, with the source grounded. NMOS transistors M5, M6, M7, and M8 form the current-driving structure, which is biased by voltage V. G2 V G3 The current distribution is controlled and adjusted to achieve dynamic gain adjustment. The current steering stage output is transmitted to the output stage through the primary coil of the interstage matching transformer XF3.

[0052] The output stage adopts a differential common-source structure, consisting of NMOS transistors M9 and M2. 10 The transistor has a width of 17.8 μm. Its gate is connected to both ends of the secondary winding of the interstage matching transformer XF3, and its drain is connected to the primary winding of the output transformer XF4. The center tap of the secondary winding of the interstage matching transformer XF3 is connected to the bias voltage V. G4 This provides a quiescent operating point for the output stage transistors. The output stage acts as an output isolator for the current-controlled stage, ensuring that changes in the load of the subsequent stage have a minimal impact on the operation of the preceding stage.

[0053] The adaptive bias circuit adopts a four-stage cascaded common-source structure, including an NMOS transistor M. 11 PMOS transistor M 12 NMOS transistor M 13 PMOS transistor M 14 The output transformer XF4 integrates a power detection coupler. The secondary coil acquires the output signal, which is then fed into the input of the adaptive bias circuit via a feedback path. After processing, it generates the control voltage V. ADB The control voltage is fed back to the current steering stage to adjust the conduction state of M6 and M7, thereby achieving dynamic adaptive adjustment of the amplifier gain.

[0054] This embodiment details the low-noise amplifier stage, which optimizes noise and linearity through source degradation inductance, achieves dynamic gain by adjusting current through the current steering stage, ensures output isolation through the output stage, implements feedback control through the adaptive bias circuit, and improves signal transmission efficiency and stability through transformer matching between stages. The overall design allows the amplifier to balance sensitivity and anti-interference capabilities in complex environments, making it suitable for W-band applications.

[0055] Example 2

[0056] This embodiment mainly describes the adaptive bias circuit, such as Figure 3 As shown, the adaptive bias circuit is based on a four-stage cascaded common-source structure, consisting of an NMOS transistor M 11 M 13 PMOS transistor M12 M 14 It consists of resistors R3, R4, R5, R6, and R7, and capacitors C1, C2, C3, C4, and C5. Its input terminal is ADB. in The output signal is fed into the coupler integrated by the output transformer XF4, and the output V ADB Resistors R1 and R2 are connected to the intermediate port g of the current rudder stage to dynamically adjust the bias voltage of the current rudder stage. Capacitors C2, C3, C4, and C5 are connected in parallel with the corresponding capacitors R4, R5, R6, and R7 to form an RC filter network, which filters out the fundamental frequency ω0 and its second harmonic frequency component 2ω0 to ensure the stability of the bias voltage.

[0057] The adaptive bias circuit samples the RF signal from the output stage via a coupler, and this signal is input to the NMOS transistor M. 11 The gate of the transistor utilizes the nonlinear current characteristics of the transistor to achieve radio frequency to direct current (RF-DC) conversion of signals. Specifically, the current relationship formula of a transistor is: Where K is the voltage-to-current conversion factor of the transistor, V gs V is the voltage between the gate and source of a field-effect transistor. th V is the threshold voltage of the transistor. ov For overdrive voltage, the RF signal coupled to the adaptive bias circuit by the amplifier is represented as Acosω0t, and thus the transistor output current formula is: Where I DC This is the DC drain current component output after the RF signal undergoes nonlinear conversion by the first-stage transistor. The formula reflects the envelope amplitude information of the RF power and is still a DC component. This DC current generates a DC voltage signal across the load resistor R4, which is then passed through transistor M. 12 M 13 M 14 The corresponding load resistors R5, R6, and R7 form a cascaded common-source amplifier stage, continuously amplifying the voltage to form a stable control voltage V whose amplitude varies with the input power. ADB Note that the RC load of the adaptive bias circuit acts as a filter, absorbing unwanted fundamental frequency and harmonic components. Furthermore, by adjusting the bias voltage V... Gadb It can flexibly change its response sensitivity to the input power of the low-noise amplifier;

[0058] As part of the overall feedback loop, the control voltage V ADB Feedback is sent to the current-guiding transistors M6 and M7 inside the LNA, adjusting their conduction levels to dynamically adjust the shunt current ratio. As the input RF power increases, V... ADBIncreasing the voltage of M6 and M7 strengthens their conduction, shunting more current and reducing the current flowing through the main amplification paths M5 and M8, thus lowering the gain and achieving automatic negative feedback control of the LNA gain. Conversely, when the input signal decreases, the control voltage decreases, the shunting current decreases, the gain recovers, and high sensitivity is maintained for weak signals. This closed-loop feedback mechanism ensures that the LNA avoids overdrive saturation over a large input dynamic range, maintains linear operation, and effectively improves the overall linearity of the system.

[0059] This embodiment describes in detail the adaptive bias circuit, which uses a four-stage cascaded common-source structure to sample the signal from the output and complete the RF-DC conversion. After amplification and filtering, a stable control voltage is formed, and the voltage is fed back to the current steering stage to dynamically adjust the shunt ratio. This allows the amplifier to automatically adapt the gain when the signal strength changes, reducing external interference, improving the circuit's adaptability to complex signal environments, and ensuring stable system operation.

[0060] Example 3

[0061] This embodiment is based on Embodiment 1 and, combined with simulation data, further illustrates the circuit performance. The circuit is designed and implemented using a 65nm CMOS process, with a low-noise amplifier power supply voltage of 1.2V and an adaptive bias supply voltage of V. DDadb 2.2V, gate voltage V Gadb When set to 1.20V, the overall power consumption of the circuit is approximately 40mW.

[0062] like Figure 4 As shown, the output transformer integrates a ring coupling circuit. The light-colored layer is metal layer 9, the striped layer is metal layer 8, and the dark-colored layer is metal layer AP. The gap between metal layer 9 and metal layer AP is 3μm to achieve electromagnetic coupling, extracting and sending a signal of about -10dB to the adaptive bias circuit, while the attenuation of the signal output can be ignored.

[0063] The input signal enters the loop structure from the output port of the output stage, and the output sampling port is ADB. in A ring coupler is strategically routed to an adaptive bias circuit, enabling real-time sampling and feedback adjustment of the amplifier's output signal power. This efficient integration of the ring coupler and adaptive bias circuit allows for rapid response to output power changes without external control signals, achieving automatic gain adjustment for the low-noise amplifier. This reduces system complexity while significantly improving dynamic range and linearity.

[0064] Simulation results show that the low-noise amplifier of this invention maintains good port matching with input reflection coefficient S11 and output reflection coefficient S22 both less than -10dB in the 86-90GHz frequency range; reverse isolation S12 is less than -40dB. The noise figure reaches 8dB at the center frequency of 88GHz and remains below 8.6dB in the 86-90GHz frequency range.

[0065] like Figure 5 As shown, with the adaptive bias voltage V ADB The amplifier gain can be dynamically adjusted from a peak value of 13.5dB to a low value of 0.8dB, while maintaining a stable center operating frequency, fully demonstrating the gain adjustment function; Figure 6 As shown, at different gate voltages V Gadb Under conditions of 1.19V, 1.20V, and 1.21V respectively, the adaptive bias voltage V ADB The relationship between V and input power. Gadb The increase of V ADB The initial rising input power point shifts towards lower power levels, and at the same input power value, V ADB The amplitude varies with V Gadb The increase is due to the increase of V. This indicates that by adjusting V... Gadb It can effectively control V ADB The response sensitivity and amplitude are adjusted to achieve adaptive gain adjustment that controls the sensitivity of a low-noise amplifier to a specific input signal level.

[0066] Linearity simulation was performed on the circuit, with the dual-tone inputs set to 88 and 88.1 GHz. The results are as follows. Figure 7 As shown, in the gain-adaptive adjustment off mode, the fundamental signal output power exhibits significant saturation as the input power increases, leading to a rapid increase in the third-order intermodulation distortion (IM3) component. However, in the gain-adaptive adjustment on mode, the amplifier significantly alleviates the saturation phenomenon of the fundamental output power through its adaptive gain control mechanism. Specifically, at Pin = -15dBm, the IM3 component decreases by approximately 17dB, although the fundamental component also decreases by 7dB. Converted to IM3C (corresponding to...) Figure 1 The Δ1) suppression level was improved by 10 dB, achieving enhanced linearity and dynamic range.

[0067] Table 1 Comparison of Performance Parameters

[0068]

[0069] The prior art listed in Table 1 above is a Chinese patent (CN119210365A - A Millimeter-Wave Low-Noise Amplifier). As shown in the table, this invention surpasses the prior art in both automatic gain control and gain control range. By combining a current-rudder structure with an adaptive bias circuit and an innovative coupler design, this invention achieves a wide dynamic gain control range of 13.5–0.8 dB, improving the system's flexibility and anti-interference capability. Furthermore, the third-order intermodulation distortion (IM3c) suppression is improved by 10 dB, exhibiting excellent linearity.

[0070] This embodiment describes in detail how the ring coupler integrated with the output transformer can efficiently sample the output signal, and with the help of the adaptive bias circuit, it can achieve automatic gain adjustment. The overall structure maintains good port matching and isolation within a specific frequency band, and the noise characteristics are stable. By adjusting the bias voltage, the response sensitivity can be flexibly controlled, reducing system complexity and improving the amplifier's adaptability and stability in complex environments, thus meeting the front-end processing requirements of related applications.

[0071] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. A W-band adaptive gain CMOS low noise amplifier, characterized by, The W-band adaptive gain CMOS low noise amplifier comprises a low noise amplification stage, a current steering stage, an output stage, and an adaptive bias circuit, and the stages are matched through transformers; The left side of the low noise amplification stage is provided with ports a and a', and the right side is provided with ports b and b'; The left side of the current steering stage is provided with ports c and c', and the right side is provided with ports d and d', and the center node is provided with a port g; The left side of the output stage is provided with ports e and e', and the right side is provided with ports f and f'; The adaptive bias circuit input end is ADB in , output end is V ADB ; The left ports a and a' of the low noise amplification stage are connected with a secondary coil of an input transformer XF1; The low noise amplifier stage right side port b, b' is connected with the primary coil of the interstage matching transformer XF2; the secondary coil of the interstage matching transformer XF2 is connected with the left side port c, c' of the current steering stage; the right side port d, d' of the current steering stage is connected with the primary coil of the interstage matching transformer XF3; the secondary coil of the interstage matching transformer XF3 is connected with the left side port e, e' of the output stage; the right side port f, f' of the output stage is connected with the primary coil of the output transformer XF4; the output transformer integrated coupler port is connected with the input end ADB of the adaptive bias circuit in The output end V ADB of the adaptive bias circuit is connected with the center port g of the current steering stage; the above structure forms an adaptive gain CMOS low noise amplifier structure; The low noise amplification stage adopts a differential common source structure with source degeneration inductor L S . The current steering stage adopts a differential common source and gate structure; The output stage adopts a differential common source structure; The adaptive bias circuit adopts a four-stage cascaded common source structure; The transformers all adopt a center-tapped structure to provide DC bias, and an output transformer is integrated with a power detection coupler for providing a feedback signal to the adaptive bias circuit.

2. The W-band self-adaptive gain CMOS low noise amplifier of claim 1, wherein, The low noise amplification stage adopts a differential common source structure with source degeneration inductance, wherein the source degeneration inductance L S for optimizing noise matching and improving linearity; the low noise amplification stage comprises an NMOS tube M1, an NMOS tube M2, a bias voltage V G1 , an inductance L S , a capacitance C C1 , a capacitance C C2 , and a power supply voltage V DD ; The port a of the low noise amplifier stage is composed of the connection of one end of the secondary coil of the input transformer XF1 and the gate of the NMOS transistor M1; the port a' is composed of the connection of the other end of the secondary coil of the input transformer XF1 and the gate of the NMOS transistor M2; the port b of the low noise amplifier stage is composed of the connection of one end of the primary coil of the interstage matching transformer XF2 and the drain of the NMOS transistor M1; the port b' is composed of the connection of the other end of the primary coil of the interstage matching transformer XF2 and the drain of the NMOS transistor M2; the center of the secondary coil of the input transformer XF1 is connected to the bias voltage V G1 ; the center of the primary coil of the interstage matching transformer XF2 is connected to the power supply voltage V DD ; one end of the capacitor C C1 is connected to the gate of the NMOS transistor M1; one end of the inductor L S is connected to the source of the NMOS transistor M1; one end of the capacitor C C2 is connected to the drain of the NMOS transistor M1; one end of the capacitor C C2 is connected to the gate of the NMOS transistor M2; one end of the inductor L S is connected to the source of the NMOS transistor M2; one end of the capacitor C C1 is connected to the drain of the NMOS transistor M2; the center of the inductor L S is connected to the ground.

3. The W-band self-adaptive gain CMOS low noise amplifier of claim 1, wherein, The current steering stage adopts a differential common source common gate structure, and realizes current shunting by controlling the gate voltage of the transistors M6 and M7, so as to achieve the purpose of variable gain; the current steering stage comprises an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, a bias voltage V G2 , a bias voltage V G3 , a power supply voltage V DD , a resistor R1, a resistor R2, a capacitor C C3 , a capacitor C C4 ; The current steering stage port c is composed of the gate of NMOS M3 and one end of the secondary coil of interstage matching transformer XF2; the port c' is composed of the gate of NMOS M4 and the other end of the secondary coil of interstage matching transformer XF2; the port d of the current steering stage is composed of the drain of NMOS M5 and one end of the primary coil of interstage matching transformer XF3; the port d' is composed of the drain of NMOS M8 and the other end of the primary coil of interstage matching transformer XF3; the center of the secondary coil of interstage matching transformer XF2 is connected to bias voltage V G2 ; the center of the primary coil of interstage matching transformer XF3 is connected to power supply voltage V DD ; one end of capacitor C C3 is connected to the gate of NMOS M3; the source of NMOS M3 is connected to ground; the drain of NMOS M3 is connected to one end of capacitor C C4 , the source of NMOS M5 and the source of NMOS M6; the other end of capacitor C C4 is connected to the gate of NMOS M4; the source of NMOS M4 is connected to ground; the drain of NMOS M4 is connected to one end of capacitor C C3 , the source of NMOS M7 and the source of NMOS M8; the gate of NMOS M5 is connected to bias voltage V G3 ; the gate of NMOS M8 is connected to bias voltage V G3 ; the gate of NMOS M6 is connected to resistor R1; the drain of NMOS M6 is connected to power supply voltage V DD ; the gate of NMOS M7 is connected to resistor R2; the drain of NMOS M7 is connected to power supply voltage V DD .

4. The W-band self-adaptive gain CMOS low noise amplifier of claim 1, wherein, The output stage is based on a differential common-source structure, comprising an NMOS transistor M9, an NMOS transistor M 10 , a bias voltage V G4 , a capacitor C C5 , a capacitor C C6 , a power supply voltage V DD ; The port e of the output stage is formed by connecting one end of the secondary coil of the interstage matching transformer XF3 with the gate of the NMOS transistor M9; the port e' is formed by connecting the other end of the secondary coil of the interstage matching transformer XF3 with the gate of the NMOS transistor M 10 ; the port f of the output stage is formed by connecting one end of the primary coil of the output transformer XF4 with the drain of the NMOS transistor M9; the port f' is formed by connecting the other end of the primary coil of the output transformer XF4 with the drain of the NMOS transistor M 10 ; the center of the secondary coil of the interstage matching transformer XF3 is connected with a bias voltage V G4 ; the center of the primary coil of the output transformer XF4 is connected with a power supply voltage V DD ; one end of the capacitor C C5 is connected with the gate of the NMOS transistor M9; the source of the NMOS transistor M9 is connected with the ground; one end of the capacitor C C6 is connected with the drain of the NMOS transistor M9; the gate of the NMOS transistor M 10 is connected with the other end of the capacitor C C6 ; the source of the NMOS transistor M 10 is connected with the ground; the drain of the NMOS transistor M 10 is connected with the other end of the capacitor C C5 .

5. The W-band self-adaptive gain CMOS low noise amplifier of claim 1, wherein, The adaptive bias circuit is based on a four-stage cascade common-source structure, and comprises NMOS tubes M 11 , PMOS tubes M 12 , NMOS tubes M 13 , PMOS tubes M 14 , a bias voltage V Gadb , capacitors C1, C2, C3, C4, C5, resistors R3, R4, R5, R6, R7, and a ground potential V SSadb , a power supply voltage V DDadb ; The input terminal of the adaptive bias circuit is ADB in The output terminal V ADB is connected to the connection node g of the resistors R1 and R2; one end of the capacitor C1 serves as the input terminal ADB in ; one end of the resistor R3 is connected to the other end of the capacitor C1, and the other end is connected to the bias voltage V Gadb ; the gate of the NMOS transistor M 11 is connected to the connection node of the resistor R3 and the capacitor C1; the drain of the NMOS transistor M 11 is connected to one end of the resistor R4; the source of the NMOS transistor M 11 is connected to the ground potential V SSadb ; the other end of the resistor R4 is connected to the power supply voltage V DDadb ; the capacitor C2 is connected in parallel with the resistor R4; the gate of the PMOS transistor M 12 is connected to the connection node of the resistor R4 and the drain of the NMOS transistor M 11 ; the source of the PMOS transistor M 12 is connected to the power supply voltage V DDadb ; the drain of the PMOS transistor M 12 is connected to one end of the resistor R5; the other end of the resistor R5 is connected to the ground potential V SSadb ; the capacitor C3 is connected in parallel with the resistor R5; the gate of the NMOS transistor M 13 is connected to the connection node of the drain of the PMOS transistor M 12 and the resistor R5; the source of the NMOS transistor M 13 is connected to the ground potential V SSadb ; the drain of the NMOS transistor M 13 is connected to one end of the resistor R6; the other end of the resistor R6 is connected to the power supply voltage V DDadb ; the capacitor C4 is connected in parallel with the resistor R6; the gate of the PMOS transistor M 14 is connected to the connection node of the drain of the NMOS transistor M 13 and the resistor R6; the source of the PMOS transistor M 14 is connected to the power supply voltage V DDadb ; the drain of the PMOS transistor M 14 is connected to one end of the resistor R7; the other end of the resistor R7 is connected to the ground potential V SSadb ; the capacitor C5 is connected in parallel with the resistor R7; the output terminal V ADB is formed by the connection node of the drain of the PMOS transistor M 14 and the resistor R7.

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