A method for manufacturing a bipolar element-CMOS-DMOS semiconductor device and a semiconductor device
By using a double damask process to form a double trench structure in the BCD device region and filling it with isolation material, the problem of the impact of deep trench isolation structure on the device was solved, and the device stability was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2025-11-20
- Publication Date
- 2026-05-12
AI Technical Summary
In the process of forming the deep trench isolation structure of the BCD device region, the existing technology is prone to causing defects to the already formed BCD device, affecting the device stability.
A dual-groove structure, comprising shallow and deep trenches, is formed using a dual damask process, and an isolation material is filled within the dual-groove structure to simplify the process and reduce its impact on the device.
This reduces the number of defects in the device fabrication process and improves the stability of semiconductor devices.
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Figure CN121194505B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for fabricating a bipolar element-CMOS-DMOS semiconductor device and the semiconductor device itself. Background Technology
[0002] BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.
[0003] In the prior art, after forming the BCD device region on the semiconductor substrate, a deep trench is formed between any two device regions of bipolar element, CMOS, and DMOS, and the deep trench is filled with insulating material to physically separate different device regions and avoid leakage and latch-up effects between different device regions.
[0004] In the above process, the deep trench isolation structure is formed after the BCD device region is formed. The formation of the deep trench isolation structure involves many process steps, which can easily affect the already formed BCD device and cause device defects.
[0005] Therefore, how to reduce defects in the semiconductor device fabrication process is a technical problem that needs to be solved. Summary of the Invention
[0006] This application provides a method for fabricating a bipolar CMOS-DMOS semiconductor device, which can reduce defects present in the fabrication process of semiconductor devices. This application also provides a bipolar CMOS-DMOS semiconductor device.
[0007] The specific plan is as follows:
[0008] In a first aspect, this application provides a method for fabricating a bipolar element-CMOS-DMOS semiconductor device. The method includes: providing a semiconductor substrate; forming a bipolar element-CMOS-DMOS device region on the semiconductor substrate; forming a double-trench structure between any two of the bipolar element, CMOS, and DMOS device regions, comprising a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located within the first trench and has a depth greater than the first trench; and filling the double-trench structure with an isolation material to form an isolation structure for the bipolar element-CMOS-DMOS device.
[0009] Secondly, this application provides a bipolar element-CMOS-DMOS semiconductor device, comprising: a semiconductor substrate, a bipolar element-CMOS-DMOS device region formed on the semiconductor substrate; a double trench structure formed between any two of the bipolar element, CMOS, and DMOS device regions, including a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located in the first trench and has a depth greater than the first trench; and an isolation material is filled in the double trench structure to form an isolation structure for the bipolar element-CMOS-DMOS device.
[0010] Compared with the prior art, this application has the following advantages:
[0011] The method for fabricating a bipolar-CMOS-DMOS semiconductor device provided in this application includes: providing a semiconductor substrate, forming a bipolar-CMOS-DMOS device region on the semiconductor substrate; forming a double-trench structure between any two of the bipolar, CMOS, and DMOS device regions, comprising a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located in the first trench and has a depth greater than the first trench; and filling the double-trench structure with an isolation material to form an isolation structure for the bipolar-CMOS-DMOS device. In fabricating the double-trench isolation structure, a double damask process is used, first forming a double-trench structure including shallow and deep trenches, and then filling the double-trench structure with an isolation material to form the isolation structure for the bipolar-CMOS-DMOS device. Compared with traditional methods, this method simplifies the process flow involved in the formation and filling of the double-trench structure, thereby reducing the impact on the bipolar-CMOS-DMOS device during the formation of the isolation structure and reducing the number of device defects. Therefore, this method can reduce defects in the fabrication process of bipolar-CMOS-DMOS semiconductor devices, thereby improving the stability of the formed semiconductor devices. Attached Figure Description
[0012] Figure 1 A flowchart illustrating the fabrication method of the bipolar CMOS-DMOS semiconductor device provided in the embodiments of this application.
[0013] Figure 2 This is a schematic diagram illustrating an example of forming a first passivation oxide layer and a first hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.
[0014] Figure 3This is a schematic diagram of a first example of forming a shallow trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0015] Figure 4 This is a schematic diagram of a first example of forming a double trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0016] Figure 5 This is a schematic diagram of a first example of filling an isolation material in a double trench in a method for fabricating a semiconductor device provided in this application embodiment.
[0017] Figure 6 This is a schematic diagram of a first example of removing an insulating material layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0018] Figure 7 This is a schematic diagram of a first example of removing a first hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0019] Figure 8 This is a schematic diagram of a first example of forming polycrystalline silicon on a first passivation oxide layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.
[0020] Figure 9 This is a schematic diagram illustrating an example of forming a second passivation oxide layer and a second hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.
[0021] Figure 10 This is a schematic diagram illustrating an example of forming a deep trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0022] Figure 11 This is a schematic diagram illustrating an example of removing a third photoresist layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0023] Figure 12 This is a schematic diagram illustrating an example of removing a second passivation oxide layer and a second hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0024] Figure 13 This is a schematic diagram illustrating an example of forming a third passivation oxide layer and a third hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.
[0025] Figure 14 This is a schematic diagram of a second example of forming a double trench on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0026] Figure 15 This is a schematic diagram of a second example of filling an isolation material in a double trench in the method for fabricating a semiconductor device provided in the embodiments of this application.
[0027] Figure 16 This is a schematic diagram of a second example of removing an insulating material layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0028] Figure 17 This is a schematic diagram of a first example of removing a third hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0029] Figure 18 This is a schematic diagram of a first example of forming polycrystalline silicon in a third passivation oxide layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application.
[0030] Figure 19 This is a schematic diagram of a first example of filling a double trench with an isolation material to form a gap in a method for fabricating a semiconductor device provided in this application.
[0031] Figure 20 This is a schematic diagram of the first example of a semiconductor device fabrication method provided in this application, in which the bottom of the gap is etched and ion implanted after filling the double trench with an isolation material.
[0032] Figure 21 This is a schematic diagram of a first example of filling the gaps with an insulating oxide layer in the method for fabricating a semiconductor device provided in this application.
[0033] Figure 22 This is a schematic diagram of a first example of removing the insulating oxide layer and the insulating layer on the semiconductor substrate in the method for fabricating a semiconductor device according to an embodiment of this application.
[0034] Figure 23 This is a schematic diagram of a second example of removing a first hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0035] Figure 24 This is a schematic diagram of a second example of filling polycrystalline silicon in a first passivation oxide layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0036] Figure 25 This is a schematic diagram of a second example of a semiconductor device fabrication method provided in this application, in which an isolation material is filled into a double trench to form a gap.
[0037] Figure 26This is a schematic diagram of a second example of a semiconductor device fabrication method provided in this application, in which the bottom of the gap is etched and ion implanted after filling the double trench with an isolation material.
[0038] Figure 27 This is a schematic diagram of a second example of filling the gaps with an insulating oxide layer in the method for fabricating a semiconductor device provided in this application.
[0039] Figure 28 This is a schematic diagram of a second example of removing the insulating oxide layer and the insulating layer on the semiconductor substrate in the method for fabricating a semiconductor device provided in this application.
[0040] Figure 29 This is a schematic diagram of a second example of removing a third hard mask layer on a semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of this application.
[0041] Figure 30 This is a schematic diagram of a second example of filling polycrystalline silicon in a third passivation oxide layer on a semiconductor substrate in a method for fabricating a semiconductor device provided in this application embodiment.
[0042] Figure 31 This is a schematic diagram of an example of a bipolar CMOS-DMOS semiconductor device provided in an embodiment of this application. Detailed Implementation
[0043] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.
[0044] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.
[0045] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.
[0046] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.
[0047] BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.
[0048] In the prior art, after forming bipolar element-CMOS-DMOS device regions on a semiconductor substrate, a deep trench is formed between any two device regions of bipolar element, CMOS, and DMOS, and the deep trench is filled with insulating material to physically separate different device regions and avoid leakage and latch-up effects between different device regions.
[0049] In the above process, after the bipolar element-CMOS-DMOS device region is formed, the deep trench isolation structure is then formed. The formation of the deep trench isolation structure involves many process steps, which can easily affect the already formed bipolar element-CMOS-DMOS device and cause device defects.
[0050] Therefore, how to reduce defects in the semiconductor device fabrication process is a technical problem that needs to be solved.
[0051] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0052] The following, combined with Figures 1-31 This application describes a method for fabricating a bipolar CMOS-DMOS semiconductor device according to embodiments of the present application.
[0053] Figure 1 The flowchart of the fabrication method of the bipolar element-CMOS-DMOS semiconductor device provided in the embodiments of this application includes the following steps S101 to S103.
[0054] Step S101: Provide a semiconductor substrate, on which a bipolar element - CMOS - DMOS device region is formed.
[0055] This step is used to provide a semiconductor substrate and form a bipolar element-CMOS-DMOS device region on the semiconductor substrate.
[0056] In semiconductor manufacturing, the semiconductor substrate is the base used to form semiconductor devices. Semiconductor substrate materials include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The semiconductor substrate material can be selected according to actual needs during the fabrication process.
[0057] Figure 2 This is a schematic diagram of an example of a semiconductor substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application. The semiconductor substrate may include a P-type substrate 01, an N-type buried layer 02, and a P-type epitaxial layer 03. The P-type epitaxial layer 03 is located above the P-type substrate 01, and the N-type buried layer 02 is disposed in the middle portion between the P-type epitaxial layer 03 and the P-type substrate 01.
[0058] A P-type substrate is typically a single-crystal silicon wafer doped with P-type impurities. A P-type substrate is a semiconductor wafer (hereinafter referred to as a wafer) where holes are the primary charge carriers, used as a substrate for manufacturing integrated circuits, power devices, or sensors. The P-type substrate provides mechanical support for the devices manufactured on it and serves as the operating platform for the semiconductor devices. P-type substrates exhibit P-type conductivity (hole concentration > electron concentration) by doping with acceptor impurities (such as boron, gallium, etc.).
[0059] An N-type buried layer (NBL) is a highly concentrated N-type doped region buried beneath a P-type epitaxial layer, typically fabricated during the initial stages of substrate preparation or before epitaxial growth. Specifically, the NBL region is defined on the surface of a P-type silicon substrate using photolithography, and then formed through high-dose ion implantation and high-temperature annealing. High-dose ion implantation refers to the implantation of N-type impurities (such as arsenic (As) or antimony (Sb)), typically with a dose of 10-1. 15 -10 16 cm -2Energy ranges from 50 to 200 keV. High-temperature annealing refers to the diffusion of implanted ions at temperatures of 1000-1200℃, forming a deep junction (1-5μm deep) and activating impurities. One function of the N-type buried layer is to reduce collector / drain resistance: in bipolar transistors (BJTs) or power MOSFETs, NBLs act as low-resistance paths, improving current transport efficiency. Isolation and latch-up prevention: in CMOS processes, NBLs can block the conduction of parasitic PNP transistors, preventing latch-up. Reducing substrate interference: shielding noise or substrate leakage current.
[0060] After NBL is formed, a P-type epitaxial layer is formed on the semiconductor substrate.
[0061] A p-type epitaxial layer is a single-crystal thin film with p-type conductivity, formed on the surface of a semiconductor substrate (such as silicon or gallium arsenide) using epitaxial growth techniques. Its main purpose is to provide specific electrical properties (such as hole conductivity, reduced resistance, and increased breakdown voltage) or structural optimization (such as reduced defect density) for semiconductor devices by precisely controlling doping and crystal structure. Epitaxial growth techniques include chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). CVD involves introducing silicon-containing gases (such as silane (SiH4), dichlorosilane (SiH2Cl2), or silicon tetrachloride (SiCl4)) and p-type dopant sources (such as borane (B2H6)) into a high-temperature reaction chamber, where a chemical reaction causes silicon atoms to deposit on the substrate surface, gradually forming a single-crystal layer. MBE, on the other hand, operates in an ultra-high vacuum environment, where silicon and dopant elements (such as boron) are evaporated, and atomic or molecular beams are directly sprayed onto the substrate surface, causing a reaction and growth into a single-crystal layer.
[0062] The bipolar element-CMOS-DMOS device region formed on the semiconductor substrate, such as Figure 31The active layer 23, consisting of a bipolar junction transistor (NPN) and a CMOS-DMOS, is disposed on the semiconductor substrate. The active layer 23 includes an NPN bipolar junction transistor (NPNB) 2301, a complementary metal-oxide-semiconductor (CMOS) 2302, an N-channel laterally diffused metal-oxide-semiconductor (N-LDMOS) 2303, and a P-channel laterally diffused metal-oxide-semiconductor (P-LDMOS) 2304. NPN is one of the core components of a bipolar transistor, primarily used for high-precision analog signal processing, high-speed switching, or driving circuits. NPN, CMOS, N-LDMOS, and P-LDMOS differ in structure, voltage, and function, as follows: NPN provides high-precision analog signals and is susceptible to noise interference; CMOS provides low-voltage data logic and is sensitive to leakage current; DMOS (N-LDMOS and P-LDMOS) handles high-voltage / high-current loads and may introduce substrate noise. N-LDMOS has a higher electron mobility than hole mobility, resulting in lower on-resistance and faster switching speed. P-LDMOS has a lower hole mobility, resulting in higher on-resistance and lower efficiency, and typically requires a larger area to achieve the same current capability as N-LDMOS.
[0063] After forming bipolar elements—CMOS-DMOS devices—on a semiconductor substrate, deep trench isolation walls need to be set between any two regions of NPN, CMOS, N-LDMOS, and P-LDMOS to isolate these devices and avoid leakage and latch-up effects.
[0064] To reduce the impact of the deep trench isolation structure fabrication process on bipolar-CMOS-DMOS devices, this application uses the following method to form the deep trench isolation structure and fills the inside of the deep trench isolation structure with isolation material, as detailed in steps S102 and S103.
[0065] Step S102: Between any two of the isolation bipolar element, CMOS, and DMOS device regions, a double trench structure is formed, including a first trench for shallow trench isolation structure and a second trench for deep trench isolation structure, wherein the second trench is located in the first trench and has a greater depth than the first trench.
[0066] This step is used to form a dual-trench structure. Specifically, a damascus process is used to first form a dual-trench structure including shallow and deep trenches. Then, in step S103, an isolation material is filled into the dual-trench structure to form an isolation structure for isolating bipolar CMOS-DMOS devices. In the prior art, shallow trenches are typically formed first and then filled with isolation material, followed by deep trenches and then filled with isolation material. In comparison, the isolation structure formation method provided in this application reduces the number of process steps, thereby reducing the number of device defects caused to the bipolar CMOS-DMOS device during the isolation structure formation process, thus improving device stability.
[0067] The following describes in detail how the double-groove structure is formed:
[0068] A first method of forming a dual trench structure: a first trench for a shallow trench isolation structure is formed on the semiconductor substrate, and a second trench for a deep trench isolation structure is formed within the first trench.
[0069] Please refer to Figures 2 to 4 This describes a first method for forming a dual-trench structure. Specifically, a first passivation oxide layer 04 and a first hard mask layer 05 are formed on the epitaxial layer 03 of the semiconductor substrate; the first hard mask layer 05 is etched to form the first trench 07 on the epitaxial layer 03 of the semiconductor substrate; and an etching process is performed at the bottom of the first trench 07 to form the second trench 09 on the semiconductor substrate 01.
[0070] The formation of a first passivation oxide layer 04 and a first hard mask layer 05 helps to precisely control the depth and shape of the shallow trench structure, while protecting the semiconductor substrate from erosion or wear in subsequent process steps.
[0071] A passivation oxide layer is a thin layer of silicon dioxide (SiO2) formed on a semiconductor substrate (e.g., a silicon substrate). Its function is to prevent contamination or oxidation of the silicon surface, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device. Passivation oxide layers can be generated through thermal oxidation or chemical vapor deposition. Thermal oxidation is a process of growing silicon dioxide by exposing the substrate to a high-temperature environment of oxygen or water vapor. Thermal oxidation includes dry oxidation and wet oxidation. Dry oxidation uses pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxidation uses water vapor to react with silicon to generate the oxide layer. Wet oxidation has a faster growth rate than dry oxidation, but the oxide layer density is lower than that of dry oxidation.
[0072] Chemical vapor deposition (CVD) is a material preparation technique that deposits solid thin films on a substrate surface through a gas-phase chemical reaction. The core principle is to utilize a gaseous precursor to undergo a chemical reaction under specific conditions, generating a solid product that is deposited on the substrate, while gaseous byproducts are removed from the system.
[0073] A hard mask layer is a thin film material with high hardness and high etch selectivity used for pattern transfer in semiconductor manufacturing. It is located between the photoresist and the material to be etched. The hard mask layer protects the passivation oxide layer and the semiconductor substrate from over-etching during subsequent etching steps.
[0074] Hard mask layers include, but are not limited to: silicon nitride (Si3N4) hard mask layers, silicon dioxide (SiO2) hard mask layers, metal hard mask layers, and amorphous carbon hard mask layers. In this embodiment, the hard mask layer is specifically a silicon nitride (Si3N4) hard mask layer.
[0075] After forming the first passivation oxide layer 04 and the first hard mask layer 05, the method further includes: defining the area on the first hard mask layer 05 on the semiconductor substrate by photolithography to form the shallow trench.
[0076] Photolithography is a process that transfers a design pattern from a photomask to a photoresist on the surface of a wafer through optical exposure. It forms a precise temporary pattern on the wafer surface, providing a template for subsequent etching or ion implantation. In the embodiments of this application, such as... Figure 3 As shown, a first photoresist layer 06 is coated on the first hard mask layer 05, and the area where shallow trenches need to be formed is defined on the first hard mask layer 05 by exposure and development.
[0077] Then, the etching process begins on the first hard mask layer 05. The etching process removes the substrate material not protected by the photoresist using physical or chemical methods, permanently transferring the photolithographic pattern onto the wafer. Its purpose is to precisely replicate the pattern to form device structures (such as gates and interconnect trenches). Etching includes wet etching and dry etching. Wet etching uses chemical solutions (such as hydrofluoric acid for silicon dioxide and phosphoric acid for silicon nitride) to selectively dissolve the material. Dry etching utilizes active ions or free radicals in plasma for etching, including physical etching (ion bombardment, such as Ar...). + Sputtering or chemical etching (gas reaction, such as carbon tetrafluoride plasma etching of silicon).
[0078] In this embodiment, based on the required depth and shape of the shallow trench, etching begins in the area on the first hard mask layer 05 where a shallow trench structure needs to be formed, forming a shallow trench that penetrates the first hard mask layer 05, the first passivation oxide layer 04, and to a first predetermined position on the epitaxial layer 03 of the semiconductor substrate, serving as the first trench 07.
[0079] Then, remove Figure 3 The first photoresist layer 06 is shown, and a second photoresist layer 08 is coated on the first hard mask layer 05 and inside a portion of the first trench 07, as shown. Figure 4 As shown, the area where a deep trench needs to be formed is defined in the bottom region of a portion of the first trench 07 by exposure and development. Then, according to the depth and shape required for etching the deep trench, etching begins in the area at the bottom of the portion of the first trench 07 where a deep trench structure needs to be formed, forming a deep trench that penetrates the portion of the first trench 07, the epitaxial layer 03 of the semiconductor substrate, and to a second predetermined position on the semiconductor substrate 01, as the second trench 09.
[0080] Then remove Figure 4 The second photoresist layer 08 shown is applied until the surface of the first hard mask layer 05 is exposed.
[0081] This forms a double-groove structure, comprising a first groove for shallow trench structures and a second groove for deep trench structures. This is the first method of forming a double-groove structure.
[0082] The following describes a second method of forming a dual trench structure: a second trench for a deep trench isolation structure is formed on the semiconductor substrate, and a first trench for a shallow trench isolation structure is formed in a predetermined area at the top corresponding to the second trench.
[0083] Please refer to Figures 9 to 14 This describes a second method for forming a dual-trench structure. Specifically, a second passivation oxide layer 13 and a second hard mask layer 14 are formed on the epitaxial layer 03 of the semiconductor substrate; the second hard mask layer 14 is etched to form the second trench 09 on the semiconductor substrate 01; the second hard mask layer 14 and the second passivation oxide layer 13 are removed; a third passivation oxide layer 16 and a third hard mask layer 17 are re-formed on the epitaxial layer 03 of the semiconductor substrate; an etching process is performed on the third hard mask layer 17 in a predetermined area corresponding to the top position of the second trench 09 to form the first trench 07 on the epitaxial layer 03 of the semiconductor substrate.
[0084] The functions of the first passivation oxide layer 04 and the first hard mask layer 05 are similar to those of the above-mentioned layers. Figure 9The function of forming the second passivation oxide layer 13 and the second hard mask layer 14 is to help precisely control the depth and shape of the deep trench structure, while protecting the semiconductor substrate from erosion or wear in subsequent process steps.
[0085] After forming the second passivation oxide layer 13 and the second hard mask layer 14, the process further includes: applying a third photoresist layer 15 onto the second hard mask layer 14 on the semiconductor substrate using a photolithography process, and defining the area on the second hard mask layer 14 where a deep trench needs to be formed by exposure and development.
[0086] According to the depth and shape required for etching the deep trench, etching begins in the area on the second hard mask layer 14 where the deep trench structure needs to be formed, forming a deep trench that penetrates the second hard mask layer 14, the second passivation oxide layer 13, the epitaxial layer 03 of the semiconductor substrate, and to a second predetermined position on the semiconductor substrate 01, as the second trench 09.
[0087] Then, remove Figure 10 The third photoresist layer 15 is shown until the surface of the second hard mask layer 14 is exposed, as shown. Figure 11 As shown.
[0088] Then, the first trench for the shallow trench structure is formed. Before forming the first trench, the second hard mask layer 14 and the second passivation oxide layer 13 need to be removed until the surface of the epitaxial layer 03 of the semiconductor substrate is exposed, such as... Figure 12 As shown. Then, the third passivation oxide layer 16 and the third hard mask layer 17 are re-formed on the epitaxial layer 03 of the semiconductor substrate, as follows. Figure 13 As shown, this helps to precisely control the depth and shape of shallow trench structures while protecting the semiconductor substrate from erosion or wear in subsequent process steps.
[0089] After forming the third passivation oxide layer 16 and the third hard mask layer 17, the process further includes: applying a fourth photoresist layer 18 onto the third hard mask layer 17 on the semiconductor substrate using a photolithography process; and defining the area where shallow trenches need to be formed on the third hard mask layer 17 by exposure and development, such as... Figure 14 As shown. The shallow trench area here is within a preset area corresponding to the top position of the deep trench, and the structure including this shallow trench and the corresponding deep trench is a double trench structure.
[0090] Then, based on the required depth and shape of the shallow trench, etching begins in the area on the third hard mask layer 17 where the shallow trench structure needs to be formed, forming a shallow trench that penetrates the third hard mask layer 17, the third passivation oxide layer 16, and to a first predetermined position on the epitaxial layer 03 of the semiconductor substrate, as the first trench 07.
[0091] This results in a double-groove structure comprising a first groove for shallow trench structures and a second groove for deep trench structures. This is the second method of forming a double-groove structure.
[0092] Step S103: Fill the double trench structure with isolation material to form an isolation structure for a bipolar element-CMOS-DMOS device.
[0093] This step is used to fill the formed double trench structure with isolation material, which is then used as the isolation structure for bipolar element-CMOS-DMOS devices.
[0094] The filling of the double-groove structure with an insulating material can fall into two categories. First, the insulating material includes an insulating material that completely fills the double-groove structure. Second, the insulating material creates a gap at the central axis of the double-groove structure, allowing for the deposition of an insulating oxide layer that fills this gap. These two scenarios are described below.
[0095] The following first describes the first filling method of filling the double trench structure with insulating material involved in step S103: depositing insulating material in the double trench structure, wherein the deposited insulating material at least fills the double trench structure.
[0096] Based on the two methods of forming the double trench structure involved in step S102, the double trench structures obtained by the above two methods are filled with isolation material according to the first filling method in step S103, so as to obtain two implementation processes of the isolation structure as a bipolar element-CMOS-DMOS device.
[0097] The first implementation of the isolation structure can be achieved through... Figures 2 to 8 The second implementation of the isolation structure can be described as follows: Figures 9 to 18 Describe it.
[0098] In the first implementation of the isolation structure, Figures 2 to 4 The first method of forming the double-groove structure has been described in step S102. Figures 5 to 8 The process of obtaining an isolation structure by filling the isolation material in a double-groove structure according to the first filling method is described in detail below.
[0099] The insulating material filling the dual-trench structure includes insulating materials, which are mainly used to isolate different device areas, reduce crosstalk, and improve the overall performance of the integrated circuit. The insulating filling materials include, but are not limited to: silicon dioxide (SiO2), silicon nitride (Si3N4), borosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, and high-molecular-weight organic polymers.
[0100] Trench filling is a process in semiconductor manufacturing where material (e.g., dielectric, metal, or polysilicon) is deposited into etched trenches, vias, or other high aspect ratio structures. The primary goals are to achieve void-free filling, high uniformity, and process compatibility. Void-free filling prevents electrical failures or reduced mechanical strength due to incomplete trench filling. High uniformity includes consistent material thickness throughout the trench. Process compatibility ensures seamless integration of the trench filling process with subsequent semiconductor device fabrication processes (e.g., etching or chemical mechanical polishing).
[0101] The filling process used to fill the insulating material in the double trench structure is related to the material type of the insulating material, the aspect ratio of the trench, and the requirements of subsequent processes. The filling process may include, but is not limited to: (1) High-density plasma chemical vapor deposition: Double trenches are deposited by high-energy plasma to achieve good step coverage and gap filling ability. This makes the insulating filling material in the trench achieve the effect of high filling density and few voids. (2) Sub-atmospheric pressure chemical vapor deposition: Oxides are deposited under low pressure, which makes the filling uniformity of the trench better. The filling process used in the embodiments of this application is to deposit insulating filling material on the semiconductor substrate forming the double trench structure by at least one of the above methods, so that the filled trenches achieve the effects of high and uniform filling density, few voids, and no gaps.
[0102] Figure 5 This is a first schematic diagram illustrating the filling of an insulating material into a double-trench structure in a method for fabricating a semiconductor device according to an embodiment of this application. Specifically, the insulating material 11 deposited within the double-trench structure at least completely fills the double-trench structure. During the process of filling the double trenches with the insulating material 11, the insulating material 11 is also deposited on the surface of the first hard mask layer 05 of the semiconductor substrate and on the surface of the top region of the double trenches. Figure 5 The insulating material layer 10 shown.
[0103] Therefore, after filling the double trench structure with insulating material, it is necessary to remove the insulating material layer 10 and the first hard mask layer 05 on the semiconductor substrate in sequence. The removal process stops at the first passivation oxide layer 04, and polysilicon is filled on the first passivation oxide layer 04.
[0104] Specifically, this includes the following: First, removing the insulating material layer 10 on the surface of the first hard mask layer 05 by etching or grinding, such as... Figure 6 As shown, the process includes at least one of the following methods: removing the insulating material layer 10 by an etching process, wherein the removal process stops at the first hard mask layer 05; or removing the insulating material layer 10 by a polishing process, wherein the polishing process stops at the first hard mask layer 05.
[0105] The etching rate of the insulating material layer is different from the etching rate of the first hard mask layer. The time to stop the etching process can be determined by the change in etching rate during the etching of the insulating material layer.
[0106] Grinding is a key technology for planarizing the surface of semiconductor substrates through mechanical or chemical mechanical action. It is primarily used to eliminate surface irregularities, improve surface roughness, control material thickness, or achieve global planarization. Grinding processes include, but are not limited to: Mechanical Grinding, Chemical Mechanical Polishing (CMP), and Electrochemical Mechanical Polishing (ECMP). Mechanical Grinding uses diamond or alumina grinding wheels to directly cut the material surface and is suitable for rough grinding of the back side of wafers. Chemical Mechanical Polishing combines chemical etching (oxidants in the slurry) with mechanical friction (polishing pads) to achieve material removal and is used for global planarization of polysilicon layers, copper interconnects, and shallow trenches. Electrochemical Mechanical Polishing introduces an electric field based on Chemical Mechanical Polishing to electrochemically dissolve and assist in material removal, reducing mechanical stress. It is suitable for ultra-thin devices and is mainly used for stress-free polishing of copper interconnects.
[0107] If the insulating material is polycrystalline silicon, chemical mechanical polishing (also known as chemical mechanical abrasion) is typically used to remove the insulating material from the semiconductor substrate. This embodiment of the application selects chemical mechanical polishing, which combines chemical reaction and mechanical abrasion to achieve higher flatness and smoothness.
[0108] The insulating material layer 10 and the first hard mask layer 05 are different materials. The different materials have the following differences, and the grinding process of the insulating material can be judged based on the following aspects: (1) Optical endpoint detection: The insulating material layer 10 and the first hard mask layer 05 have different refractive indices, and the intensity and wavelength of the reflected light will change. The grinding process of the insulating material layer 10 is determined by monitoring the changes in the reflected light generated during the grinding process. (2) Friction monitoring: The friction between the insulating material layer 10 and the first hard mask layer 05 and the grinding head is different. The grinding process of the insulating material layer 10 is determined by monitoring the difference in the friction coefficient between the grinding head and the grinding surface. (3) Acoustic endpoint detection: The changes in the sound characteristics of the interface between the different materials are monitored by ultrasonic waves or other acoustic methods to determine whether the grinding process of the insulating material layer 10 is complete.
[0109] The second step involves removing the first hard mask layer 05 from the surface of the first passivation oxide layer 04 by etching or grinding, such as... Figure 7 As shown, the process includes at least one of the following methods: removing the first hard mask layer 05 by an etching process, wherein the removal process stops at the first passivation oxide layer 04; or removing the first hard mask layer 05 by a polishing process, wherein the polishing process stops at the first passivation oxide layer 04. Accordingly, the etching rate of the first hard mask layer and the etching rate of the first passivation oxide layer are different, and the time to stop the etching process can be determined by the change time of the etching rate during the etching of the first hard mask layer. The purpose of retaining the first passivation oxide layer is to prevent contamination or oxidation of the silicon surface during subsequent polysilicon filling, reduce interface state density, isolate the metal layer, avoid short circuits, and alleviate mechanical stress inside the device.
[0110] The third step is to fill polysilicon 12 onto the first passivation oxide layer 04, such as... Figure 8 As shown, polysilicon 12 is filled on the surface of the first passivation oxide layer 04 and a portion of the shallow trench filled with insulating material to form a gate electrode. The first passivation oxide layer serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.
[0111] The above describes the first implementation process of obtaining a double-trench structure using the first formation method and filling the double-trench structure with isolation material using the first filling method to obtain an isolation structure. In this process, a double-trench structure is obtained by first forming shallow trenches and then forming deep trenches, followed by filling the double-trench structure with isolation material. This method reduces the number of process steps in the trench structure formation and filling processes, thereby reducing the number of device defects caused to the pre-formed bipolar element-CMOS-DMOS device on the semiconductor substrate, thus improving the electrical stability of the device.
[0112] The following combination Figures 9 to 18 Describe the second implementation process of the isolation structure. Among them, Figures 9 to 14 A second method for forming the double-groove structure is described, in which a second groove is first formed, and a first groove is formed in the top region corresponding to the second groove, as described in step S102. Figures 15 to 18 The process of obtaining an isolation structure by filling the isolation material in a double-groove structure according to the second filling method is described in detail below.
[0113] The insulating material filling the double-groove structure here includes an insulating material, which can be the same as the insulating material used in the first method of forming the insulating structure, as described in the corresponding description in the first method of forming the insulating structure. Figure 15 This is a second schematic diagram illustrating the filling of an insulating material into a double-trench structure in a method for fabricating a semiconductor device according to an embodiment of this application. Specifically, an insulating material 11 is deposited within the double-trench structure, and the deposited insulating material 11 at least fills the double-trench structure. During the process of filling the double trenches with the insulating material 11, the insulating material 11 is also deposited on the surface of the third hard mask layer 17 of the semiconductor substrate and on the surface of the top region of the double trenches, i.e. Figure 15 The insulating material layer 10 shown.
[0114] Therefore, after filling the double trench structure with insulating material, it is necessary to remove the insulating material layer 10 and the third hard mask layer 17 on the semiconductor substrate in sequence. The removal process stops at the third passivation oxide layer 16, and polysilicon is filled on the third passivation oxide layer 16.
[0115] Specifically, this includes the following: First, removing the insulating material layer 10 on the surface of the third hard mask layer 17 by etching or grinding, such as... Figure 16 As shown, the method includes at least one of the following: removing the insulating material layer 10 by an etching process, wherein the removal process stops at the third hard mask layer 17; or removing the insulating material layer 10 by a polishing process, wherein the polishing process stops at the third hard mask layer 17.
[0116] The process for removing the insulating material layer 10 here is the same as the removal process used in the formation of the first isolation structure, as described above.
[0117] The second step involves removing the third hard mask layer 17 from the surface of the third passivation oxide layer 16 by etching or grinding, such as... Figure 17 As shown, the process includes at least one of the following methods: removing the third hard mask layer 17 by an etching process, wherein the removal process stops at the third passivation oxide layer 16; or removing the third hard mask layer 17 by a polishing process, wherein the polishing process stops at the third passivation oxide layer 16. Accordingly, the etching rates of the third hard mask layer 17 and the third passivation oxide layer 16 are different, and the time to stop the etching process can be determined by the change in etching rate during the etching of the third hard mask layer 17. The purpose of retaining the third passivation oxide layer 16 is to prevent contamination or oxidation of the silicon surface during subsequent polysilicon filling, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress inside the device.
[0118] The third step is to fill the third passivation oxide layer 16 with polysilicon 12, such as... Figure 18 As shown, polysilicon 12 is filled on the surface of the third passivation oxide layer 16 and a portion of the shallow trench that has been filled with insulating material to form a gate electrode. The third passivation oxide layer serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.
[0119] The above describes the second implementation process of obtaining a double-trench structure using the second formation method and filling the double-trench structure with isolation material using the first filling method to obtain an isolation structure. In this process, a double-trench structure is obtained by first forming a deep trench and then a shallow trench, followed by filling the double-trench structure with isolation material. This method reduces the number of process steps in the trench structure formation and filling processes, thereby reducing the number of device defects caused to the pre-formed bipolar element-CMOS-DMOS device on the semiconductor substrate, thus improving the electrical stability of the device.
[0120] The above describes the first and second implementation processes of obtaining the isolation structure by combining the double-groove structure obtained by the two formation methods involved in step S102 with the double-groove structure obtained by filling it according to the first filling method in step S103.
[0121] The following describes the third and fourth implementation processes of obtaining the double-groove structure obtained by the two formation methods involved in step S102, respectively, in combination with the third and fourth implementation processes of obtaining the isolation structure after filling the double-groove structure according to the second filling method involved in step S103.
[0122] First, the second filling method involving filling the double trench structure with an insulating material in step S103 is described: an insulating material is deposited in the double trench structure, and the deposited insulating material forms a gap at the central axis position of the double trench structure; the bottom of the second trench in the double trench structure is etched and ion implantation is performed at the bottom; an insulating oxide layer corresponding to the insulating material is formed at the gap, and the formed insulating oxide layer at least fills the gap.
[0123] Based on the two methods of forming the double trench structure involved in step S102, the double trench structures obtained by the above two methods are filled with isolation material according to the second filling method in step S103, so as to obtain two implementation processes of the isolation structure as a bipolar element-CMOS-DMOS device.
[0124] The third implementation process of the isolation structure can be referred to Figures 2 to 4 ,as well as Figures 19 to 24 The fourth implementation process of the isolation structure can be described in detail. Figures 9 to 14 ,as well as Figures 25 to 30 Describe it.
[0125] First, let's describe the third implementation process of the isolation structure: Figures 2 to 4 The first method of forming the double-groove structure has been described in step S102. Figures 19 to 24 The process of obtaining an isolation structure by filling the isolation material in a double-groove structure according to the second filling method is described in detail below.
[0126] The type of insulating material used to fill the double-groove structure is the same as that used in the first filling method described above. For details, please refer to the description of the insulating material in the first filling method described above.
[0127] Combination Figure 19 It is known that in the second filling method, the insulating material used for filling includes an insulating material sidewall layer 19 located on the inner sidewall of the double trench structure and an insulating material layer 10 located on the surface of the first hard mask layer 05 on the semiconductor substrate. In this case, a gap 20 exists at the central axis of the double trench structure. Therefore, it is necessary to fill the gap 20 to completely fill the double trench structure. Before performing the filling process on the gap 20, the bottom of the gap 20 is first etched and ion implanted, such as... Figure 20 As shown, ion 21 was injected into the bottom.
[0128] Ion implantation at the bottom of the deep trench is an optional process step. In other embodiments, ion implantation may be omitted, and insulating material may be directly filled into the trench.
[0129] The ion implantation process involves placing a wafer into an ion implanter, selecting appropriate dopant elements based on design requirements, and determining the implantation energy and dosage. The implantation energy determines the depth to which ions can penetrate, while the dosage controls the doping concentration. For ion implantation at the bottom of deep trenches, higher energy is typically required to ensure ions reach the trench bottom. Performing ion implantation is used to customize the electrical properties of different regions within a semiconductor device to meet specific application requirements.
[0130] In addition, a high-temperature annealing process is required after ion implantation. This step helps activate the implanted impurity atoms and repairs crystal damage caused by ion bombardment.
[0131] Then, an insulating oxide layer is filled into the gap 20. Specifically, this can be achieved by oxidizing the insulating material. To ensure the insulating oxide layer completely fills the gaps within the double-trench structure, the insulating oxide layer used in this process includes a first insulating oxide layer 22-1 located on the semiconductor substrate and a second insulating oxide layer 22-2 located on the insulating sidewall layer 19 within the double-trench structure, such as... Figure 21 As shown.
[0132] It can obtain an oxide layer of insulating material by low-temperature oxidation of the insulating material, which can fill the gaps. Moreover, the low-temperature oxidation process can reduce device defects caused to the bipolar element - CMOS - DMOS device area.
[0133] Then, after obtaining the filled double trench structure, the process further includes: sequentially removing the insulating oxide layer, the insulating layer, and the first hard mask layer on the semiconductor substrate, with the removal process stopping at the first passivation oxide layer; and filling the first passivation oxide layer with polysilicon.
[0134] Specific combination Figure 22 The first insulating oxide layer 22-1 and the insulating layer 10 on the semiconductor substrate are removed by etching and / or grinding. After removal, the first hard mask layer 05 is exposed, resulting in... Figure 22 The diagram shown is shown in the image.
[0135] Then, the first hard mask layer 05 is removed, while the first passivation oxide layer 04 is retained. Figure 23 The diagram shows a structure for removing the first hard mask layer 05 while retaining the first passivation oxide layer 04. The purpose of retaining the first passivation oxide layer 04 is to prevent contamination or oxidation of the silicon surface during subsequent polysilicon filling, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device.
[0136] After the above steps, the process further includes: filling the first passivation oxide layer with polysilicon. For example... Figure 24 As shown, polysilicon 12 is filled on the surface of the first passivation oxide layer 04 and a portion of the shallow trench that has been filled with insulating material to form a gate electrode. The first passivation oxide layer 04 serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.
[0137] The above describes the third implementation process: obtaining a double-trench structure using the first formation method and filling the double-trench structure with isolation material using the second filling method to obtain an isolation structure. In the above process, a double-trench structure is obtained by first forming shallow trenches and then forming deep trenches. Then, isolation material is filled into the double-trench structure. This method reduces the number of process steps in the trench structure formation and filling processes, thereby reducing the number of device defects caused to the pre-formed bipolar element—CMOS-DMOS device—on the semiconductor substrate, thus improving the electrical stability of the device.
[0138] The following is passed Figures 9 to 14 ,as well as Figures 25 to 30 Describe the fourth implementation process of the isolation structure. Figures 9 to 14 A second method of forming the double-groove structure has been described in step S102. Figures 25 to 30 The process of obtaining an isolation structure by filling the isolation material in a double-groove structure according to the second filling method is described in detail below.
[0139] The type of insulating material used to fill the double-groove structure is the same as that used in the first filling method described above. For details, please refer to the description of the insulating material in the first filling method described above.
[0140] Combination Figure 25 It is known that the third passivation oxide layer 16 and the third hard mask layer 17 located on the semiconductor substrate are formed during the process of forming the double trench structure in step S102 using the second method. During the process of filling the double trench structure with insulating material according to the second filling method in step S103, the filled insulating material includes the insulating material sidewall layer 19 located on the inner sidewall of the double trench structure and the insulating material layer 10 located on the surface of the third hard mask layer 17 on the semiconductor substrate.
[0141] In addition, in the second filling method, there is a gap 20 at the central axis of the double-groove structure in the filling insulating material. Therefore, it is necessary to fill the gap 20 to completely fill the double-groove structure. Before performing the filling process on the gap 20, the bottom of the gap 20 is first etched and ion implanted, such as... Figure 26As shown. The process of creating the gap and performing bottom etching and ion implantation at the gap is similar to the third implementation of the isolation structure, and can be referred to the above description.
[0142] Then, an insulating oxide layer is filled into the gap 20. Specifically, this can be achieved by oxidizing the insulating material. To ensure the insulating oxide layer completely fills the gaps within the double-trench structure, the insulating oxide layer used in this process includes a first insulating oxide layer 22-1 located on the semiconductor substrate and a second insulating oxide layer 22-2 located on the insulating sidewall layer 19 inside the double-trench structure, such as... Figure 27 As shown. The process of obtaining the insulating oxide layer is consistent with the description in the third implementation process of the isolation structure, and can be referred to the corresponding description.
[0143] After obtaining the filled double trench structure, the process further includes: sequentially removing the insulating oxide layer, the insulating layer, and the third hard mask layer on the semiconductor substrate, with the removal process stopping at the third passivation oxide layer; and filling the third passivation oxide layer with polysilicon.
[0144] Specific combination Figure 27 The first insulating oxide layer 22-1 and the insulating layer 10 on the semiconductor substrate are removed by etching and / or grinding. After removal, the third hard mask layer 17 is exposed, resulting in... Figure 28 The diagram shown is shown in the image.
[0145] Then, the third hard mask layer 17 is removed, while the third passivation oxide layer 16 is retained. Figure 29 The diagram shows the structure of removing the third hard mask layer 17 while retaining the third passivation oxide layer 16. The purpose of retaining the third passivation oxide layer 16 is to prevent contamination or oxidation of the silicon surface during subsequent polysilicon filling, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device.
[0146] Following the above steps, the process further includes filling the third passivation oxide layer with polysilicon. For example... Figure 30 As shown, polysilicon 12 is filled on the surface of the third passivation oxide layer 16 and a portion of the shallow trench that has been filled with insulating material to form a gate electrode. The third passivation oxide layer 16 serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.
[0147] The above describes the fourth implementation process for obtaining a double-trench structure using the second formation method and filling the double-trench structure with isolation material using the second filling method. In this process, a double-trench structure is obtained by first forming a deep trench and then a shallow trench. Then, isolation material is filled into the double-trench structure. This method reduces the number of process steps in the trench formation and filling processes, thereby reducing the number of device defects caused to the pre-formed bipolar element—CMOS-DMOS device—on the semiconductor substrate, thus improving the electrical stability of the device.
[0148] The second embodiment of this application provides a bipolar element-CMOS-DMOS semiconductor device, comprising: a semiconductor substrate, a bipolar element-CMOS-DMOS device region formed on the semiconductor substrate; a double-trench structure formed between any two of the bipolar element, CMOS, and DMOS device regions, including a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located in the first trench and has a depth greater than the first trench; and an isolation material is filled in the double-trench structure to form an isolation structure for the bipolar element-CMOS-DMOS device. The semiconductor device provided in this embodiment can be obtained by the fabrication method of the bipolar element-CMOS-DMOS semiconductor device provided in the first embodiment of this application. For details, please refer to the detailed description of the fabrication method of the bipolar element-CMOS-DMOS semiconductor device provided in the first embodiment of this application, which will not be repeated here.
[0149] The bipolar-CMOS-DMOS semiconductor device provided in the second embodiment of this application integrates a bipolar transistor, a complementary metal-oxide-semiconductor (CMOS), and a diffused metal-oxide-semiconductor (DMOS) onto the same chip. For example... Figure 31 As shown, the structure includes a semiconductor substrate 01, an epitaxial layer 03 on the semiconductor substrate, and an active layer 23 disposed on the semiconductor substrate. The active layer 23 includes an NPN bipolar junction transistor (NPN BJT) 2301, a complementary metal-oxide-semiconductor (CMOS) transistor 2302, an N-channel laterally diffused metal-oxide-semiconductor (N-LDMOS) transistor 2303, and a P-channel laterally diffused metal-oxide-semiconductor (P-LDMOS) transistor 2304. The NPN transistor is one of the core components of a bipolar transistor, primarily used for high-precision analog signal processing, high-speed switching, or driving circuits.
[0150] In the fabrication of semiconductor devices, a bipolar CMOS-DMOS device is first formed on a semiconductor substrate. Then, a deep trench isolation wall structure is formed between any two device regions within the bipolar CMOS-DMOS device. To reduce device defects caused by the formation of the deep trench isolation wall structure, the method provided in the first embodiment of this application is adopted. A double-trench structure containing shallow and deep trenches is first formed using a damascus process, and then an isolation material is filled within the double-trench structure. The methods for forming the double-trench structure include at least the two formation methods involved in step S102 of the first embodiment, and the methods for filling the double-trench structure with isolation material include at least the two filling methods involved in step S103 of the first embodiment. The resulting isolation structure reduces the number of process steps in the formation of the double-trench structure and the filling of the isolation material, thereby reducing the number of device defects caused by the bipolar CMOS-DMOS device formed on the semiconductor substrate and improving the electrical stability of the device.
[0151] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. A method for fabricating a bipolar-CMOS-DMOS semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided on which a bipolar element-CMOS-DMOS device region is formed; Between any two of the isolation regions of the bipolar element, CMOS, and DMOS devices, a dual trench structure is formed, including a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located in the first trench and has a depth greater than the first trench. The dual trench structure is filled with an isolation material to form an isolation structure for a bipolar element-CMOS-DMOS device; The formation of the double-groove structure, comprising a first trench for shallow trench isolation and a second trench for deep trench isolation, includes: A second passivation oxide layer and a second hard mask layer are formed on the epitaxial layer of the semiconductor substrate; the second hard mask layer is etched to form the second trench on the semiconductor substrate; the second hard mask layer and the second passivation oxide layer are removed; a third passivation oxide layer and a third hard mask layer are re-formed on the epitaxial layer of the semiconductor substrate; an etching process is performed on the third hard mask layer in a predetermined area corresponding to the top position of the second trench to form the first trench on the epitaxial layer of the semiconductor substrate.
2. The method according to claim 1, characterized in that, The filling of the double-groove structure with an insulating material includes: An insulating material is deposited within the double trench structure, wherein the deposited insulating material at least fills the double trench structure, including: the deposited insulating material fills the double trench structure, and an insulating material layer is deposited on the surface of the third hard mask layer and the surface of the top region of the double trench.
3. The method according to claim 1, characterized in that, The filling of the double-groove structure with an insulating material includes: An insulating material is deposited within the double trench structure. The deposited insulating material forms a gap at the central axis of the double trench structure. The deposited insulating material includes an insulating material sidewall layer located on the inner sidewall of the double trench structure and an insulating material layer located on the surface of the third hard mask layer on the semiconductor substrate. The second trench in the dual-trench structure is bottom-etched and ion implanted at the bottom. An insulating oxide layer corresponding to the insulating material is formed at the gap, and the formed insulating oxide layer at least fills the gap.
4. The method according to claim 2, characterized in that, Also includes: The insulating material layer and the third hard mask layer on the semiconductor substrate are removed sequentially, and the removal process stops at the third passivation oxide layer. Polycrystalline silicon is filled on the third passivation oxide layer.
5. The method according to claim 3, characterized in that, Also includes: The insulating oxide layer, the insulating layer, and the third hard mask layer on the semiconductor substrate are removed sequentially, and the removal process stops at the third passivation oxide layer. Polycrystalline silicon is filled on the third passivation oxide layer.
6. A bipolar-CMOS-DMOS semiconductor device, fabricated by the method described in any one of claims 1 to 5, characterized in that, include: A semiconductor substrate, on which a bipolar element-CMOS-DMOS device region is formed; A dual-trench structure is formed between any two of the bipolar element, CMOS, and DMOS device regions, including a first trench for a shallow trench isolation structure and a second trench for a deep trench isolation structure, wherein the second trench is located in the first trench and has a depth greater than the first trench. The dual trench structure is filled with an isolation material to form an isolation structure for a bipolar element-CMOS-DMOS device.