Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate, an electrostatic discharge circuit, a first metal layer, an organic film layer, an inorganic packaging layer and a first binding part. The electrostatic discharge circuit includes a first voltage line; the first metal layer is located in the display area, the first area, the second area and the third area; the organic film layer comprises a retaining wall part and a flat part, the retaining wall part is located in the first area, and the flat part is located in the second area; the inorganic packaging layer is continuously arranged in the display area, the first area and the second area, the edge of the side, away from the display area, of the inorganic packaging layer is flush with the edge of the side, away from the display area, of the first voltage line, and the first binding part is electrically connected with the first voltage line. According to the invention, the water oxygen corrosion of the metal wire between the binding area and the retaining wall structure can be reduced, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In the related art, in order to reduce the water and oxygen corrosion of the metal wires between the binding area and the retaining wall structure, two structures are usually used. One is to set a passivation layer on the metal wires, and extend the passivation layer to the vicinity of the binding area. The passivation layer can reduce the water and oxygen corrosion of the metal wires between the binding area and the retaining wall structure. The other is to set a touch substrate on the driving substrate, the touch substrate is formed by a touch electrode and two inorganic layers, and the inorganic layer of the touch substrate is extended to the vicinity of the binding area. The inorganic layer of the touch substrate can also reduce the water and oxygen corrosion of the metal wires between the binding area and the retaining wall structure.

[0003] However, in a display panel structure currently launched, the film layer structure of the touch substrate and the passivation layer is cancelled for the purpose of cost reduction, and only the remaining structure is reserved. At this time, only organic material is left above the metal wires between the binding area and the retaining wall structure. The organic material cannot block the invasion of water and oxygen, so that the metal wires between the binding area and the retaining wall structure are easily corroded by water and oxygen. After the metal wires in this part are corroded by water and oxygen, dark spots appear on the edge of the display picture, which affects the display effect.

[0004] Therefore, it is necessary to propose a new technical scheme to solve the above technical problems. SUMMARY

[0005] The purpose of the present application is to provide a display panel and a display device, which can reduce the water and oxygen corrosion of the metal wires between the binding area and the retaining wall structure, and improve the display effect.

[0006] To solve the above problems, the technical scheme of the present application is as follows: In a first aspect, the present application provides a display panel, which has a display area and a non-display area located on at least one side of the display area, the non-display area includes a first area, a second area and a third area connected in sequence on one side of the display area; The display panel comprises: a substrate; an electrostatic discharge circuit comprising a first voltage line; a first metal layer provided on one side of the substrate and located in the display area, the first area, the second area and the third area, part of the first metal layer located in the second area includes the first voltage line; an organic film layer disposed on a side of the first metal layer away from the substrate, the organic film layer including a barrier portion and a flat portion, the barrier portion being located in the first region, and the flat portion being located in the second region, the flat portion covering the first voltage line; an inorganic encapsulation layer continuously disposed on a side of the display region and the organic film layer away from the substrate, in a thickness direction of the display panel, the inorganic encapsulation layer being flush with the first voltage line away from a side edge of the display region; and a first binding portion disposed in the third region and electrically connected to the first voltage line.

[0007] In an embodiment of the present application, the electrostatic discharge circuit further includes a second voltage line. The first metal layer in the second region includes the second voltage line, the second voltage line being located between the first voltage line and the display region, the second voltage line being spaced apart from the first voltage line along the first direction, the first voltage line and the second voltage line extending along the second direction, the first direction intersecting the second direction, the first direction pointing from the display region to the non-display region. The inorganic encapsulation layer covers the second voltage line. The display panel further includes a second binding portion, the second binding portion being electrically connected to the second voltage line.

[0008] In an embodiment of the present application, a distance between the binding portion and an edge of the inorganic encapsulation layer is less than or equal to 400 microns.

[0009] In an embodiment of the present application, the second region includes a first sub-region and a second sub-region connected to each other, the first sub-region being connected to the first region, and the second sub-region being connected to the third region. The flat portion includes a first flat sub-portion and a second flat sub-portion connected to each other, the first flat sub-portion being disposed in the first sub-region, and the second flat sub-portion being disposed in the second sub-region, the first flat sub-portion covering the first voltage line, and a projection of the first voltage line on the substrate being located close to a side of a projection of the second flat sub-portion on the substrate away from the display region. The inorganic encapsulation layer continuously covers the barrier portion and the first flat sub-portion, and an edge of the inorganic encapsulation layer stops at the second sub-region.

[0010] In an embodiment of the present application, the barrier wall portion includes a first barrier wall and a second barrier wall, the first barrier wall and the second barrier wall are arranged in the first area, the second barrier wall is located between the first barrier wall and the first flat sub-portion, the second barrier wall is arranged in the first flat sub-portion and forms a recess, and the recess exposes part of the first metal layer; The inorganic encapsulation layer covers the recess and the part of the first metal layer exposed by the recess.

[0011] In an embodiment of the present application, the display panel further includes a third binding portion, a fourth binding portion, and a fifth binding portion; The first metal layer includes a plurality of metal traces, and the plurality of metal traces includes: a first cathode line, one end of the first cathode line is electrically connected to the third binding portion, and the other end of the first cathode line extends to the display area; a first data line, one end of the first data line is electrically connected to the fourth binding portion, and the other end of the first data line extends to the display area; and a first power line, one end of the first power line is electrically connected to the fifth binding portion, and the other end of the first power line extends to the display area; The inorganic encapsulation layer covers the part of the first cathode line located in the second area, the part of the first data line located in the second area, and the part of the first power line located in the second area. An average width of the part of the metal trace overlapping the recess is less than an average width of the part of the metal trace overlapping the flat portion.

[0012] In an embodiment of the present application, the display panel further includes a sixth binding portion; The display panel further includes: a gate drive circuit arranged on one side of the substrate; and a first connection line arranged in the second area and electrically connecting the gate drive circuit and the sixth binding portion, a part of the first connection line is arranged in a different layer from the first metal layer, and the inorganic encapsulation layer covers the first connection line. In a plan view of the display panel, the part of the first cathode line located in the second area, the part of the first data line located in the second area, and the part of the first power line located in the second area all cross a part of the first connection line.

[0013] In an embodiment of the present application, in a plan view of the display panel, the plurality of metal traces located in the first area and the second area all extend in a first direction and are arranged in a second direction, the first direction intersects the second direction. The first connection line comprises: a connection portion, one end of the connection portion being electrically connected with the sixth binding portion, the other end of the connection portion extending in the first direction, the connection portion being located in the second area; a cross-line portion, one end of the cross-line portion being electrically connected with the one end of the connection portion away from the sixth binding portion, the cross-line portion extending in the second direction, the cross-line portion being located in the second area, the cross-line portion being different from the first metal layer in layer, in a plan view of the display panel, the part of the first cathode line located in the second area, the part of the first data line located in the second area, and the part of the first power line located in the second area all intersecting with the cross-line portion; an extension portion, one end of the extension portion being electrically connected with the one end of the cross-line portion away from the connection portion, the other end of the extension portion being electrically connected with the gate drive circuit, at least part of the extension portion being located in the second area; The first metal layer comprises the connection portion and the extension portion, the sheet resistance of the first metal layer being less than the sheet resistance of the cross-line portion. The inorganic encapsulation layer covers at least part of the connection portion, the cross-line portion and the extension portion.

[0014] In an embodiment of the present application, the display panel further comprises a seventh binding portion. The display panel further comprises: a second metal layer, disposed between the substrate and the first metal layer, the second metal layer comprising the cross-line portion; a first insulating layer, disposed between the second metal layer and the first metal layer; a third metal layer, disposed between the first insulating layer and the first metal layer, the third metal layer comprising a fan-out trace, the fan-out trace being electrically connected with the seventh binding portion; and an interlayer dielectric layer, disposed between the third metal layer and the first metal layer; The connection portion is connected with the cross-line portion through the interlayer dielectric layer and the first insulating layer, and the extension portion is connected with the cross-line portion through the interlayer dielectric layer and the first insulating layer.

[0015] In an embodiment of the present application, the first metal layer comprises: a first metal sub-layer, disposed on a side of the interlayer dielectric layer away from the substrate; a second metal sub-layer, disposed on a side of the first metal sub-layer away from the substrate; and a third metal sub-layer, disposed on a side of the second metal sub-layer away from the substrate; The sheet resistance of the first metal layer is less than the sheet resistance of the second metal layer.

[0016] In an embodiment of the present application, the second metal sub-layer includes cathode line metal sub-parts, data line metal sub-parts, and power line metal sub-parts arranged at intervals. The first cathode line includes the cathode line metal sub-parts, the first data line includes the data line metal sub-parts, and the first power line includes the power line metal sub-parts. The average width of the cathode line metal sub-parts in the first area is less than the average width of the cathode line metal sub-parts in the second area. The average width of the data line metal sub-parts in the first area is less than the average width of the data line metal sub-parts in the second area. The average width of the power line metal sub-parts in the first area is less than the average width of the power line metal sub-parts in the second area.

[0017] In an embodiment of the present application, the display panel further includes an eighth binding part and a ninth binding part. The first data line is in a plurality, and the plurality of first data lines are arranged at intervals between the first data line and the first power line. The plurality of metal traces further include: A second power line, one end of the second power line being electrically connected to the eighth binding part, and the other end of the second power line extending to the display area; and A second cathode line, one end of the second cathode line being electrically connected to the ninth binding part, and the other end of the second cathode line extending to the display area. The inorganic encapsulation layer covers the part of the second power line in the second area and the part of the second cathode line in the second area. In a plan view of the display panel, the plurality of metal traces in the first area and the part of the second area extend in a first direction, wherein the second cathode line, the second power line, the first cathode line, the plurality of first data lines, and the first power line are arranged in a second direction at intervals.

[0018] In an embodiment of the present application, the organic film layer is in direct contact with the first metal layer.

[0019] In an embodiment of the present application, the display panel further includes: An adhesive layer, arranged on the side of the inorganic encapsulation layer away from the substrate and in direct contact with the inorganic encapsulation layer; and A first film layer, arranged on the side of the adhesive layer away from the substrate and in direct contact with the adhesive layer. The first film layer is one of a cover plate or an optical film.

[0020] In a second aspect, the present application provides a display device, comprising a display panel having a display area and a non-display area located at least one side of the display area, the non-display area comprising a first area, a second area and a third area connected in sequence at one side of the display area; the display panel comprising a substrate, an electrostatic discharge circuit, a first metal layer, an organic film layer, an inorganic encapsulation layer and a first binding portion, the electrostatic discharge circuit comprising a first voltage line; the first metal layer is located at one side of the substrate and located in the display area, the first area, the second area and the third area, part of the first metal layer located in the second area comprising the first voltage line; the organic film layer is located at one side of the first metal layer away from the substrate, comprising a barrier portion and a flat portion, the barrier portion is located in the first area, the flat portion is located in the second area, and the flat portion covers the first voltage line; the inorganic encapsulation layer is continuously provided at one side of the display area and one side of the organic film layer away from the substrate, in the thickness direction of the display panel, one side edge of the inorganic encapsulation layer away from the display area is flush with one side edge of the first voltage line away from the display area; the first binding portion is provided in the third area and electrically connected with the first voltage line.

[0021] In the present application, the area between the first binding portion and the barrier portion is the second area. The flat portion covers the first metal layer located in the second area, and the flat portion is part of the organic film layer and cannot block the invasion of water and oxygen into the first metal layer. The inorganic encapsulation layer has good water and oxygen blocking effect, and the present application extends the inorganic encapsulation layer to the second area, so that one side edge of the inorganic encapsulation layer away from the second area is flush with one side edge of the first voltage line away from the display area, thereby making the inorganic encapsulation layer cover the first metal layer located in the second area, reducing the water and oxygen corrosion of the first metal layer located in the second area, and improving the display effect. The first binding portion of the present application is located in the third area, and since the edge of the inorganic encapsulation layer is located in the second area, the extended inorganic encapsulation layer will not cover the first binding portion in the subsequent process of binding the chip or the chip packaging structure to the first binding portion, which can guarantee the normal binding requirement of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0023] For a more complete understanding of the present application and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which like numbers represent like parts.

[0024] Figure 1 is a schematic diagram of a display panel of the related art; Figure 2 is a plan view of an embodiment of the display panel of the present application; Figure 3 is Figure 2 is an enlarged view of B in Figure 4 is Figure 3 is a sectional view along the section line C-C' in Figure 5 is Figure 2 is a sectional view along the section line D-D' in Figure 6 is a plan view of another embodiment of the display panel of the present application; Figure 7 is a sectional view of still another embodiment of the display panel of the present application.

[0025] BRIEF DESCRIPTION OF DRAWINGS 100, display panel; 200, chip; NA, non-display area; NA1, first area; NA2, second area; NA21, first sub-area; NA22, second sub-area; NA3, third area; D1, first direction; D2, second direction; 10, first metal layer; VSS1, first cathode line; VI, first data line; VDD1, first power supply line; VSS2, second cathode line; VDD2, second power supply line; 20, organic film layer; 21, barrier wall part; 211, first barrier wall; 212, second barrier wall; 22, flat part; 221, first flat sub-part; 222, second flat sub-part; T, recessed part; 30, inorganic encapsulation layer; S, shadow part; 40, first connection line; 41, connection part; 42, cross line part; 43, extension part; 50, fan-out wiring; 61, substrate; 62, first insulating layer; 63, interlayer dielectric layer; P1, first binding part; P2, second binding part; P3, third binding part; P4, fourth binding part; P5, fifth binding part; P6, sixth binding part; P7, seventh binding part; P8, eighth binding part; P9, ninth binding part; ESD, electrostatic discharge circuit; VGL, first voltage line; VGH, second voltage line. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0027] Please refer to Figure 1 In the organic light emitting display panel without a touch substrate and a passivation layer in the related art, the inorganic encapsulation layer 30a is cut off at the outside of the barrier structure 21a, and the organic film layer 20a above the metal trace 10a between the barrier structure 21a and the bonding part P cannot play a role of blocking water and oxygen, resulting in that the metal trace 10a between the bonding part P and the barrier structure 21a is easily corroded by water and oxygen.

[0028] The display device can be a tablet computer, an electronic reader, an electronic display screen, a notebook computer, a mobile phone, an augmented reality (AR) \ virtual reality (VR) device, a media player, a wearable device, a digital camera, a vehicle-mounted navigator, etc. The display device includes a display panel.

[0029] Optionally, the display panel 100 is an organic light emitting diode (OLED) display panel 100. The difference between the organic light emitting diode display panel 100 and the liquid crystal display panel 100 is that the organic light emitting display panel 100 is provided with a light emitting device for active light emission in the display area, and light emission can be achieved without a backlight module.

[0030] Please refer to Figure 2 The display panel 100 proposed in the present application has a display area and a non-display area NA located at least one side of the display area. The non-display area NA includes a first area NA1, a second area NA2 and a third area NA3 connected to one side of the display area in sequence.

[0031] The display panel 100 includes a substrate 61, an electrostatic discharge circuit ESD, a first metal layer 10, an organic film layer 20, an inorganic encapsulation layer 30 and a first bonding part P1.

[0032] The electrostatic discharge circuit ESD includes a first voltage line VGL.

[0033] The first metal layer 10 is arranged at one side of the substrate 61 and located in the display area, the first area NA1, the second area NA2 and the third area NA3.

[0034] Please refer toFigure 3 The portion of the first metal layer 10 located in the second area NA2 includes the first voltage line VGL.

[0035] Referring to Figure 4 The organic film layer 20 is located on the side of the first metal layer 10 away from the substrate 61. The organic film layer 20 includes a barrier wall portion 21 and a flat portion 22. The barrier wall portion 21 is located in the first area NA1. The flat portion 22 is located in the second area NA2. The flat portion 22 covers the first voltage line VGL.

[0036] The inorganic encapsulation layer 30 is continuously provided on the side of the display area and the organic film layer 20 away from the substrate. In the thickness direction of the display panel, the side edge of the inorganic encapsulation layer 30 away from the display area is flush with the side edge of the first voltage line VGL away from the display area.

[0037] The first binding portion P1 is provided in the third area NA3 and is electrically connected with the first voltage line VGL.

[0038] In the embodiment, the region between the first binding portion P1 and the barrier wall portion 21 is the second area NA2. The flat portion 22 is provided on the first metal layer 10 located in the second area NA2 and is a part of the organic film layer 20, which cannot block the water and oxygen from invading the first metal layer 10. The inorganic encapsulation layer 30 has a good water and oxygen blocking effect. In the embodiment, the inorganic encapsulation layer 30 is extended to the second area NA2, so that the side edge of the inorganic encapsulation layer 30 away from the second area NA2 is flush with the side edge of the first voltage line VGL away from the display area, thereby making the inorganic encapsulation layer 30 cover the first metal layer 10 located in the second area NA2, reducing the water and oxygen corrosion of the first metal layer 10 located in the second area NA2, and improving the display effect. The first binding portion P1 of the present application is located in the third area. Since the edge of the inorganic encapsulation layer 30 is located in the second area, in the subsequent process of binding the chip 200 or the chip 200 encapsulation structure to the first binding portion P1, the extended inorganic encapsulation layer 30 will not cover the first binding portion P1, which can guarantee the normal binding requirement of the display panel 100.

[0039] Referring to Figure 3 Optionally, the electrostatic discharge circuit ESD further includes a second voltage line VGH.

[0040] The portion of the first metal layer 10 located in the second area NA2 includes the second voltage line VGH. The second voltage line VGH is located between the first voltage line VGL and the display area. The second voltage line VGH is provided in the first direction D1 away from the first voltage line VGL. The first voltage line VGL and the second voltage line VGH extend in the second direction D2. The first direction D1 intersects with the second direction D2, and the first direction D1 points from the display area to the non-display area NA.

[0041] Referring to Figure 4The inorganic encapsulation layer 30 covers the second voltage line VGH.

[0042] The display panel further comprises a second binding portion P2. The second binding portion P2 is electrically connected with the second voltage line VGH.

[0043] In the embodiment, the electrostatic discharge circuit ESD comprises the first voltage line VGL and the second voltage line VGH. When the static charge invades the first metal layer 10, the electrostatic discharge circuit ESD can quickly and safely discharge the invading static charge to the first voltage line VGL and the second voltage line VGH. The inorganic encapsulation layer 30 covers the first voltage line VGL and the second voltage line VGH, which can prevent the first voltage line VGL and the second voltage line VGH from being corroded by water and oxygen, ensure the electrostatic discharge effect of the electrostatic discharge circuit ESD, and improve the anti-static performance of the display panel.

[0044] Optionally, the second binding portion P2 is arranged apart from the first binding portion P1 along the second direction.

[0045] Optionally, the first voltage line VGL and the first binding portion P1 are connected by a wire.

[0046] Optionally, the second voltage line VGH and the second binding portion P2 are connected by a wire.

[0047] Optionally, the first binding portion P1 is arranged apart from the edge of the inorganic encapsulation layer 30 by a distance L1. Figure 4

[0048] The first binding portion P1 of the present application is arranged apart from the edge of the inorganic encapsulation layer 30 by a distance. In the subsequent process of binding the chip 200 or the chip 200 encapsulation structure to the first binding portion P1, if the binding precision of the chip 200 or the chip 200 encapsulation structure is low and the chip 200 or the chip 200 encapsulation structure is offset, the distance can ensure that the offset chip 200 or the chip 200 encapsulation structure is qualified for binding to the first binding portion P1.

[0049] Because of the distance, the inorganic encapsulation layer 30 does not cover the first binding portion P1, which results in that the offset chip 200 is unqualified for binding to the first binding portion P1.

[0050] The chip 200 encapsulation structure can be a chip on film (COF) or a chip on glass (COG). Herein, the chip 200 encapsulation structure is not limited.

[0051] ​Optionally, the inorganic encapsulation layer 30 includes a first inorganic encapsulation layer 30 and a second inorganic encapsulation layer 30 arranged in a stack. The first inorganic encapsulation layer 30 and the second inorganic encapsulation layer 30 are prepared by a chemical vapor deposition (CVD) method. During the preparation of the first inorganic encapsulation layer 30 and the second inorganic encapsulation layer 30 by the chemical vapor deposition method, a metal mask plate is used for film plating. There is a mechanical gap between the mask plate and the substrate. After the reaction gas of the chemical vapor deposition diffuses into the gap from above, a thickness-reduced inorganic encapsulation layer 30 is also deposited below the outside of the edge of the mask pattern. This section of the inorganic encapsulation layer 30 is referred to as the shadow S of the inorganic encapsulation layer 30. The shadow S is located on the side of the preset pattern of the inorganic encapsulation layer 30 close to the first bonding part P1. If the edge of the inorganic encapsulation layer 30 is designed to directly abut the first bonding part P1, the shadow S will cover part of the first bonding part P1 in actual production, resulting in a bonding failure problem. In actual production, the length of the shadow S is usually about 200 microns. The shadow S can be regarded as the edge of the inorganic encapsulation layer 30. Due to the influence of the process, the thickness of the shadow S gradually decreases in the direction away from the display area.

[0052] In consideration of the length of the shadow S and the offset of the chip 200, preferably, the distance L1 between the first bonding part P1 and the edge of the inorganic encapsulation layer 30 is in the range of 200 microns to 400 microns. When the distance between the first bonding part P1 and the edge of the inorganic encapsulation layer 30 is greater than or equal to 200 microns, the problem of bonding failure can be solved. When the distance L1 between the first bonding part P1 and the inorganic encapsulation layer 30 is less than or equal to 400 microns, the area of the part of the first metal layer 10 not covered by the inorganic encapsulation layer 30 can be reduced, thereby reducing the water and oxygen corrosion of the part of the first metal layer 10 located in the second area NA2.

[0053] It should be understood that the display panel 100 also needs to be subjected to RA testing before it is shipped. The RA testing is usually also referred to as double 85 testing. The display panel 100 is subjected to corresponding testing in an environment with an ambient temperature of 85 degrees Celsius and an ambient humidity of 85%. In the RA testing environment, if only the organic film layer 20 is arranged above the first metal layer 10 of the second area NA2, the organic film layer 20 cannot block the invasion of water and oxygen, and the RA testing will accelerate the water and oxygen corrosion of the first metal layer 10 of the second area NA2. However, in the present embodiment, the inorganic encapsulation layer 30 is arranged above the first metal layer 10 of the second area NA2, which can reduce the water and oxygen corrosion of the first metal layer 10 of the second area NA2 and improve the display effect.

[0054] Optionally, in an embodiment, the first bonding portion P1 is disposed in a layer different from the first metal layer 10. In this embodiment, the first metal layer 10 extends to the third area NA3. The organic film layer 20 extends to the third area NA3. After the organic film layer 20 is formed, a bonding hole is formed in the portion of the organic film layer 20 located in the third area NA3, and the bonding hole exposes the portion of the first metal layer 10 located in the third area NA3. After the bonding hole is formed, the first bonding portion P1 is formed on the organic film layer 20 in the third area NA3. The first bonding portion P1 passes through the bonding hole and is electrically connected to the first metal layer 10.

[0055] Please refer to Figure 5 Optionally, in another embodiment, the first bonding portion P1 is disposed in the same layer as the first metal layer 10, and the first metal layer 10 is integrally connected to the first bonding portion P1. Compared with the previous embodiment, one process of separately forming the first bonding portion P1 can be reduced, thereby achieving the effect of further reducing costs, and the thickness of the display panel 100 can be reduced, thereby achieving the design of an ultra-thin display panel 100.

[0056] In order to avoid redundancy, subsequent embodiments are described by taking the first bonding portion P1 disposed in the same layer as the first metal layer 10 and the first metal layer 10 integrally connected to the first bonding portion P1 as an example. However, embodiments in which the first bonding portion P1 is disposed in a layer different from the first metal layer 10 are not excluded.

[0057] Optionally, the organic film layer 20 is in direct contact with the first metal layer 10.

[0058] In this embodiment, in order to reduce costs, the film layer structure of the passivation layer between the first metal layer 10 and the organic film layer 20 is cancelled in the display panel 100 of this embodiment. After the first metal layer 10 is formed, the organic film layer 20 is directly formed on the side of the first metal layer 10 away from the substrate 61.

[0059] Optionally, the organic film layer 20 can be a single-layer structure or a multi-layer structure. When the organic film layer 20 is a single-layer structure, the thickness of the organic film layer 20 is relatively thin, and is suitable for a display panel 100 with a relatively thin thickness. When the organic film layer 20 is a multi-layer structure, the thickness of the organic film layer 20 is relatively thick, and is suitable for a display panel 100 with a relatively high flatness requirement.

[0060] Optionally, when the organic film layer 20 is a single-layer structure, the flat portion 22 is made of the same material as the flat layer under the anode in the display area, and is formed by the same process.

[0061] Optionally, when the organic film layer 20 is a double-layer structure, the flat portion 22 is also a double-layer structure. One layer of the flat portion 22 is made of the same material as the flat layer under the anode in the display area and is made in the same process. The other layer of the flat layer is made of the same material as the pixel defining layer in the display area and is made in the same process. The pixel defining layer in the display area is arranged on the flat layer in the display area, and the pixel defining layer has a pixel opening that exposes the anode on the flat layer.

[0062] Optionally, when the organic film layer 20 is a triple-layer structure, the flat portion 22 is also a triple-layer structure. One layer of the flat portion 22 is made of the same material as the flat layer under the anode in the display area and is made in the same process. The other layer of the flat layer is made of the same material as the pixel defining layer in the display area and is made in the same process. The third layer of the flat portion 22 is made of the same material as the photo spacer (PS) in the display area and is made in the same process. The photo spacer in the display area is arranged on the pixel defining layer and supports the upper film layer.

[0063] Optionally, the display panel 100 further includes a glue layer and a first film layer.

[0064] The glue layer is arranged on the inorganic encapsulation layer 30 away from the substrate 61 and directly contacts the inorganic encapsulation layer 30.

[0065] The first film layer is arranged on the glue layer away from the substrate 61 and directly contacts the glue layer. The first film layer is one of a cover plate and an optical film.

[0066] In this embodiment, in order to reduce the cost, the touch substrate is cancelled above the inorganic encapsulation layer 30 in the display panel 100 of this embodiment, and the glue layer is directly arranged above the inorganic encapsulation layer 30. The first film layer is directly arranged above the glue layer. This embodiment further reduces the cost by cancelling the touch substrate between the glue layer and the encapsulation layer, directly forming the glue layer and the first film layer on the side of the inorganic encapsulation layer 30 away from the substrate 61 after forming the inorganic encapsulation layer 30.

[0067] Optionally, in an embodiment, the first film layer is a polarizing sheet, and the polarizing sheet directly contacts the glue layer.

[0068] Optionally, in another embodiment, the first film layer is a cover plate. In this embodiment, the side of the glue layer of the display panel 100 away from the substrate 61 cancels the design of the polarizing sheet, which is a POL Less structure. This embodiment reduces the reflection by using the pixel defining layer made of BPDL, so that the polarizing sheet is not needed, the process of preparing the polarizing sheet is reduced, and the production cost is reduced.

[0069] Please refer to Figure 5Optionally, the second area NA2 includes a first sub-area NA21 and a second sub-area NA22 connected to each other. The first sub-area NA21 is connected to the first area NA1, and the second sub-area NA22 is connected to the third area NA3.

[0070] The flat portion 22 includes a first flat sub-portion 221 and a second flat sub-portion 222 connected to each other. The first flat sub-portion 221 is arranged in the first sub-area NA21. The second flat sub-portion 222 is arranged in the second sub-area NA22.

[0071] The first flat sub-portion 221 covers the first voltage line VGL. The orthographic projection of the first voltage line VGL on the substrate is located on one side of the orthographic projection of the second flat sub-portion 222 on the substrate close to the display area.

[0072] The inorganic encapsulation layer 30 continuously covers the barrier portion 21 and the first flat sub-portion 221. The edge of the inorganic encapsulation layer 30 stops at the second sub-area NA22.

[0073] In the present embodiment, the edge of the inorganic encapsulation layer 30 stopping at the second sub-area NA22 means that the edge portion of the inorganic encapsulation layer 30 formed in the preset away from the display area only covers the first sub-area NA21 and does not cover the second sub-area NA22. However, since the inorganic encapsulation layer 30 is formed by chemical vapor deposition using a metal mask plate. Therefore, the edge of the inorganic encapsulation layer 30 is also connected to a shadow portion S, which is not considered as part of the inorganic encapsulation layer 30 formed in the preset in the present embodiment. The shadow portion S covers a part of the second sub-area NA22, but the shadow portion S does not extend to the third area NA3.

[0074] The inorganic encapsulation layer 30 covering the first flat sub-portion 221 can reduce the water and oxygen corrosion of the first metal layer 10 under the first flat sub-portion 221 and improve the display effect. The inorganic encapsulation layer 30 is not formed in the second sub-area NA22, in order to reserve a certain area for the formation of the shadow portion S, so as to avoid the formation of the shadow portion S in the third area NA3, which leads to the failure of binding.

[0075] Optionally, the barrier portion 21 includes a first barrier 211 and a second barrier 212. The first barrier 211 and the second barrier 212 are arranged in the first area NA1. The second barrier 212 is located between the first barrier 211 and the first flat sub-portion 221. The second barrier 212 is arranged in the first flat sub-portion 221 and forms a recess T. The recess T exposes a part of the first metal layer 10. The inorganic encapsulation layer 30 covers the recess T and the part of the first metal layer 10 exposed by the recess T.

[0076] In the embodiment, the first barrier wall 211 and the second barrier wall 212 are used to block the organic encapsulation layer of the display area from overflowing outward. The organic encapsulation layer of the display area is formed by inkjet printing, and the ink of the organic encapsulation layer has fluidity. The first barrier wall 211 and the second barrier wall 212 can block the overflow. The first barrier wall 211 and the second barrier wall 212 are arranged at intervals to form an overflow groove, which can accommodate part of the ink overflowing from the first barrier wall 211, and avoid the organic ink from further overflowing outward from the second area NA2. In the embodiment, the recess T is arranged between the second barrier wall 212 and the first flat sub-part 221 to separate the second barrier wall 212 and the first flat sub-part 221. The water and oxygen from the outside are prevented from invading the display area along the continuous first flat sub-part 221 and the second barrier wall 212. The recess T can separate the invasion path of the water and oxygen, and improve the encapsulation effect of the display panel 100. The area where the recess T is located is the organic clearance area of the display panel 100, that is, the organic film layer 20 in the area is completely removed. The inorganic encapsulation layer 30 covers the first metal layer 10 exposed to the recess T, which can reduce the water and oxygen corrosion of the first metal layer 10 at the position.

[0077] Please refer to Figure 6 Optionally, the display panel further comprises a third binding part P3, a fourth binding part P4, and a fifth binding part P5. The third binding part P3, the fourth binding part P4, and the fifth binding part P5 are arranged at intervals in the third area NA3.

[0078] The first metal layer 10 comprises a plurality of metal wires.

[0079] The plurality of metal wires comprises a first cathode line VSS1, a first data line VI, and a first power line VDD1.

[0080] One end of the first cathode line VSS1 is electrically connected to the third binding part P3, and the other end of the first cathode line VSS1 extends to the display area.

[0081] One end of the first data line VI is electrically connected to the fourth binding part P4, and the other end of the first data line VI extends to the display area.

[0082] One end of the first power line VDD1 is electrically connected to the fifth binding part P5, and the other end of the first power line VDD1 extends to the display area.

[0083] The inorganic encapsulation layer 30 covers the part of the first cathode line VSS1 located in the second area NA2, the part of the first data line VI located in the second area NA2, and the part of the first power line VDD1 located in the second area NA2.

[0084] The average width of the part of the metal wire overlapping the recess T is smaller than the average width of the part of the metal wire overlapping the flat part 22.

[0085] In the embodiment, the first power line VDD1 is used to provide a stable high potential for the pixel driving transistor and the anode of the light emitting device, so that the device can emit light normally. The first cathode line VSS1 is used to provide a common low potential, form a current loop with the power line, and pull the whole cathode potential to be flat. The first data line VI is used to send the analog voltage or current signal generated by the chip 200 bound to the fourth binding part P4 to each light emitting device, and determine the brightness of each light emitting device. The application extends the inorganic packaging layer 30 to the second area NA2, and covers the part of the first cathode line VSS1, the first data line VI and the first power line VDD1 located in the second area NA2, so as to weaken the water and oxygen corrosion of the part of the first cathode line VSS1, the first data line VI and the first power line VDD1 located in the second area NA2.

[0086] Due to the large pressure difference between adjacent metal wires, during the process of forming the recess T, side etching phenomenon will occur to the part of the metal wire overlapping the recess T, and in the RA test, the electrochemical corrosion of the part of the metal wire overlapping the recess T will be accelerated. Therefore, the embodiment narrows the line width of the part of the metal wire overlapping the recess T, so that the average width of the part of the metal wire overlapping the recess T is smaller than the average width of the part of the metal wire overlapping the flat part 22. The electrochemical corrosion of the part of the metal wire overlapping the recess T is reduced, and the display effect is improved.

[0087] The organic film layer 20 above the part of the metal wire overlapping the flat part 22 is continuous and is not interrupted by the recess T, and the metal wire in this part will not be affected by the patterning method such as ashing and dry etching, and side etching phenomenon will not occur, so that the electrochemical corrosion phenomenon of this part is weakened, and the line width of the metal wire in this part can be increased, thereby reducing the overall resistance of the metal wire and reducing the load.

[0088] Optionally, the display panel further comprises an eighth binding part P8 and a ninth binding part P9.

[0089] The number of the first data lines VI is multiple. The multiple first data lines VI are arranged between the first data line VI and the first power line VDD1.

[0090] The multiple metal wires further comprise a second power line VDD2 and a second cathode line VSS2.

[0091] One end of the second power line VDD2 is electrically connected to the eighth binding part P8, and the other end of the second power line VDD2 extends to the display area.

[0092] One end of the second cathode line VSS2 is electrically connected to the ninth binding part P9, and the other end of the second cathode line VSS2 extends to the display area.

[0093] The inorganic encapsulation layer 30 covers the portion of the second power supply line VDD2 located in the second area NA2 and the portion of the second cathode line VSS2 located in the second area NA2.

[0094] In a plan view of the display panel 100, the plurality of metal traces located in the portion of the first area NA1 and the portion of the second area NA2 all extend along the first direction D1, wherein the second cathode line VSS2, the second power supply line VDD2, the first cathode line VSS1, the plurality of first data lines VI, and the first power supply line VDD1 are sequentially and spacedly arranged along the second direction D2.

[0095] In the embodiment, the design of the plurality of first data lines VI can increase the number of wires, thereby reducing the RC Loading of each first data line VI and improving the display effect.

[0096] In the embodiment, the second power supply line VDD2 and the second cathode line VSS2 are added on the basis of the first power supply line VDD1 and the first cathode line VSS1. By increasing the number of wires, the load of the first power supply line VDD1 and the first cathode line VSS1 is reduced, and the display effect is improved.

[0097] In the embodiment, since the plurality of metal traces located in the portion of the first area NA1 and the portion of the second area NA2 all extend along the first direction D1, and the second cathode line VSS2, the second power supply line VDD2, the first cathode line VSS1, the plurality of first data lines VI, and the first power supply line VDD1 are sequentially and spacedly arranged along the second direction D2, the reasonable wiring can reduce the size of the non-display area NA and realize the design of the narrow-frame display panel 100.

[0098] Optionally, the display panel further comprises a sixth binding portion P6.

[0099] The display panel 100 further comprises a gate driver on array (GOA) and a first connection line 40.

[0100] The gate driver on array is arranged on one side of the substrate 61.

[0101] The first connection line 40 is arranged in the second area NA2 and electrically connected to the gate driver on array and the sixth binding portion P6. A portion of the first connection line 40 is arranged in a layer different from the first metal layer 10. The inorganic encapsulation layer 30 covers the first connection line 40.

[0102] In a plan view of the display panel 100, the portion of the first cathode line VSS1 located in the second area NA2, the portion of the first data line VI located in the second area NA2, and the portion of the first power supply line VDD1 located in the second area NA2 all cross a portion of the first connection line 40.

[0103] In the embodiment, the gate driving circuit can be arranged in the second area NA2, or arranged in the third area NA3, or arranged in other areas such as the non-display area NA on the left or right side of the display area, and the arrangement position of the gate driving circuit is not limited herein.

[0104] The first connection line 40 is used for electrically connecting the gate driving circuit and the sixth binding part P6, and realizing the electrical communication between the chip 200 and the gate driving circuit inside the panel. In the embodiment, the inorganic packaging layer 30 covers the first connection line 40, which can reduce the water and oxygen corrosion of the first connection line 40, ensure the transmission effect of the first connection line 40, and thus improve the display effect.

[0105] In the embodiment, in order to realize the design of the narrow-frame display panel 100, it is necessary to reduce the size of the non-display area NA of the display panel 100. However, no matter the first connection line 40, the first power line VDD1, the first cathode line VSS1 or the first data line VI, a certain area is needed to arrange the wiring, which leads to the fact that the area of the non-display area NA cannot be reduced. In the embodiment, the first connection line 40 is arranged in a layer different from the first metal layer 10, so that the first connection line 40 is crossed with the part of the first cathode line VSS1 located in the second area NA2, the part of the first data line VI located in the second area NA2, and the part of the first power line VDD1 located in the second area NA2, thereby reducing the area of the non-display area NA originally arranged with the first connection line 40, reducing the size of the non-display area NA, and realizing the design of the narrow-frame display panel 100.

[0106] Optionally, in the plan view of the display panel 100, the plurality of metal wires located in the part of the first area NA1 and the part of the second area NA2 all extend along the first direction D1 and are arranged at intervals along the second direction D2, and the first direction D1 intersects the second direction D2.

[0107] The first connection line 40 includes a connection part 41, a cross-line part 42 and an extension part 43.

[0108] One end of the connection part 41 is electrically connected with the sixth binding part P6, and the other end of the connection part 41 extends along the first direction D1. The connection part 41 is located in the second area NA2.

[0109] One end of the cross-line part 42 is electrically connected with the end of the connection part 41 away from the sixth binding part P6. The cross-line part 42 extends along the second direction D2. The cross-line part 42 is located in the second area NA2. The cross-line part 42 is arranged in a layer different from the first metal layer 10.

[0110] In the plan view of the display panel 100, the part of the first cathode line VSS1 located in the second area NA2, the part of the first data line VI located in the second area NA2, and the part of the first power line VDD1 located in the second area NA2 are all crossed with the cross-line part 42.

[0111] One end of the extension part 43 is electrically connected to the other end of the cross-line part 42 away from the connection part 41, and the other end of the extension part 43 is electrically connected to the gate drive circuit. At least part of the extension part 43 is located in the second area NA2.

[0112] The first metal layer 10 includes the connection part 41 and the extension part 43. The sheet resistance of the first metal layer 10 is smaller than the sheet resistance of the cross-line part 42.

[0113] The inorganic encapsulation layer 30 covers at least part of the connection part 41, the cross-line part 42, and the extension part 43.

[0114] In the present embodiment, the connection part 41 is arranged in the same layer as the sixth bonding part P6, and thus the sixth bonding part P6 is integrally connected to the connection part 41. The cross-line part 42 crosses the part of the first cathode line VSS1 located in the second area NA2, the part of the first data line VI located in the second area NA2, and the part of the first power line VDD1 located in the second area NA2, which can reduce the size of the cross-line part 42 originally arranged in the second area NA2, thereby reducing the area of the non-display area NA and achieving a narrow frame design. After the first connection line 40 crosses the metal trace of the first metal layer 10, the extension part 43 is electrically connected to the cross-line part 42 away from the connection part 41. This is because the sheet resistance of the film layer where the cross-line part 42 is located is relatively large, while the sheet resistance of the film layer where the first metal layer 10 is located as the main trace of the display panel 100 is relatively small. After the cross-line part 42 completes the cross-line, in order to reduce the overall sheet resistance of the first connection line 40, the extension part 43 of the first connection line 40 is arranged to the film layer where the first metal layer 10 is located. The first metal layer 10 with relatively small sheet resistance can reduce voltage drop, reduce power consumption, reduce heat and RC delay, and improve display effect.

[0115] Optionally, the display panel further includes a seventh bonding part P7.

[0116] Please refer to Figure 7 , the display panel 100 further includes a second metal layer, a first insulating layer 62, a third metal layer, and an interlayer dielectric layer 63.

[0117] The second metal layer is arranged between the substrate 61 and the first metal layer 10. The second metal layer includes the cross-line part 42.

[0118] The first insulating layer 62 is arranged between the second metal layer and the first metal layer 10.

[0119] The third metal layer is arranged between the first insulating layer 62 and the first metal layer 10. The third metal layer includes the fan-out trace 50. The fan-out trace 50 is electrically connected to the seventh bonding part P7.

[0120] The interlayer dielectric layer 63 is arranged between the third metal layer and the first metal layer 10.

[0121] The connecting portion 41 is connected to the crossover portion 42 through the interlayer dielectric layer 63 and the first insulating layer 62.

[0122] In the embodiment, the film layer where the crossover portion 42 is located is the second metal layer. The second metal layer is a single-layer metal. The second metal layer is used as the gate of the thin film transistor in the display area. The material of the second metal layer can be molybdenum. The third metal layer is the film layer where the fan-out wire 50 is located. The connecting portion 41 and the extension portion 43 of the first connecting wire 40 are connected to the crossover portion through the interlayer dielectric layer 63 and the first insulating layer 62.

[0123] Optionally, the first metal layer 10 includes a first metal sub-layer, a second metal sub-layer, and a third metal sub-layer.

[0124] The first metal sub-layer is located on the side of the interlayer dielectric layer 63 away from the substrate 61.

[0125] The second metal sub-layer is located on the side of the first metal sub-layer away from the substrate 61.

[0126] The third metal sub-layer is located on the side of the second metal sub-layer away from the substrate 61.

[0127] The sheet resistance of the first metal layer 10 is less than that of the second metal layer.

[0128] In the embodiment, the reason why the sheet resistance of the first metal layer 10 is less than that of the second metal layer is that the first metal layer 10 is a three-layer structure. In the embodiment, the material of the first metal sub-layer can be titanium. The material of the second metal sub-layer can be aluminum. The material of the third metal sub-layer can be titanium. The thickness of the three-layer structure of the first metal layer 10 is greater than that of the single-layer structure of the second metal layer. Therefore, the sheet resistance of the first metal layer 10 is less than that of the second metal layer, and the use of the first metal layer 10 for wiring can improve the display effect.

[0129] Optionally, the second metal sub-layer includes a cathode line metal sub-portion, a data line metal sub-portion, and a power line metal sub-portion arranged at intervals.

[0130] The first cathode line VSS1 includes the cathode line metal sub-portion. The first data line VI includes the data line metal sub-portion. The first power line VDD1 includes the power line metal sub-portion.

[0131] The average width L2 of the part of the first area NA1 where the cathode line metal sub-portion is located is less than the average width L3 of the part of the second area NA2 where the cathode line metal sub-portion is located.

[0132] The average width L4 of the part of the first area NA1 where the data line metal sub-portion is located is less than the average width L5 of the part of the second area NA2 where the data line metal sub-portion is located.

[0133] The average width L6 of the power line metal sub-portion in the portion of the first area NA1 is less than the average width L7 of the power line metal sub-portion in the portion of the second area NA2.

[0134] In the present embodiment, after the organic film layer 20 is formed, the recess T needs to be formed to separate the flat portion 22 and the barrier portion 21, so as to achieve the effect of blocking the water and oxygen from the outside to invade the display area along the organic film layer 20. In the present embodiment, the organic film layer 20 can be processed by the patterning mode of Ash and Dry, to form the recess T between the barrier portion 21 and the flat portion 22. Since the organic film layer 20 is in direct contact with the first metal layer 10, the first metal layer 10 under the recess T will also be etched by the etchant. Among them, the materials of the first metal sub-layer and the third metal sub-layer are titanium, which has good etching resistance. The material of the second metal sub-layer is aluminum, and the etching selectivity ratio of aluminum is greater than that of titanium in the patterning process of the organic film layer 20. Therefore, the metal trace of the first metal layer 10 will appear side etching phenomenon.

[0135] Since the first data line VI is arranged between the first power line VDD1 and the first cathode line VSS1, the pressure difference of the first power line VDD1 and the first cathode line VSS1 is large, and since the first data line VI has side etching phenomenon, in the RA test, the electrochemical corrosion of the first data line VI will be accelerated. Therefore, the present embodiment narrows the line width of the portion of the first data line VI, the first power line VDD1, and the first cathode line VSS1 in the first area NA1, so that the average width of the metal trace in the portion of the first area NA1 is less than that in the portion of the second area NA2, thereby increasing the distance between two adjacent traces in the first area NA1, reducing the electrochemical corrosion of the first data line VI in the portion of the first area NA1, and improving the display effect.

[0136] In the second area NA2, since the organic film layer 20 of the second area NA2 is continuous and does not have a recess T to separate it, the metal trace in this part will not be affected by the patterning mode such as Ash and Dry, and will not have side etching phenomenon, so the electrochemical corrosion phenomenon in this part is weakened, and the line width of the metal trace in this part can be increased, thereby reducing the overall resistance of the metal trace and reducing the load.

[0137] Optionally, the average width of the trace of the first data line VI in the portion of the first area NA1 away from the second area NA2 is greater than the average width of the portion of the first data line VI in the first area NA1.

[0138] The first data line VI is located in the part of the first area NA1 far away from the second area NA2, and the side etching does not occur in the part, so the electrochemical corrosion phenomenon is weakened, and the line width of the first data line VI itself is small, so the line width of the first data line VI in the part can be increased, so as to reduce the overall resistance of the first data line VI and reduce the load.

[0139] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0140] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0141] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0142] The above is only the preferred embodiment of the present application, and does not limit the present application in any form, but any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application without departing from the technical scheme of the present application still belongs to the scope of the technical scheme of the present application.

Claims

1. A display panel having a display area and a non-display area located on at least one side of the display area, characterized in that, The non-display area includes a first area, a second area, and a third area that are sequentially connected to one side of the display area; The display panel includes: Substrate; An electrostatic discharge circuit, including a first voltage line; A first metal layer is disposed on one side of the substrate and located in the display area, the first area, the second area and the third area. The portion of the first metal layer located in the second area includes the first voltage line. An organic film layer is disposed on the side of the first metal layer away from the substrate, and includes a barrier portion and a flat portion. The barrier portion is located in the first region, the flat portion is located in the second region, and the flat portion covers the first voltage line. An inorganic encapsulation layer is continuously disposed on the side of the display area and the organic film layer away from the substrate. In the thickness direction of the display panel, the edge of the inorganic encapsulation layer away from the display area is flush with the edge of the first voltage line away from the display area. The first binding part is located in the third region and is electrically connected to the first voltage line.

2. The display panel as described in claim 1, characterized in that, The electrostatic discharge circuit also includes a second voltage line; The portion of the first metal layer located in the second region includes the second voltage line, which is located between the first voltage line and the display area. The second voltage line and the first voltage line are spaced apart along the first direction. The first voltage line and the second voltage line extend along the second direction, which intersects the second direction. The first direction points from the display area to the non-display area. The inorganic encapsulation layer covers the second voltage line; The display panel further includes a second bonding part, which is electrically connected to the second voltage line.

3. The display panel as described in claim 1, characterized in that, The distance between the bonding portion and the edge of the inorganic encapsulation layer is less than or equal to 400 micrometers.

4. The display panel as described in claim 1, characterized in that, The second region includes a first sub-region and a second sub-region that are connected to each other, the first sub-region being connected to the first region, and the second sub-region being connected to the third region; The flat portion includes a first flat sub-portion and a second flat sub-portion connected to each other. The first flat sub-portion is disposed in the first sub-region, and the second flat sub-portion is disposed in the second sub-region. The first flat sub-portion covers the first voltage line, and the orthographic projection of the first voltage line on the substrate is located on the side of the orthographic projection of the second flat sub-portion on the substrate that is closer to the display area. The inorganic encapsulation layer continuously covers the retaining wall portion and the first flat sub-portion, and the edge of the inorganic encapsulation layer terminates at the second sub-region.

5. The display panel as described in claim 4, characterized in that, The retaining wall portion includes a first retaining wall and a second retaining wall, the first retaining wall and the second retaining wall being spaced apart in the first area, the second retaining wall being located between the first retaining wall and the first flat sub-part, the second retaining wall being spaced apart from the first flat sub-part and forming a recessed portion, the recessed portion exposing a portion of the first metal layer; The inorganic encapsulation layer covers the recess and the portion of the first metal layer that exposes the recess.

6. The display panel as described in claim 5, characterized in that, The display panel also includes a third binding part, a fourth binding part, and a fifth binding part; The first metal layer includes multiple metal traces, and the multiple metal traces include: A first cathode line, one end of which is electrically connected to the third bonding portion, and the other end of which extends to the display area; A first data line, one end of which is electrically connected to the fourth binding part, and the other end of which extends to the display area; and A first power line, one end of which is electrically connected to the fifth binding part, and the other end of which extends to the display area; The inorganic encapsulation layer covers the portion of the first cathode line located in the second region, the portion of the first data line located in the second region, and the portion of the first power line located in the second region; The average width of the portion where the metal trace overlaps with the recess is less than the average width of the portion where the metal trace overlaps with the flat portion.

7. The display panel as described in claim 6, characterized in that, The display panel also includes a sixth bonding part; The display panel also includes: A gate driving circuit is disposed on one side of the substrate; and A first connection line is disposed in the second region and electrically connects the gate driving circuit and the sixth bonding portion. A portion of the first connection line is disposed in a different layer from the first metal layer, and the inorganic encapsulation layer covers the first connection line. In a plan view of the display panel, the portion of the first cathode line located in the second area, the portion of the first data line located in the second area, and the portion of the first power line located in the second area all intersect with a portion of the first connecting line.

8. The display panel as described in claim 7, characterized in that, In the plan view of the display panel, the portions of the multiple metal traces located in the first area and the second area all extend along the first direction and are arranged at intervals along the second direction, with the first direction intersecting the second direction; The first connecting line includes: A connecting portion, one end of which is electrically connected to the sixth binding portion, and the other end of which extends along a first direction, the connecting portion being located in the second region; A crossover portion, one end of which is electrically connected to the end of the connecting portion away from the sixth binding portion, the crossover portion extends along the second direction, the crossover portion is located in the second region, the crossover portion is disposed in a different layer from the first metal layer, and in the plan view of the display panel, the portion of the first cathode line located in the second region, the portion of the first data line located in the second region, and the portion of the first power line located in the second region all intersect with the crossover portion; An extension portion, one end of which is electrically connected to the end of the cross-line portion away from the connecting portion, and the other end of which is electrically connected to the gate driving circuit, wherein at least a portion of the extension portion is located in the second region; The first metal layer includes the connecting portion and the extension portion, and the sheet resistance of the first metal layer is less than the sheet resistance of the cross-line portion; The inorganic encapsulation layer covers at least a portion of the connection portion, the crossover portion, and the extension portion.

9. The display panel as described in claim 8, characterized in that, The display panel also includes a seventh binding part; The display panel also includes: A second metal layer is disposed between the substrate and the first metal layer, and the second metal layer includes the crossover portion; A first insulating layer is disposed between the second metal layer and the first metal layer; A third metal layer is disposed between the first insulating layer and the first metal layer, the third metal layer including a fan-out trace, the fan-out trace being electrically connected to the seventh bonding portion; and An interlayer dielectric layer is disposed between the third metal layer and the first metal layer; The connecting portion passes through the interlayer dielectric layer and the first insulating layer and connects to the crossover portion, and the extension portion passes through the interlayer dielectric layer and the first insulating layer and connects to the crossover portion.

10. The display panel as claimed in claim 9, characterized in that, The first metal layer includes: A first metal sublayer is disposed on the side of the interlayer dielectric layer away from the substrate; A second metal sublayer is disposed on the side of the first metal sublayer away from the substrate; and A third metal sublayer is disposed on the side of the second metal sublayer away from the substrate; The sheet resistance of the first metal layer is less than that of the second metal layer.

11. The display panel as claimed in claim 10, characterized in that, The second metal sublayer includes a cathode wire metal sublayer, a data wire metal sublayer, and a power wire metal sublayer that are spaced apart. The first cathode line includes the cathode line metal sub-section, the first data line includes the data line metal sub-section, and the first power line includes the power line metal sub-section. The average width of the portion of the cathode wire metal sub-section located in the first region is less than the average width of the portion of the cathode wire metal sub-section located in the second region; The average width of the portion of the data cable metal sub-section located in the first area is less than the average width of the portion of the data cable metal sub-section located in the second area; The average width of the portion of the power cord metal sub-section located in the first region is less than the average width of the portion of the power cord metal sub-section located in the second region.

12. The display panel as claimed in claim 6, characterized in that, The display panel further includes an eighth binding part and a ninth binding part; The number of the first data lines is multiple, and the multiple first data lines are spaced apart between the first data lines and the first power lines; The plurality of the aforementioned metal traces also include: A second power line, one end of which is electrically connected to the eighth binding part, and the other end of which extends to the display area; and The second cathode wire has one end electrically connected to the ninth binding part and the other end extending to the display area. The inorganic encapsulation layer covers the portion of the second power line located in the second region and the portion of the second cathode line located in the second region; In the plan view of the display panel, the portions of the multiple metal traces located in the first area and the second area all extend along the first direction, wherein the second cathode line, the second power line, the first cathode line, the multiple first data lines, and the first power line are arranged at intervals along the second direction.

13. The display panel as described in any one of claims 1-12, characterized in that, The organic film layer is in direct contact with the first metal layer.

14. The display panel as described in any one of claims 1-12, characterized in that, The display panel also includes: An adhesive layer is disposed on the side of the inorganic encapsulation layer away from the substrate and is in direct contact with the inorganic encapsulation layer; and The first film layer is disposed on the side of the adhesive layer away from the substrate and is in direct contact with the adhesive layer; The first film layer is either a cover plate or an optical film.

15. A display device, characterized in that, The display device includes a display panel as claimed in any one of claims 1-14.

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