Data acceleration processing method, apparatus and device for cryptographic operation and medium

Abstract

The application provides a data acceleration processing method, device and equipment for cryptographic operation and a medium, the method comprising: receiving a to-be-processed polynomial data acceleration processing instruction for cryptographic operation; obtaining n coefficient vectors of to-be-processed polynomial data according to the acceleration processing instruction; inputting the n coefficient vectors into a forward acceleration operation module of n-level parallel operation to perform forward acceleration operation respectively, obtaining n forward operation results; performing shaping processing on the n forward operation results to obtain shaping results of the n forward operation results; inputting the shaping results of the n forward operation results into a reverse acceleration operation module of n-level parallel operation to perform reverse acceleration operation respectively, obtaining a reverse operation result, and outputting the reverse operation result. The scheme of the application enables fast parallel calculation of polynomial coefficients, greatly improving the efficiency of polynomial multiplication in signature, verification and key exchange.

Description

Technical Field

[0001] This invention relates to the field of cryptographic hardware acceleration and reconfigurable computing, and in particular to a data acceleration processing method, apparatus and device for cryptographic operations. Background Technology

[0002] Currently, with the development of quantum computing, traditional public-key algorithms face security threats compared to quantum algorithms. Post-quantum cryptography algorithms will replace classical public-key cryptography algorithms. Most current post-quantum cryptography algorithms involve a large amount of complex computation and repetitive mathematical operations. Pure software implementations are not well-suited for parallel computing; a single encryption or decryption on a microprocessor may require a significant number of clock cycles. Therefore, employing hardware design to accelerate the computation process and evaluating various post-quantum cryptography algorithms on hardware platforms such as Field Programmable Gate Arrays (FPGAs) is crucial.

[0003] Existing hardware and software implementations mainly include: processor / vector instruction optimization: relying on Single Instruction Multiple Data (SIMD) / cache optimization, but limited by memory access bandwidth and data migration overhead, it is difficult to meet the needs of high-concurrency scenarios.

[0004] Graphics processing unit (GPU) parallelism: High parallelism but irregular memory access, thread divergence and PCIe transmission lead to limited energy efficiency, and insufficient deterministic timing and side-channel protection.

[0005] Existing FPGA implementations often suffer from drawbacks including serial single-butterfly operator behavior, pipeline bubbles caused by memory conflicts, inefficient twiddle factor generation / memory access, large modular multiplication / reduction delays, and inflexible configuration. In particular, some designs, in pursuit of extreme resource conservation, fail to achieve pipelining, exhibit severe functional coupling, and hinder functional expansion. Summary of the Invention

[0006] This invention provides a data acceleration processing method, apparatus, device, and medium for cryptographic operations. It ensures fast parallel computation of individual polynomial coefficients while also being compatible with parallel computation between different polynomials. The efficiency of polynomial multiplication can be flexibly configured between speed and area, significantly improving the efficiency of polynomial multiplication in signature, verification, and key exchange.

[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0008] A method for accelerating data processing in cryptographic operations includes:

[0009] The system receives an acceleration processing instruction for polynomial data to be processed for cryptographic operations, the acceleration processing instruction including: the number n of coefficients n in the polynomial data to be processed participating in the acceleration operation, where n is a positive integer;

[0010] According to the acceleration processing instruction, obtain the n coefficient vectors of the polynomial data to be processed;

[0011] The n coefficient vectors are input into the forward acceleration module of the n-level parallel operation for forward acceleration operation, and n forward operation results are obtained. Among them, the i-th coefficient vector is input into the i-th level forward acceleration module for forward acceleration operation, and the n-level forward acceleration module is an n-level parallel operation forward acceleration module based on field-programmable gate array; 1≤i≤n.

[0012] The n forward operation results are shaped to obtain the shaped results of the n forward operation results;

[0013] The shaped results of n forward operations are input into the n-stage parallel reverse acceleration module for reverse acceleration, and the reverse operation results are obtained and output.

[0014] Optionally, according to the acceleration processing instruction, obtain n coefficient vectors of the polynomial data to be processed, including:

[0015] According to the acceleration processing instruction, n coefficient vectors of the polynomial data to be processed are read from the first random access memory corresponding to the i-th stage acceleration operation module.

[0016] Optionally, the n coefficient vector is input into the forward acceleration module of the n-level parallel operation for forward acceleration operation to obtain n forward operation results, including:

[0017] Read the rotation factor corresponding to the coefficient vector from the i-th random access memory corresponding to the i-th stage acceleration module;

[0018] The n coefficient vector and rotation factor are input into the butterfly operation module in the forward acceleration operation module of the n-level parallel operation to perform butterfly operation and obtain n forward operation results.

[0019] Optionally, the n coefficient vector and the rotation factor are input into the butterfly operation module in the n-level parallel forward acceleration operation module to perform butterfly operation, obtaining n forward operation results, including:

[0020] Determine the number of layers L of the coefficient vector, L = log(n) - 1;

[0021] Based on the layer number L of the coefficient vector, the coefficient vectors of the corresponding layer number are operated on sequentially according to the rotation factor to obtain n forward operation results.

[0022] Optionally, after obtaining the results of n forward operations, it also includes:

[0023] The results of n forward operations are stored in the i-th second random access memory corresponding to the i-th stage acceleration module in a first-in-first-out order.

[0024] Optionally, the n forward operation results are shaped to obtain shaped results of the n forward operation results, including:

[0025] Perform a modulo operation on the results of n forward operations to obtain the modulo result;

[0026] The address is shaped based on the modulo operation result to obtain the shaped result of n forward operation results.

[0027] Optionally, the shaped results of the n forward operations are input into the n-stage parallel reverse acceleration module for reverse acceleration, and the reverse operation results are obtained, including:

[0028] Read the inverse factor of the rotation factor corresponding to the i-th coefficient vector from the i-th third random access memory corresponding to the i-th level inverse acceleration module;

[0029] Perform a butterfly operation on the i-th coefficient vector based on the i-th inverse factor to obtain the i-th inverse operation result, until n inverse operation results are obtained.

[0030] Embodiments of the present invention also provide a data acceleration processing apparatus for cryptographic operations, comprising:

[0031] The receiving module is used to receive an acceleration processing instruction for polynomial data to be processed for cryptographic operations, wherein the acceleration processing instruction includes: the number n of coefficients n in the polynomial data to be processed participating in the acceleration operation, wherein n is a positive integer;

[0032] The processing module is configured to: acquire n coefficient vectors of the polynomial data to be processed according to the acceleration processing instructions; input the n coefficient vectors into the forward acceleration processing module of the n-level parallel operation for forward acceleration operation to obtain n forward operation results; wherein the i-th coefficient vector is input into the i-th level forward acceleration processing module for forward acceleration operation, and the n-level forward acceleration processing module is an n-level parallel operation forward acceleration processing module based on field-programmable gate array; 1≤i≤n; perform shaping processing on the n forward operation results to obtain the shaped result of the n forward operation results; input the shaped result of the n forward operation results into the reverse acceleration processing module of the n-level parallel operation for reverse acceleration operation to obtain the reverse operation result, and output it.

[0033] Embodiments of the present invention also provide a computing device, including: a processor and a memory storing a computer program, wherein the computer program, when executed by the processor, performs the method described above.

[0034] Embodiments of the present invention also provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method described above.

[0035] The above-described solution of the present invention has at least the following beneficial effects:

[0036] The method of the present invention involves receiving an acceleration processing instruction for polynomial data to be processed for cryptographic operations. The acceleration processing instruction includes: the number n of coefficients in the polynomial data to be processed participating in the acceleration operation, where n is a positive integer; obtaining n coefficient vectors of the polynomial data to be processed according to the acceleration processing instruction; inputting the n coefficient vectors into an n-level parallel forward acceleration module for forward acceleration operations to obtain n forward operation results; wherein the i-th coefficient vector is input into the i-th level forward acceleration module for forward acceleration operations, and the n-level forward acceleration module is an n-level parallel forward acceleration module based on a field-programmable gate array; 1 ≤ i ≤ n; performing an integer processing on the n forward operation results to obtain an integer result of the n forward operation results; inputting the integer result of the n forward operation results into an n-level parallel reverse acceleration module for reverse acceleration operations to obtain a reverse operation result, and outputting it. It ensures fast parallel computation of individual polynomial coefficients and is compatible with parallel computation between different polynomials. It can be flexibly configured between speed and area, which greatly improves the efficiency of polynomial multiplication in signing, verification and key exchange. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating the data acceleration processing method for cryptographic operations according to the present invention;

[0038] Figure 2 This is a schematic diagram of the overall processing flow of the data acceleration processing method for cryptographic operations of the present invention;

[0039] Figure 3 This is a schematic diagram of the processing flow of the data acceleration computing module of the present invention;

[0040] Figure 4 This is a schematic diagram of the data acceleration processing device for cryptographic operations according to the present invention. Detailed Implementation

[0041] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a data acceleration processing method for cryptographic operations, comprising:

[0043] Step 11: Receive an acceleration processing instruction for the polynomial data to be processed for cryptographic operations. The acceleration processing instruction includes: the number n of the coefficients n of the polynomial data to be processed participating in the acceleration operation, where n is a positive integer.

[0044] Step 12: According to the acceleration processing instruction, obtain the n coefficient vectors of the polynomial data to be processed;

[0045] Step 13: Input the n coefficient vector into the forward acceleration module of the n-level parallel operation to perform forward acceleration operation respectively, and obtain n forward operation results; wherein, the i-th coefficient vector is input into the i-th level forward acceleration module for forward acceleration operation, and the n-level forward acceleration module is an n-level parallel operation forward acceleration module based on field-programmable gate array; 1≤i≤n;

[0046] Step 14: Reshape the n forward operation results to obtain the reshaped result of the n forward operation results;

[0047] Step 15: The shaped results of the n forward operation results are input into the n-level parallel reverse acceleration operation module for reverse acceleration operation, and the reverse operation results are obtained and output.

[0048] The method of this invention involves inputting n coefficient vectors of the polynomial data to be processed for cryptographic operations into an n-stage parallel forward acceleration module for forward acceleration operations, obtaining n forward operation results; shaping the n forward operation results to obtain shaped results of the n forward operation results; and inputting the shaped results of the n forward operation results into an n-stage parallel reverse acceleration module for reverse acceleration operations, obtaining reverse operation results, and outputting them. This ensures fast parallel computation of individual polynomial coefficients while also being compatible with parallel computation between different polynomials, allowing for flexible configuration between speed and area, and significantly improving the efficiency of polynomial multiplication in signature, verification, and key exchange.

[0049] In an optional embodiment of the present invention, step 11, receiving instructions for accelerating the processing of polynomial data to be processed for cryptographic operations, includes:

[0050] The instruction scheduling module, which corresponds one-to-one with the forward acceleration module, obtains polynomial data acceleration processing instructions for cryptographic operations. These instructions include the number of coefficients *n* in the polynomial data to be processed, where *n* is a positive integer. Further, they may include: operation flow control for the forward acceleration module, including coefficient layer mapping, butterfly factor selection, address generation, and data storage / writing, as well as configuring the forward acceleration module's size *n*, modulus *q*, whether to perform reverse operation, parallelism *P*, pipeline depth, and constant-time switching. By configuring the forward acceleration module through the instruction scheduling module, the instruction channel and data channel are separated, greatly facilitating expansion and maintenance.

[0051] In an optional embodiment of the present invention, step 12, obtaining n coefficient vectors of the polynomial data to be processed according to the acceleration processing instruction, includes:

[0052] Step 121: According to the acceleration processing instruction, read the n coefficient vectors of the polynomial data to be processed from the i-th first random access memory corresponding to the i-th stage forward acceleration operation module.

[0053] In this embodiment, each first-level forward acceleration module corresponds to a random access memory (RAM) for storing intermediate computation data, rotation factors used in forward computation, etc. Data to be processed is written into different RAM spaces according to the corresponding format via the RAM interface, facilitating reading by the forward acceleration module and thus improving data reading speed and efficiency. In an optional embodiment of the present invention, in step 13, the n-coefficient vector is input into the n-level parallel forward acceleration module for forward acceleration computation to obtain n forward computation results, including:

[0054] Step 131: Read the rotation factor corresponding to the coefficient vector from the first random access memory corresponding to the i-th level forward acceleration module;

[0055] Step 132: Input the n coefficient vector and rotation factor into the butterfly operation module in the forward acceleration operation module of the n-level parallel operation to perform butterfly operation and obtain n forward operation results.

[0056] In this embodiment, each coefficient vector is butterfly-shaped with the corresponding rotation factor, converting the convolution into a coefficient dot product, which greatly reduces the complexity of polynomial multiplication.

[0057] In an optional embodiment of the present invention, in step 132, the n coefficient vector and the rotation factor are input into the butterfly operation module of the n-level parallel forward acceleration operation module to perform butterfly operation, obtaining n forward operation results, including:

[0058] Step 1321, determine the number of layers L of the coefficient vector, L = log(n);

[0059] Step 1322: According to the number of layers L of the coefficient vector, perform operations on the coefficient vector of the corresponding layer in sequence according to the rotation factor to obtain n forward operation results.

[0060] In this embodiment, a specific implementation process is as follows, taking n=4 as an example:

[0061] Input polynomial coefficients: a = [a0, a1, a2, a3];

[0062] Let the rotation factors be W0 = ω^0 = 1, W1 = ω^1 = ω; all operations modulo q.

[0063] Coefficient vector distance = 2 (first layer, two pairs of butterfly shapes, explicit multiplication by W0)

[0064] For (0, 2): b0 = a0 + W0·a2; b2 = a0 − W0·a2;

[0065] For (1, 3): b1 = a1 + W0·a3; b3 = a1 − W0·a3;

[0066] Coefficient vector distance = 1 (second layer, two pairs of butterfly shapes)

[0067] Multiply (0, 1) by W0: c0 = b0 + W0·b1; c2 = b0 − W0·b1;

[0068] Multiply (2, 3) by W1: c1 = b2 + W1·b3; c3 = b2 − W1·b3;

[0069] The result of the forward operation is: NTT(a) = [c0, c1, c2, c3].

[0070] In an optional embodiment of the present invention, after obtaining n forward operation results in step 1322, the method may further include:

[0071] Step 1323: Store the n forward operation results in the i-th second random access memory corresponding to the i-th stage acceleration module in first-in-first-out order.

[0072] In this embodiment, the n forward operation results are written back to the i-th second random access memory (RAM) corresponding to the i-th stage acceleration operation module in conflict avoidance order, corresponding to the stride and twiddle base address update in the next stage.

[0073] In an optional embodiment of the present invention, step 14 involves shaping the n forward operation results to obtain a shaped result of the n forward operation results, including:

[0074] Step 141: Perform a modulo operation on the n forward operation results to obtain the modulo operation result;

[0075] Step 142: Perform address shaping based on the modulo operation result to obtain the shaped result of n forward operation results.

[0076] In this embodiment, after the last stage of n forward operation results is completed, the result is output through the RAM interface; the result is multiplied by n^{-1}modq in the last stage to obtain the modulo operation result; the address of the modulo operation result is shaped so that the final output result of the i-th stage forward operation module can be input into the i-th stage reverse acceleration operation module for reverse acceleration operation.

[0077] In an optional embodiment of the present invention, in step 15, the shaped results of the n forward operation results are input into the n-stage parallel reverse acceleration operation module for reverse acceleration operation to obtain the reverse operation result, including:

[0078] Step 151: Read the inverse factor of the rotation factor corresponding to the i-th coefficient vector from the i-th third random access memory corresponding to the i-th level inverse acceleration module;

[0079] Step 152: Perform a butterfly operation on the i-th coefficient vector based on the i-th inverse factor to obtain the i-th inverse operation result, until n inverse operation results are obtained.

[0080] In this embodiment, a specific implementation process is as follows, taking n=4 as an example:

[0081] Given that the output of the forward acceleration operation is C=[c0, c1, c2, c3], use the inverse root and the final scaling to restore a=[a0, a1, a2, a3].

[0082] If we assume that the same set of tw factors w0, w1, w2, w3 are used for the forward operation, then the reverse acceleration operation uses its inverse wk^{-1} at each level.

[0083] 1: Level 1 (corresponding to Level 2 of the forward acceleration module, distance = 1, paired with (0,1) and (2,3))

[0084] Let v = c1 · w2^{-1}, then d0 = c0 + v, d1 = c0 – v;

[0085] Let v = c3 · w3^{-1}, then d2 = c2 + v, d3 = c2 – v;

[0086] 2: Level 2 (corresponding to Level 1 of the forward acceleration module, distance = 2, paired with (0,2) and (1,3));

[0087] Let v = d2 · w0^{-1}, then a0' = d0 + v, a2' = d0 – v;

[0088] Let v = d3 · w1^{-1}, then a1' = d1 + v, a3' = d1 – v;

[0089] 3: Final scaling (restoring to the time domain)

[0090] a0 = a0' · 4^{-1}, a1 = a1' · 4^{-1}, a2 = a2' · 4^{-1}, a3 = a3' · 4^{-1} (modulo q), thus restoring the original coefficient a from `C.

[0091] The configurable FPGA-based computing acceleration core of this invention ensures both rapid parallel computation of individual polynomial coefficients and compatibility with parallel computation between different polynomials during accelerated computation, allowing for flexible configuration between speed and area. The functional modules implemented within the acceleration module are independent, with forward and backward acceleration operations being separate, enabling flexible expansion of acceleration and adaptation to acceleration algorithms with different security levels. Furthermore, the instruction and data channels are separated, greatly facilitating expansion and maintenance.

[0092] The implementation process of the above method is as follows: Figure 1 As shown, it mainly includes the following modules:

[0093] Instruction scheduling module: mainly responsible for encoding the instructions for the entire calculation process and scheduling the instructions to control the entire calculation process.

[0094] Random Access Memory (RAM): An internal storage resource on a chip used to store intermediate computational data.

[0095] The forward acceleration module is mainly used to perform forward acceleration calculations and storage.

[0096] The reverse acceleration module is mainly used to perform reverse acceleration calculations and storage.

[0097] The accelerated computation module, as a key operator in ring / lattice cryptography, is used to transform polynomial convolution into dot product, which greatly improves the efficiency of polynomial multiplication in signature, verification and key exchange.

[0098] The specific implementation process of accelerating computation is as follows: Figure 2 As shown:

[0099] The acceleration control module handles the process control for accelerated computation. This primarily includes layer mapping, butterfly factor selection, address generation and data storage / writing, as well as configuring the accelerated computation scale n, modulus q, whether to perform reverse acceleration computation, parallelism P, pipeline depth, and constant-time switching.

[0100] The forward acceleration operation conversion rotation factor storage module is mainly used to store the rotation factors used in the forward calculation.

[0101] The butterfly operation module is mainly used to perform butterfly factor calculations. It contains four parallel programming operations (PEs), each of which includes a modular multiplication module, an adder / subtractor, and a modular reduction module. It supports radix-2 or mixed-radix (radix-2 / radix-4) butterflies. Modular multiplication is implemented using either Montgomery or Barrett reduction, and is pipelined to the L-level for high-frequency operation.

[0102] The modulo calculation module is mainly used to perform modulo calculations on Q.

[0103] The reverse acceleration calculation conversion rotation factor storage module is mainly used to store the rotation factor calculated in reverse. It is pre-generated and stored in ROM in bit-reverse order or segmented order.

[0104] Address generator: The address generator uses a step size stride and a base address to generate number theory transformation storage and rotation factor addresses, advances in stages and outputs round completion signals, and switches to reverse flow and reverse rotation factor during reverse acceleration calculation.

[0105] The main data processing flow described above is as follows:

[0106] 1) Parameter configuration: n, q, P, mode (forward acceleration / backward acceleration), pipeline depth and start register are written through the instruction scheduling module;

[0107] 2) Data loading: The data to be processed is written into different RAM spaces according to the corresponding format through the RAM interface;

[0108] 3) Staged calculation: For each stage of s=0…log2(n)-1, the address generator produces parallel butterfly pairs for index and bank selection, and P PEs execute in parallel: y0=x0+w·x1, y1=x0−w·x1, and all modulo operations are performed in the modulo q domain;

[0109] 4) Write-back and next stage: The results are written back to BRAM in conflict avoidance order, corresponding to the stride and twiddle base address updates in the next stage;

[0110] 5) Forward acceleration operation output and completion: After the last stage is completed, the result is output through the RAM interface; in the reverse acceleration operation mode, the result is multiplied by n^{-1} mod q in the last stage;

[0111] 6) Output and Completion of Reverse Acceleration Operation: After the forward acceleration operation is completed, the console needs to transfer the result of the forward acceleration operation to the reverse acceleration operation module to complete the reverse acceleration operation. The forward acceleration / reverse acceleration module of this invention adopts standardized IP core packaging, supports multiple interface protocols and configuration methods, and is easy to integrate directly into FPGA or ASIC designs.

[0112] AXI4-Lite configuration interface: 32-bit address space, supports register read and write configuration parameters (n, q, mode, parallelism P, pipeline depth L, etc.).

[0113] AXI4-Stream data interface: Supports burst transmission, configurable data bit width (96-bit / 192-bit / 384-bit), and supports backpressure mechanism.

[0114] Clock domain management: Supports multi-clock domain design, configuration interface and data interface can be independent clock, built-in asynchronous FIFO and cross-clock domain synchronization.

[0115] Reset strategy: Supports both soft reset and hard reset, and automatically restores the default configuration state after reset.

[0116] This invention relates to the field of cryptographic hardware acceleration and reconfigurable computing, specifically to forward / backward acceleration computing technologies based on Field-Programmable Gate Arrays (FPGAs), targeting post-quantum cryptography (PQC) applications, particularly achieving high-efficiency acceleration in lattice-based public-key systems (such as CRYSTALS-Dilithium signature / verification) and polynomial operations. Specifically, it features high throughput and high-frequency operation: simultaneous computation with multiple PEs and multiple coefficient-level parallelism, combined with dual-port / multi-channel TwiddleROM parallel reads, effectively reducing data bubbles and supporting stable high-frequency operation. Memory conflict avoidance: multi-bank BRAM layout and staged stride address generation, combined with bit-reversed / linear-order write-back strategies, significantly reduce port conflicts and structural hazards in memory access. Control / data decoupling: instruction scheduling and data channels are separated; forward / backward acceleration operations are independent; address_unit, Twiddle ROM, and butterfly PE modules are modularly decoupled, facilitating reuse and independent optimization. Energy efficiency advantage: On-chip parallel and pipelined computing reduces unnecessary data movement, resulting in higher energy efficiency and lower system overhead compared to CPUs / GPUs at the same throughput.

[0117] like Figure 4As shown, an embodiment of the present invention provides a data acceleration processing device 40 for cryptographic operations, comprising:

[0118] The receiving module 41 is used to receive a command to accelerate the processing of polynomial data to be processed for cryptographic operations. The command includes the number n of the coefficients n of the polynomial data to be processed participating in the accelerated operation, where n is a positive integer.

[0119] Processing module 42 is used to obtain n coefficient vectors of the polynomial data to be processed according to the acceleration processing instruction; input the n coefficient vectors into the forward acceleration processing module of n-level parallel operation to perform forward acceleration operation respectively, and obtain n forward operation results; wherein, the i-th coefficient vector is input into the i-th level forward acceleration processing module for forward acceleration operation, and the n-level forward acceleration processing module is an n-level parallel operation forward acceleration processing module based on field-programmable gate array; 1≤i≤n; perform shaping processing on the n forward operation results to obtain the shaped result of the n forward operation results; input the shaped result of the n forward operation results into the reverse acceleration processing module of n-level parallel operation to perform reverse acceleration operation respectively, obtain the reverse operation result, and output it.

[0120] Optionally, according to the acceleration processing instruction, obtain n coefficient vectors of the polynomial data to be processed, including:

[0121] According to the acceleration processing instruction, n coefficient vectors of the polynomial data to be processed are read from the first random access memory corresponding to the i-th stage acceleration operation module.

[0122] Optionally, the n coefficient vector is input into the forward acceleration module of the n-level parallel operation for forward acceleration operation to obtain n forward operation results, including:

[0123] Read the rotation factor corresponding to the coefficient vector from the i-th random access memory corresponding to the i-th stage acceleration module;

[0124] The n coefficient vector and rotation factor are input into the butterfly operation module in the forward acceleration operation module of the n-level parallel operation to perform butterfly operation and obtain n forward operation results.

[0125] Optionally, the n coefficient vector and the rotation factor are input into the butterfly operation module in the n-level parallel forward acceleration operation module to perform butterfly operation, obtaining n forward operation results, including:

[0126] Determine the number of layers L of the coefficient vector, L = log(n) - 1;

[0127] Based on the layer number L of the coefficient vector, the coefficient vectors of the corresponding layer number are operated on sequentially according to the rotation factor to obtain n forward operation results.

[0128] Optionally, after obtaining n forward operation results, the processing module 42 is also used for:

[0129] The results of n forward operations are stored in the i-th second random access memory corresponding to the i-th stage acceleration module in a first-in-first-out order.

[0130] Optionally, the n forward operation results are shaped to obtain shaped results of the n forward operation results, including:

[0131] Perform a modulo operation on the results of n forward operations to obtain the modulo result;

[0132] The address is shaped based on the modulo operation result to obtain the shaped result of n forward operation results.

[0133] Optionally, the shaped results of the n forward operations are input into the n-stage parallel reverse acceleration module for reverse acceleration, and the reverse operation results are obtained, including:

[0134] Read the inverse factor of the rotation factor corresponding to the i-th coefficient vector from the i-th third random access memory corresponding to the i-th level inverse acceleration module;

[0135] Perform a butterfly operation on the i-th coefficient vector based on the i-th inverse factor to obtain the i-th inverse operation result, until n inverse operation results are obtained.

[0136] It should be noted that this system is a device corresponding to the above method, and all implementations of the above method are applicable to the embodiments of this device and can achieve the same technical effect.

[0137] Embodiments of the present invention also provide a computing device, including: a processor and a memory storing a computer program, wherein the computer program, when executed by the processor, performs the above-described method. All implementations in the above method embodiments are applicable to this embodiment and can achieve the same technical effects.

[0138] Embodiments of the present invention also provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the methods described above. All implementations in the above method embodiments are applicable to this embodiment and can achieve the same technical effects.

[0139] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0140] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0141] In the embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0142] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0143] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0144] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0145] Furthermore, it should be noted that in the apparatus and method of the present invention, it is obvious that the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent solutions of the present invention. Moreover, the steps performing the above series of processes can naturally be executed in the order described, but are not necessarily required to be executed in chronological order; some steps can be executed in parallel or independently of each other. Those skilled in the art will understand that all or any step or component of the method and apparatus of the present invention can be implemented in any computing device (including processors, storage media, etc.) or network of computing devices, in hardware, firmware, software, or a combination thereof. This is something that those skilled in the art can achieve by using their basic programming skills after reading the description of the present invention.

[0146] Therefore, the object of the present invention can also be achieved by running a program or a set of programs on any computing device. The computing device can be a known general-purpose device. Therefore, the object of the present invention can also be achieved simply by providing a program product containing program code implementing the method or apparatus. That is, such a program product also constitutes the present invention, and the storage medium storing such a program product also constitutes the present invention. Obviously, the storage medium can be any known storage medium or any storage medium developed in the future. It should also be noted that in the apparatus and method of the present invention, it is obvious that the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent to the present invention. Furthermore, the steps performing the above series of processes can naturally be performed in the order described, but are not necessarily required to be performed in chronological order. Some steps can be performed in parallel or independently of each other.

[0147] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data acceleration processing method for cryptographic operations, characterized in that, include: The system receives an acceleration processing instruction for polynomial data to be processed for cryptographic operations, the acceleration processing instruction including: the number n of coefficients n in the polynomial data to be processed participating in the acceleration operation, where n is a positive integer; According to the acceleration processing instruction, obtain the n coefficient vectors of the polynomial data to be processed; The n coefficient vectors are input into the forward acceleration module of the n-level parallel operation for forward acceleration operation, and n forward operation results are obtained. Among them, the i-th coefficient vector is input into the i-th level forward acceleration module for forward acceleration operation, and the n-level forward acceleration module is an n-level parallel operation forward acceleration module based on field-programmable gate array; 1≤i≤n. The n forward operation results are shaped to obtain the shaped result of the n forward operation results. Specifically, this includes: performing a modulo operation on the n forward operation results to obtain the modulo operation result; and performing address shaping based on the modulo operation result to obtain the shaped result of the n forward operation results. The shaped results of n forward operations are input into the n-stage parallel reverse acceleration module for reverse acceleration, and the reverse operation results are obtained and output.

2. The data acceleration processing method for cryptographic operations according to claim 1, characterized in that, According to the acceleration processing instruction, obtain n coefficient vectors of the polynomial data to be processed, including: According to the acceleration processing instruction, n coefficient vectors of the polynomial data to be processed are read from the first random access memory corresponding to the i-th stage acceleration operation module.

3. The data acceleration processing method for cryptographic operations according to claim 2, characterized in that, The n coefficient vector is input into the forward acceleration module of the n-level parallel operation for forward acceleration operation, and n forward operation results are obtained, including: Read the rotation factor corresponding to the coefficient vector from the i-th first random access memory corresponding to the i-th stage forward acceleration module; The n coefficient vector and rotation factor are input into the butterfly operation module in the forward acceleration operation module of the n-level parallel operation to perform butterfly operation and obtain n forward operation results.

4. The data acceleration processing method for cryptographic operations according to claim 3, characterized in that, The n coefficient vector and the rotation factor are input into the butterfly operation module in the forward acceleration operation module of the n-level parallel operation to perform butterfly operation, and n forward operation results are obtained, including: determining the number of layers L of the coefficient vector, L=log(n)-1; Based on the layer number L of the coefficient vector, the coefficient vectors of the corresponding layer number are operated on sequentially according to the rotation factor to obtain n forward operation results.

5. The data acceleration processing method for cryptographic operations according to claim 3, characterized in that, After obtaining the results of n forward operations, it also includes: The results of n forward operations are stored in the i-th second random access memory corresponding to the i-th stage acceleration module in a first-in-first-out order.

6. The data acceleration processing method for cryptographic operations according to claim 1, characterized in that, The shaped results of n forward operations are input into the n-stage parallel reverse acceleration module for reverse acceleration, yielding the reverse operation results, including: Read the inverse factor of the rotation factor corresponding to the i-th coefficient vector from the i-th third random access memory corresponding to the i-th level inverse acceleration module; Perform a butterfly operation on the i-th coefficient vector based on the i-th inverse factor to obtain the i-th inverse operation result, until n inverse operation results are obtained.

7. A data acceleration processing device for cryptographic operations, characterized in that, include: The receiving module is used to receive an acceleration processing instruction for polynomial data to be processed for cryptographic operations, wherein the acceleration processing instruction includes: the number n of coefficients n in the polynomial data to be processed participating in the acceleration operation, wherein n is a positive integer; The processing module is used to obtain n coefficient vectors of the polynomial data to be processed according to the acceleration processing instructions; input the n coefficient vectors into the forward acceleration module of n-level parallel operation for forward acceleration operation to obtain n forward operation results; wherein, the i-th coefficient vector is input into the i-th level forward acceleration module for forward acceleration operation, and the n-level forward acceleration module is an n-level parallel operation forward acceleration module based on field-programmable gate array; 1≤i≤n; perform shaping processing on the n forward operation results to obtain the shaped results of the n forward operation results, specifically including: performing modulo operation on the n forward operation results to obtain the modulo operation result; performing address shaping according to the modulo operation result to obtain the shaped results of the n forward operation results; input the shaped results of the n forward operation results into the reverse acceleration module of n-level parallel operation for reverse acceleration operation to obtain the reverse operation result, and output it.

8. A computing device, characterized in that, include: A processor, a memory storing a computer program, wherein the computer program, when executed by the processor, performs the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Store instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 6.

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