Processor and program processing methods

Abstract

This application discloses a processor and a program processing method, relating to the field of computer technology. The processor includes: a processor core; a bus matrix including multiple master ports and multiple slave ports; master ports are used to connect to the processor core or other master devices, and slave ports are used to connect to slave devices; an instruction bus, through which the processor core is connected to a first master port; a data bus, through which the processor core is connected to a second master port; and private local memory, connected to the processor core via the instruction bus and / or the data bus. The processor sets up private local memory between the bus matrix and the processor core, allowing the processor core to connect to the processor core via the instruction bus and / or the data bus. During program execution, the processor core can retrieve program instructions from the private local memory via the instruction bus, or retrieve program data from the private local memory via the data bus. This reduces bus access latency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically to a processor and a program processing method. Background Technology

[0002] With social development, technological advancements, and improved living standards, the demand for consumer electronics is increasing daily, leading to a proliferation of electronic products. Consumer electronics come in a wide variety of types, with varying performance requirements, different chip design requirements, and vastly different main control processor choices. Processors used in home interconnect control modules and low-power control sections of large-scale designs generally have lower performance. Improving the performance of such processors is a key technical problem that needs to be addressed. Summary of the Invention

[0003] The purpose of this application is to provide a processor and a program processing method to solve the technical problem of how to improve processor performance in the prior art.

[0004] To achieve the above objectives, a first aspect of this application provides a processor, comprising: a processor core;

[0005] The bus matrix includes multiple master ports and multiple slave ports; the master ports are used to connect to the processor core or other master devices, and the slave ports are used to connect to slave devices.

[0006] Instruction bus: The processor core is connected to the first master port via the instruction bus.

[0007] The processor core connects to the second master port via the data bus.

[0008] Private local memory is connected to the processor core via the instruction bus and / or data bus.

[0009] In this embodiment, the private local memory includes: a first private local memory, which is provided with a first port and a second port; the first port of the first private local memory is connected to the instruction bus, and the second port of the first private local memory is connected to the data bus; the first private local memory is used to load program instructions of the program run by the processor core through the second port, and to transmit program instructions to the processor core through the first port.

[0010] In this embodiment of the application, the private local memory includes: a second private local memory; the second private local memory is used to store program data of the program running by the processor core.

[0011] In this embodiment, the private local memory includes: a first private local memory, which is provided with a first port and a second port; the first private local memory is divided into a program data storage area and a program instruction storage area; the first port of the first private local memory is connected to the instruction bus, and the second port of the first private local memory is connected to the data bus; the first private local memory is used to load program instructions of the program run by the processor core into the instruction storage area through the second port, and to transmit program instructions from the instruction storage area to the processor core through the first port; the first private local memory is also used to store program data of the program run by the processor core.

[0012] In this embodiment of the application, the first private local memory is a dual-port random access memory.

[0013] In this embodiment, the processor further includes a system bus, and the processor core is connected to a third master port via the system bus.

[0014] In this embodiment of the application, other master devices include: a DMA controller and a Flash controller.

[0015] In this embodiment of the application, the slave device includes: a boot read-only memory and a system static random access memory.

[0016] The second aspect of this application provides a program processing method applied to the processor provided in the first aspect of this application. The program processing method includes: a processor core acquiring a first program instruction via an instruction bus in a first clock cycle; the processor core acquiring a second program instruction via an instruction bus in a second clock cycle, and acquiring first program data via a data bus based on the decoding result of the first program instruction; and in a third clock cycle, the processor core determining the execution result of the first program instruction based on the first program instruction and the first program data, acquiring second program data via a data bus based on the decoding result of the second program instruction, and acquiring a third program instruction via an instruction bus.

[0017] In this embodiment of the application, the private local memory includes: a first private local memory, which is provided with a first port and a second port; the first private local memory is divided into a program data storage area and a program instruction storage area;

[0018] The processor core fetches the first program instructions via the instruction bus in the first clock cycle, including:

[0019] In the first clock cycle, the processor core retrieves the first program instruction from the program instruction memory area via the instruction bus and the first port.

[0020] In the second clock cycle, the processor core acquires a second program instruction via the instruction bus and, based on the decoding result of the first program instruction, acquires first program data via the data bus, including:

[0021] In the second clock cycle, the processor core retrieves the second program instruction from the program instruction memory area via the instruction bus and the first port.

[0022] In the second clock cycle, the processor core retrieves the first program data from the program data storage area via the data bus and the second port, based on the decoding result of the first program instruction.

[0023] The processor provided by the above technical solution sets up private local memory between the bus matrix and the processor core, and connects the processor core to the bus via the instruction bus and / or data bus. Thus, during program execution, the processor core can fetch program instructions from the private local memory via the instruction bus, or retrieve program data from the private local memory via the data bus. This reduces the bus access latency of the processor core, improving processor performance while reducing power consumption.

[0024] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings:

[0026] Figure 1 This schematic diagram illustrates a structural block diagram of a processor according to an embodiment of the present application;

[0027] Figure 2 A schematic block diagram of another processor according to an embodiment of this application is shown;

[0028] Figure 3 A schematic block diagram of another processor according to an embodiment of this application is shown.

[0029] Figure 4 The illustration shows a flowchart of a program processing method according to an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures

[0031] Processor core 102; Bus matrix 104; Instruction bus 106; Data bus 108;

[0032] System bus 110; First private local memory 112; Second private local memory 114;

[0033] First main port 116; Second main port 118; Third main port 120; First port 122; Second port 124. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0035] It should be noted that the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with relevant laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the solution has been or necessarily been used.

[0036] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0037] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0038] Processors used in home interconnect control modules and low-power control sections of large-scale designs typically have low performance, and these applications often require low power consumption, thus limiting processor performance. To improve performance, the first obvious approach is to increase the processor's clock speed. However, increasing the clock speed increases power consumption, which contradicts the low-power requirement, making it an unwise solution. Therefore, this application provides a processor that avoids the aforementioned conflict between processor clock speed and low power consumption by reducing bus access latency and increasing bandwidth utilization to improve processor performance.

[0039] like Figure 1 As shown, this application embodiment provides a processor. The processor includes: a processor core 102, a bus matrix 104, an instruction bus 106, a data bus 108, and private local memory.

[0040] Bus matrix 104 includes multiple master ports and multiple slave ports; the master ports are used to connect to processor core 102 or other master devices, and the slave ports are used to connect to slave devices.

[0041] Instruction bus 106, processor core 102 is connected to first master port 116 through instruction bus 106;

[0042] Data bus 108, processor core 102 is connected to the second master port 118 through data bus 108;

[0043] Private local memory is connected to the processor core 102 via the instruction bus 106 and / or the data bus 108.

[0044] The processor provided in this embodiment sets up private local memory between the bus matrix 104 and the processor core 102, and connects the processor core 102 via the instruction bus 106 and / or the data bus 108. Thus, during program execution, the processor core 102 can retrieve program instructions from the private local memory via the instruction bus 106, or retrieve program data from the private local memory via the data bus 108. This reduces the bus access latency of the processor core 102, improving processor performance while reducing power consumption.

[0045] Understandably, the bus matrix 104 can achieve data interaction between multiple master ports and multiple slave ports through its internal circuit structure arbitration and routing logic. The processor core 102 and other master devices can initiate bus access requests and send addresses, control signals, and write data to the bus. Slave devices can respond to bus access requests and, after being selected based on address decoding, provide read data or receive write data. The number of other master devices can be multiple. Figure 1Mn is used to represent the nth master device; S1, S2, S3 to Sn are used to represent the n slave devices.

[0046] like Figure 1 or Figure 2 As shown, in some embodiments of this application, the private local memory may include: a second private local memory 114. The second private local memory 114 is used to store program data of the program running by the processor core 102.

[0047] like Figure 1 or Figure 2 The processor shown does not have a cache (CATCH) or tightly coupled memory (TCM). The processor provided in this embodiment modifies the storage area for program data to be located next to the processor's data bus 108 by setting a second private local memory, and adds the second private local memory on the data bus 108. Since the data bus 108 can initiate read and write operations, program data can be pre-written into the second private local memory via the data bus 108. The processor core 102 accesses program data with the second private local memory through the data bus 108.

[0048] like Figure 1 As shown, in some embodiments of this application, the private local memory may include: a first private local memory 112, which is provided with a first port 122 and a second port 124. The first port 122 of the first private local memory 112 is connected to the instruction bus 106, and the second port 124 of the first private local memory 112 is connected to the data bus 108. The first private local memory 112 is used to load program instructions of the program executed by the processor core 102 through the second port 124, and to transmit program instructions to the processor core 102 through the first port 122.

[0049] Since the processor core 102 can read program instructions via the instruction bus 106, and the instruction bus 106 only performs read operations, the first private local memory 112 configured in the above embodiment is provided with a first port 122 and a second port 124. The first port 122 is connected to the instruction bus 106, and the second port 124 is connected to the data bus 108. The first private local memory 112 can load program instructions via the second port 124 and the data bus 108, and the first private local memory 112 stores program instructions. The processor core 102 can read and execute program instructions from the first private local memory 112 via the instruction bus 106 and the first port 122, thereby reducing the access latency of the instruction bus 106.

[0050] As an example, Figure 1 The processor shown includes a first private local memory 112 and a second private local memory 114. Figure 1The processor shown can simultaneously reduce the access latency of the instruction bus 106 and the access latency of the data bus 108.

[0051] like Figure 3 As shown, in some embodiments of this application, the private local memory may include a first private local memory 112. The first private local memory 112 is provided with a first port 122 and a second port 124; the first private local memory 112 is divided into a program data storage area and a program instruction storage area.

[0052] The first port 122 of the first private local memory 112 is connected to the instruction bus 106, and the second port 124 of the first private local memory 112 is connected to the data bus 108. The first private local memory 112 is used to load program instructions of the program executed by the processor core 102 into the instruction storage area through the second port 124, and to transfer program instructions from the instruction storage area to the processor core 102 through the first port 122. The first private local memory 112 is also used to store program data of the program executed by the processor core 102.

[0053] Figure 3 The processor shown has a first private local memory 112 divided into a program data storage area and a program instruction storage area, which can store program data and program instructions. Figure 3 The processor shown can dynamically allocate program data storage area and program instruction storage area based on a first private local memory 112 with a program data storage area and a program instruction storage area, thereby maximizing the program's operation based on the first private local memory 112 and improving the efficiency of the processor core 102 in executing programs.

[0054] Specifically, the storage space occupied by the program instructions and program data of the software program is less than or equal to the total storage space of the first private local memory 112.

[0055] Understandably, a software program can be divided into code segments and data segments during the compilation phase. The code segment represents program instructions, and the data segment represents program data. Before the software program runs, the data and code segments can be burned into the first private local memory 112 via a host computer, and a program data storage area and a program instruction storage area can be correspondingly allocated. Therefore, if the total storage space required by the software program's data and code segments is less than or equal to the total storage space of the first private local memory 112, the program data storage area and program instruction storage area of ​​the first private local memory 112 can be dynamically allocated based on the size of the data segment and the size of the code segment.

[0056] In some embodiments of this application, since the instruction bus 106 only performs read operations, the first private local memory 112 can be a dual-port random access memory (DRAM). A DRAM is a memory with two ports, such as... Figure 1 or Figure 3 As shown, the second port 124 of the dual-port random access memory is used to load the program instructions that the instruction bus 106 needs to transmit using the data bus 108. After the program instructions are loaded, the instruction bus 106 reads the program instructions through the first port 122 of the dual-port random access memory and executes them, thus minimizing the delay value of the instruction bus 106.

[0057] In some embodiments of this application, other master devices may include a DMA controller and a Flash controller. Understandably, the DMA controller can be used for data transfer, and the Flash controller can be responsible for managing access to the Flash memory of the slave node by the processor core 102 or the DMA controller.

[0058] In some embodiments of this application, the slave device may include a boot read-only memory and a system static random access memory. Specifically, the boot read-only memory is typically used once during power-on for loading the bootloader; to avoid wasting the slave port, the boot read-only memory and the system static random access memory may reuse a single slave port. In such cases... Figures 1 to 3 The first slave device S1 shown may include a boot read-only memory (bootrom) and a first system static random access memory (sram0), and the second slave device S2 may include a second system static random access memory (sram1).

[0059] like Figures 1 to 3 As shown, in some embodiments of this application, the processor further includes a system bus 110, through which the processor core 102 is connected to a third master port 120. Specifically, the system bus 110 can be used to enable the processor core 102 to access data from slave devices and perform read / write operations.

[0060] This application also provides a program processing method applicable to the aforementioned processor. The program processing method includes:

[0061] S402, the processor core 102 obtains the first program instruction through the instruction bus 106 in the first clock cycle;

[0062] S404, the processor core 102 obtains the second program instruction through the instruction bus 106 in the second clock cycle, and obtains the first program data through the data bus 108 according to the decoding result of the first program instruction.

[0063] In the third clock cycle, the processor core 102 determines the execution result of the first program instruction based on the first program instruction and the first program data, obtains the second program data through the data bus 108 based on the decoding result of the second program instruction, and obtains the third program instruction through the instruction bus 106.

[0064] Based on the above steps, the processor core 102 can synchronously acquire program instructions, acquire program data, and execute program instructions within the same clock cycle, thereby achieving synchronous processing of multiple instructions and reducing the latency of the processor core 102 in executing program instructions.

[0065] like Figure 3 As shown, in some embodiments of this application, the private local memory may include: a first private local memory 112, which is provided with a first port 122 and a second port 124; the first private local memory 112 is divided into a program data storage area and a program instruction storage area. Step S402 may include: the processor core 102 obtaining a first program instruction from the program instruction storage area through the instruction bus 106 and the first port 122 in a first clock cycle. Step S404 may include: the processor core 102 obtaining a second program instruction from the program instruction storage area through the instruction bus 106 and the first port 122 in a second clock cycle; the processor core 102 obtaining first program data from the program data storage area through the data bus 108 and the second port 124 according to the decoding result of the first program instruction in the second clock cycle.

[0066] Based on the above steps, the effect of synchronous processing of multiple instructions on reducing the latency of the processor core 102 executing program instructions can be combined with the effect of the first private local memory 112 on reducing the access latency of the processor core 102 accessing the instruction bus 106 and the data bus 108, thereby further reducing the access latency of the processor core 102 and improving the operating efficiency of the processor.

[0067] As an example, Table 1 below provides access latency and bandwidth utilization for the same software program executed on different processors.

[0068] Table 1 Comparison of Access Latency and Bandwidth Utilization

[0069]

[0070] The access latency in Table 1 is represented by the processor's clock cycles. As can be seen from Table 1, the multi-instruction synchronous processing combined with private local memory technology significantly reduces access latency and significantly improves bandwidth utilization compared to existing technologies.

[0071] In summary, the processor provided in this application reduces bus access latency by setting up private local memory on the data bus 108 and / or instruction bus 106 between the mainline matrix and the processor core 102. Furthermore, by combining the program processing method provided in this application with the technical solution of synchronous processing of multiple instructions and setting up private local memory, the access latency of the processor core 102 is further reduced, thereby improving the operating efficiency of the processor.

[0072] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0077] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0078] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0079] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0080] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A processor, characterized in that, include: Processor core; The bus matrix includes multiple master ports and multiple slave ports; The master port is used to connect to the processor core or other master devices, and the slave port is used to connect to slave devices; Instruction bus, through which the processor core is connected to the first master port; A data bus, through which the processor core is connected to a second master port; Private local memory is connected to the processor core via the instruction bus and / or the data bus; The processor is used in a home interconnect control module, and the processor has no cache and tightly coupled memory; The private local memory includes: a first private local memory, which is provided with a first port and a second port; the first private local memory is divided into a program data storage area and a program instruction storage area. The first port of the first private local memory is connected to the instruction bus, and the second port of the first private local memory is connected to the data bus; the first private local memory is used to load program instructions of the program run by the processor core into the program instruction storage area through the second port, and to transmit program instructions of the program instruction storage area to the processor core through the first port; the first private local memory is also used to store program data of the program run by the processor core. The bus matrix is ​​used to realize data interaction between the multiple master ports and the multiple slave ports through arbitration and routing logic of the internal circuit structure. This enables the processor core and other master devices to initiate bus access requests and send addresses, control signals and write data to the bus. Slave devices respond to the bus access requests and provide read data or receive write data after being selected according to the address decoding.

2. The processor according to claim 1, characterized in that, The private local memory includes: a second private local memory; The second private local memory is used to store program data of the program running by the processor core.

3. The processor according to claim 1, characterized in that, The first private local memory is a dual-port random access memory.

4. The processor according to claim 1, characterized in that, The processor also includes: The processor core is connected to a third master port via the system bus.

5. The processor according to claim 1, characterized in that, The other main equipment includes: DMA controller and Flash controller.

6. The processor according to claim 1, characterized in that, The slave device includes: Start the read-only memory and system static random access memory.

7. A program processing method, characterized in that, Applied to the processor according to any one of claims 1-6, the program processing method includes: The processor core acquires a first program instruction via the instruction bus in the first clock cycle. The processor core acquires a second program instruction via the instruction bus in the second clock cycle, and acquires first program data via the data bus based on the decoding result of the first program instruction. In the third clock cycle, the processor core determines the execution result of the first program instruction based on the first program instruction and the first program data, obtains the second program data through the data bus based on the decoding result of the second program instruction, and obtains the third program instruction through the instruction bus.

8. The program processing method according to claim 7, characterized in that, The processor core acquires a first program instruction via the instruction bus in the first clock cycle, including: The processor core retrieves the first program instruction from the program instruction storage area via the instruction bus and the first port in the first clock cycle. The processor core acquires a second program instruction via the instruction bus in the second clock cycle, and acquires first program data via the data bus based on the decoding result of the first program instruction, including: During the second clock cycle, the processor core retrieves the second program instruction from the program instruction storage area via the instruction bus and the first port. During the second clock cycle, the processor core acquires the first program data in the program data storage area through the data bus and the second port, based on the decoding result of the first program instruction.

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