Server system and circuit verification method

Abstract

A server system includes a management circuit and a processing circuit. The management circuit comprises a first control circuit, a second control circuit and a first memory. The first control circuit includes a storage unit and firmware. The storage unit is used for storing a first list. The firmware includes a plurality of resident programs (Daemon). The second control circuit is coupled to the first control circuit. The first memory is coupled to the first control circuit. The first memory is used for storing a first verification value. The processing circuit is coupled to the management circuit. The processing circuit includes a second memory and a power control circuit. The second memory is coupled to the first control circuit. The second memory is used for storing a second verification value and processing circuit identification information. The power supply control circuit is coupled to the second control circuit and the power supply.

Description

Technical Field

[0001] This invention relates to a security technology, specifically a server system and circuit verification method with circuit compatibility verification and accelerated boot verification time functions. Background Technology

[0002] In a typical server, the server's management board and system board are somewhat interdependent. The basic input / output system (BIOS) firmware and its baseboard management controller (BMC) firmware on the server's management board are usually developed specifically for the hardware contained in the server's system board.

[0003] However, there is currently no verification method available to verify the compatibility between the server's management board and the server's system board. This means that when a server has both incompatible system and management boards, problems are often not detected immediately after powering on. Instead, the server may crash or even fail due to incompatibility, causing damage to components. Only after maintenance personnel analyze the causes of the errors layer by layer do they discover that the errors or damage are caused by hardware and software problems resulting from the incompatible management board paired with the server's system board. Summary of the Invention

[0004] Therefore, the purpose of this invention is to provide a server system and a circuit verification method.

[0005] In some embodiments, a server system includes a management circuit and a processing circuit. The management circuit includes a first control circuit, a second control circuit, and a first memory. The first control circuit includes a storage unit and firmware. The storage unit stores a first inventory. The firmware includes a plurality of daemons. The second control circuit is coupled to the first control circuit. The first memory is coupled to the first control circuit. The first memory stores a first verification value. The processing circuit is coupled to the management circuit. The processing circuit includes a second memory and a power control circuit. The second memory is coupled to the first control circuit. The second memory stores a second verification value and processing circuit identification information. The power control circuit is coupled to the second control circuit and a power supply. The first control circuit compares the first verification value and the second verification value to verify the processing circuit. When the processing circuit passes verification, the first control circuit provides a first signal to the second control circuit, and the second control circuit provides a start signal to the power control circuit based on the first signal. The power control circuit controls the power supply to the processing circuit to start the processing circuit based on the start signal. When the processing circuit starts normally and all the resident programs execute normally after the processing circuit starts, the first control circuit stores the processing circuit identification information in the first list.

[0006] In some embodiments, the storage unit is further used to store a second list. When the processing circuit fails verification, the first control circuit provides a second signal to the second control circuit, and the second control circuit provides a startup rejection signal to the power control circuit based on the second signal. The power control circuit controls the power supply to not supply power to the processing circuit based on the startup rejection signal so that the processing circuit does not start. Furthermore, when the processing circuit fails verification, the first control circuit stores the processing circuit identification information in the second list.

[0007] In some embodiments, when the processing circuit fails to start normally or when the resident programs malfunction after the processing circuit starts, the first control circuit stores the processing circuit identification information into the second list.

[0008] In some embodiments, before comparing the first verification value and the second verification value to verify the processing circuit, the first control circuit further checks whether the processing circuit identification information has been stored in the first list or the second list. When the processing circuit identification information has been stored in the first list, the first control circuit provides the first signal to the second control circuit, and the second control circuit provides the start signal to the power control circuit based on the first signal. The power control circuit controls the power supply to power the processing circuit to start the processing circuit based on the start signal.

[0009] In some embodiments, when the processing circuit identification information is stored in the second list, the first control circuit provides the second signal to the second control circuit, and the second control circuit provides the restart rejection signal to the power control circuit based on the second signal. The power control circuit controls the power supply not to supply power to the processing circuit based on the restart rejection signal so that the processing circuit does not start.

[0010] In some embodiments, when the processing circuit identifies that the information is not stored in the first list or the second list, the first control circuit compares the first verification value and the second verification value to verify the processing circuit.

[0011] In some embodiments, when the processing circuit fails to start normally or the resident programs malfunction after the processing circuit starts, the first control circuit executes a repair procedure. If the processing circuit still fails to start normally or the resident programs still malfunction after the first control circuit executes the repair procedure multiple times, the first control circuit stores the processing circuit identification information in the second list.

[0012] In some embodiments, the server system further includes a display device. When the processing circuit fails verification, the processing circuit fails to start normally, or the resident programs malfunction after the processing circuit starts, and when the processing circuit identification information is stored in the second list, the first control circuit displays an error message on the display device.

[0013] In some embodiments, a circuit verification method is applicable to a server system. The server system includes a management circuit and a processing circuit. The processing circuit is coupled to the management circuit. The management circuit includes a first control circuit, a second control circuit, and a first memory. The first control circuit includes a storage unit and firmware. The second control circuit is coupled to the first control circuit. The processing circuit includes a second memory and a power control circuit. The second memory is coupled to the first control circuit. The power control circuit is coupled to the second control circuit. The circuit verification method includes: the first control circuit comparing a first verification value stored in the first memory with a second verification value stored in the second memory to verify the processing circuit; when the processing circuit passes the verification, the first control circuit provides a first signal to the second control circuit, the second control circuit provides a start signal to the power control circuit based on the first signal, the power control circuit controls a power supply to power the processing circuit based on the start signal to start the processing circuit; and when the processing circuit starts normally and the multiple resident programs contained in the firmware are all executed normally after the processing circuit starts, the first control circuit stores the processing circuit identification information stored in the second memory into a first list of the storage unit.

[0014] In some embodiments, the storage unit is further configured to store a second list. The circuit verification method further includes: when the processing circuit fails verification, the first control circuit provides a second signal to the second control circuit, the second control circuit provides a restart rejection signal to the power control circuit based on the second signal, and the power control circuit controls the power supply not to supply power to the processing circuit based on the restart rejection signal so that the processing circuit does not start; and when the processing circuit fails verification, the first control circuit stores the processing circuit identification information in the second list.

[0015] Compared with existing technologies, the server system and circuit verification method of the present invention allow the first control circuit to verify the compatibility between the management circuit and the processing circuit by comparing a first verification value and a second verification value. Only when the processing circuit passes the verification does the first control circuit supply power to the processing circuit to enable it to start. Therefore, by implementing this circuit verification method, the server system can avoid hardware and software problems caused by incompatibility between the management circuit and the processing circuit after the processing circuit starts.

[0016] The following detailed description of the features and advantages of the present invention is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the content disclosed in this specification, the claims and the accompanying drawings, anyone skilled in the art can easily understand the relevant objectives and advantages of the present invention. Attached Figure Description

[0017] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0018] Figure 1 A block diagram illustrating one embodiment of a server system;

[0019] Figure 2 A flowchart of one embodiment of a circuit verification method;

[0020] Figure 3 A flowchart of another embodiment of the circuit verification method; and

[0021] Figure 4 and Figure 5 This is a flowchart of yet another embodiment of the circuit verification method. Detailed Implementation

[0022] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0023] Please see Figure 1 Server system 1 includes management circuitry 10 and processing circuitry 20. The management circuitry includes a first control circuitry 11, a second control circuitry 12, and a first memory 13. The first control circuitry 11 includes a storage unit 111 and firmware. The storage unit 111 stores a first manifest 112 and a second manifest 113, and the firmware contains multiple daemons. The second control circuitry 12 and the first memory 13 are coupled to the first control circuitry 11. The first memory 13 stores a first verification value 131. The processing circuitry 20 is coupled to the management circuitry 10. The processing circuitry 20 includes second memory 21 and a power control circuitry 22. The second memory 21 is coupled to the first control circuitry 11. The second memory 21 stores a second verification value 211 and processing circuit identification information 212. The power control circuitry 22 is coupled to the second control circuitry 12 and a power supply (not shown).

[0024] In some embodiments, the management circuit 10 may be, but is not limited to, a DC-SCM module (Data Center-ready Secure Control Module). In some embodiments, the processing circuit 20 may be, but is not limited to, a Host Processor Module (HPM). In some embodiments, the management circuit 10 and the processing circuit 20 are disposed on different circuit boards, but the present invention is not limited thereto. In some embodiments, the management circuit 10 and the processing circuit 20 are disposed on the same circuit board. In some embodiments, the processing circuit 20 is pluggably connected to the management circuit 10. In some embodiments, the first control circuit 11 may be, but is not limited to, a Baseboard Management Controller (BMC). In some embodiments, the second control circuit 12 may be, but is not limited to, a Complex Programmable Logic Device (CPLD). In some embodiments, the second control circuit 12 is connected via an integrated bus circuit (I 2 The first memory 13 and the second memory 21 are connected to the second memory 21 via a C-bus, but this invention is not limited thereto. In some embodiments, the first memory 13 and the second memory 21 are electronically erasable rewritable read-only memories (EEPROMs), but this invention is not limited thereto. In some embodiments, the first memory 13 and the second memory 21 can be any non-volatile storage medium, such as a read-only memory (ROM), such as a rewritable read-only memory (PROM), an erasable rewritable read-only memory (EPROM), an EEPROM, a programmable-once read-only memory (OTPROM), or flash memory, and the types of the first memory 13 and the second memory 21 are not limited herein. In some embodiments, the first memory 13 and the second memory 21 can be, but are not limited to, a field replaceable unit (FRU). In some embodiments, the storage unit 111 can be any non-volatile storage medium, such as a ROM, PROM, EPROM, EEPROM, OTPROM, or flash memory, and the type of storage unit 111 is not limited herein.

[0025] Please see Figure 1 and Figure 2In some embodiments, the first control circuit 11 compares the first verification value 131 and the second verification value 211 to verify the processing circuit 20 (step S01). When the processing circuit 20 passes the verification, the first control circuit 11 provides a first signal S1 to the second control circuit 12, and the second control circuit 12 provides a start signal S3 to the power control circuit 22 according to the first signal S1. The power control circuit 22 controls the power supply to the processing circuit 20 according to the start signal S3 to start the processing circuit 20 (step S02). When the processing circuit 20 starts normally and multiple resident programs execute normally after the processing circuit 20 starts, the first control circuit 11 stores the processing circuit identification information 212 in the first list 112 (step S03).

[0026] In some embodiments, prior to step S01, the management circuit 10 further detects the connection status between the processing circuit 20 and the management circuit 10. When the management circuit 10 detects a connected connection, it triggers the first control circuit 11 to compare the first verification value 131 and the second verification value 211 to verify the processing circuit 20 (i.e., step S01). In some embodiments, when the management circuit 10 detects a disconnected connection, it does not trigger the first control circuit 11 to execute step S01. In some embodiments, the management circuit 10 detects the connection status between the processing circuit 20 and the management circuit 10 via a detection pin, but the present invention is not limited thereto.

[0027] In some embodiments, the first verification value 131 is the product ID and SKU ID of the management circuit 10, and the second verification value 211 is the product ID and SKU ID of the processing circuit 20, but the present invention is not limited thereto. In some embodiments, the processing circuit identification information 212 is the address information of the processing circuit 20, such as the media access control address (MAC address) of the processing circuit 20, but the present invention is not limited thereto. In some embodiments, in step S03, when the processing circuit 20 starts normally and multiple resident programs execute normally after the processing circuit 20 starts, the first control circuit 11 stores the second verification value 211 in the first list 112. In some embodiments, the power supply is located in the processing circuit 20, but the present invention is not limited thereto. In some embodiments, the power supply is located in the management circuit 10 or at any location other than the management circuit 10 and the processing circuit 20, and the location of the power supply is not limited here.

[0028] In some embodiments, when the processing circuit 20 fails verification, the first control circuit 11 provides a second signal S2 to the second control circuit 12, and the second control circuit 12 provides a restart rejection signal S4 to the power control circuit 22 based on the second signal S2. The power control circuit 22 controls the power supply not to supply power to the processing circuit 20 based on the restart rejection signal S4 so that the processing circuit 20 does not start (step S04). Furthermore, when the processing circuit 20 fails verification, the first control circuit 11 stores the processing circuit identification information 212 in the second list 113 (step S05). In some embodiments, in step S05, when the processing circuit 20 fails verification, the first control circuit 11 stores the second verification value 211 in the second list 113.

[0029] In some embodiments, the first control circuit 11 is implemented via a serial general purpose input / output (SGPIO) or I / O. 2 CBus is connected to the second control circuit 12, that is, the first control circuit 11 is connected via SGPIO or I 2 The C-bus transmits a first signal S1 or a second signal S2 to the second control circuit 12, but the present invention is not limited thereto. In some embodiments, the second control circuit 12 is connected to the power control circuit 22 through a Data Center Secure Control Interface (DC-SCI), that is, the second control circuit 12 transmits a start signal S3 or a reject start signal S4 to the power control circuit 22 through the DC-SCI, but the present invention is not limited thereto.

[0030] In some embodiments, when the processing circuit 20 fails to start normally or multiple resident programs malfunction after the processing circuit 20 starts, the first control circuit 11 stores the processing circuit identification information 212 into the second list 113 (step S06). In some embodiments, in step S06, when the processing circuit 20 fails to start normally or multiple resident programs malfunction after the processing circuit 20 starts, the first control circuit 11 stores the second verification value 211 into the second list 113.

[0031] In some embodiments, the first control circuit 11 verifies the method by executing multiple resident programs, but the present invention is not limited thereto.

[0032] In summary, the first control circuit 11 can verify the compatibility between the management circuit 10 and the processing circuit 20 by comparing the first verification value 131 and the second verification value 211. Only when the processing circuit 20 passes the verification will the first control circuit 11 supply power to the processing circuit 20 to start it up. Therefore, by implementing the circuit verification method, the server system 1 can avoid hardware and software problems caused by incompatibility between the management circuit 10 and the processing circuit 20 after the processing circuit 20 starts up.

[0033] Please see Figure 1 and Figure 3 In some embodiments, when the processing circuit 20 fails to start normally or multiple resident programs malfunction after the processing circuit 20 starts, the first control circuit 11 executes a repair procedure (step S07). When the first control circuit 11 executes the repair procedure multiple times, and the processing circuit 20 still fails to start normally or multiple resident programs still malfunction (step S08), the first control circuit 11 stores the processing circuit identification information 212 in the second list 113 (step S06).

[0034] In some embodiments, the server system 1 further includes a display device (not shown). In some embodiments, when the processing circuit 20 fails verification, the first control circuit 11 displays an error message on the display device (step S09). In some embodiments, when the processing circuit 20 fails to start normally or multiple resident programs malfunction after the processing circuit 20 starts, the first control circuit 11 also displays an error message on the display device (step S10).

[0035] Please see Figure 1 and Figures 4 to 5 In some embodiments, before comparing the first verification value 131 and the second verification value 211 to verify the processing circuit 20, the first control circuit 11 checks whether the processing circuit identification information 212 has been stored in the first list 112 or the second list 113 (step S11). When the processing circuit identification information 212 has been stored in the first list 112, the first control circuit 11 provides a first signal S1 to the second control circuit 12, and the second control circuit 12 provides a start signal S3 to the power control circuit 22 according to the first signal S1. The power control circuit 22 controls the power supply to the processing circuit 20 according to the start signal S3 to start the processing circuit 20 (step S12).

[0036] In some embodiments, prior to step S11, the management circuit 10 further detects the connection status between the processing circuit 20 and the management circuit 10. When the management circuit 10 detects that the connection status is connected, the management circuit 10 triggers the first control circuit 11 to check whether the processing circuit identification information 212 has been stored in the first list 112 or the second list 113 (i.e., step S11). In some embodiments, when the management circuit 10 detects that the connection status is not connected, the management circuit 10 does not trigger the first control circuit 11 to execute step S11.

[0037] In some embodiments, when the processing circuit identification information 212 has been stored in the second list 113, the first control circuit 11 provides a second signal S2 to the second control circuit 12, and the second control circuit 12 provides a restart rejection signal S4 to the power control circuit 22 according to the second signal S2. The power control circuit 22 controls the power supply not to supply power to the processing circuit 20 according to the restart rejection signal S4 so that the processing circuit 20 does not start (step S13).

[0038] In some embodiments, the first control circuit 11 executes only when the processing circuit identification information 212 is not stored in the first list 112 or the second list 113. Figure 2 The circuit verification method shown or Figure 3 The circuit verification method shown is to verify the compatibility between the management circuit 10 and the processing circuit 20 by comparing the first verification value 131 and the second verification value 211.

[0039] Through steps S11 and S12, for processing circuits 20 whose processing circuit identification information 212 has been stored in the first list 112, the first control circuit 11 does not need to re-execute. Figure 2 or Figure 3 The circuit verification method shown can directly power the processing circuit 20. In other words, the processing circuit 20, which has passed the compatibility verification with the management circuit 10 by comparing the first verification value 131 and the second verification value 211, can be directly powered by the first control circuit 11 to start the processing circuit 20 when it is powered on again, thereby accelerating the power-on verification time of the processing circuit 20.

[0040] Similarly, through steps S11 and S13, for processing circuits 20 whose processing circuit identification information 212 has been stored in the second list 113, the first control circuit 11 does not need to re-execute. Figure 2 or Figure 3The circuit verification method shown can directly disable power supply to the processing circuit 20. In other words, if the processing circuit 20 fails the compatibility verification with the management circuit 10 by comparing the first verification value 131 and the second verification value 211, the first control circuit 11 can directly disable power supply to the processing circuit 20 upon restarting, thereby accelerating the power-on verification time of the processing circuit 20.

[0041] In some embodiments, if in step S03, the first control circuit 11 stores the second verification value 211 into the first list 112, and in steps S05 and S06, the first control circuit 11 stores the second verification value 211 into the second list 113, then in step S11, the first control circuit 11 checks whether the second verification value 211 has been stored in the first list 112 or the second list 113.

[0042] In some embodiments, when the processing circuit identification information 212 has been stored in the second list 113, the first control circuit 11 displays an error message on the display device (step S14).

[0043] In summary, in some embodiments, the server system 1 can avoid hardware and software problems caused by incompatibility between the management circuit 10 and the processing circuit 20 after the processing circuit 20 is started by executing the circuit verification method. Furthermore, the server system 1 can accelerate the startup verification time of the processing circuit 20 when it is restarted by executing steps S11 to S13.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A server system, characterized in that, Include: A management circuit, comprising: A first control circuit includes a storage unit and a firmware, the storage unit being used to store a first list, the firmware including a plurality of daemons; A second control circuit is coupled to the first control circuit; and A first memory, coupled to the first control circuit, is used to store a first verification value; and A processing circuit, coupled to the management circuit, includes: A second memory, coupled to the first control circuit, is used to store a second verification value and processing circuit identification information; and A power control circuit is coupled to the second control circuit and a power supply; The first control circuit is used to compare the first verification value and the second verification value to verify the processing circuit. When the processing circuit passes the verification, the first control circuit provides a first signal to the second control circuit. The second control circuit provides a start signal to the power control circuit based on the first signal. The power control circuit controls the power supply to the processing circuit based on the start signal to start the processing circuit. When the processing circuit starts normally and the resident programs are executed normally after the processing circuit starts, the first control circuit stores the processing circuit identification information in the first list.

2. The server system according to claim 1, characterized in that, The storage unit is further used to store a second list. When the processing circuit fails verification, the first control circuit provides a second signal to the second control circuit. The second control circuit provides a restart rejection signal to the power control circuit based on the second signal. The power control circuit controls the power supply not to supply power to the processing circuit based on the restart rejection signal so that the processing circuit does not start. When the processing circuit fails verification, the first control circuit stores the processing circuit identification information in the second list.

3. The server system according to claim 2, characterized in that, When the processing circuit fails to start normally or when the resident programs malfunction after the processing circuit starts, the first control circuit stores the processing circuit identification information into the second list.

4. The server system according to claim 3, characterized in that, Before comparing the first verification value and the second verification value to verify the processing circuit, the first control circuit checks whether the processing circuit identification information has been stored in the first list or the second list. When the processing circuit identification information has been stored in the first list, the first control circuit provides the first signal to the second control circuit. The second control circuit provides the start signal to the power control circuit based on the first signal. The power control circuit controls the power supply to power the processing circuit to start the processing circuit based on the start signal.

5. The server system according to claim 4, characterized in that, When the processing circuit identification information has been stored in the second list, the first control circuit provides the second signal to the second control circuit. The second control circuit provides the restart rejection signal to the power control circuit based on the second signal. The power control circuit controls the power supply not to supply power to the processing circuit based on the restart rejection signal so that the processing circuit does not start.

6. The server system according to claim 5, characterized in that, When the processing circuit identifies that the information is not stored in the first list or the second list, the first control circuit compares the first verification value and the second verification value to verify the processing circuit.

7. The server system according to claim 6, characterized in that, When the processing circuit fails to start normally or the resident programs malfunction after the processing circuit starts, the first control circuit executes a repair program. When the first control circuit executes the repair program multiple times and the processing circuit still fails to start normally or the resident programs still malfunction, the first control circuit stores the processing circuit identification information in the second list.

8. The server system according to claim 7, characterized in that, It also includes a display device. When the processing circuit fails to pass verification, the processing circuit cannot start normally, or the resident programs malfunction after the processing circuit starts, and when the processing circuit identification information has been stored in the second list, the first control circuit will display an error message on the display device.

9. A circuit verification method applicable to a server system, the server system comprising a management circuit and a processing circuit, the processing circuit being coupled to the management circuit, the management circuit comprising a first control circuit, a second control circuit, and a first memory, the first control circuit comprising a storage unit and firmware, the second control circuit being coupled to the first control circuit, the processing circuit comprising a second memory and a power control circuit, the second memory being coupled to the first control circuit, and the power control circuit being coupled to the second control circuit, characterized in that... The circuit verification method includes: The first control circuit compares a first verification value stored in the first memory with a second verification value stored in the second memory to verify the processing circuit; When the processing circuit passes the verification, the first control circuit provides a first signal to the second control circuit, the second control circuit provides a start signal to the power control circuit based on the first signal, and the power control circuit controls a power supply to power the processing circuit based on the start signal to start the processing circuit. and When the processing circuit starts normally and the multiple resident programs contained in the firmware are executed normally after the processing circuit starts, the first control circuit stores the processing circuit identification information stored in the second memory into a first list of the storage unit.

10. The circuit verification method according to claim 4, characterized in that, The storage unit is further used to store a second list, and the circuit verification method further includes: When the processing circuit fails verification, the first control circuit provides a second signal to the second control circuit, and the second control circuit provides a restart rejection signal to the power control circuit based on the second signal. The power control circuit controls the power supply to stop supplying power to the processing circuit based on the restart rejection signal so that the processing circuit does not start; and When the processing circuit fails verification, the first control circuit stores the processing circuit identification information in the second list.

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