Integrated circuit abnormal interconnection detection method and device, storage medium and electronic equipment

Abstract

The application discloses an integrated circuit abnormal interconnection detection method and device, a storage medium and an electronic equipment. The integrated circuit abnormal interconnection detection method comprises the following steps: obtaining layout data that passes LVS checking; extracting the physical layout features of each interconnection network from the layout data, and converting the physical layout features into feature vectors; analyzing all the feature vectors by using an unsupervised clustering algorithm, and calculating the abnormal scores of each interconnection network according to the analysis results; screening out suspected abnormal interconnection networks from all the interconnection networks based on the abnormal scores and a preset screening strategy; performing electric-thermal cooperative simulation on the suspected abnormal interconnection networks, obtaining the electrical performance indexes of the suspected abnormal interconnection networks, and determining whether the suspected abnormal interconnection networks are target abnormal interconnection networks based on the electrical performance indexes. The application can improve the accuracy of abnormal interconnection detection.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a method, apparatus, storage medium, and electronic device for detecting abnormal interconnections in integrated circuits. Background Technology

[0002] With the continuous evolution of semiconductor processes, 2.5D / 3D integration technology, through through-silicon vias (TSVs), interposers, and other methods, enables high-density interconnection of multiple bare dies, becoming a key path to extend Moore's Law and improve chip performance and integration density. However, this type of structure also brings unprecedented design complexity, especially in systems containing a large number of homogeneous or heterogeneous chiplets, where the size of the interconnect network grows exponentially, and verifying the correctness of its physical layout has become a major challenge restricting design cycles and product reliability.

[0003] Verification of such interconnected networks currently relies on layout and principles. Figure 1 LayoutversusSchematic (LVS) verification tool. This tool ensures complete electrical connectivity by comparing the geometric connections of the physical layout with the logical connections of the circuit schematic.

[0004] However, traditional LVS testing has an insurmountable blind spot when dealing with abnormal interconnections caused by design input errors, where "the electrical connection is correct but the logic function is wrong," resulting in low testing accuracy. Summary of the Invention

[0005] This application provides a method, apparatus, storage medium, and electronic device for detecting abnormal interconnections in integrated circuits, which can improve the accuracy of abnormal interconnection detection.

[0006] In a first aspect, embodiments of this application provide a method for detecting abnormal interconnections in integrated circuits, including:

[0007] Obtain layout data verified by LVS;

[0008] Extract the physical layout features of each interconnect network from the layout data, and transform the physical layout features into feature vectors;

[0009] An unsupervised clustering algorithm is used to analyze all the feature vectors, and an anomaly score for each interconnection network is calculated based on the analysis results.

[0010] Based on the anomaly score and a preset filtering strategy, suspected abnormal interconnection networks are filtered out from all the interconnection networks;

[0011] Electrothermal co-simulation is performed on the suspected abnormal interconnect network to obtain the electrical performance indicators of the suspected abnormal interconnect network, and the target abnormal interconnect network is determined based on the electrical performance indicators.

[0012] In the integrated circuit abnormal interconnect detection method provided in this application embodiment, the step of analyzing all the feature vectors using an unsupervised clustering algorithm and calculating the abnormal score of each interconnect network based on the analysis results includes:

[0013] An unsupervised clustering algorithm is used to cluster all the feature vectors to form at least one cluster.

[0014] The relationship between each feature vector and its cluster is analyzed according to a preset strategy, and the anomaly score of each interconnection network is determined based on the relationship.

[0015] In the integrated circuit abnormal interconnect detection method provided in this application embodiment, the step of analyzing the relationship between each feature vector and its cluster according to a preset strategy, and determining the abnormal score of each interconnect network based on the relationship, includes:

[0016] Calculate the distance from each of the aforementioned feature vectors to the cluster center of its respective cluster;

[0017] The anomaly score of the corresponding interconnection network is determined based on the distance.

[0018] In the integrated circuit abnormal interconnect detection method provided in this application embodiment, the step of analyzing the relationship between each feature vector and its cluster according to a preset strategy, and determining the abnormal score of each interconnect network based on the relationship, includes:

[0019] Obtain the membership degree of each cluster corresponding to each of the aforementioned feature vectors;

[0020] The anomaly score of the corresponding interconnection network is determined based on the membership degree.

[0021] In the integrated circuit abnormal interconnect detection method provided in the embodiments of this application, for the feature vector that does not belong to any cluster, the abnormal score of its corresponding interconnect network is assigned a preset maximum value.

[0022] In the integrated circuit abnormal interconnect detection method provided in this application embodiment, the step of filtering out suspected abnormal interconnect networks from all the interconnect networks based on the abnormality score and a preset screening strategy includes:

[0023] Based on a preset score threshold, interconnect networks with abnormal scores higher than the threshold are identified as suspected abnormal interconnect networks; or,

[0024] Based on a preset number of rankings, the interconnection networks ranked in the top N are identified as suspected abnormal interconnection networks, in descending order of abnormal scores, where N is a preset positive integer.

[0025] In the integrated circuit abnormal interconnect detection method provided in this application embodiment, the step of performing electrothermal co-simulation on the suspected abnormal interconnect network to obtain the electrical performance index of the suspected abnormal interconnect network, and determining whether the suspected abnormal interconnect network is a target abnormal interconnect network based on the electrical performance index, includes:

[0026] Extract the parasitic parameters of the suspected anomalous interconnect network under local heat distribution;

[0027] Based on the parasitic parameters, rapid circuit simulation is performed to obtain electrical performance indicators;

[0028] The electrical performance indicators are compared with the preset performance specifications;

[0029] If the electrical performance indicators do not meet the preset performance specifications, then the suspected abnormal interconnection network is determined to be the target abnormal interconnection network.

[0030] Secondly, embodiments of this application provide an integrated circuit abnormal interconnection detection device, comprising:

[0031] The acquisition unit is used to acquire layout data verified by LVS;

[0032] An extraction unit is used to extract the physical layout features of each interconnection network from the layout data and convert the physical layout features into a feature vector.

[0033] An analysis unit is used to analyze all the feature vectors using an unsupervised clustering algorithm and calculate the anomaly score of each interconnection network based on the analysis results.

[0034] A filtering unit is used to filter out suspected abnormal interconnection networks from all the interconnection networks based on the abnormality score and a preset filtering strategy;

[0035] The simulation unit is used to perform electrothermal co-simulation on the suspected abnormal interconnection network, obtain the electrical performance indicators of the suspected abnormal interconnection network, and determine whether the suspected abnormal interconnection network is the target abnormal interconnection network based on the electrical performance indicators.

[0036] Thirdly, this application provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the integrated circuit abnormal interconnection detection method described in any of the preceding claims.

[0037] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the integrated circuit abnormal interconnection detection method described in any of the preceding claims.

[0038] In summary, the integrated circuit abnormal interconnect detection method provided in this application first acquires the layout data verified by LVS and extracts the physical layout features of each interconnect network to generate feature vectors. Then, an unsupervised clustering algorithm is used to analyze all feature vectors, calculating anomaly scores for each interconnect network. Based on the anomaly scores and a preset strategy, suspected abnormal interconnect networks are selected. Finally, electrothermal co-simulation is performed on the selected suspected abnormal interconnect networks, and the final target abnormal interconnect network is determined based on its electrical performance indicators. This solution effectively identifies abnormal interconnects that are "electrically connected correctly but with logical design errors" by introducing intelligent physical feature analysis and electrical verification steps after traditional LVS verification. This significantly reduces the detection blind spots in the traditional verification process and improves the accuracy and reliability of abnormal interconnect detection. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating an application scenario of the integrated circuit abnormal interconnection detection method provided in this application embodiment.

[0041] Figure 2 This is a flowchart illustrating the integrated circuit abnormal interconnection detection method provided in the embodiments of this application.

[0042] Figure 3 This is a schematic diagram of the integrated circuit abnormal interconnection detection device provided in the embodiments of this application.

[0043] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0046] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0047] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0048] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] Verification of such interconnected networks currently relies on the LVS (Low Voltage Spectroscopy) testing tool. This tool ensures complete electrical connectivity by comparing the geometric connections of the physical layout with the logical connections of the circuit schematic. However, the LVS tool can only verify whether the physical implementation "correctly" connects the networks defined in the schematic; it cannot determine whether the schematic's logical connection intent is "reasonable" or "correct."

[0050] For example, in an array of multiple homogeneous computing chips, if a design script or tool malfunctions, a critical signal network that should be connected to chip A might be incorrectly connected to the corresponding port of the adjacent chip B. Because the layout "perfectly" implements this incorrect logical definition, the LVS check will pass smoothly and report "Clean," but the chip already has a fatal functional defect.

[0051] Therefore, traditional LVS (Low-Level Screening) inspection has an insurmountable verification blind spot when dealing with abnormal interconnects that are "electrically connected but logically malfunctioning" due to design input errors. Although theoretically this can be compensated for by manual review, relying on designers' visual inspection to find such "mismatched" errors in massive and highly repetitive interconnect networks is not only extremely inefficient, but also prone to omissions due to visual fatigue. This brings huge potential functional and yield risks to the design of highly complex 2.5D / 3D integrated circuits.

[0052] Based on this, embodiments of this application provide a method, apparatus, storage medium, and electronic device for detecting abnormal interconnections in integrated circuits. Specifically, the abnormal interconnection detection apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablet computers, laptops, and personal computers (PCs), etc., as well as other computer and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0053] For example, such as Figure 1 As shown, the electronic device can acquire layout data verified by LVS; extract the physical layout features of each interconnect network from the layout data and convert the physical layout features into feature vectors; use an unsupervised clustering algorithm to analyze all feature vectors and calculate the anomaly score of each interconnect network based on the analysis results; filter out suspected abnormal interconnect networks from all interconnect networks based on the anomaly score and a preset screening strategy; perform electrothermal co-simulation on the suspected abnormal interconnect networks to obtain the electrical performance indicators of the suspected abnormal interconnect networks, and determine whether the suspected abnormal interconnect networks are the target abnormal interconnect networks based on the electrical performance indicators.

[0054] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0055] Please see Figure 2 , Figure 2This is a flowchart illustrating the integrated circuit abnormal interconnect detection method provided in this application embodiment. The specific flow of the integrated circuit abnormal interconnect detection method can be as follows:

[0056] 101. Obtain layout data verified by LVS.

[0057] In this embodiment of the application, layout data verified by LVS can be obtained from a specified storage location or from the upstream EDA toolchain via an interface.

[0058] This layout data is typically stored in GDSII or OASIS format and contains complete physical layout information of the chip.

[0059] 102. Extract the physical layout features of each interconnection network from the layout data, and transform the physical layout features into feature vectors.

[0060] Specifically, the layout data can be parsed to obtain a database containing several interconnected networks. Then, the physical layout features of each interconnected network can be extracted. These physical layout features can include geometric features, topological features, spatial distribution features, and connectivity features, among others.

[0061] For geometric feature extraction, the total physical length of the interconnect network can be obtained by traversing the wiring segments on all metal layers and summing the actual lengths of each segment. Simultaneously, the Manhattan distance is calculated, which is the sum of the absolute displacements in the X and Y directions from the center point of the driving unit to the center point of the main receiving unit. In some embodiments, based on the Manhattan distance and the total physical length, the winding rate, i.e., the ratio of the total physical length to the Manhattan distance, can be further calculated. This ratio effectively reflects the degree of routing detour.

[0062] To extract topological features, the number of turning points where the path direction changes can be accurately counted by analyzing the path point sequence, typically reflected in the number of vias. Simultaneously, by separately counting the total length of horizontal and vertical segments across all layers of the interconnect network and calculating their ratio or the proportion of horizontal segments, the routing direction dominance can be obtained. This routing direction dominance can capture the directional preference of the routing.

[0063] To extract spatial distribution features, the coordinates of the driving and receiving ends within their respective chip cells can be normalized to eliminate absolute coordinate differences caused by cells of different sizes. For homogeneous chip cell designs, the cross-cell relative displacement vector is calculated by determining the coordinate difference between the current network endpoint and the corresponding network endpoint in the reference cell. This cross-cell relative displacement vector is highly indicative of errors in detecting connection targets.

[0064] To extract connectivity features, the cell types of both the driver and receiver can be digitally encoded (usually using one-hot encoding to convert the cell types into binary vectors). Simultaneously, the relative position information of the ports used on the cell boundaries is recorded.

[0065] After extracting the physical layout features as described above, all physical layout features can be combined into a fixed-dimensional feature vector in a predetermined order. In some embodiments, to ensure the stability and convergence efficiency of subsequent machine learning algorithms, the dimensions of the feature vector can be standardized, typically using the Z-score standardization method, to eliminate the influence of differences in the dimensions and numerical ranges of different features.

[0066] 103. Use an unsupervised clustering algorithm to analyze all feature vectors and calculate the anomaly score of each interconnection network based on the analysis results.

[0067] Specifically, an unsupervised clustering algorithm can be used to cluster all feature vectors to form at least one cluster; the relationship between each feature vector and its cluster can be analyzed according to a preset strategy, and the anomaly score of each interconnection network can be determined based on the relationship.

[0068] In the specific implementation process, an appropriate unsupervised clustering algorithm can be selected based on the data characteristics and detection requirements. This unsupervised clustering algorithm can include distance-based hard clustering algorithms (such as K-Means and DBSCAN) and probability-based soft clustering algorithms (such as Gaussian mixture models).

[0069] Understandably, in a proper design, interconnected networks with the same function should exhibit high similarity in their physical characteristics and form natural clusters; while in a flawed design, interconnected networks will exhibit anomalies in their physical characteristics, becoming outliers that deviate from the group.

[0070] When the unsupervised clustering algorithm is a distance-based hard clustering algorithm, the distance from each feature vector to the cluster center of its respective cluster can be calculated first; then the anomaly score of the corresponding interconnection network can be determined based on the distance.

[0071] Specifically, when using the K-Means algorithm, the number of clusters K can be pre-determined based on prior design knowledge or the elbow rule. Iterative optimization divides the feature vectors into K clusters, where the distance from each feature vector within a cluster to the cluster center is minimized. For each feature vector, its Euclidean distance to the center of its cluster is calculated, and this distance is then normalized to an outlier score within the range of 0 to 1. When using the DBSCAN algorithm, cluster structures can be automatically identified by analyzing data distribution density, and points that cannot be classified into any dense region are marked as outliers. These outliers are directly assigned the highest outlier score of 1.0; for points within a cluster, their relative distance to the nearest cluster boundary is calculated as the outlier score.

[0072] When the unsupervised clustering algorithm is a probability-based soft clustering algorithm, the membership degree of each feature vector corresponding to each cluster can be obtained first; then the anomaly score of the corresponding interconnection network can be determined based on the membership degree.

[0073] Specifically, when using the Gaussian Mixture Model (GMM) algorithm, it can be assumed that the feature vector data of all interconnect networks are generated by a mixture of K multivariate Gaussian distributions. Each Gaussian distribution corresponds to a potential physical design pattern, ideally associated with a 'cluster' formed by correctly functioning interconnect networks. By calculating the membership degree of each interconnect network to each distribution, its fit with the design pattern can be quantified, thus calculating the anomaly score. The anomaly score is calculated based on the maximum membership principle, using the formula S = 1 - max(P(i|x)), where max(P(i|x)) represents the maximum probability that the feature vector belongs to any cluster. The lower the membership degree, the less certain the feature vector is about belonging to any cluster, and the higher its anomaly score.

[0074] To ensure the completeness and practicality of anomaly scoring, special cases can be handled specifically. Specifically, for feature vectors that do not belong to any cluster, the anomaly score of their corresponding interconnection network can be assigned a preset maximum value.

[0075] 104. Based on the anomaly score and the preset filtering strategy, filter out suspected abnormal interconnection networks from all interconnection networks.

[0076] The preset filtering strategy includes a filtering method based on a preset score threshold and a filtering method based on a preset number of rankings.

[0077] Specifically, when the preset filtering strategy is based on a preset score threshold, a score threshold (e.g., 0.85) can be set to identify interconnect networks with abnormal scores higher than the threshold as suspected abnormal interconnect networks. When the preset filtering strategy includes a preset ranking number filtering method, interconnect networks ranked in the top N positions according to their abnormal scores from highest to lowest can be identified as suspected abnormal interconnect networks, where N is a preset positive integer.

[0078] In some embodiments, the preset screening strategy can also be a hybrid screening strategy, combining the advantages of score threshold screening and ranking quantity screening. For example, it can be configured to "report all interconnected networks with abnormal scores exceeding 0.7, but no more than 200", which ensures that seriously abnormal interconnected networks are not missed while controlling the overall review workload.

[0079] After the screening process is complete, a structured list of suspected anomalous interconnects can be generated. This list includes a unique identifier, anomaly score, cluster information, and a summary of key feature deviations for each interconnect. This list can be used as direct input for downstream electrothermal co-simulation and as a highlighting basis for the visualization module. Designers can directly access detailed diagnostic information by clicking on the highlighted interconnects and observe their relative position in the cluster within the visualization module.

[0080] 105. Perform electrothermal co-simulation on suspected abnormal interconnection networks to obtain electrical performance indicators of the suspected abnormal interconnection networks, and determine whether the suspected abnormal interconnection network is the target abnormal interconnection network based on the electrical performance indicators.

[0081] In some embodiments, the list of suspected anomalous interconnect networks can be converted into a simulation task queue. An independent simulation environment is created for each suspected anomalous interconnect network via EDA tool interfaces (such as the API of Cadence Virtuoso or Synopsys Custom Compiler) or script control, ensuring full automation of the verification process.

[0082] Specifically, parasitic parameters of suspected abnormal interconnect networks under local thermal distribution can be extracted; rapid circuit simulation can be performed based on parasitic parameters to obtain electrical performance indicators; the electrical performance indicators can be compared with preset performance specifications; if the electrical performance indicators do not meet the preset performance specifications, the suspected abnormal interconnect network can be identified as the target abnormal interconnect network.

[0083] If any electrical performance indicator exceeds the normal range (e.g., delay exceeds 10% of the timing budget, noise margin is below the safety threshold, IR drop exceeds the voltage tolerance), the suspected abnormal interconnect network is identified as a "target abnormal interconnect network." If all electrical performance indicators are within the normal range, even if its physical layout characteristics are abnormal, it is marked as "physically abnormal but functionally normal" and excluded from or downgraded from the abnormal list. Subsequently, all decision results and supporting data are recorded in the final report and fed back to the designer through a visualization module.

[0084] This application embodiment analyzes the physical layout feature patterns of the interconnect network, which can effectively identify abnormal interconnects that are "electrically connected but logically malfunctioning" and cannot be detected by traditional LVS tools. This fills a key gap in the verification process and prevents chip function failure caused by design input errors from the source.

[0085] Furthermore, by introducing electrothermal co-simulation as the final adjudication mechanism, the physical anomalies identified by the machine learning model are correlated with real electrical performance defects for verification. This effectively distinguishes between "harmless physical anomalies" and "real functional defects," significantly reducing false alarms and allowing designers to focus on solving real performance problems, thereby improving the accuracy of detection.

[0086] Furthermore, in this embodiment, the entire detection process, from feature extraction and anomaly scoring to simulation verification, is automated, completely freeing designers from tedious and unreliable manual visual inspection. This is particularly suitable for handling 2.5D / 3D integrated circuit design scenarios involving massive amounts of repetitive interconnects, improving verification efficiency by several orders of magnitude compared to purely manual inspection. By employing an unsupervised learning mechanism, there is no need to prepare pre-labeled "correct" or "incorrect" samples for model training, allowing direct application to early-stage projects or exploratory verification of new architectures. It demonstrates excellent adaptability to design changes and different process nodes. Through anomaly score quantification, visual highlighting, and root cause analysis reports, designers are provided with clear guidance for problem localization and decision-making, significantly shortening the problem debugging and root cause analysis cycle and effectively ensuring the first-time success rate of complex chip designs.

[0087] In summary, the integrated circuit abnormal interconnect detection method provided in this application first acquires the layout data verified by LVS and extracts the physical layout features of each interconnect network to generate feature vectors. Then, an unsupervised clustering algorithm is used to analyze all feature vectors, calculating anomaly scores for each interconnect network. Based on the anomaly scores and a preset strategy, suspected abnormal interconnect networks are selected. Finally, electrothermal co-simulation is performed on the selected suspected abnormal interconnect networks, and the final target abnormal interconnect network is determined based on its electrical performance indicators. This application, by introducing intelligent physical feature analysis and electrical verification steps after traditional LVS verification, effectively identifies abnormal interconnects where "the electrical connection is correct but the logic design is incorrect," significantly reducing the detection blind spots in the traditional verification process and improving the accuracy and reliability of abnormal interconnect detection.

[0088] To facilitate better implementation of the integrated circuit abnormal interconnection detection method provided in this application, this application also provides an integrated circuit abnormal interconnection detection device. The meanings of the terms used are the same as in the aforementioned integrated circuit abnormal interconnection detection method, and specific implementation details can be found in the descriptions within the method embodiments.

[0089] Please see Figure 3 , Figure 3 This is a schematic diagram of the integrated circuit abnormal interconnection detection device provided in an embodiment of this application. The integrated circuit abnormal interconnection detection device may include an acquisition unit 201, an extraction unit 202, an analysis unit 203, a screening unit 204, and a simulation unit 205.

[0090] Acquisition unit 201 is used to acquire layout data verified by LVS;

[0091] Extraction unit 202 is used to extract the physical layout features of each interconnection network from the layout data and convert the physical layout features into feature vectors;

[0092] Analysis unit 203 is used to analyze all feature vectors using an unsupervised clustering algorithm and calculate the anomaly score of each interconnection network based on the analysis results;

[0093] The filtering unit 204 is used to filter out suspected abnormal interconnection networks from all interconnection networks based on the anomaly score and a preset filtering strategy;

[0094] Simulation unit 205 is used to perform electrothermal co-simulation on suspected abnormal interconnection networks, obtain electrical performance indicators of suspected abnormal interconnection networks, and determine whether the suspected abnormal interconnection network is the target abnormal interconnection network based on the electrical performance indicators.

[0095] For specific implementation methods of each of the above units, please refer to the embodiments of the integrated circuit abnormal interconnection detection method described above, which will not be repeated here.

[0096] In summary, the integrated circuit abnormal interconnect detection device provided in this application embodiment can acquire layout data verified by LVS by acquisition unit 201; extract physical layout features of each interconnect network from the layout data by extraction unit 202 and convert the physical layout features into feature vectors; analyze all feature vectors using an unsupervised clustering algorithm by analysis unit 203 and calculate the abnormal score of each interconnect network based on the analysis results; filter unit 204 filters out suspected abnormal interconnect networks from all interconnect networks based on the abnormal score and a preset filtering strategy; and perform electrothermal co-simulation on the suspected abnormal interconnect networks by simulation unit 205 to obtain the electrical performance indicators of the suspected abnormal interconnect networks and determine whether the suspected abnormal interconnect networks are the target abnormal interconnect networks based on the electrical performance indicators. This application embodiment effectively identifies abnormal interconnects that are "electrically connected but logically designed incorrectly" by introducing intelligent physical feature analysis and electrical verification steps after traditional LVS verification, significantly reducing the detection blind spots in the traditional verification process and improving the accuracy and reliability of abnormal interconnect detection.

[0097] This application also provides an electronic device that may integrate the integrated circuit abnormal interconnection detection device of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically:

[0098] The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0099] The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0100] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0101] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows:

[0102] Obtain layout data verified by LVS;

[0103] Extract the physical layout features of each interconnection network from the layout data, and transform the physical layout features into feature vectors;

[0104] An unsupervised clustering algorithm is used to analyze all feature vectors, and an anomaly score for each interconnection network is calculated based on the analysis results.

[0105] Based on anomaly scores and preset filtering strategies, suspected abnormal interconnected networks are filtered out from all interconnected networks;

[0106] Electrothermal co-simulation was performed on suspected abnormal interconnect networks to obtain their electrical performance indicators, and the identity of the suspected abnormal interconnect network as the target abnormal interconnect network was determined based on these indicators.

[0107] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0108] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps:

[0109] Obtain layout data verified by LVS;

[0110] Extract the physical layout features of each interconnection network from the layout data, and transform the physical layout features into feature vectors;

[0111] An unsupervised clustering algorithm is used to analyze all feature vectors, and an anomaly score for each interconnection network is calculated based on the analysis results.

[0112] Based on anomaly scores and preset filtering strategies, suspected abnormal interconnected networks are filtered out from all interconnected networks;

[0113] Electrothermal co-simulation was performed on suspected abnormal interconnect networks to obtain their electrical performance indicators, and the identity of the suspected abnormal interconnect network as the target abnormal interconnect network was determined based on these indicators.

[0114] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0115] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0116] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0117] The above provides a detailed description of the integrated circuit abnormal interconnection detection method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An integrated circuit abnormal interconnect detection method, characterized by, The method comprises the following steps: obtaining layout data that passes LVS checking; extracting physical layout features of each interconnection network from the layout data and converting the physical layout features into feature vectors; analyzing all the feature vectors by using an unsupervised clustering algorithm and calculating an anomaly score of each interconnection network according to the analysis result; screening out suspected abnormal interconnection networks from all the interconnection networks based on the anomaly scores and a preset screening strategy; performing electro-thermal co-simulation on the suspected abnormal interconnection networks to obtain electrical performance indexes of the suspected abnormal interconnection networks and determining whether the suspected abnormal interconnection networks are target abnormal interconnection networks based on the electrical performance indexes.

2. The integrated circuit abnormal interconnect detection method of claim 1, wherein, The step of analyzing all the feature vectors by using an unsupervised clustering algorithm and calculating an anomaly score of each interconnection network according to the analysis result comprises the following steps: clustering all the feature vectors by using an unsupervised clustering algorithm to form at least one cluster; analyzing the relationship between each feature vector and the cluster to which the feature vector belongs according to a preset strategy and determining an anomaly score of each interconnection network based on the relationship.

3. The integrated circuit abnormal interconnect detection method of claim 2, wherein, The step of analyzing the relationship between each feature vector and the cluster to which the feature vector belongs according to a preset strategy and determining an anomaly score of each interconnection network based on the relationship comprises the following steps: calculating the distance between each feature vector and the cluster center of the cluster to which the feature vector belongs; determining the anomaly score of the corresponding interconnection network according to the distance.

4. The integrated circuit abnormal interconnect detection method of claim 2, wherein, The step of analyzing the relationship between each feature vector and the cluster to which the feature vector belongs according to a preset strategy and determining an anomaly score of each interconnection network based on the relationship comprises the following steps: obtaining the membership degree of each feature vector to each cluster; determining the anomaly score of the corresponding interconnection network according to the membership degree.

5. The integrated circuit abnormal interconnection detection method according to claim 3 or 4, characterized by, For the feature vectors that do not belong to any cluster, the anomaly score of the corresponding interconnection network is assigned as a preset maximum value.

6. The integrated circuit abnormal interconnect detection method of claim 1, wherein, The step of screening out suspected abnormal interconnection networks from all the interconnection networks based on the anomaly scores and a preset screening strategy comprises the following steps: screening based on a preset score threshold, and determining the interconnection networks with anomaly scores higher than the score threshold as suspected abnormal interconnection networks; or screening based on a preset ranking number, and determining the interconnection networks ranked in the top N positions in the order of anomaly scores from high to low as suspected abnormal interconnection networks, wherein N is a preset positive integer.

7. The integrated circuit abnormal interconnect detection method of claim 1, wherein, The step of performing electro-thermal co-simulation on the suspected abnormal interconnection networks to obtain electrical performance indexes of the suspected abnormal interconnection networks and determining whether the suspected abnormal interconnection networks are target abnormal interconnection networks based on the electrical performance indexes comprises the following steps: extracting parasitic parameters of the suspected abnormal interconnection networks under local thermal distribution; performing fast circuit simulation based on the parasitic parameters to obtain electrical performance indexes; comparing the electrical performance indexes with preset performance specifications; if the electrical performance indexes do not meet the preset performance specifications, determining that the suspected abnormal interconnection networks are target abnormal interconnection networks.

8. An integrated circuit abnormal interconnect detection apparatus, characterized by: The method comprises the following steps: an obtaining unit is configured to obtain layout data that passes LVS checking; an extracting unit is configured to extract physical layout features of each interconnection network from the layout data and convert the physical layout features into feature vectors; an analysis unit, configured to analyze all the feature vectors by using an unsupervised clustering algorithm, and calculate an anomaly score of each of the interconnection networks according to an analysis result; a screening unit, configured to screen a suspected abnormal interconnection network from all the interconnection networks based on the anomaly score and a preset screening strategy; a simulation unit, configured to perform an electro-thermal synergistic simulation on the suspected abnormal interconnection network, obtain an electrical performance index of the suspected abnormal interconnection network, and determine whether the suspected abnormal interconnection network is a target abnormal interconnection network based on the electrical performance index.

9. A storage medium, characterized by The storage medium stores a plurality of instructions, which are adapted to be loaded by the processor to execute the integrated circuit abnormal interconnection detection method according to any one of claims 1-7.

10. An electronic device, comprising: The computer program product comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the integrated circuit abnormal interconnection detection method according to any one of claims 1-7 when executing the computer program.

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