Control method, display device and storage medium

Abstract

A control method, a display device and a storage medium, the control method is applied to a driving circuit of the display device, the driving circuit comprises a time sequence control module, the time sequence control module is used for outputting a clock signal, and the clock signal comprises at least one group of adjacent first sub-clock signal and second sub-clock signal. The method comprises the following steps: acquiring the waveform of a first sub-clock signal and the waveform of a second sub-clock signal; determining a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining a first preset value based on the first vertical resolution of the display device; determining an overload current based on the first numerical value, a first preset numerical value and the cycle length of one of the second sub-clock signals; and when the signal current of the driving circuit is greater than or equal to the overload current, the driving circuit is disconnected, so that the overcurrent protection degree of display equipment with different refresh rates is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a control method, display device and storage medium. BACKGROUND

[0002] At present, the display is loved by the majority of users, but in the use process of the display, when the current of the display exceeds the bearing capacity of the display, the display is short-circuited and burned out, and the overcurrent protection measure can help to protect the display from damage caused by excessive current. In the prior art, the setting of the overload current can only set a group of inherent parameters for one display, and the display with multiple refresh rates cannot be protected. SUMMARY

[0003] The purpose of the present application is to provide a control method, display device and storage medium, which improves the overcurrent protection degree of display devices with different refresh rates.

[0004] To achieve the purpose of the present application, the present application provides the following technical solutions:

[0005] In a first aspect, the present application provides a control method applied to a driving circuit of a display device, the driving circuit comprising a timing control module, the timing control module being configured to output a clock signal, the clock signal comprising at least one group of adjacent first sub-clock signals and second sub-clock signals, the method comprising: obtaining a waveform of the first sub-clock signal and a waveform of the second sub-clock signal; determining a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining a first preset value based on a first vertical resolution of the display device; determining an overload current based on the first value, the first preset value, and a period length of one of the second sub-clock signals; and disconnecting the driving circuit when a signal current of the driving circuit is greater than or equal to the overload current.

[0006] It can be understood that the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are obtained, the first value is determined based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal, the first preset value is determined based on the first vertical resolution of the display device, the overload current is determined based on the first value, the first preset value, and the period length of one of the second sub-clock signals, and the driving circuit is disconnected when the signal current of the driving circuit is greater than or equal to the overload current. According to different refresh rates of the display device, the corresponding first vertical resolution is determined, the first preset value is determined based on the first vertical resolution of the display device, the overload current is determined based on the period length of the second sub-clock signal when the first value is equal to the first preset value, so that the overcurrent protection of the display device with different refresh rates can be realized.

[0007] In a possible example, the determining the first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal comprises: judging a same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; and determining the first value based on the same degree.

[0008] It can be understood that the judging the same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal and the determining the first value based on the same degree can detect a slight difference between the waveform of the first sub-clock signal and the waveform of the second sub-clock signal, and improve quantization accuracy.

[0009] In a possible example, the judging the same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal comprises: performing analog-to-digital conversion on the first sub-clock signal to obtain a first sequence; performing analog-to-digital conversion on the second sub-clock signal to obtain a second sequence; performing fast Fourier transform on the first sequence and the second sequence in a frame of a preset number of points; calculating a root mean square value of a difference between two frame spectrum amplitudes of the first sequence after transformation and the second sequence after transformation; when the root mean square value is less than a preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are the same; and when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are different.

[0010] It can be understood that the performing analog-to-digital conversion on the first sub-clock signal to obtain a first sequence, the performing analog-to-digital conversion on the second sub-clock signal to obtain a second sequence, the performing fast Fourier transform on the first sequence and the second sequence in a frame of a preset number of points, the calculating a root mean square value of a difference between two frame spectrum amplitudes of the first sequence after transformation and the second sequence after transformation, when the root mean square value is less than a preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are the same, and when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are different. This comparison method has higher robustness to noise and jitter, reduces the false detection rate, and the preset limit value can be set according to requirements, facilitating adaptive adjustment for different panels or wires, and improving universality.

[0011] In a possible example, the determining the first value based on the same degree comprises: when the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are the same, adding 1 to the first value, and the first value starts from 0; and when the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are different, clearing the first value.

[0012] It can be understood that when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is added by 1, and the first value is counted from 0; when the waveform of the first sub-clock signal is not the same as the waveform of the second sub-clock signal, the first value is cleared. This method quantifies the number of continuous same waveforms, and clears zero as soon as the waveforms are different, which can prevent historical cumulative errors, ensure accurate counting, and improve the accuracy of calculating the first value.

[0013] In a possible example, the determination of the overload current based on the first value, a first preset value, and the period length of one of the second sub-clock signals includes: determining whether the first value is equal to the first preset value; when the timing control module outputs the one of the second sub-clock signals, the first value is equal to the first preset value, the counting of the first value is stopped, and the overload current is determined based on the period length of the one of the second sub-clock signals; and when the first value is less than the first preset value, the counting of the first value is continued.

[0014] It can be understood that a precise starting threshold is set for the determination of the overload current. When the first value does not reach the preset value, the counting is continued to ensure the integrity of data acquisition and avoid detection deviation caused by insufficient data. Only when the first value meets the preset condition, the overload current is calculated based on the period length of one of the second sub-clock signals, which effectively excludes interference factors in non-overload scenarios, significantly reduces the probability of misjudgment or omission, guarantees the reliability of the current detection result, and improves the accuracy of determining the overload current.

[0015] In a possible example, the determination of the overload current based on the first value, a first preset value, and the period length of one of the second sub-clock signals includes: determining the overload current based on the period length of the one of the second sub-clock signals and a preset relationship, the preset relationship including at least one of the period length of the second sub-clock signal and at least one of the overload current, and each of the period length of the second sub-clock signal corresponding to one of the overload current.

[0016] It can be understood that the overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship, the preset relationship including at least one of the period length of the second sub-clock signal and at least one of the overload current, and each of the period length of the second sub-clock signal corresponding to one of the overload current, which establishes a connection between the period length and the refresh rate, and maps the overload current quickly and accurately with the period length as an index, avoids complex operations, and improves the accuracy and efficiency of determining the overload current.

[0017] In a possible example, the determining the overload current based on the period length of the one of the second sub-clock signals and the preset relationship comprises: determining a first refresh rate based on the period length of the one of the second sub-clock signals; the preset relationship comprises a first sub-preset relationship, the first sub-preset relationship comprises at least one of the first refresh rate and at least one of the overload current, and each of the first refresh rate matches one of the overload current; and the determining the overload current based on the first refresh rate and the first sub-preset relationship.

[0018] It can be understood that the determining the first refresh rate based on the period length of the one of the second sub-clock signals, the preset relationship comprising the first sub-preset relationship, the first sub-preset relationship comprising at least one of the first refresh rate and at least one of the overload current, and each of the first refresh rate matching one of the overload current, and the determining the overload current based on the first refresh rate and the first sub-preset relationship make the matching relationship between the first refresh rate and the overload current more intuitive, facilitate engineers to debug, and improve the accuracy and efficiency of determining the overload current.

[0019] In a possible example, the determining the overload current based on the period length of the one of the second sub-clock signals and the preset relationship further comprises: debugging the matched overload current based on all the first refresh rates in advance to generate the first sub-preset relationship; and storing the first sub-preset relationship in advance.

[0020] It can be understood that the debugging the matched overload current based on all the first refresh rates in advance to generate the first sub-preset relationship, and the storing the first sub-preset relationship in advance ensure that the display device can be called as soon as it is powered on, without the need for calibration each time, and the first sub-preset relationship between the first refresh rate and the overload current obtained through actual measurement of the whole machine is more in line with the characteristics of the actual display device, thereby improving the accuracy of the overload current protection.

[0021] In a second aspect, an embodiment of the present application provides a display device, comprising a memory and a processor, wherein the memory is configured to store computer instructions, and the processor is configured to invoke the computer instructions to execute the method provided in the first aspect or any of the implementation manners of the first aspect.

[0022] In a third aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program causes a computer to execute to implement the method provided in the first aspect or any of the implementation manners of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings belong to the protection scope of the present application.

[0024] Figure 1 It is a schematic diagram of the application scenario of the control method of an embodiment.

[0025] Figure 2 It is a schematic diagram of the flow of the control method of an embodiment.

[0026] Figure 3 It is a schematic diagram of the structure of a display device of an embodiment.

[0027] Figure 4 It is a schematic diagram of the structure of processing the first preset relationship of an embodiment.

[0028] Figure 5 It is a schematic diagram of the structure of the first sub-preset lookup table of an embodiment.

[0029] Figure 6 It is a schematic diagram of the structure of a display device of an embodiment.

[0030] Explanation of reference signs:

[0031] 101 - user, 102 - display device, 103 - server, 300 - display device, 301 - acquisition module, 302 - processing module, 401 - flash memory module, 402 - timing control module, 403 - level conversion module, 601 - processor, 602 - memory. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0033] It should be noted that when a component is referred to as "fixed" to another component, it can be directly on the other component or there can be a middle component. When a component is referred to as "connected" to another component, it can be directly connected to the other component or there can be a middle component.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. The use herein of the terms "and / or" includes a combination of one or more of the associated listed items, in any of their possible permutations.

[0035] Some embodiments of the present application will be described in detail with reference to the drawings, in which like reference numerals refer to like elements, and in which the scope of the application is not limited by the features of the embodiments described in the specification and / or drawings. Embodiments described in the specification and / or drawings are illustrative only and are not intended to be limiting of the scope of the application. The scope of the application is defined only by the claims.

[0036] Please refer to Figure 1 , Figure 1 is a schematic diagram of an application scenario of a control method of an embodiment. As shown in Figure 1 , the schematic diagram of the application scenario includes a user 101, a display device 102, and a server 103. Optionally, the display device 102 can be a thin film transistor liquid crystal display, and the structure of the display device 102 is not limited in the present application. Optionally, one user 101 can use multiple display devices 102. Optionally, multiple display devices 102 can perform data transmission with one server 103.

[0037] Optionally, the server 103 can be a stand-alone server 103, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms, and the like basic cloud computing services. The server 103 can also be implemented by a server cluster composed of multiple sub-servers.

[0038] It should be noted that Figure 1 the number of each device in the system and the form of each device, and the number of users 101 are used for example, and do not constitute a limitation on the embodiments of the present application.

[0039] Please refer to Figure 2 , Figure 2 is a flowchart of a control method of an embodiment. The control method is applied to a driving circuit of a display device, the driving circuit includes a timing control module, the timing control module is used to output a clock signal, the clock signal includes at least one group of adjacent first sub-clock signal and second sub-clock signal, and the method includes the following steps S201-S205, wherein

[0040] S201: Obtain the waveform of the first sub-clock signal and the waveform of the second sub-clock signal.

[0041] S202: Determine the first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal.

[0042] Determine the first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal, comprising: judging the same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining the first value based on the same degree.

[0043] Optionally, the at least one group of adjacent first sub-clock signals and second sub-clock signals comprises a first group of adjacent first sub-clock signals and second sub-clock signals, a second group of adjacent third sub-clock signals and fourth sub-clock signals, and a third group of adjacent fifth sub-clock signals and sixth sub-clock signals, wherein the second sub-clock signal and the third sub-clock signal are also adjacent, and the fourth sub-clock signal and the fifth sub-clock signal are also adjacent. The above is an example and should not be construed as limiting.

[0044] Optionally, a first analog-to-digital converter and a second analog-to-digital converter are arranged inside the timing control module to synchronously sample the first sub-clock signal and the second sub-clock signal, respectively. Synchronous sampling eliminates comparison errors caused by clock offset.

[0045] Optionally, the rising edge time difference Δt1 of the first sub-clock signal and the second sub-clock signal is calculated, the falling edge time difference Δt2 of the first sub-clock signal and the second sub-clock signal is calculated, and the duty cycle difference ΔD of the first sub-clock signal and the second sub-clock signal is calculated. When Δt1 is less than a preset first limit value, Δt2 is less than a preset second limit value, and ΔD is less than a preset third limit value, it is determined that the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal. Otherwise, the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal.

[0046] It can be understood that judging the same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal, and determining the first value based on the same degree, can detect the slight difference between the waveform of the first sub-clock signal and the waveform of the second sub-clock signal, and improve the quantization precision.

[0047] Judging the same degree of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal comprises: analog-to-digital converting the first sub-clock signal to obtain a first sequence; analog-to-digital converting the second sub-clock signal to obtain a second sequence; performing fast Fourier transform on the first sequence and the second sequence with a preset number of points as one frame; calculating the root mean square value of the two-frame spectral amplitude difference of the transformed first sequence and the transformed second sequence; when the root mean square value is less than a preset limit value, the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal; when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal.

[0048] Optionally, the drive circuit includes a fast Fourier transform processor, the first analog-digital converter samples the first sub-clock signal to generate a first digital sequence, and the second analog-digital converter samples the second sub-clock signal to generate a second digital sequence. The first digital sequence and the second digital sequence are framed by a preset number of points (e.g., 1024 points per frame) and sent to the fast Fourier transform processor to perform fast Fourier transform on each frame of data. Then, the root mean square value of the spectral amplitude difference of the two frames corresponding to the two signals is calculated.

[0049] It can be understood that the first sub-clock signal is analog-digital converted to obtain a first sequence, the second sub-clock signal is analog-digital converted to obtain a second sequence, the first sequence and the second sequence are fast Fourier transformed by a preset number of points per frame, the root mean square value of the spectral amplitude difference of the two frames of the transformed first sequence and the transformed second sequence is calculated, when the root mean square value is less than a preset limit value, the waveforms of the first sub-clock signal and the second sub-clock signal are the same, and when the root mean square value is greater than or equal to the preset limit value, the waveforms of the first sub-clock signal and the second sub-clock signal are different. This comparison method has higher robustness to noise and jitter, reduces the false detection rate, and the preset limit value can be set according to requirements, facilitating adaptive adjustment for different panels or wires and improving universality.

[0050] The first value is determined based on the same degree, including: when the waveforms of the first sub-clock signal and the second sub-clock signal are the same, the first value is added by 1, and the first value is counted from 0; and when the waveforms of the first sub-clock signal and the second sub-clock signal are different, the first value is cleared.

[0051] Optionally, the drive circuit includes a counter, and first, the counter is initialized: when the waveforms of the first sub-clock signal and the second sub-clock signal are the same, N=N+1, and when the waveforms of the first sub-clock signal and the second sub-clock signal are different, N=0.

[0052] It can be understood that when the waveforms of the first sub-clock signal and the second sub-clock signal are the same, the first value is added by 1, and the first value is counted from 0; and when the waveforms of the first sub-clock signal and the second sub-clock signal are different, the first value is cleared. This method quantifies the number of consecutive same waveforms, clears zero as soon as the waveforms are different, prevents historical cumulative errors, ensures accurate counting, and improves the accuracy of calculating the first value.

[0053] S203: Determine a first preset value based on the first vertical resolution of the display device.

[0054] S204: Determine an overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals.

[0055] In a possible example, the determining the overload current based on the first value, the first preset value and the period length of the one of the second sub-clock signals comprises: determining whether the first value is equal to the first preset value; when the first value is equal to the first preset value due to the output of the one of the second sub-clock signals by the timing control module, stopping counting the first value and determining the overload current based on the period length of the one of the second sub-clock signals; and when the first value is less than the first preset value, continuing to count the first value.

[0056] Optionally, the clock signals comprise a first sub-clock signal, a second sub-clock signal and a third sub-clock signal in sequence, and when the first value is equal to the first preset value due to the output of the third sub-clock signal by the timing control module, the third sub-clock signal is regarded as the one of the second sub-clock signals, the counting of the first value is stopped, and the overload current is determined based on the period length of the third sub-clock signal.

[0057] Optionally, the first sub-clock signal is regarded as an n-th sub-clock signal, and the second sub-clock signal is regarded as an (n+1)-th sub-clock signal, where n is an integer ranging from 1 to any positive integer.

[0058] It can be understood that a precise starting threshold is set for the determination of the overload current, and when the first value does not reach the preset value, the counting is continued to ensure the integrity of data acquisition and avoid detection deviation caused by insufficient data; and only when the first value meets the preset condition, the overload current is calculated based on the period length of the one of the second sub-clock signals when the first value reaches the preset value, so that interference factors in non-overload scenarios are effectively excluded, the probability of misjudgment or omission is significantly reduced, the reliability of the current detection result is ensured, and the accuracy of the determination of the overload current is improved.

[0059] The stopping of the counting of the first value and the determining of the overload current based on the period length of the second sub-clock signal comprises: determining the overload current based on the period length of the second sub-clock signal and a preset relationship, the preset relationship comprising the period length of at least one second sub-clock signal and at least one overload current, and the period length of each second sub-clock signal corresponding to one overload current.

[0060] Optionally, when the first value is equal to the first preset value, the period length of the second sub-clock signal under this condition is obtained, the overload current of the period length of the second sub-clock signal under this condition is debugged based on the period length of the second sub-clock signal under this condition, and the preset relationship is generated.

[0061] Optionally, the at least one group of adjacent first sub-clock signals and second sub-clock signals comprises a first group of adjacent first sub-clock signals and second sub-clock signals, a second group of adjacent third sub-clock signals and fourth sub-clock signals, and a third group of adjacent fifth sub-clock signals and sixth sub-clock signals, wherein the second sub-clock signal is adjacent to the third sub-clock signal, and the fourth sub-clock signal is adjacent to the fifth sub-clock signal; when the first number is equal to the first preset number and the sixth sub-clock signal is output, the period length of the sixth sub-clock signal is taken as the period length of the second sub-clock signal defined above, and the period length of the sixth sub-clock signal and the preset relationship are used to determine the overload current.

[0062] Optionally, when the first number is equal to the first preset number, the period length of the second sub-clock signal, the total horizontal pixels, and the total vertical pixels are obtained, and the first refresh rate is determined according to the period length of the second sub-clock signal, the total horizontal pixels, and the total vertical pixels, each first refresh rate corresponds to a unique overload current, and a mapping relationship between the period length of the second sub-clock signal and the overload current is formed.

[0063] It can be understood that the overload current is determined based on the period length of the second sub-clock signal, which comprises determining the overload current based on the period length of the second sub-clock signal and a preset relationship, the preset relationship comprises at least one period length of the second sub-clock signal and at least one overload current, each period length of the second sub-clock signal corresponds to one overload current, the period length is associated with the refresh rate, and the period length is indexed to quickly and accurately map to the overload current, thereby avoiding complex operations and improving the accuracy and efficiency of determining the overload current.

[0064] Stopping counting the first number and determining the overload current based on the period length of one of the second sub-clock signals comprises determining the first refresh rate based on the period length of one of the second sub-clock signals; the preset relationship comprises a first sub-preset relationship, the first sub-preset relationship comprises at least one first refresh rate and at least one overload current, each first refresh rate matches one overload current; and the overload current is determined based on the first refresh rate and the first sub-preset relationship.

[0065] It should be noted that when detecting the CLK period inside the timing control module and setting the parameters corresponding to multiple refresh rate intervals (the refresh rate corresponds to the refresh rate interval parameter one by one, and the refresh rate interval parameter corresponds to the overload current one by one), the CLK integrated on the array substrate is output through a level shifter, the level shifter is output through the CLK of the timing control module, and then CLK1, CLK2, CLK3, etc. are generated. The CLK period inside the timing control module corresponds to the time of each H (the falling edge of the Tp signal corresponds to the current row source output, so the falling edge of Tp to the falling edge of the next Tp, that is, the period of the Tp signal, also corresponds to the time of one H, which can also be determined by detecting the period of Tp). That is, the phase difference between CLK1 and CLK2, taking a conventional 60Hz display screen as an example, H*V=4400*2250, so the time of one H is H=1 / 60 / 2250, where 60 is the refresh rate, and the width of H corresponds to the refresh rate, and then the corresponding refresh rate interval parameter is queried.

[0066] Based on the above scheme, the refresh rate can be determined by detecting different signals, and then the refresh rate interval parameter setting is performed. However, in actual application, taking a 50-inch 1G1D UD product as an example, the current face design is 10CLK, the typ is 144Hz, and the HSR is 288Hz. The HSR is in the case where the data amount is unchanged (transmission rate = 4400*2250*144*3*8*1.03 / 12). Since the scanning signal is output through a level shifter chip, the level shifter only supports 4 / 6 / 8 channel output, and the demand is 10CLK, so a two-level shifter chip (first level shifter chip and second level shifter chip) cascade scheme is adopted and 6 channels are set. It can also be determined to use a multiple level shifter chip cascade scheme, wherein the first level shifter chip outputs 1&3&5&7&9&11 channels, and the second level shifter chip outputs 2&4&6&8&10&12 channels. This scheme has a total of 12 CLKs, and 12 CLKs are repeated, but the 11th CLK and the 12th CLK are redundant and actually not used, so that the 10th CLK and the 1st CLK of the next period cannot form a continuous waveform, which cannot meet the charging demand. The 10th CLK and the 1st CLK are invalid. Therefore, the 11th&12th CLK is edited separately, which means that for a single level shifter chip, the 6th or multiple of 6 CLK_IN (input signal of timing control module output to LS IC) waveforms of each level shifter chip are hidden between the 5th CLK_IN and the next 1st CLK_IN. The number of effective CLKs in every 12 CLKs is 10, and the period of CLK is not the same, so it is not possible to guarantee the absolute accuracy of detection according to the CLK period.

[0067] Optionally, the first sub preset relationship can be a first sub preset lookup table, and the first sub preset lookup table shows a matching relationship between the first refresh rate and the overload current.

[0068] It can be understood that the first refresh rate is determined based on the length of the period of the second sub clock signal; the preset relationship includes the first sub preset relationship, the first sub preset relationship includes at least one first refresh rate and at least one overload current, each first refresh rate is matched with an overload current; the overload current is determined based on the first refresh rate and the first sub preset relationship, so that the matching relationship between the first refresh rate and the overload current is more intuitive, which is convenient for engineers to debug, and the accuracy and efficiency of determining the overload current are improved.

[0069] The length of the period of one of the second sub clock signals and the preset relationship are used to determine the overload current, and the method further includes: pre-determining the matching overload current based on all the first refresh rates, and generating the first sub preset relationship; and pre-storing the first sub preset relationship.

[0070] Optionally, when the first value is equal to the first preset value, the length of the period of the second sub clock signal under the condition is obtained, the first refresh rate is calculated based on the length of the period of the second sub clock signal under the condition, the overload current under the first refresh rate is debugged, all the overload currents of the display panel under different first refresh rates are tested, the first sub preset relationship is generated and stored in the display device.

[0071] Optionally, the display device is debugged in advance using a program-controlled power supply and an oscilloscope and the like, different first refresh rates are set, for example, 24Hz to 240Hz are traversed, and the overload current corresponding to the changed first refresh rate is measured every 5Hz.

[0072] Optionally, the overcurrent protection detection of the display device includes a rest time and a detection time, when the current of the signal reaches the overload current set by us and the time duration is greater than or equal to the detection time, we will count once, and when the number of times reaches the detection number, the overcurrent protection will be performed.

[0073] Optionally, taking a display device with a display frequency of 120Hz as an example, a common 1920H*1200V (H*V represents the horizontal and vertical pixel numbers of the resolution, i.e. horizontal resolution*vertical resolution) indicates that the display has 1920 horizontal pixels and 1200 vertical pixels, and our H*V total is 4400*2250, so the time T1 of one line is: T1=1 / 120 / 2250=3.7us, and the sum of the rest time and the detection time cannot exceed 3.7us.

[0074] It can be understood that the first sub preset relationship is generated based on the matched overload current pre-adjusted at all the first refresh rates; the first sub preset relationship is pre-stored, the pre-stored manner ensures that the display device can be called after being powered on, without calibration each time, and moreover, the first sub preset relationship between the first refresh rate and the overload current obtained through the whole machine actually is more in line with the characteristics of the actual display device, and the accuracy of the overload protection is improved.

[0075] Optionally, the first preset value is determined based on the first vertical resolution of the display device, including:

[0076] When the first vertical resolution is switched to a second vertical resolution within a preset time length, the first preset value is determined based on the second vertical resolution;

[0077] When the first vertical resolution is switched to the second vertical resolution outside the preset time length, the first preset value is determined based on the first vertical resolution.

[0078] It can be understood that the preset time length is introduced to avoid mis-switching caused by transient jitter, and the accuracy and stability of determining the first preset value are improved.

[0079] S205: When the signal current of the driving circuit is greater than or equal to the overload current, the driving circuit is disconnected.

[0080] Optionally, when the signal current of the driving circuit is greater than or equal to the overload current, a disconnection signal is sent to the timing control module, the frame buffer data is immediately frozen, then the black screen protection mode (all pixels are zeroed) is started, and an error code is displayed, so as to prevent the occurrence of a flower screen or a residual image when the driving circuit is disconnected, reduce power consumption, and improve the operability of the user.

[0081] It can be understood that the waveform of the first sub clock signal and the waveform of the second sub clock signal are obtained; the first value is determined based on the waveform of the first sub clock signal and the waveform of the second sub clock signal; the first preset value is determined based on the first vertical resolution of the display device; when the first value is equal to the first preset value, the overload current is determined based on the cycle length of the second sub clock signal; when the signal current of the driving circuit is greater than or equal to the overload current, the driving circuit is disconnected, the corresponding first vertical resolution is determined according to the display device of different refresh rates, the first preset value is determined based on the first vertical resolution of the display device, when the first value is equal to the first preset value, the overload current is determined based on the cycle length of the second sub clock signal, so that the overcurrent protection can be performed on the display device of different refresh rates.

[0082] It should be noted that the overcurrent protection driving circuit or the measure of protecting the display device from excessive current damage, when the signal current of the driving circuit is greater than or equal to the overload current, exceeds the bearing capacity of the driving circuit or the display device, which may cause arc, overheating, fire and other safety problems. Overcurrent protection cuts off the excessive current in time to prevent potential hazards. When excessive current occurs in the driving circuit, it may cause the voltage of the power supply to drop, thereby affecting the normal operation of the entire power system. Overcurrent protection can quickly cut off the excessive current to maintain the stable operation of the circuit and ensure uninterrupted power supply.

[0083] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of a display device of an embodiment. Based on the above-mentioned system architecture, the display device 300 can be a server or a device, or a module in a server. The display device 300 at least includes an acquisition module 301 and a processing module 302, wherein,

[0084] The acquisition module 301 is configured to acquire a waveform of a first sub-clock signal and a waveform of a second sub-clock signal.

[0085] The processing module 302 is configured to determine a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; the processing module 302 is configured to determine a first preset value based on a first vertical resolution of the display device; the processing module 302 is configured to determine an overload current based on the first value, the first preset value, and a period length of one of the second sub-clock signals; and the processing module 302 is configured to disconnect the driving circuit when the signal current of the driving circuit is greater than or equal to the overload current.

[0086] In one possible example, the processing module 302 is configured to process the following steps:

[0087] determining a degree of sameness of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal;

[0088] determining the first value based on the degree of sameness.

[0089] In one possible example, the processing module 302 is configured to process the following steps:

[0090] performing analog-to-digital conversion on the first sub-clock signal to obtain a first sequence;

[0091] performing analog-to-digital conversion on the second sub-clock signal to obtain a second sequence;

[0092] performing fast Fourier transform on the first sequence and the second sequence with a preset number of points as one frame;

[0093] calculating a root mean square value of a difference between two frame spectrum amplitudes of the transformed first sequence and the transformed second sequence;

[0094] When the root mean square value is less than the preset limit value, the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal; when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal.

[0095] In one possible example, the processing module 302 is configured to process the following steps:

[0096] When the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first number is added by 1, and the first number is counted from 0;

[0097] When the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, the first number is cleared.

[0098] In one possible example, the processing module 302 is configured to process the following steps:

[0099] Determine whether the first number is equal to the first preset number;

[0100] When the timing control module outputs one of the second sub-clock signals, the first number is equal to the first preset number, the counting of the first number is stopped, and the overload current is determined based on the cycle length of the one of the second sub-clock signals;

[0101] When the first number is less than the first preset number, the counting of the first number is continued.

[0102] In one possible example, the processing module 302 is configured to process the following steps:

[0103] The overload current is determined based on the cycle length of one of the second sub-clock signals and a preset relationship, the preset relationship includes at least one cycle length of the second sub-clock signal and at least one overload current, and the cycle length of each second sub-clock signal corresponds to one overload current.

[0104] In one possible example, the processing module 302 is configured to process the following steps:

[0105] The first refresh rate is determined based on the cycle length of one of the second sub-clock signals;

[0106] The preset relationship includes a first sub-preset relationship, the first sub-preset relationship includes at least one first refresh rate and at least one overload current, and each first refresh rate matches one overload current;

[0107] The overload current is determined based on the first refresh rate and the first sub-preset relationship.

[0108] In one possible example, the processing module 302 is configured to process the following steps:

[0109] The first sub preset relationship is generated in advance based on all the first refresh rates matched with the overload current;

[0110] The first sub preset relationship is stored in advance.

[0111] Referring to Figure 4 , Figure 4 is a structural schematic diagram of processing the first preset relationship in an embodiment. As shown in Figure 4 , the display device 300 includes a flash module 401, a timing control module 402, and a level conversion module 403. The flash module 401 is electrically connected to the timing control module 402, and the level conversion module 403 is electrically connected to the timing control module 402. The timing control module 402 looks up the first preset relationship in the flash module 401. The flash module 401 loads the first preset relationship in the timing control module 402. The timing control module 402 burns the first preset relationship in the level conversion module 403.

[0112] Referring to Figure 5 , Figure 5 is a structural schematic diagram of the first sub preset lookup table in an embodiment. As shown in Figure 5 , the first sub preset lookup table displays the matching relationship between the first refresh rate and the overload current. The first refresh rate corresponds to the refresh rate interval corresponding parameter one by one, and the refresh rate interval corresponding parameter corresponds to the overload current one by one. The matching relationship between the first refresh rate and the overload current can be obtained therefrom. For example, the first refresh rate can be 40 Hz, 50 Hz, and 60 Hz, and the overload current can be C1, C2, and C3. 40 Hz to 50 Hz corresponds to C1, 50 Hz to 60 Hz corresponds to C2, 60 Hz to 70 Hz corresponds to C3, 70 Hz to 80 Hz corresponds to C4, and 80 Hz to 90 Hz corresponds to C5.

[0113] Referring to Figure 6 , Figure 6 is a structural schematic diagram of a display device in an embodiment. As shown in Figure 6 , the display device 102 includes a processor 601 and a memory 602. The memory 602 is used to store computer instructions, and the processor 601 is used to call the computer instructions to execute the instructions of the following steps:

[0114] Obtain the waveform of the first sub clock signal and the waveform of the second sub clock signal;

[0115] Determine the first value based on the waveform of the first sub clock signal and the waveform of the second sub clock signal;

[0116] Determine the first preset value based on the first vertical resolution of the display device;

[0117] determine the overload current based on the first value, the first preset value, and a period length of one of the second sub-clock signals;

[0118] when the signal current of the driving circuit is greater than or equal to the overload current, disconnect the driving circuit.

[0119] In one possible example, the processor 601 is specifically configured to execute instructions for the following steps:

[0120] determine a degree of similarity between the waveform of the first sub-clock signal and the waveform of the second sub-clock signal;

[0121] determine the first value based on the degree of similarity.

[0122] In one possible example, the processor 601 is specifically configured to execute instructions for the following steps:

[0123] perform analog-to-digital conversion on the first sub-clock signal to obtain a first sequence;

[0124] perform analog-to-digital conversion on the second sub-clock signal to obtain a second sequence;

[0125] perform fast Fourier transform on the first sequence and the second sequence in a preset number of points as one frame;

[0126] calculate a root mean square value of a difference between two frame spectral amplitudes of the transformed first sequence and the transformed second sequence;

[0127] when the root mean square value is less than a preset limit value, the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal; and when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal.

[0128] In one possible example, the processor 601 is specifically configured to execute instructions for the following steps:

[0129] when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, add 1 to the first value, and the first value starts from 0;

[0130] when the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, clear the first value.

[0131] In one possible example, the processor 601 is specifically configured to execute instructions for the following steps:

[0132] determine whether the first value is equal to the first preset value;

[0133] when the timing control module outputs one of the second sub-clock signals and the first value is equal to the first preset value, stop counting the first value and determine the overload current based on a period length of the one of the second sub-clock signals;

[0134] When the first value is less than the first preset value, continue to count the first value.

[0135] In one possible example, the processor 601 is specifically configured to execute the instructions of the following steps:

[0136] determine the overload current based on the period length of one of the second sub-clock signals and a preset relationship, the preset relationship comprising at least one second sub-clock signal period length and at least one overload current, the period length of each second sub-clock signal corresponding to one overload current.

[0137] In one possible example, the processor 601 is specifically configured to execute the instructions of the following steps:

[0138] determine the first refresh rate based on the period length of one of the second sub-clock signals;

[0139] The preset relationship comprises a first sub-preset relationship, the first sub-preset relationship comprising at least one first refresh rate and at least one overload current, each first refresh rate matching one overload current;

[0140] determine the overload current based on the first refresh rate and the first sub-preset relationship.

[0141] In one possible example, the processor 601 is specifically configured to execute the instructions of the following steps:

[0142] generate the first sub-preset relationship in advance based on all the first refresh rates debugging the matched overload currents;

[0143] prestore the first sub-preset relationship.

[0144] Those skilled in the art can understand that, for the convenience of illustration, Figure 6 Only one memory 602 and processor 601 are shown in the terminal or server. In actual terminal or server, there can be multiple processors 601 and memories 602. The memory 602 can also be referred to as a storage medium or a storage device, and the present application embodiments do not limit this.

[0145] It should be understood that, in the present application, the processor 601 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 601 can also be a general-purpose microprocessor, a graphics processing unit (GPU), or one or more integrated circuits, for executing programs to implement the functions required by the embodiments of the present application.

[0146] The processor 601 can also be an integrated circuit chip with a signal processing capability. In the implementation process, the various steps of the present application can be completed by the integrated logic circuits or the software form instructions in the processor 601. The processor 601 described above can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The steps of the methods disclosed in the embodiments of the present application can be directly embodied as hardware code processing or executed by hardware and software module combinations in the code processing. The software module can be located in the random access memory, the flash memory and the read-only memory, the programmable read-only memory or the electrically erasable programmable memory, the register, etc. The storage medium in the art is mature. The storage medium is located in the memory 602, and the processor 601 reads the information in the memory 602, and combines the hardware to complete the functions required by the units included in the methods, devices and storage media of the embodiments of the present application.

[0147] It should also be appreciated that the memory 602 referred to in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memory. Among them, the non-volatile memory can be a read-only memory (Read-Only Memory, ROM for short), a programmable read-only memory (Programmable ROM, PROM for short), an erasable programmable read-only memory (Erasable PROM, EPROM for short), or a flash memory. The volatile memory can be a random access memory (Random Access Memory, RAM for short) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (Static RAM, SRAM for short), dynamic random access memory (Dynamic RAM, DRAM for short), synchronous dynamic random access memory (Synchronous DRAM, SDRAM for short), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM for short), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM for short), synchronous link dynamic random access memory (Synchl ink DRAM, SLDRAM for short), and direct memory bus random access memory (Direct Rambus RAM, DR RAM for short). The memory can also be a compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but not limited to. The memory can be independently present and connected to the processor through a bus. The memory 602 can also be integrated with the processor 601, and the memory 602 can store programs, and when the programs stored in the memory are executed by the processor 601, the processor 601 is configured to perform the steps of the determination method described in the embodiments of the present application.

[0148] It should be noted that when the processor 601 is a general-purpose processor, a DSP, an ASIC, a field programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, the memory 602 (storage module) is integrated in the processor. It should be noted that the memory 602 described herein is intended to include but not limited to these and any other suitable type of memory.

[0149] It should be understood that the term "and / or" in this document merely describes an associated relationship between associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this document generally represents an "or" relationship between the associated objects before and after it.

[0150] In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 601 or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor 601. The software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, register, etc. The storage medium is located in the memory 602, and the processor reads the information in the memory 602, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0151] Those of ordinary skill in the art can realize that the various illustrative logical blocks (ILB) and steps described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0152] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a program product of computer programming. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the processor 601, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a computer network or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber) or wireless (such as infrared, wireless, microwave, etc.) mode, or can be transmitted from one website, computer, server or data center to mobile phone processor through wired mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk), optical media (such as DVD), or semiconductor media (such as solid state disk) and the like.

[0153] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A control method characterized by, The control method is applied to a driving circuit of a display device, the driving circuit comprising a timing control module configured to output a clock signal, the clock signal comprising at least one set of adjacent first and second sub-clock signals, the method comprising: acquiring a waveform of the first sub-clock signal and a waveform of the second sub-clock signal; determining a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining a first preset value based on a first vertical resolution of the display device; determining an overload current based on the first value, the first preset value, and a period length of one of the second sub-clock signals; when a signal current of the driving circuit is greater than or equal to the overload current, disconnecting the driving circuit.

2. The control method according to claim 1, characterized by, The determining of the first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal comprises: judging a degree of sameness of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining the first value based on the degree of sameness.

3. The control method according to claim 2, characterized by, The judging of the degree of sameness of the waveform of the first sub-clock signal and the waveform of the second sub-clock signal comprises: analog-to-digital conversion of the first sub-clock signal to obtain a first sequence; analog-to-digital conversion of the second sub-clock signal to obtain a second sequence; fast Fourier transform of the first sequence and the second sequence with a preset number of points as one frame; calculation of a root mean square value of a difference between two frame spectral amplitudes of the transformed first sequence and the transformed second sequence; when the root mean square value is less than a preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are the same; and when the root mean square value is greater than or equal to the preset limit value, the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are different.

4. The control method according to claim 2, characterized by, The determining of the first value based on the degree of sameness comprises: when the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are the same, adding 1 to the first value, the first value being counted from 0; when the waveform of the first sub-clock signal and the waveform of the second sub-clock signal are different, clearing the first value.

5. The control method according to claim 4, characterized by The determining of the overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals comprises: judging whether the first value is equal to the first preset value; when the timing control module outputs the one of the second sub-clock signals, the first value is equal to the first preset value, stopping counting of the first value and determining the overload current based on the period length of the one of the second sub-clock signals; when the first value is less than the first preset value, continuing to count the first value.

6. The control method according to claim 5, characterized by The stopping of the counting of the first value and the determining of the overload current based on the period length of the one of the second sub-clock signals comprise: Determine an overload current based on a period length of one of the second sub-clock signals and a preset relationship, the preset relationship including at least one period length of the second sub-clock signals and at least one overload current, each period length of the second sub-clock signals corresponding to one overload current.

7. The control method according to claim 6, characterized by The determining of the overload current based on the period length of one of the second sub-clock signals and the preset relationship includes: Determine a first refresh rate based on the period length of one of the second sub-clock signals; The preset relationship includes a first sub-preset relationship, the first sub-preset relationship including at least one first refresh rate and at least one overload current, each first refresh rate matching one overload current; Determine the overload current based on the first refresh rate and the first sub-preset relationship.

8. The control method according to claim 7, characterized by, The determining of the overload current based on the period length of one of the second sub-clock signals and the preset relationship further includes: Pre-debug the matching overload current based on all the first refresh rates to generate the first sub-preset relationship; Pre-store the first sub-preset relationship.

9. A display device, characterized by A computer readable storage medium stores a computer program, the computer program causing a computer to execute to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, the computer program causing a computer to execute to implement the method of any one of claims 1 to 7.

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