Pseudo-static random access memory and its access methods, I / O interfaces, electronic devices

Abstract

This disclosure relates to pseudo-static random access memory and its access method, I / O interface, and electronic device. The I / O interface includes: first and second sets of data terminals for first and second interface protocols, respectively, with the second set having more terminals than the first set; a set of control terminals for the first and second interface protocols; a mode register cache configured to cache mode register values ​​input via a first portion of the first set of data terminals or the first set of control terminals, wherein at least one bit is used as an interface protocol selection signal; and a control logic unit including first and second control logic modules for instruction decoding according to the first and second interface protocols, respectively, and configured to decode instruction values ​​using the corresponding control logic modules according to the interface protocol selection signal. The I / O interface of this disclosure is compatible with two interface protocols, one of which supports a larger data width, achieves higher bandwidth, and allows protocol switching via a protocol selection signal, making it suitable for a wider range of application scenarios.

Description

Technical Field

[0001] This disclosure relates to the field of storage, and in particular to a pseudo-static random access memory (PSRAM) and its access method, an I / O (input / output) interface, and an electronic device containing the memory. Background Technology

[0002] With the development of scenarios such as multimedia, artificial intelligence and high-speed communication, the performance requirements of electronic devices and systems continue to grow, and PSRAM, as a low-power memory, has an increasing demand for high bandwidth.

[0003] Therefore, it is desirable to provide PSRAM with higher bandwidth. Summary of the Invention

[0004] One technical problem this disclosure aims to solve is to provide a pseudo-static random access memory with higher bandwidth.

[0005] According to a first aspect of this disclosure, an I / O interface for a pseudo-static random access memory is provided, selectively operating in a first interface protocol mode or a second interface protocol mode, the I / O interface comprising:

[0006] The first set of data terminals for the first interface protocol;

[0007] The second set of data terminals used for the second interface protocol has a greater number of terminals than the first set of data terminals;

[0008] A set of control terminals for the first and second interface protocols;

[0009] The mode register buffer is configured to buffer mode register values ​​input via the first set of data terminals or via a first portion of the terminals in the set of control terminals, wherein at least one bit of the mode register value is used as an interface protocol selection signal;

[0010] The control logic unit includes a first control logic module and a second control logic module that perform instruction decoding according to the first interface protocol and the second interface protocol, respectively, and is configured to perform instruction decoding processing on instruction values ​​input via the first group of data terminals or via the first partial terminals using a corresponding one of the first control logic modules and the second control logic module according to the interface protocol selection signal.

[0011] Optionally, the first set of data terminals is used to transmit access data, instruction values, address values, and mode register values ​​in a time-division multiplexing manner according to the first interface protocol; the second set of data terminals is used to transmit only access data according to the second interface protocol.

[0012] Optionally, the set of control terminals includes a first subgroup of control terminals for transmitting control signals required by the first interface protocol other than instruction values, address values, and mode register values, and a second subgroup of control terminals for transmitting all control signals required by the second interface protocol, wherein the second subgroup of control terminals includes instruction / address multiplexed terminals for time-division multiplexing instruction values, address values, and mode register values ​​according to the second interface protocol as the first part of the terminals;

[0013] When the I / O interface is operating in the first interface protocol mode, both the mode register value and the instruction value are input via the first set of data terminals. When the I / O interface is operating in the second interface protocol mode, both the mode register value and the instruction value are input via the instruction / address multiplexing terminal.

[0014] Optionally, at least a portion of the first set of data terminals is further used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol;

[0015] The set of control terminals includes a first sub-set of control terminals for transmitting control signals required by the first interface protocol other than instruction values, address values, and mode register values. The first sub-set of control terminals is also used to transmit at least a portion of the control signals required by the second interface protocol other than instruction values, address values, and mode register values.

[0016] When the I / O interface is operating in the first interface protocol mode and the second interface protocol mode, both the mode register value and the instruction value are input via the first set of data terminals.

[0017] Optionally, the first control logic module is configured to receive a first instruction / address value and a first clock signal, and according to the first interface protocol and the first clock signal, decode the instruction value extracted from the first instruction / address value to obtain a first internal operation signal, and extract the address value from the first instruction / address value as a first address signal.

[0018] Optionally, the second control logic module is configured to receive a second instruction / address value, a second clock signal, and a specified portion of the mode register value, and according to the second interface protocol and the second clock signal, combine the specified portion of the mode register value to perform instruction decoding on the instruction value extracted from the second instruction / address value to obtain a second internal operation signal, and extract the address value from the second instruction / address value as a second address signal.

[0019] Optionally, in the first case where the first group of data terminals is used for time-division multiplexing of access data, instruction value, address value, and mode register value according to the first interface protocol, and the first part of the terminals is used for time-division multiplexing of instruction value, address value, and mode register value according to the second interface protocol, the first instruction / address value is a plurality of values ​​obtained by sampling the input of the first group of data terminals at the first clock edge, and the second instruction / address value is a plurality of values ​​obtained by sampling the input of the first part of the terminals at the second clock edge; or, in the second case where the first group of data terminals is used for time-division multiplexing of access data, instruction value, address value, and mode register value according to the first interface protocol, and at least a portion of the first group of data terminals is also used for time-division multiplexing of instruction value, address value, and mode register value according to the second interface protocol, the first instruction / address value and the second instruction / address value are respectively a plurality of values ​​obtained by sampling the input of the first group of data terminals at the third clock edge and the fourth clock edge;

[0020] The first clock signal and the second clock signal are respectively input from the first clock terminal and the second clock terminal of the set of control terminals, which are respectively used to transmit the clock signals required by the first interface protocol and the second interface protocol, or both are input from the clock terminal of the set of control terminals that are multiplexed to transmit the clock signals required by the first interface protocol and the second interface protocol.

[0021] Optionally, the first control logic module includes:

[0022] A first instruction decoder is configured to decode the first instruction / address value according to the first interface protocol to obtain a first decoded signal.

[0023] The first clock gating unit is configured to convert the first clock signal into a first instruction clock signal and a first address clock signal according to the first interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the first instruction / address value.

[0024] The first internal operation signal buffer unit is configured to sample and buffer the first decoded signal as the first internal operation signal at the time indicated by the first instruction clock signal, and

[0025] The first address cache unit is configured to sample and cache the first instruction / address value as the first address signal at the time indicated by the first address clock signal.

[0026] Optionally, the second control logic module includes:

[0027] The second instruction decoder is configured to decode the second instruction / address value according to the second interface protocol and in conjunction with the mode register value of the specified portion to obtain a second decoded signal.

[0028] The second clock gating unit is configured to convert the second clock signal into a second instruction clock signal and a second address clock signal according to the second interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the second instruction / address value.

[0029] The second internal operation signal buffer unit is configured to sample and buffer the second decoded signal as the second internal operation signal at the time indicated by the second instruction clock signal, and

[0030] The second address cache unit is configured to sample and cache the second instruction / address value as the second address signal at the time indicated by the second address clock signal.

[0031] Optionally, when the first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol, and at least a portion of the first set of data terminals is also used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol, and the clock terminals in the set of control terminals are multiplexed for transmitting clock signals required by the first interface protocol and the second interface protocol, the control logic unit further includes:

[0032] The first demultiplexer receives, at its input terminal, an instruction / address value sampled from the input of the first group of data terminals at the third or fourth clock edge; at its control terminal, it receives the interface protocol selection signal; and at its two output terminals, it outputs the first instruction / address value and the second instruction / address value, respectively.

[0033] The second demultiplexer receives a clock signal input from the clock terminal, receives the interface protocol selection signal at its control terminal, and outputs the first clock signal and the second clock signal at its two output terminals, respectively.

[0034] Optionally, the control logic unit further includes:

[0035] The output module is configured to receive the first internal operation signal, the second internal operation signal, the first address signal, and the second address signal, and to output a final internal operation signal and a final address signal, wherein the final internal operation signal is equal to one of the first internal operation signal and the second internal operation signal that corresponds to the interface protocol selection signal, and the final address signal is equal to one of the first address signal and the second address signal that corresponds to the interface protocol selection signal.

[0036] Optionally, if the final internal operation signal indicates a mode register write operation, at least a portion of the final address signal is cached in the mode register cache as the latest mode register value.

[0037] Optionally, the control logic unit further includes:

[0038] The first switch is located between the first control logic module and the power supply voltage it uses.

[0039] A second switch is located between the second control logic module and its power supply voltage; and

[0040] The power control module is configured to output the interface protocol selection signal and its inverted signal to the control terminals of the first switch and the second switch, respectively, such that when the interface protocol selection signal indicates that the first interface protocol is currently selected, the first switch is turned on and the second switch is turned off, and when the interface protocol selection signal indicates that the second interface protocol is currently selected, the second switch is turned on and the first switch is turned off.

[0041] Optionally, the IO interface further includes: an IO buffer coupled to the first group of data terminals, the second group of data terminals, and the group of control terminals, and includes a plurality of receivers for receiving signals input from the first group of data terminals, the second group of data terminals, and the group of control terminals, and a plurality of drivers for driving signals output from a portion of the first group of data terminals, the second group of data terminals, and the group of control terminals.

[0042] Optionally, the IO buffer is configured to turn off the receiver and / or driver for the idle terminal according to the interface protocol selection signal, wherein the idle terminal is a terminal that is not used to transmit signals required by the interface protocol corresponding to the interface protocol selection signal.

[0043] Optionally, the I / O interface further includes:

[0044] An internal access data bus, used for transmitting access data between the memory array within the pseudo-static random access memory and the first set of data terminals, and between the memory array and the second set of data terminals, wherein the number of bits is equal to the number of terminals in the second set of data terminals; and

[0045] The access data I / O unit is configured to concatenate multiple write data samples obtained from the input of the first group of data terminals on the fifth group of clock edges into a single internal write data for output to the internal access data bus at the same time, and to split a single internal read data received at the same time via the internal access data bus into multiple read data for output multiple times via the first group of data terminals.

[0046] Optionally, the first set of data terminals uses DDR timing to transmit the read data and the write data, and the access data I / O unit includes:

[0047] The write driver is configured to concatenate two write data samples obtained from the input of the first set of data terminals on two consecutive clock edges in the fifth set of clock edges into an intermediate write data for output at the same time.

[0048] The data interface is configured to concatenate multiple consecutively output intermediate write data into a single internal write data;

[0049] The read data caching module is configured to cache the aforementioned internal read data;

[0050] A read data multiplexer is configured to split buffered internal read data into multiple intermediate read data and output them sequentially, wherein the number of bits in the intermediate read data is twice the number of terminals in the first group of data terminals; and

[0051] The read driver is configured to split one of the intermediate read data into two read data for output on two consecutive clock edges via the first set of data terminals.

[0052] Optionally, the set of control terminals includes a first subgroup of control terminals used only for transmitting at least some of the control signals required by the first interface protocol and a second subgroup of control terminals used only for transmitting at least some of the control signals required by the second interface protocol, or the set of control terminals includes at least one control terminal multiplexed for the first and second interface protocols.

[0053] Optionally, at least a portion of the first set of data terminals may also be used to transmit at least a portion of the control signals and / or access data required by the second interface protocol, or at least a portion of the second set of data terminals may also be used to transmit at least a portion of the control signals and / or access data required by the first interface protocol.

[0054] Optionally, the first interface protocol is the xSPI protocol, and the second interface protocol is the LPDDR protocol.

[0055] Optionally, the first group of data terminals has 8 terminals, and the second group of data terminals has 64 terminals.

[0056] According to a second aspect of this disclosure, a pseudo-static random access memory is provided, comprising: an I / O interface according to any of the embodiments of the first aspect described above; a memory array; and an access processing unit configured to perform corresponding access operations on the memory array based on the result of instruction decoding processing performed by the control logic unit in the I / O interface.

[0057] According to a third aspect of this disclosure, a method for accessing a pseudo-static random access memory according to any of the embodiments in the second aspect is provided, comprising: receiving a mode register value via a first set of data terminals or a first portion of terminals; receiving an instruction value via the first set of data terminals or the first portion of terminals; performing instruction decoding processing on the instruction value using a corresponding one of a first control logic module and a second control logic module based on an interface protocol selection signal in the mode register value; and performing a corresponding access operation on the memory array using the access processing unit based on the result of the instruction decoding processing.

[0058] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a pseudo-static random access memory (PSRAM) according to any of the embodiments of the second aspect above; and a first host coupled to a first set of data terminals in an I / O interface in the PSRAM, and a first sub-set of control terminals in the set of control terminals for transmitting control signals required for a first interface protocol, and configured to input the mode register value to the I / O interface via the first set of data terminals or the first portion of the terminals when accessing the PSRAM, such that an interface protocol selection signal indicates that the first interface protocol mode is currently selected.

[0059] Optionally, the electronic device further includes:

[0060] The second host is coupled to the second set of data terminals in the IO interface and the second sub-set of control terminals in the set of control terminals for transmitting control signals required for the second interface protocol, and is configured to input the mode register value to the IO interface via the first set of data terminals or the first part of the terminals when accessing the pseudo-static random access memory, such that the interface protocol selection signal indicates that the second interface protocol mode is currently selected.

[0061] The first host and the second host each further include a first occupancy status terminal and a second occupancy status terminal. The first occupancy status terminal is coupled together with the second occupancy status terminal and is used to exchange the occupancy status of the pseudo-static random access memory between the first host and the second host to ensure that the first host and the second host access the pseudo-static random access memory in a time-sharing manner.

[0062] Therefore, the IO interface design of this embodiment is compatible with two interface protocols, one of which can support a larger data width, thereby achieving higher bandwidth. Furthermore, it can switch between interface protocols through a protocol selection signal, thus making it suitable for a wider range of application scenarios. Attached Figure Description

[0063] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0064] Figure 1 An exemplary compositional schematic diagram of a PSRAM and its I / O interface according to some embodiments of the present disclosure is shown.

[0065] Figure 2 An exemplary compositional schematic diagram of a PSRAM and its I / O interface according to some embodiments of the present disclosure is shown.

[0066] Figure 3 An exemplary compositional schematic diagram of a control logic unit according to some embodiments of the present disclosure is shown.

[0067] Figure 4 An exemplary compositional schematic diagram of a control logic unit according to some embodiments of the present disclosure is shown.

[0068] Figure 5 An exemplary compositional schematic diagram of an I / O buffer section according to some embodiments of the present disclosure is shown.

[0069] Figure 6 An exemplary composition diagram of the access data I / O unit according to some embodiments of the present disclosure is shown.

[0070] Figure 7 An exemplary schematic diagram of a PSRAM and a host accessing the PSRAM according to some embodiments of the present disclosure is shown.

[0071] Figure 8 An exemplary flowchart of a method for accessing PSRAM according to some embodiments of the present disclosure is shown.

[0072] Figure 9 An exemplary compositional schematic diagram of an electronic device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0073] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0074] Currently, the highest performance of typical PSRAM is 200MHz, usually employing an I / O (Input / Output) interface that follows the SPI (Serial Peripheral Interface) protocol. With DDR (Double Data Rate) timing and an x8 I / O interface (i.e., the I / O interface has a data width of 8 bits, receiving 8 bits of data in parallel), its maximum bandwidth is 400MBps. With DDR timing and an x16 I / O interface, its maximum bandwidth is only 800MBps, which is insufficient to meet the demands of some high-performance applications. In this article, "SPI protocol" includes various extended serial peripheral interface protocols, such as multi-I / O SPI protocols, including QSPI (Quad Serial Peripheral Interface), OSPI (Octal Serial Peripheral Interface), and xSPI (eXtended Serial Peripheral Interface) protocols.

[0075] Therefore, this disclosure proposes a new I / O interface design for PSRAM that is compatible with two interface protocols, one of which supports a larger data width to achieve higher bandwidth. Furthermore, it can switch between interface protocols via a protocol selection signal, making it suitable for a wider range of application scenarios.

[0076] For example, the IO interface according to embodiments of this disclosure can operate in either the interface protocol originally used by PSRAM (such as the SPI protocol) or in an interface protocol that supports a larger data width (such as the LPDDR (Low Power Double Data Rate) protocol). This allows users to choose to use the original PSRAM instruction format and interface protocol in general application scenarios, while selecting an interface protocol with a larger data width to achieve greater bandwidth in high-bandwidth application scenarios. Therefore, high-bandwidth performance can be achieved in the PSRAM product form factor, while retaining the application interface protocols originally supported by PSRAM through mode switching.

[0077] In some embodiments described below, the IO interface according to the present disclosure can also support two hosts using different interface protocols to access the same PSRAM simultaneously, thereby making it applicable to more and more complex application scenarios.

[0078] The following will take an I / O interface compatible with the xSPI protocol with a data width of 8 (corresponding to the first interface protocol described herein) and the LPDDR protocol with a data width of 64 (corresponding to the second interface protocol described herein) as examples to describe in detail the technical solution of this disclosure. However, those skilled in the art will understand that this disclosure is not limited to this, but can also be similarly applied to I / O interfaces compatible with other two different interface protocols. Moreover, the data widths used by the two interface protocols are only exemplary and can be modified as needed.

[0079] Figure 1 and Figure 2 Exemplary schematic diagrams of two PSRAMs and their I / O interfaces according to embodiments of this disclosure are shown respectively. The main difference between the two is: Figure 1 The I / O interface provides two independent sets of terminals for each of the two interface protocols, while Figure 2 In the I / O interface, the second interface protocol reuses at least some of the terminals of the first interface protocol. Let's first combine... Figure 1 The following diagrams will discuss the PSRAM and its I / O interface in the embodiments of this disclosure in detail, and in conjunction with... Figure 2 Description of embodiments and examples of this terminal multiplexing Figure 1 The difference between the terminal-independent embodiments.

[0080] like Figure 1 As shown, the PSRAM includes an I / O interface that selectively operates in either a first interface protocol mode or a second interface protocol mode. Therefore, the I / O interface includes terminals for implementing both interface protocols. Those skilled in the art will understand that... Figure 1The terminals, parts, or modules in the I / O interface are merely exemplary and not restrictive. They can be added, removed, or modified as needed in actual use.

[0081] In example Figure 1 In the example shown, the first interface protocol is the xSPI protocol, and the second interface protocol is the LPDDR protocol. Furthermore, these two interface protocols each use their own independent sets of terminals, for example... Figure 1 The rightmost shown is a set of terminals used for the first interface protocol, and Figure 1 The topmost part shows a set of terminals used for the second interface protocol.

[0082] Each set of terminals can be divided into a data section and a control section. The data section terminals are used to transmit at least access data (i.e., read data and write data), while the control section terminals are used to transmit all control signals required by the corresponding interface protocol, excluding the signals transmitted by the data section terminals. In this article, "control signals" refers to all signals required by the corresponding interface protocol other than access data, such as command values, address values ​​(i.e., the address corresponding to the access data), mode register values, clock (CLK) signals, chip select (CS) signals, data strobe (DQS) signals, data mask (DM) signals, reset signals, etc.

[0083] The data terminals used for the first interface protocol can also be referred to as the first set of data terminals. When the first interface protocol is xSPI or a similar protocol, the first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol. That is, access data, instruction values, and address values ​​according to the first interface protocol are time-division multiplexed using the same set of terminals for transmission. Furthermore, in the instruction format for writing the mode register, the instruction value and the mode register value are also time-division multiplexed using the same set of terminals for transmission. Figure 1 In the example, terminals A / DQ[7:0] can be used as the first set of data terminals, which has a number of 8 terminals.

[0084] The data terminals used for the second interface protocol can also be referred to as the second set of data terminals. The number of terminals in this set is greater than that in the first set of data terminals. That is, the second interface protocol transmits more bits of access data in parallel than the first interface protocol, thus achieving higher bandwidth. When the second interface protocol is LPDDR or a similar protocol, the second set of data terminals is used to transmit only access data according to the second interface protocol. In other words, according to the second interface protocol, access data and instruction / address values ​​are transmitted independently by different terminals, thus achieving even faster access speeds. Figure 1 In the example, terminal DQ[63:0] can be used as a second set of data terminals, which can achieve a 64-bit data width, increasing the bandwidth by 8 times compared to the first interface protocol of x8; in some cases, terminal DQ[63:0] can also be backward compatible with the second interface protocol of x32 or x16, which can also increase the bandwidth by 4 times or 2 times respectively.

[0085] The control terminals for the first interface protocol and the control terminals for the second interface protocol can also be collectively referred to as a set of control terminals for the first and second interface protocols. This set of control terminals is used to transmit at least a portion of the control signals required by the first and second interface protocols, because in some cases, some control signals can also be transmitted time-division multiplexed by data terminals, such as the instruction values, address values, and mode register values ​​according to the first interface protocol mentioned above. This set of control terminals can be divided into a first subgroup of control terminals and a second subgroup of control terminals, wherein the first subgroup of control terminals is used to transmit at least a portion of the control signals required by the first interface protocol, and the second subgroup of control terminals is used to transmit at least a portion of the control signals required by the second interface protocol. Figure 1 In the example where the two interface protocols each have their own independent terminals, the first subgroup of control terminals is used only for the first interface protocol, and the second subgroup of control terminals is used only for the second interface protocol. (As will be discussed later...) Figure 2In the illustrated case where two interface protocols share some terminals, the set of control terminals includes at least one control terminal multiplexed for both the first and second interface protocols. That is, at least a portion of the first subgroup of control terminals can also be used to transmit at least a portion of the control signals required by the second interface protocol, or at least a portion of the second subgroup of control terminals can also be used to transmit at least a portion of the control signals required by the first interface protocol, or the first and second subgroups of control terminals completely overlap when the entire set of control terminals is multiplexed for both the first and second interface protocols. In some cases, in addition to control terminals or as an alternative, at least a portion of the first set of data terminals can also be multiplexed to transmit at least a portion of the control signals and / or access data required by the second interface protocol, or at least a portion of the second set of data terminals can also be multiplexed to transmit at least a portion of the control signals and / or access data required by the first interface protocol.

[0086] exist Figure 1 In the illustrated example, the first subgroup control terminal is used to transmit control signals required by the first interface protocol, in addition to instruction values, address values, and mode register values, such as... Figure 1 As shown, it may include control terminals for transmitting chip select signal, clock signal, data strobe signal / data mask signal, and reset signal, namely terminals CS1#, CLK1, DQS / DM, and RESET1#.

[0087] The second subgroup control terminals are used to transmit all control signals required by the second interface protocol, such as... Figure 1 As shown, it may include control terminals for transmitting data strobe signals, instruction / address values ​​or mode register values, clock signals, chip select signals, and reset signals, namely terminals DQS[7:0], CA[5:0], CLK2, CS2#, and RESET2#. It can be understood that CA[5:0] is an instruction / address multiplexed terminal used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol. Additionally, although... Figure 1 Not shown, but in some examples, the second subgroup control terminals may also include control terminals for inputting data mask signals, namely terminals DM[7:0].

[0088] like Figure 1 As shown, except for terminals DQS / DM and DQS[7:0], which are bidirectional terminals that can both input and output signals, all other control terminals are unidirectional terminals that can only input signals.

[0089] Those skilled in the art will understand that Figure 1The types and quantities of control terminals shown are merely illustrative. In actual use, the types and quantities of control terminals can be configured according to the interface protocol used. The first group of data terminals and the first subgroup of control terminals described above can support various xSPI instruction operations, while the second group of data terminals and the second subgroup of control terminals can support various LPDDR instruction operations. Those skilled in the art will understand their specific instruction formats, operation timings, etc., and will not be elaborated upon here.

[0090] The interface protocol selection signal Mode_Sel can be used to select whether the I / O interface is operating in the first interface protocol mode or the second interface protocol mode. This Mode_Sel signal can be represented by a single bit in the mode register; for example, a value of 0 indicates that the I / O interface is currently operating in the first interface protocol mode, and a value of 1 indicates that the I / O interface is currently operating in the second interface protocol mode. The Mode_Sel signal can be used to control the corresponding components in the I / O interface to operate according to the corresponding interface protocol, thereby implementing the corresponding interface protocol mode.

[0091] Therefore, as Figure 1 As shown, the I / O interface may also include a mode register buffer and a control logic section.

[0092] The mode register buffer is configured to buffer the mode register value MR input via the first set of data terminals (e.g., terminals A / DQ[7:0]) or via the first part of the control terminals in the first set (e.g., terminals CA[5:0]), wherein at least one bit is used as the interface protocol selection signal Mode_Sel to indicate whether to select the first interface protocol or the second interface protocol. Figure 1 The Mode_Reg in the register can be the remaining part of the MR register except for Mode_Sel. The mode register cache can include, for example, multiple latches or registers.

[0093] In some examples, the interface protocol selection signal Mode_Sel can be fixed to a specific value before the PSRAM leaves the factory, as needed by the user, and this value cannot be changed during subsequent user use. For example, during the chip testing phase, a specific MR write operation can be performed using the first set of data terminals or the aforementioned first part of the terminals to write and fix the interface protocol selection signal Mode_Sel in the chip. Therefore, when packaging the PSRAM, only the pads of the terminals used by the corresponding interface protocol can be bonded to the package pins.

[0094] In other examples, the value of the interface protocol selection signal Mode_Sel can be configured by the host using the PSRAM. For instance, the host can use only one interface protocol, thus coupling only to the terminals of the corresponding interface protocol, and write the value of the corresponding interface protocol selection signal Mode_Sel using an MR write instruction. Alternatively, the host can switch between the two interface protocols depending on the use case, thus coupling to all terminals of the PSRAM, and switching the value of the interface protocol selection signal Mode_Sel using the corresponding MR write instruction.

[0095] The control logic unit includes a first control logic module and a second control logic module that perform instruction decoding according to a first interface protocol and a second interface protocol, respectively, and is configured to perform instruction decoding processing on instruction values ​​input via a first group of data terminals or via a first part of terminals using a corresponding one of the first control logic modules and the interface protocol selection signal Mode_Sel.

[0096] For example, when the Mode_Sel signal indicates that the first interface protocol is selected, an instruction value is input via the first set of data terminals. The first control logic module decodes the instruction value according to the first interface protocol to obtain a set of internal operation signals to control the access processing unit in the PSRAM (e.g., including...). Figure 1 The RA&CA control logic module, IO control module, row decoder, and column access control module (shown) perform corresponding access operations on the storage array. RA and CA are abbreviations for "Row Address" and "Column Address," respectively. Those skilled in the art will understand that... Figure 1 The RA&CA control logic module, IO control module, row decoder, and column access control module shown are merely exemplary, and the access processing unit according to this disclosure is not limited thereto. This access processing unit can be configured to perform corresponding access operations on the memory array based on the result of instruction decoding processing performed by the control logic unit in the IO interface.

[0097] For example, when the Mode_Sel signal indicates that the second interface protocol is selected, the instruction value is input through the first part terminal, and the second control logic module decodes the instruction value according to the second interface protocol to obtain a set of internal operation signals to control the access processing unit in the PSRAM to perform corresponding access operations on the memory array.

[0098] In some examples, when the first interface protocol is currently selected, the mode register write instruction format of the first interface protocol can be used to input MR via the first set of data terminals; when the second interface protocol is currently selected, the mode register write instruction format of the second interface protocol can be used to input MR via the first set of terminals.

[0099] In some cases, the control logic unit needs to decode the instruction to determine if the input in the instruction format is an MR and update the MR accordingly. Therefore, when switching interface protocols, the mode register of the previous interface protocol can be used to rewrite the instruction format to Mod_Sel, thereby switching to the currently required interface protocol. Afterward, various operations can be performed using the switched interface protocol. In other cases, the I / O interface can be designed so that when switching interface protocols, the value of Mod_Sel is rewritten using the currently required interface protocol (i.e., the switched interface protocol), and then various operations can be performed using the switched interface protocol.

[0100] exist Figure 1 In the example shown, when the IO interface is working in the first interface protocol mode, the above-mentioned mode register value MR and instruction value are both input via the first set of data terminals, such as terminals A / DQ[7:0]. When the IO interface is working in the second interface protocol mode, the above-mentioned mode register value MR and instruction value are both input via instruction / address multiplexing terminals, such as terminals CA[5:0].

[0101] In cases where instruction values ​​and address / mode register values ​​are time-multiplexed and transmitted using the same set of terminals, the multiple sets of values ​​sampled from the input of this set of terminals at specified clock edges (also referred to as a set of clock edges) can be collectively referred to as instruction / address values. It is understood that this collective term is a common expression in the art; for the sake of brevity, "mode register value" is omitted, while the "address value" in "instruction / address value" actually includes the mode register value. The value sampled at the specified clock edges in the various instruction formats supported by the protocol may be an instruction value, an address value, or a mode register value. Depending on the instruction, the input at the same clock edge may be either an address value or a mode register value. For example, in an access instruction, an address value is input at the Nth clock edge after the transmission starts, while in a mode register write instruction, the mode register value is input at the same clock edge.

[0102] The specified multiple clock edges can be determined according to the interface protocol (such as the various instruction formats it adopts, SDR or DDR transmission timing, etc.). For example, it can be a series of consecutive valid clock edges after the chip select signal is valid (i.e., after transmission starts). The so-called "valid clock edge" refers to the clock edge that is sampled according to the transmission timing, etc. In the case of using DDR transmission timing, sampling is performed twice in one clock cycle, and the valid clock edge includes the rising edge and falling edge of the clock signal.

[0103] The instruction / address value is sent to the control logic unit for processing. The control logic unit can extract the instruction value and address value (or mode register value) from it at different times and process them separately.

[0104] In example Figure 1 In the example shown, which uses two independent sets of terminals to support two interface protocols respectively, there are a first instruction / address value Cmd / Addr1 and a second instruction / address value Cmd / Addr2. The first instruction / address value is obtained by sampling multiple sets of values ​​at the input (e.g., A / DQ[7:0]_v) of the first set of data terminals (e.g., terminals A / DQ[7:0]) at the first set of clock edges. The second instruction / address value is obtained by sampling multiple sets of values ​​at the input (e.g., CA[5:0]_v) of the first set of terminals (e.g., terminals CA[5:0]) at the second set of clock edges. The first set of clock edges and the second set of clock edges are determined according to the first interface protocol and the second interface protocol, respectively, and their number and corresponding transmission order may be the same or different. In addition, the first clock signal CLK1_v and the second clock signal CLK2_v are respectively input from the first clock terminal and the second clock terminal used to transmit the clock signals required by the first interface protocol and the second interface protocol. The first set of clock edges are all clock edges of the first clock signal CLK1_v, and the second set of clock edges are all clock edges of the second clock signal CLK2_v.

[0105] In an alternative implementation, such as Figure 1 As shown in the example, the I / O interface may also include an instruction / address buffer configured to buffer a first instruction / address value Cmd / Addr1 input via a first set of data terminals (e.g., terminals A / DQ[7:0]) and a second instruction / address value Cmd / Addr2 input via a first set of terminals (e.g., terminals CA[5:0]), and output the first instruction / address value Cmd / Addr1 and the second instruction / address value Cmd / Addr2 to the control logic unit. For example, in Figure 1In this process, the instruction / address buffer can receive the value A / DQ[7:0]_v input via terminals A / DQ[7:0] and the first control clock CLK1_Ctrl. On the effective clock edge of the first control clock CLK1_Ctrl, the value A / DQ[7:0]_v input via terminals A / DQ[7:0] is sampled and buffered to obtain the first instruction / address value Cmd / Addr1. The first control clock CLK1_Ctrl can be generated by the first IO buffer module according to the input clock CLK1_v and the first interface protocol. Similarly, the instruction / address buffer can also receive the value CA[5:0]_v input via terminals CA[5:0] and the second control clock CLK2_Ctrl. On the effective clock edge of the second control clock CLK2_Ctrl, the value CA[5:0]_v input via terminals CA[5:0] is sampled and buffered to obtain the second instruction / address value Cmd / Addr2. The second control clock CLK2_Ctrl can be generated by the second IO buffer module based on the input clock CLK2_v and the second interface protocol. The instruction / address buffer can have two different buffer areas to store the first instruction / address value Cmd / Addr1 and the second instruction / address value Cmd / Addr2, respectively.

[0106] In some examples, the first control logic module can be configured to receive a first instruction / address value Cmd / Addr1 and a first clock signal CLK1_v, and according to the first interface protocol and the first clock signal CLK1_v, decode the instruction value extracted from the first instruction / address value Cmd / Addr1 to obtain a first internal operation signal, and extract the address value from the first instruction / address value as a first address signal.

[0107] In some examples (such as those compatible with certain LPDDR protocols), the second control logic module also needs to consider the mode register value when performing instruction decoding. For example, the second control logic module determines the internal operation signal corresponding to a read instruction or write instruction based on the read latency (RDlatency) or write latency (WR latency) set in the mode register. Thus, the second control logic module can be configured to receive the second instruction / address value Cmd / Addr2, the second clock signal CLK2_v, and a specified portion of the mode register value, and, according to the second interface protocol and the second clock signal CLK2_v, decode the instruction value extracted from the second instruction / address value Cmd / Addr2 in combination with the specified portion of the mode register value to obtain the second internal operation signal, and extract the address value from the second instruction / address value Cmd / Addr2 as the second address signal. This specified portion of the mode register value can be determined according to the second interface protocol, for example, it can be a specified one-bit or multiple-bit mode register value.

[0108] When the input instruction is a mode register write instruction, i.e., the first internal operation signal or the second internal operation signal indicates that a mode register write operation is to be performed, the address value extracted above is actually the mode register value and other optional related values. Therefore, at least a portion of the corresponding first or second address signal can be cached in the mode register cache as the latest mode register value, i.e., the mode register value is updated.

[0109] Figure 3 It shows Figure 1 A schematic diagram of the composition of a specific example of the control logic section.

[0110] like Figure 3 As shown, the first control logic module includes a first instruction decoder, a first clock gating unit, a first internal operation signal buffer unit, and a first address buffer unit.

[0111] The first instruction decoder is configured to decode the first instruction / address value Cmd / Addr1 according to the first interface protocol to obtain the first decoded signal Dec1.

[0112] The first clock gating unit is configured to convert the first clock signal CLK1_v into a first instruction clock signal Cmd_Clk1 and a first address clock signal Addr_Clk1 according to the first interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the first instruction / address value Cmd / Addr1.

[0113] The first internal operation signal buffer unit is configured to sample and buffer the first decoded signal Dec1 as the first internal operation signal Internal_Oper1 at the time indicated by the first instruction clock signal Cmd_Clk1.

[0114] The first address cache unit is configured to sample and cache the first instruction / address value Cmd / Addr1 as the first address signal Addr1 at the time indicated by the first address clock signal Addr_Clk1.

[0115] Similarly, the second control logic module includes a second instruction decoder, a second clock gating unit, a second internal operation signal buffer unit, and a second address buffer unit.

[0116] The second instruction decoder is configured to decode the second instruction / address value Cmd / Addr2 according to the second interface protocol and in conjunction with the specified part of the mode register value Mode_Reg_p to obtain the second decoded signal Dec2.

[0117] The second clock gating unit is configured to convert the second clock signal CLK2_v into a second instruction clock signal Cmd_Clk2 and a second address clock signal Addr_Clk2 according to the second interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the second instruction / address value Cmd_Clk2.

[0118] The second internal operation signal buffer unit is configured to sample and buffer the second decoded signal Dec2 as the second internal operation signal Internal_Oper2 at the time indicated by the second instruction clock signal Cmd_Clk2.

[0119] The second address cache unit is configured to sample and cache the second instruction / address value Cmd / Addr2 as the second address signal Addr2 at the time indicated by the second address clock signal Addr_Clk2.

[0120] The first or second instruction decoder and the first or second clock gating unit described above can both be implemented using digital logic circuits. For example, the circuit of the first or second instruction decoder can be designed based on the correspondence between the code values ​​of each instruction used by the first or second interface protocol and the internal operation signals required by each instruction. The first or second internal operation signals described above can be one or more signals to be sent to one or more subsequent internal processing modules to control these internal processing modules to perform corresponding operations, thereby realizing the indication of the PSRAM by the corresponding instruction. For example, in... Figure 1 In the example, the final internal operation signal output by the control logic unit (which is equal to the first or second internal operation signal) is input to the subsequent RA&CA control logic module and IO control module. Since, as will be detailed later, the IO control module is only used to control the input and output of access data under the first interface protocol on its data terminals, the second internal operation signal will not enable the IO control module.

[0121] For example, the circuit of the first or second clock gating unit can be designed according to the clock edge settings for transmitting instruction values ​​and address / mode register values ​​in the instruction formats used by the first or second interface protocol. For example, in the case where the instruction values ​​are transmitted on the first and second valid clock edges (i.e., the rising and falling edges of the first clock cycle) and the address values ​​are transmitted on the third to sixth valid clock edges (i.e., the rising and falling edges of the second and third clock cycles), or where some of the valid clock edges transmit the mode register values, a first gating part can be set in the first clock gating unit such that CLK1_v is passed to its output only in the first clock cycle, becoming the first instruction clock signal Cmd_Clk1, and a second gating part can be set such that CLK1_v is passed to its output only in the second and third clock cycles, becoming the first address clock signal Addr_Clk1.

[0122] The aforementioned first or second internal operation signal buffer unit and first or second address buffer unit may each include, for example, a set of latches or registers, which may sample and buffer the input signals, i.e., the first or second decoded signals and the first or second instruction / address values, at the effective clock edges of the first or second instruction clock signal and the first or second address clock signal, respectively. For example, these buffer units may be triggered to perform sampling and buffering operations at both the rising and falling edges of the input clock signal, i.e., the effective clock edges of the aforementioned clock signal may include both rising and falling edges.

[0123] In an alternative embodiment, the control logic unit may further include an output module for merging the outputs of the first control logic module and the second control logic module.

[0124] In one example, the output module can be configured to receive a first internal operation signal Internal_Oper1, a second internal operation signal Internal_Oper2, a first address signal Addr1, and a second address signal Addr2, and output a final internal operation signal Internal_Oper and a final address signal Addr.

[0125] The final internal operation signal, Internal_Oper, is equal to the one of the first internal operation signals, Internal_Oper1 and Internal_Oper2, corresponding to the interface protocol selection signal, Mode_Sel. Similarly, the final address signal, Addr, is equal to the one of the first address signals, Addr1 and Addr2, corresponding to the interface protocol selection signal, Mode_Sel. Here, "final" refers to the signal output by this output module to the outside.

[0126] For example, the output module may include Figure 3 The diagram shows an OR gate OR1 and a multiplexer MUX1. The two inputs of OR1 receive a first internal operation signal Internal_Oper1 and a second internal operation signal Internal_Oper2, respectively, and its output is the final internal operation signal Internal_Oper. The two inputs of multiplexer MUX1 receive a first address signal Addr1 and a second address signal Addr2, respectively. Its control terminal receives an interface protocol selection signal Mode_Sel, and its output is the final address signal Addr. For example, when Mode_Sel is 0, it indicates the selection of the first interface protocol, and multiplexer MUX1 outputs the first address signal Addr1 as the final address signal Addr; when Mode_Sel is 1, it indicates the selection of the second interface protocol, and multiplexer MUX1 outputs the second address signal Addr2 as the final address signal Addr. It is understandable that when both inputs of OR gate OR1 or multiplexer MUX1 contain multiple bits, OR gate OR1 or multiplexer MUX1 also includes multiple OR gate units or multiplexer units, which perform OR (or) operations or multiplexing operations on the corresponding bits of the two inputs.

[0127] In this case, the internal operation signals output by the inactive control logic module are all low-level. Therefore, the final internal operation signal obtained through the OR gate OR1 is the internal operation signal output by the active control logic module. However, the address signals output by the inactive control logic module are not necessarily all low-level. Therefore, a multiplexer is needed to select one input signal corresponding to the interface protocol selection signal Mode_Sel for output. However, in other cases, both control logic modules can be reset before startup. In this case, the address signals output by the inactive control logic module are also all low-level. Therefore, another OR gate can be used instead of multiplexer MUX1 to obtain the final output address signal.

[0128] Alternatively, in an optional implementation, the power supply to the control logic module that is not currently in operation can be turned off to save power consumption.

[0129] In such Figure 3 In the example, the control logic unit may also include a first switch M1, a second switch M2, and a power control module. It is understood that, although... Figure 3 The invention illustrates the use of a PMOS (P-channel Metal-Oxide-Semiconductor) transistor as a switch, but this disclosure is not limited to this, and other devices may be used as needed to implement the first and second switches.

[0130] The first switch M1 is located between the first control logic module and its power supply voltage VDD. The second switch M2 is located between the second control logic module and its power supply voltage VDD. For example, the first or second switch can be set between the power lines used by the circuit devices inside the first or second control logic module and the external power lines transmitting VDD. Thus, the on / off state of the switches can determine whether each control logic module is connected to the power supply.

[0131] The power control module is configured to output the interface protocol selection signal Mode_Sel and its inverted signal to the control terminals of the first switch M1 and the second switch M2, respectively, so that when the interface protocol selection signal Mode_Sel indicates that the first interface protocol is currently selected, the first switch M1 is turned on and the second switch M2 is turned off, and when the interface protocol selection signal Mode_Sel indicates that the second interface protocol is currently selected, the second switch M2 is turned on and the first switch M1 is turned off.

[0132] For example, in Figure 3 In the example, the power control module may include a buffer and an inverter. The interface protocol selection signal Mode_Sel is input to this buffer and inverter, resulting in POWER_EN1 and POWER_EN2, which are equivalent to the interface protocol selection signal Mode_Sel and its inverted signal, respectively. POWER_EN1 is output to the gate of PMOS transistor M1, whose source and drain are coupled to VDD and the first control logic module (e.g., its internal power line), respectively. POWER_EN2 is output to the gate of PMOS transistor M2, whose source and drain are coupled to VDD and the second control logic module (e.g., its internal power line), respectively. When Mode_Sel is 0, the first interface protocol is selected; M1 is turned on and M2 is turned off, thus powering on the first control logic module and powering off the second control logic module. When Mode_Sel is 1, the second interface protocol is selected; M2 is turned on and M1 is turned off, thus powering on the second control logic module and powering off the first control logic module.

[0133] Back Figure 1 .like Figure 1 As shown, in an optional embodiment, the I / O interface may further include an I / O buffer. Figure 1 For ease of illustration, the IO buffer section is divided into a first IO buffer module and a second IO buffer module, which are used for all terminals used by the first interface protocol and all terminals used by the second interface protocol, respectively.

[0134] The I / O buffer can be coupled to the first set of data terminals, the second set of data terminals, and the set of control terminals described above. It includes multiple receivers for receiving signals input from the first set of data terminals, the second set of data terminals, and the set of control terminals, and multiple drivers for driving signals output from portions of the first set of data terminals, the second set of data terminals, and the set of control terminals. This allows for better signal transmission between the I / O interface and the host computer outside the PSRAM. In some cases, differential signaling techniques can be used for transmission, for example, using methods described later. Figure 6 The differential signals CLK1_t and CLK1_c shown are used to input the first clock signal CLK1_v. In this case, the receiver and / or driver in the IO buffer may accordingly include a differential signal receiver and / or transmitter.

[0135] exist Figure 1 In the example, for terminals A / DQ[7:0], DQ[63:0], and DQS / DM and DQS[7:0], which are bidirectional terminals, the I / O buffer provides a receiver and a driver for each of these terminals. For the remaining terminals, which are unidirectional terminals, the I / O buffer provides only a receiver for each of these terminals.

[0136] Additionally, to save power, receivers and / or drivers for terminals not used to transmit signals required by the currently selected interface protocol (i.e., the interface protocol selection signal Mode_Sel) can be turned off. These terminals can also be referred to as idle terminals. The I / O buffer can be configured to turn off receivers and / or drivers for idle terminals according to the interface protocol selection signal Mode_Sel.

[0137] For example, when the first interface protocol is currently selected, such as when Mode_Sel is 0, the second I / O buffer module can be disabled, as mentioned above. Figure 3 Similarly, the control logic unit can turn off the power to the second IO buffer module; when the second interface protocol is currently selected, for example, when Mode_Sel is 1, the first IO buffer module can be turned off, for example, the power to the first IO buffer module can be turned off in a similar way.

[0138] Figure 5 An exemplary configuration diagram of an IO buffer section according to some embodiments of the present disclosure is shown, taking bidirectional terminals A / DQ[7:0] and unidirectional terminals CS1# as examples.

[0139] like Figure 5As shown, for the bidirectional terminals A / DQ[7:0], the IO buffer provides a receiver and driver for each terminal, as well as a set of ODT (On-Die Termination) resistors Rttp, Rttn, and Rttw. For the unidirectional terminal CS1#, the IO buffer provides a receiver and a set of ODT resistors Rttp, Rttn, and Rttw. Resistors Rttp, Rttn, and Rttw have their own different resistance values. It can be understood that the number of each set of ODT resistors is not limited to 3, but can be determined as needed.

[0140] In addition, the I / O buffer also includes an ODT control unit and an OCD (Off-Chip Driver) control unit. The ODT control unit is used to control which resistor in a set of ODT resistors for each terminal is enabled in order to match the transmission line impedance, etc. The OCD control unit is used to control the output impedance of each driver in order to match the transmission line impedance, etc.

[0141] Figure 5 The ellipsis indicates the portion of the IO buffer used for the other terminals. It can be understood that its specific structure can be the same as the structure used for bidirectional or unidirectional terminals as described above, and will not be repeated here.

[0142] Back Figure 1 .like Figure 1 As shown, in an optional embodiment, the IO interface may further include an internal access data bus DBUS[63:0] and an access data IO unit.

[0143] The internal access data bus DBUS[63:0] is used to transmit access data between the memory array within the PSRAM and terminals A / DQ[7:0], and between the memory array and terminals DQ[63:0]. Its bit width is equal to the number of terminals DQ[63:0]. Therefore, the first interface protocol and the second interface protocol can share the same data bus to exchange access data with the memory array, and the data bit width of the second interface protocol is the same as the bit width of the internal access data bus, thus avoiding bit width conversion.

[0144] For the first interface protocol, since its data bit width does not match the bit width of the internal access data bus, it is necessary to access the data I / O section to perform bit width conversion.

[0145] The access data IO unit is configured to concatenate multiple write data obtained by sampling the input of the first set of data terminals, such as terminals A / DQ[7:0], on the fifth clock edge into a single internal write data so as to output to the internal access data bus DBUS[63:0] at the same time, and to split a single internal read data received at the same time via the internal access data bus DBUS[63:0] into multiple read data so as to output them in multiple times via the first set of data terminals, such as terminals A / DQ[7:0].

[0146] For example, during a write operation, eight consecutive write data inputs from the first set of data terminals, such as terminals A / DQ[7:0], can be concatenated into a single 64-bit internal write data. During a read operation, the simultaneously read 64-bit internal read data can be split into eight read data segments for continuous output eight times from the first set of data terminals, such as terminals A / DQ[7:0]. The aforementioned fifth set of clock edges can be eight consecutive valid clock edges determined according to the write instruction format of the first interface protocol.

[0147] In some examples, the first set of data terminals, such as terminals A / DQ[7:0], uses DDR timing to access data, and the data access I / O section may include a write driver, a data interface, a read data buffer module, a read data multiplexer, and a read driver. The write driver (e.g., subsequently...) Figure 6 The write driver shown in the write driver and input logic module is configured to concatenate two write data samples obtained from two consecutive clock edges on the fifth set of clock edges to the input of the first set of data terminals, such as terminals A / DQ[7:0], into a single intermediate write data for output at the same time. The data interface (e.g., subsequent...) Figure 6 The data interface shown is configured to concatenate multiple consecutively output intermediate write data into a single internal write data. A read data caching module (e.g., subsequent...) Figure 6 The read data FIFO (First-In First-Out buffer) shown and the read data FIFO in the MUX module are configured to buffer the aforementioned internal read data. Figure 6 The read data FIFO and the MUX module in the MUX module shown are configured to split the cached internal read data into multiple intermediate read data and output them sequentially, wherein the number of bits of the intermediate read data is twice the number of terminals of the first group of data terminals, such as terminals A / DQ[7:0]. The read driver (e.g., the subsequent...) Figure 6 The read driver shown is configured to split one of the intermediate read data into two read data to be output on two consecutive clock edges via a first set of data terminals, such as terminals A / DQ[7:0].

[0148] Figure 6 Taking the DDR transmission timing of terminals A / DQ[7:0] as an example, an exemplary composition diagram of the access data I / O unit according to some embodiments of the present disclosure is shown.

[0149] like Figure 6 As shown, the data access I / O unit includes a write driver and input logic module, a data interface, a read data FIFO and MUX module, and a read driver. Additionally, in some examples, the data access I / O unit may also include a DLL (Delay-Locked Loop) to ensure that the output clock CLK1_v is synchronized with an externally received clock. Although the figure shows the DLL receiving a pair of differential signals CLK1_t and CLK1_c, it can be understood that, as mentioned earlier, this pair of differential signals can be converted into a single-ended clock signal by the differential signal receiver in the first I / O buffer module before being input to the DLL.

[0150] During the write operation, the input logic module of the write driver and input logic module can determine the fifth set of clock edges mentioned above based on the input clock CLK1_v and the first interface protocol. This allows the write driver to sequentially concatenate two 8-bit write data samples obtained from the input of terminals A / DQ[7:0] on every two consecutive clock edges into a single 16-bit intermediate write data for output at the same time. Additionally, the write driver and input logic module can also receive the DM signal input from terminal DQS / DM and perform corresponding write data masking processing.

[0151] After receiving four consecutive intermediate write data from the write driver and input logic module, the data interface concatenates these four intermediate write data into a 64-bit internal write data and outputs it to the internal access data bus DBUS[63:0].

[0152] During the read operation, the read data FIFO and the read data FIFO (First-In-First-Out buffer) in the MUX module can sequentially receive and buffer multiple 64-bit internal read data from the internal access data bus DBUS[63:0], and output them to the MUX module for splitting processing in the order of input. The MUX module splits a 64-bit internal read data into four 16-bit intermediate read data and outputs them sequentially.

[0153] The read driver splits each intermediate read data received from the MUX module into two 8-bit read data segments for output via terminals A / DQ[7:0] on two consecutive clock edges. Additionally, the read driver can simultaneously output a DQS signal for synchronizing the read data to terminal DQS / DM.

[0154] The following will combine Figure 2This describes an embodiment where some terminals are multiplexed for two interface protocols. For example... Figure 2 As shown in the rightmost terminal, the second interface protocol reuses at least some of the terminals of the first interface protocol.

[0155] It is understood that this disclosure is not limited to this method of multiplexing terminals, and at least some terminals of the second interface protocol may also be multiplexed by the first interface protocol. As mentioned above, for example, the set of control terminals may include at least one control terminal multiplexed for the first and second interface protocols; and / or, at least some of the first set of data terminals may also be used to transmit at least some of the control signals and / or access data required by the second interface protocol, or at least some of the second set of data terminals may also be used to transmit at least some of the control signals and / or access data required by the first interface protocol.

[0156] By reusing terminals, the number of terminals required can be reduced, thereby reducing chip size and saving packaging costs.

[0157] The following will mainly describe Figure 2 China is different from Figure 1 For the remaining identical parts, please refer to the above combination. Figure 1 The relevant descriptions will not be repeated here.

[0158] like Figure 2 As shown, compared to Figure 1 The terminals CS2#, RESET2#, CLK2, CA[5:0], and DQS[0] originally used for the second interface protocol have been omitted, and their functions are now combined with those of the terminals CS1#, RESET1#, CLK1, A / DQ[7:0], and DQS / DM originally used for the first interface protocol. For ease of demonstration, in... Figure 2 In this context, the terminals that are used for both interface protocols are renamed CS#, RESET#, CLK, A / DQ[7:0] / CA[5:0], and DQS / DM / DQS[0]. It can be understood that CA[5:0] only reuses 6 terminals in A / DQ[7:0], such as the terminals corresponding to the lowest 6 bits.

[0159] It can be said that, in Figure 2 In the I / O interface, at least a portion of the first group of data terminals is also used for time-sharing transmission of instruction values, address values, and mode register values ​​according to the second interface protocol, for example... Figure 2 Terminals A / DQ[7:0] / CA[5:0] are used. Therefore, in Figure 2 When the IO interface operates in the first interface protocol mode and the second interface protocol mode, the mode register value and the instruction value are both input via the first set of data terminals, such as terminals A / DQ[7:0] / CA[5:0].

[0160] The aforementioned set of control terminals includes a first sub-set of control terminals for transmitting control signals required by the first interface protocol, excluding instruction values, address values, and mode register values. It is also used to transmit at least a portion of the control signals required by the second interface protocol, excluding instruction values, address values, and mode register values, such as including... Figure 2 The terminals CS#, RESET#, CLK, and DQS / DM / DQS[0] are used. Figure 2 In the example, the set of control terminals may further include a second sub-set of control terminals for transmitting remaining control signals required for the second interface protocol, such as including... Figure 2 Terminal DQS[7:1].

[0161] In other examples, in order to achieve better signal matching, the DQS[0] terminal may not be reused to transmit DQS[0], but the terminal may be set independently to transmit DQS[0], just like DQS[7:1]. Therefore, the second subgroup control terminal mentioned above may include the DQS[7:0] terminal.

[0162] In addition, Figure 2 In this configuration, the instruction / address buffer only needs to buffer the instruction / address value Cmd / Addr input via the first set of data terminals, such as terminals A / DQ[7:0] / CA[5:0], and output the instruction / address value Cmd / Addr to the control logic unit. It is understandable that the different instruction formats of the two interface protocols may lead to different input times for the instruction / address value Cmd / Addr under different interface protocols. For example, when operating under the first interface protocol, the corresponding instruction / address value Cmd / Addr can be multiple values ​​sampled from the input (e.g., A / DQ[7:0] / CA[5:0]_v) of the first data terminal, such as terminal A / DQ[7:0] / CA[5:0], at the third clock edge; when operating under the second interface protocol, the corresponding instruction / address value Cmd / Addr can be multiple values ​​sampled from the input (e.g., A / DQ[7:0] / CA[5:0]_v) of the first data terminal, such as terminal A / DQ[7:0] / CA[5:0], at the fourth clock edge. The third and fourth clock edges can be the same or different, and can be determined by the control clock CLK_Ctrl, which can be generated by the first IO buffer module based on the currently input clock CLK_v and the currently selected interface protocol.

[0163] In addition, the clock signal when operating under both protocols is also input from the clock terminal CLK, which is multiplexed to transmit the clock signals required by the first interface protocol and the second interface protocol.

[0164] Therefore, the instruction / address value Cmd / Addr and clock signal CLK_v input to the control logic unit are signals multiplexed for the two interface protocols. They need to be demultiplexed in the control logic unit into first and second instruction / address values, and first and second clock signals, so that they can be used by the first control logic module and the second control logic module respectively. For example... Figure 4 shown.

[0165] Figure 4 A schematic diagram illustrating the composition of a specific example of a control logic unit is shown, which is related to... Figure 3 The difference is that a first demultiplexer DEMUX1 and a second demultiplexer DEMUX2 are added.

[0166] like Figure 4 As shown, the input of the first demultiplexer DEMUX1 receives the instruction / address value Cmd / Addr, its control terminal receives the interface protocol selection signal Mode_Sel, and its two output terminals output the first instruction / address value Cmd / Addr1 and the second instruction / address value Cmd / Addr2, respectively. As mentioned above, the instruction / address value Cmd / Addr is a set of multiple values ​​obtained by sampling the input (e.g., A / DQ[7:0] / CA[5:0]_v) of the first set of data terminals, such as the input of terminal A / DQ[7:0] / CA[5:0], on the third or fourth clock edge.

[0167] The input terminal of the second demultiplexer DEMUX2 receives the clock signal CLK_v input from the clock terminal, its control terminal receives the interface protocol selection signal Mode_Sel, and its two output terminals output the first clock signal CLK1_v and the second clock signal CLK2_v respectively.

[0168] For example, when Mode_Sel is 0, it indicates that the first interface protocol is selected. The first demultiplexer DEMUX1 outputs the input instruction / address value Cmd / Addr to the first output terminal as the first instruction / address value Cmd / Addr1, and the second demultiplexer DEMUX2 outputs the input clock signal CLK_v to the first output terminal as the first clock signal CLK1_v. When Mode_Sel is 1, it indicates that the second interface protocol is selected. The first demultiplexer DEMUX1 outputs the input instruction / address value Cmd / Addr to the second output terminal as the second instruction / address value Cmd / Addr2, and the second demultiplexer DEMUX2 outputs the input clock signal CLK_v to the second output terminal as the second clock signal CLK2_v.

[0169] Figure 4 The rest of the control logic section is related to Figure 3 The corresponding parts are the same; please refer to the above combination. Figure 3The relevant descriptions will not be repeated here.

[0170] The following will combine Figure 7 and Figure 8 A method for accessing PSRAM according to an embodiment of this disclosure is described.

[0171] like Figure 7 As shown, the PSRAM includes an I / O interface, an access processing unit, and a memory array according to the foregoing embodiments. As previously described, the access processing unit is configured to perform corresponding access operations on the memory array based on the result of instruction decoding processing by the control logic unit in the I / O interface. The specific structure of the I / O interface can be found in the preceding figures and descriptions, and will not be repeated here.

[0172] Additionally, the host is coupled to the I / O interface to interact with the PSRAM and perform access operations. The host can be coupled to multiple terminals of the I / O interface as needed. For example, if the host wants to access the PSRAM using a first interface protocol, it can be coupled to all terminals of the I / O interface used for the first interface protocol, namely the first set of data terminals and the control terminals used to transmit the control signals required for the first interface protocol. If the host wants to access the PSRAM using a second interface protocol, it can be coupled to all terminals of the I / O interface used for the second interface protocol, namely the second set of data terminals and the control terminals used to transmit the control signals required for the second interface protocol. If the host wants to switch between the first and second interface protocols to access the PSRAM, it can be coupled to all terminals of the I / O interface.

[0173] The host exchanges data with the PSRAM via the I / O interface to access the PSRAM. For example, the host sends various data required for access to the PSRAM as described above to the PSRAM via the I / O interface and receives data related to reading from the PSRAM as described above.

[0174] Figure 8 The PSRAM access method is described from the PSRAM side, namely... Figure 8 The method is executed by PSRAM. However, it is understandable that... Figure 8 In this method, the other party exchanging data via the I / O interface terminals is the host. Figure 8 For details of the operation, please refer to the descriptions of the aforementioned figures, which will not be repeated here.

[0175] As shown in Figure 8, at step S810, the mode register value is received via the first set of data terminals or the first part of the terminals in the IO interface. Then, at step S820, the instruction value is received via the first set of data terminals or the first part of the terminals.

[0176] Then, at step S830, according to the interface protocol selection signal in the mode register value, the instruction value is decoded using one of the corresponding first control logic module and the second control logic module in the IO interface.

[0177] Then, in step S840, based on the result of the instruction decoding process, the access processing unit performs corresponding access operations on the memory array.

[0178] For example, in the IO interface using Figure 1 In the structure shown, and where the host intends to access the PSRAM using the LPDDR protocol as the second interface protocol, the host can sequentially input the mode register value and the instruction value via terminals CA[5:0] in the manner specified by the LPDDR protocol. Correspondingly, the PSRAM receives the mode register value and the instruction value sequentially via terminals CA[5:0]. Based on the value of the interface protocol selection signal in the received mode register value, the PSRAM determines that the LPDDR protocol will be used for the access operation next, and therefore uses the corresponding second control logic module to perform instruction decoding processing on the received instruction value. The PSRAM can transmit the result of the instruction decoding processing to the access processing unit so as to control the access processing unit to perform the corresponding access operation on the memory array.

[0179] The following will combine Figure 9 This invention describes an embodiment of a PSRAM that simultaneously supports access from two hosts using different interface protocols, according to the present disclosure.

[0180] Figure 9 An exemplary compositional schematic diagram of an electronic device according to some embodiments of the present disclosure is shown, wherein the electronic device includes a PSRAM, a first host, and a second host according to the preceding embodiments.

[0181] like Figure 9 As shown, the I / O interface in the PSRAM includes a first interface protocol terminal for a first interface protocol and a second interface protocol terminal for a second interface protocol. The first interface protocol terminal includes a first subgroup of control terminals from the aforementioned first group of data terminals and a group of control terminals for transmitting control signals required for the first interface protocol. The second interface protocol terminal includes a second subgroup of control terminals from the aforementioned second group of data terminals and a group of control terminals for transmitting control signals required for the second interface protocol. Furthermore, in the presence of multiplexed data terminals, the first interface protocol terminal may also include a multiplexed second group of data terminals, and / or the second interface protocol terminal may also include a multiplexed first group of data terminals; in the presence of multiplexed control terminals, the aforementioned first and second subgroups may overlap, meaning that the control terminals multiplexed for both protocols belong to both the first and second subgroups.

[0182] The first host is coupled to the first interface protocol terminal and is configured to input the mode register value MR to the IO interface via the first set of data terminals or the first part of the terminals when accessing the PSRAM, so that the interface protocol selection signal Mode_Sel indicates that the first interface protocol mode is currently selected. The first host can interact with the PSRAM using the first interface protocol to realize the access operation.

[0183] The second host is coupled to the second interface protocol terminal and is configured to input the mode register value MR to the IO interface via the first set of data terminals or the first part of the terminals when accessing the PSRAM, so that the interface protocol selection signal Mode_Sel indicates that the second interface protocol mode is currently selected. The second host can interact with the PSRAM using the second interface protocol to perform access operations.

[0184] Additionally, the first host includes a first occupancy status terminal 91, and the second host includes a second occupancy status terminal 92. The first occupancy status terminal 91 and the second occupancy status terminal 92 are coupled together and used to exchange occupancy statuses of the PSRAM between the first and second hosts to ensure time-sharing access to the PSRAM by both hosts. The occupancy status of the PSRAM may include information indicating whether an interaction with the PSRAM is currently in progress. In some examples, the first occupancy status terminal 91 and the second occupancy status terminal 92 may also be referred to as BUSY terminals, exchanging a BUSY signal between them to indicate their respective occupancy statuses of the PSRAM.

[0185] For example, the first host can learn the second host's occupation status of the PSRAM from the second occupation status terminal 92 before initiating an interaction with the PSRAM. The first host can only initiate an interaction with the PSRAM if it is not occupied. After initiating an interaction with the PSRAM, the first host changes its own occupation status to occupied, preventing the second host from interacting with the PSRAM.

[0186] Therefore, PSRAM can support two interface protocols working simultaneously, and by adopting a time-sharing multiplexing method, it can avoid access conflicts between two hosts to PSRAM, ensuring that only one host accesses it at a time, thus making it suitable for more and more complex application scenarios.

[0187] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An I / O interface for a pseudo-static random access memory, selectively operating in a first interface protocol mode or a second interface protocol mode, the I / O interface comprising: The first set of data terminals for the first interface protocol; The second set of data terminals used for the second interface protocol has a greater number of terminals than the first set of data terminals; A set of control terminals for the first and second interface protocols; The mode register buffer is configured to buffer mode register values ​​input via the first set of data terminals or via a first portion of the terminals in the set of control terminals, wherein at least one bit of the mode register value is used as an interface protocol selection signal; The control logic unit includes a first control logic module and a second control logic module that perform instruction decoding according to the first interface protocol and the second interface protocol, respectively, and is configured to perform instruction decoding processing on instruction values ​​input via the first group of data terminals or via the first part of the terminals using a corresponding one of the first control logic module and the second control logic module according to the interface protocol selection signal. The first control logic module is configured to receive a first instruction / address value and a first clock signal, and according to the first interface protocol and the first clock signal, decode the instruction value extracted from the first instruction / address value to obtain a first internal operation signal, and extract the address value from the first instruction / address value as a first address signal. And / or, The second control logic module is configured to receive a second instruction / address value, a second clock signal, and a specified portion of the mode register value, and according to the second interface protocol and the second clock signal, combine the specified portion of the mode register value to perform instruction decoding on the instruction value extracted from the second instruction / address value to obtain a second internal operation signal, and extract the address value from the second instruction / address value as a second address signal.

2. The I / O interface according to claim 1, wherein, The first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol; and The second set of data terminals is used to transmit access data only according to the second interface protocol.

3. The I / O interface according to claim 2, wherein, The set of control terminals includes a first subgroup of control terminals for transmitting control signals required by the first interface protocol other than instruction values, address values, and mode register values, and a second subgroup of control terminals for transmitting all control signals required by the second interface protocol. The second subgroup of control terminals includes instruction / address multiplexed terminals for time-division multiplexing instruction values, address values, and mode register values ​​according to the second interface protocol as the first part of the terminals. When the I / O interface is operating in the first interface protocol mode, both the mode register value and the instruction value are input via the first set of data terminals. When the I / O interface is operating in the second interface protocol mode, both the mode register value and the instruction value are input via the instruction / address multiplexing terminal.

4. The I / O interface according to claim 2, wherein, At least a portion of the first set of data terminals is also used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol; The set of control terminals includes a first sub-set of control terminals for transmitting control signals required by the first interface protocol other than instruction values, address values, and mode register values. The first sub-set of control terminals is also used to transmit at least a portion of the control signals required by the second interface protocol other than instruction values, address values, and mode register values. When the I / O interface is operating in the first interface protocol mode and the second interface protocol mode, both the mode register value and the instruction value are input via the first set of data terminals.

5. The I / O interface according to claim 1, wherein, In the first case where the first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol, and the first portion of the terminals is used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol, the first instruction / address value is a plurality of values ​​obtained by sampling the input of the first set of data terminals at the first clock edge, and the second instruction / address value is a plurality of values ​​obtained by sampling the input of the first portion of the terminals at the second clock edge; or, in the second case where the first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol, and at least a portion of the first set of data terminals is also used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol, the first instruction / address value and the second instruction / address value are respectively a plurality of values ​​obtained by sampling the input of the first set of data terminals at the third clock edge and the fourth clock edge; The first clock signal and the second clock signal are respectively input from the first clock terminal and the second clock terminal of the set of control terminals, which are respectively used to transmit the clock signals required by the first interface protocol and the second interface protocol, or both are input from the clock terminal of the set of control terminals that are multiplexed to transmit the clock signals required by the first interface protocol and the second interface protocol.

6. The I / O interface according to claim 1, wherein, The first control logic module includes: A first instruction decoder is configured to decode the first instruction / address value according to the first interface protocol to obtain a first decoded signal. The first clock gating unit is configured to convert the first clock signal into a first instruction clock signal and a first address clock signal according to the first interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the first instruction / address value. A first internal operation signal buffer unit is configured to sample and buffer the first decoded signal as the first internal operation signal at the time indicated by the first instruction clock signal, and The first address cache unit is configured to sample and cache the first instruction / address value as the first address signal at the time indicated by the first address clock signal; and / or, The second control logic module includes: The second instruction decoder is configured to decode the second instruction / address value according to the second interface protocol and in conjunction with the mode register value of the specified portion to obtain a second decoded signal. The second clock gating unit is configured to convert the second clock signal into a second instruction clock signal and a second address clock signal according to the second interface protocol, which respectively indicate the sampling time of the instruction value and the address value in the second instruction / address value. The second internal operation signal buffer unit is configured to sample and buffer the second decoded signal as the second internal operation signal at the time indicated by the second instruction clock signal, and The second address cache unit is configured to sample and cache the second instruction / address value as the second address signal at the time indicated by the second address clock signal.

7. The I / O interface according to claim 1, wherein, In the case where the first set of data terminals is used for time-division multiplexing of access data, instruction values, address values, and mode register values ​​according to the first interface protocol, at least a portion of the first set of data terminals is also used for time-division multiplexing of instruction values, address values, and mode register values ​​according to the second interface protocol, and the clock terminals in the set of control terminals are multiplexed for transmitting clock signals required by the first interface protocol and the second interface protocol, the control logic unit further includes: The first demultiplexer receives, at its input terminal, an instruction / address value sampled from the input of the first group of data terminals at the third or fourth clock edge; at its control terminal, it receives the interface protocol selection signal; and at its two output terminals, it outputs the first instruction / address value and the second instruction / address value, respectively. The second demultiplexer receives a clock signal input from the clock terminal, receives the interface protocol selection signal at its control terminal, and outputs the first clock signal and the second clock signal at its two output terminals, respectively.

8. The I / O interface according to claim 1, wherein, The control logic unit further includes: The output module is configured to receive the first internal operation signal, the second internal operation signal, the first address signal, and the second address signal, and to output a final internal operation signal and a final address signal, wherein the final internal operation signal is equal to one of the first internal operation signal and the second internal operation signal that corresponds to the interface protocol selection signal, and the final address signal is equal to one of the first address signal and the second address signal that corresponds to the interface protocol selection signal.

9. The I / O interface according to claim 8, wherein, When the final internal operation signal indicates a mode register write operation, at least a portion of the final address signal is cached in the mode register cache as the latest mode register value.

10. The I / O interface according to claim 1, wherein, The control logic unit further includes: The first switch is located between the first control logic module and the power supply voltage it uses; A second switch is located between the second control logic module and its power supply voltage; and The power control module is configured to output the interface protocol selection signal and its inverted signal to the control terminals of the first switch and the second switch, respectively, such that when the interface protocol selection signal indicates that the first interface protocol is currently selected, the first switch is turned on and the second switch is turned off, and when the interface protocol selection signal indicates that the second interface protocol is currently selected, the second switch is turned on and the first switch is turned off.

11. The I / O interface according to claim 1, further comprising: An I / O buffer is coupled to the first set of data terminals, the second set of data terminals, and the set of control terminals, and includes multiple receivers for receiving signals input from the first set of data terminals, the second set of data terminals, and the set of control terminals, and multiple drivers for driving signals output from a portion of the first set of data terminals, the second set of data terminals, and the set of control terminals.

12. The I / O interface according to claim 11, wherein, The IO buffer is configured to turn off the receiver and / or driver for the idle terminal according to the interface protocol selection signal, wherein the idle terminal is a terminal that is not used to transmit signals required by the interface protocol corresponding to the interface protocol selection signal.

13. The I / O interface according to claim 1, further comprising: An internal access data bus is used to transmit access data between the storage array in the pseudo-static random access memory and the first set of data terminals, and between the storage array and the second set of data terminals, wherein the number of bits is equal to the number of terminals in the second set of data terminals. as well as The access data I / O unit is configured to concatenate multiple write data samples obtained from the input of the first group of data terminals on the fifth group of clock edges into a single internal write data for output to the internal access data bus at the same time, and to split a single internal read data received at the same time via the internal access data bus into multiple read data for output multiple times via the first group of data terminals.

14. The I / O interface according to claim 13, wherein, The first set of data terminals uses DDR timing to transmit the read data and the write data, and the access data I / O unit includes: The write driver is configured to concatenate two write data samples obtained from the input of the first set of data terminals on two consecutive clock edges in the fifth set of clock edges into an intermediate write data for output at the same time. The data interface is configured to concatenate multiple consecutively output intermediate write data into a single internal write data; The read data caching module is configured to cache the aforementioned internal read data; A read data multiplexer is configured to split buffered internal read data into multiple intermediate read data and output them sequentially, wherein the number of bits in the intermediate read data is twice the number of terminals in the first group of data terminals; and The read driver is configured to split one of the intermediate read data into two read data for output on two consecutive clock edges via the first set of data terminals.

15. The I / O interface according to claim 1, wherein, The set of control terminals includes a first subgroup of control terminals used only for transmitting at least a portion of the control signals required by the first interface protocol and a second subgroup of control terminals used only for transmitting at least a portion of the control signals required by the second interface protocol; or the set of control terminals includes at least one control terminal multiplexed for the first and second interface protocols; and / or At least a portion of the first set of data terminals is also used to transmit at least a portion of the control signals and / or access data required by the second interface protocol; or at least a portion of the second set of data terminals is also used to transmit at least a portion of the control signals and / or access data required by the first interface protocol; and / or The first interface protocol is the xSPI protocol, and the second interface protocol is the LPDDR protocol; And / or The first group of data terminals has 8 terminals, and the second group of data terminals has 64 terminals.

16. A pseudo-static random access memory, comprising: The I / O interface according to any one of claims 1-15; Storage array; The access processing unit is configured to perform corresponding access operations on the memory array based on the result of instruction decoding processing performed by the control logic unit in the I / O interface.

17. A method for accessing a pseudo-static random access memory according to claim 16, comprising: The mode register value is received via the first set of data terminals or the first portion of the terminals; The instruction value is received via the first set of data terminals or the first portion of the terminals; Based on the interface protocol selection signal in the mode register value, the instruction value is decoded using one of the first control logic module and the second control logic module. as well as Based on the result of the instruction decoding process, the access processing unit performs corresponding access operations on the memory array.

18. An electronic device comprising: The pseudo-static random access memory according to claim 16; as well as A first host is coupled to the first set of data terminals in the I / O interface of the pseudo-static random access memory, and a first sub-set of control terminals in the set of control terminals for transmitting control signals required for the first interface protocol, and is configured to input the mode register value to the I / O interface via the first set of data terminals or the first set of terminals when accessing the pseudo-static random access memory, such that the interface protocol selection signal indicates that the first interface protocol mode is currently selected.

19. The electronic device of claim 18, further comprising: The second host is coupled to the second set of data terminals in the IO interface and the second sub-set of control terminals in the set of control terminals for transmitting control signals required for the second interface protocol, and is configured to input the mode register value to the IO interface via the first set of data terminals or the first part of the terminals when accessing the pseudo-static random access memory, such that the interface protocol selection signal indicates that the second interface protocol mode is currently selected. The first host and the second host each further include a first occupancy status terminal and a second occupancy status terminal. The first occupancy status terminal is coupled together with the second occupancy status terminal and is used to exchange the occupancy status of the pseudo-static random access memory between the first host and the second host to ensure that the first host and the second host access the pseudo-static random access memory in a time-sharing manner.

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