A solid state disk temperature cycle test method based on multi-stress coupling

Abstract

The present application relates to the technical field of data storage, and discloses a solid state disk temperature cycle test method based on multi-stress coupling, which comprises the following steps: initializing a test environment; determining a temperature range of dynamic temperature variation test and a voltage range of dynamic voltage test; testing running records of a solid state disk to be tested according to the temperature range of dynamic temperature variation test and the voltage range of dynamic voltage test; increasing a vibration frequency of simulated environmental vibration in the dynamic temperature variation test of the solid state disk to be tested in a preset time range, and executing a specific type of I / O operation mode test; and recording SMART data, real-time power consumption and link-level error rate output by the I / O operation mode based on a data acquisition system. The present application comprehensively reflects the complex environment of the solid state disk in an actual application scenario, overcomes the limitation of traditional temperature cycle tests which only consider a single environmental stress, and improves the comprehensiveness and accuracy of the test.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a method for temperature cycling testing of solid-state drives based on multi-stress coupling. Background Technology

[0002] With the rapid development of electronic technology, solid-state drives (SSDs) are increasingly widely used in data storage. However, SSDs face complex environmental stress challenges in real-world use, including temperature changes, voltage fluctuations, and vibrations. These factors can lead to performance degradation or failure of SSDs. While traditional temperature cycling testing methods can assess the reliability of SSDs to some extent, they often only simulate single environmental stresses and cannot comprehensively reflect the multi-dimensional stress conditions encountered in actual use.

[0003] Furthermore, existing accelerated life testing methods are mostly based on single or dual stress models, which are difficult to fully simulate the multi-dimensional stress conditions of SSDs in real-world application scenarios, and also ignore the coupling effects between multiple stresses. For complex SSD products, the task stages they experience and the environmental factors they face throughout their entire life cycle are diverse, and the failure mechanisms and sensitive stresses of different components are different. The combined effect of multiple factors has a more complex impact on the failure modes and failure mechanisms of SSDs. Summary of the Invention

[0004] This invention provides a temperature cycling test method for solid-state drives based on multi-stress coupling, which can solve the technical problem that existing accelerated life test methods are mostly based on single or dual stress models, making it difficult to fully simulate the multi-dimensional stress conditions of SSDs in real-world application scenarios.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a solid-state drive temperature cycling test method based on multi-stress coupling, the method comprising:

[0006] Initialize the test environment, which includes setting test equipment parameters, installing the solid-state drive under test, and initializing the data acquisition system.

[0007] Determine the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing, and then test the operating records of the solid-state drive under test based on the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing.

[0008] In the dynamic temperature change test, which maintains the test within a preset time range, the solid-state drive under test is subjected to a vibration frequency that simulates environmental vibration, and a specific type of I / O operation mode test is performed.

[0009] The data acquisition system records SMART data, real-time power consumption, and link-level bit error rate output in real time based on the I / O operation mode.

[0010] An anomaly detection model is established. Based on historical normal solid-state drive data, the anomaly detection model is trained using the isolated forest or autoencoder algorithm. The real-time recorded SMART data is compared with the anomaly detection model. The health status score of the solid-state drive under test is calculated based on the comparison results. The health status score is then analyzed, and the analysis results are used to generate a health test report.

[0011] The beneficial effects of this invention are as follows: By introducing a multi-stress coupling mechanism, it comprehensively simulates multi-dimensional stress conditions such as temperature changes, voltage fluctuations, and vibrations, fully reflecting the complex environment of solid-state drives in real-world application scenarios. This overcomes the limitations of traditional temperature cycling tests that only consider single-environment stresses, improving the comprehensiveness and accuracy of the test. Employing online real-time monitoring and intelligent diagnostic technology, it continuously monitors and collects data from multiple dimensions of the SSD, including physical health parameters, SMART information, and real-time power consumption, achieving full-process monitoring and dynamic analysis of the SSD during testing. This effectively solves the blindness problem of the traditional "post-test inspection" mode. Targeted test modes and evaluation criteria are designed according to different SSD types and application scenarios, especially for QLC / PLC flash memory, ZNS SSDs, and Compute Express Link (CXL). Corresponding testing methods have been developed for emerging technologies and architectures such as SSDs, improving the relevance and applicability of testing. By introducing a dynamic temperature change rate testing mechanism, which combines rapid temperature rise and fall with slow temperature rise and fall, defects such as solder joint fatigue and chip cracking caused by mismatch in the thermal expansion coefficients of materials are effectively tested, improving the comprehensiveness and depth of testing. A comprehensive data integrity verification mechanism has been designed, which ensures that no silent errors occur in the data during the entire rigorous testing process by comparing the CRC checksum recorded during writing, effectively improving the reliability and accuracy of testing. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the solid-state drive temperature cycling test method based on multi-stress coupling according to the first embodiment of the present invention.

[0013] Figure 2 yes Figure 1 A flowchart illustrating step 1.

[0014] Figure 3 yes Figure 1 A flowchart illustrating step 2.

[0015] Figure 4 yes Figure 1 A flowchart illustrating step 3.

[0016] Figure 5 yes Figure 1 A flowchart illustrating step 4.

[0017] Figure 6 yes Figure 1 A flowchart illustrating step 5. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] The terms "comprising" and "having," and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] Figure 1 This is a flowchart illustrating the solid-state drive temperature cycling test method based on multi-stress coupling according to the first embodiment of the present invention. Figure 1 As shown, the system includes hardware and software components:

[0022] Step 1: Initialize the test environment, which includes setting the test equipment parameters, installing the solid-state drive under test, and initializing the data acquisition system;

[0023] Step 2: Determine the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing, and record the operation of the solid-state drive under test according to the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing.

[0024] Step 3: In the dynamic temperature change test, which is conducted within a preset time range, the solid-state drive under test is subjected to a vibration frequency that simulates environmental vibration, and a specific type of I / O operation mode test is performed.

[0025] Step 4: Based on the data acquisition system, record the SMART data output in the I / O operation mode, real-time power consumption, and link-level bit error rate in real time;

[0026] Step 5: Establish an anomaly detection model. Based on historical normal SSD data, train the anomaly detection model using the isolated forest or autoencoder algorithm. Compare the real-time recorded SMART data with the anomaly detection model. Calculate the health status score of the SSD under test based on the comparison results. Analyze the health status score and generate a health test report from the analysis results.

[0027] By simulating extreme or dynamically changing environmental conditions (temperature, voltage, vibration) and combining specific I / O operation modes, the key parameters of the SSD (SMART data, power consumption, bit error rate) are monitored in real time, and its health status is evaluated using an anomaly detection model. Ultimately, the stability and reliability of the SSD in complex environments are verified.

[0028] Step 1: Test Environment Initialization: Test Equipment Parameter Settings: Define the accuracy range of the test equipment (e.g., temperature control accuracy ±1℃, voltage regulation accuracy ±0.1V), and the connection method with the SSD (e.g., PCIe / NVMe interface stability assurance). SSD Installation: Ensure the SSD is securely fixed (especially important for subsequent vibration testing) to avoid poor physical contact affecting data transmission; simultaneously record the SSD's initial state (e.g., initial SMART data, firmware version). Data Acquisition System: Define the acquisition frequency (e.g., 1 second / time) to ensure synchronous recording of environmental parameters (real-time temperature, voltage, vibration frequency) and SSD output data, avoiding timeline deviation.

[0029] Step 2: Dynamic Temperature and Voltage Range Testing: Temperature Range: Based on the SSD's design specifications (e.g., commercial grade 0~70℃, industrial grade -40~85℃), set a dynamic temperature change curve (e.g., increasing from -40℃ to 85℃ at a rate of 5℃ / min, then cycling down). Voltage Range: For the SSD's power supply specifications (e.g., 12V±5%, 5V±5%), set a fluctuation mode (e.g., step change or sinusoidal fluctuation) to simulate unstable power grids or power supply noise. Operation Records: Specify the test duration (e.g., holding each temperature / voltage point for 30 minutes) and record whether the SSD experiences basic failures such as disk drops or read / write interruptions.

[0030] Step 3: I / O Testing under Vibration Coupling Environment: Vibration Frequency: Set vibration parameters (e.g., 10~2000Hz sweep frequency, 20G acceleration) according to the application scenario (e.g., automotive, industrial equipment). This should be performed simultaneously with temperature / voltage testing to simulate a real, complex environment. I / O Operation Modes: Typical scenarios should be covered, such as: random read / write (4K / 8K block size, simulating a database); continuous large file read / write (128MB block, simulating video storage); mixed read / write (70% read + 30% write, simulating general server load). I / O queue depth (e.g., QD1~QD32) needs to be controlled to comprehensively evaluate stability under different loads.

[0031] Step 4: Real-time Data Acquisition Focus: SMART Data: Pay attention to key metrics (such as remaining lifetime percentage, erase count, remapped sectors, CRC error count), which are core indicators of SSD health degradation. Real-time Power Consumption: Monitor power consumption fluctuations under different environments (such as whether power consumption drops sharply due to overheat protection at high temperatures), reflecting hardware stability. Link-level Bit Error Rate: Record bit errors using PCIe / NVMe link monitoring tools (such as PCIe Analyzer) to assess the signal integrity of the interface under vibration / temperature changes.

[0032] Step 5: Anomaly Detection and Health Scoring: Model Training: Historical normal data should cover the "health baseline" of the same model SSD under the same test conditions to ensure the model's adaptability to environmental variables. Algorithm Selection: Isolation Forest is suitable for quickly detecting outliers (such as sudden surges in remapped sectors); Autoencoders are better suited for capturing data trend anomalies (such as nonlinear changes in power consumption with increasing temperature).

[0033] Health score: Multiple indicators (SMART, power consumption, bit error rate) can be weighted and quantified (e.g., 0~100 points), thresholds can be set (e.g., a score below 60 points is considered abnormal), and the environmental conditions corresponding to the abnormal nodes can be noted in the report (e.g., "the bit error rate suddenly increased by 3 orders of magnitude at 85℃ and 15V voltage").

[0034] In extreme temperature / pressure testing, protection mechanisms must be implemented (such as automatic power-off when the SSD temperature exceeds 95°C) to prevent hardware damage. It is recommended to repeat the same test procedure at least three times to eliminate random errors and ensure the reliability of the results. Add a correlation chart between "environmental parameters and performance indicators" (such as a correlation curve between temperature and the number of remapped sectors) to the report for a more intuitive identification of weak points. This process completes the reliability certification and extreme environment adaptability testing of solid-state drives, making it particularly suitable for quality verification in high-requirement scenarios such as industrial and automotive applications.

[0035] Figure 2 yes Figure 1 The flowchart for step 1 is as follows: Figure 2As shown, Step 1 includes: Step 101, initializing the test environment and setting the test equipment parameters, including a temperature range of -40℃ to 125℃, a humidity range of 0% to 100%RH, a vibration frequency range of 10Hz to 200Hz, and a vibration amplitude range of 0.1g to 10g; Step 102, installing the solid-state drive under test and embedding temperature sensors in at least the controller, NAND chip, and DRAM of the solid-state drive; Step 103, initializing the data acquisition system, including setting the data acquisition frequency, data storage path, and anomaly detection model parameters; Step 104, calibrating all sensors and test equipment to ensure that the measurement accuracy of temperature, humidity, vibration, and electrical parameters meets the standards, and starting the subsequent test process after completing the initialization verification.

[0036] Step 101: In the test environment parameter settings, the temperature range (-40℃ to 125℃) covers extreme industrial environments (such as high-temperature server rooms and low-temperature outdoor equipment). However, it is important to note that the temperature change rate must be clearly defined (e.g., 5℃ / min or 10℃ / min) to avoid rapid temperature changes causing condensation inside the SSD or excessive material stress (especially when combined with humidity testing). 125℃ far exceeds the operating limit of most commercial SSDs (usually ≤70℃). Confirm the design level of the SSD under test in advance (e.g., military-grade may be supported) and set an over-temperature protection threshold (e.g., forced interruption at 130℃ to prevent hardware burnout). Humidity range (0% to 100% RH): High humidity (e.g., 80%~100% RH) requires temperature control to avoid condensation under low temperature and high humidity conditions (this can be controlled through "humidity hysteresis," such as increasing humidity only when the temperature is 5℃ above the dew point). Low humidity (e.g., 0%~20% RH) requires electrostatic discharge protection; the test equipment must be grounded to prevent electrostatic discharge from damaging the SSD chip. Vibration parameters (10Hz to 200Hz, 0.1g to 10g): 10Hz~200Hz covers common frequency bands of mechanical vibration (such as automotive and industrial machinery). The vibration direction (single-axis / tri-axis) needs to be clearly defined to simulate actual installation scenarios (such as the horizontal / vertical mounting method of the SSD in the device). A vibration amplitude of 10g is considered a medium-to-high intensity impact. It is necessary to ensure that the physical mounting method of the SSD (such as screw fastening, shock-absorbing pads) can withstand this stress to avoid poor contact due to loosening during testing.

[0037] Step 102: Sensor Implantation and Monitoring of the Target. Main Control Chip: Temperature directly reflects its workload and heat dissipation capacity. High temperatures may lead to decreased computing power and increased data processing latency, requiring close monitoring. NAND Chip: Temperature significantly affects the write / erase cycle (P / E cycle) and data retention of NAND (low temperatures may prolong charge retention time, while high temperatures shorten it). Real-time recording of temperature differences between each NAND die is necessary (especially for multi-die designs). DRAM (if present): As a cache, its temperature stability affects the reliability of temporary data storage. High temperatures may cause data errors (such as bit flips). Sensor Installation Recommendations: Use a surface-mount temperature sensor (such as PT1000), firmly attached to the chip surface with thermally conductive adhesive to reduce thermal resistance errors. Sensor leads must be fixed to prevent signal interference or chip pulling during vibration testing.

[0038] Step 103: Key configuration of the data acquisition system, acquisition frequency: needs to be dynamically adjusted according to the test scenario: Environmental parameters (temperature, humidity, vibration): 1~10Hz is sufficient for trend monitoring. SSD internal sensor (controller / NAND temperature): 10~100Hz is recommended to capture instantaneous temperature fluctuations (such as temperature spikes under sudden I / O load). Electrical parameters (voltage, current, power consumption): must be ≥1kHz to avoid missing transient pulses (such as poor power supply contact caused by vibration).

[0039] Data storage and synchronization: Timestamp synchronization (such as NTP or hardware synchronization pulses) is used to ensure that environmental parameters, sensor data, and SSD performance data (such as I / O latency) are aligned on the timeline, facilitating subsequent correlation analysis. Storage paths must be named hierarchically according to "test batch + environmental conditions + time" (e.g., . / TestBatch01 / Temp-40_Vib10Hz / 20251107_1000 / ) to avoid data corruption.

[0040] Anomaly detection model parameter initialization: A "normal threshold baseline" needs to be preset (e.g., based on historical data of the same model SSD), such as: controller temperature ≤ 95℃, NAND temperature ≤ 85℃, link bit error rate during vibration ≤ 1e-12. The model needs to support dynamic updates (e.g., if a new normal fluctuation range is found during testing, the threshold can be adjusted in real time).

[0041] Step 104: In the core standards for calibration and initialization verification, sensor calibration includes: Temperature sensor: Calibrate at three points using a constant temperature bath at -40℃, 25℃, and 125℃, with an error ≤ ±0.5℃. Humidity sensor: Calibrate using a standard humidity generator at 30%, 60%, and 90% RH, with an error ≤ ±3% RH.

[0042] Vibration sensors (such as accelerometers): calibrated at 50Hz, 100Hz, and 200Hz using a vibration table, with an amplitude error ≤ ±5%.

[0043] Test equipment calibration: Incubator: Verify the consistency between the set temperature and the actual temperature inside the chamber (measured using multiple sensors to avoid local temperature differences).

[0044] Voltage regulator: The output accuracy is tested within ±10% of the rated voltage, and the error is ≤ ±0.1V.

[0045] Initialization verification: Start the "no-load test" (no I / O operation) and run for 15 or 30 minutes to confirm that all sensor data are stable and there are no abnormal fluctuations, and that the test equipment responds normally (e.g., the temperature fluctuation is ≤ ±1℃ after reaching the set value).

[0046] Verify the integrity of the data acquisition system: check for issues such as data loss and incorrect timestamps to ensure the validity of subsequent test data.

[0047] Figure 3 yes Figure 1 The flowchart for step 2 is as follows: Figure 3 As shown, step 2 includes: step 201, performing a dynamic temperature change test, which includes two test modes: rapid temperature rise and fall, and slow temperature rise and fall; step 202, performing a dynamic voltage test, where the voltage fluctuates within ±15% of the nominal value, and the response latency and data write success rate of the solid-state drive under test are recorded simultaneously under different voltage conditions; step 203, combining temperature change and voltage disturbance to construct a composite stress scenario, where the temperature response and voltage fluctuation coupled data of the solid-state drive under test are collected in real time under the composite stress scenario, and the I / O performance fluctuation and error retransmission count are recorded simultaneously, and analyzed in real time through the data processing system.

[0048] Step 201: In the design of the two modes of dynamic temperature change test, 1. Rapid temperature rise and fall mode (simulating sudden environmental changes), the temperature rise rate is recommended to be 5~10℃ / min (e.g., from -40℃ to 125℃, the whole process takes about 16~33 minutes). Adjust according to the heat capacity of the SSD to ensure that the temperature change rate exceeds its own heat dissipation capacity and create thermal shock.

[0049] Cooling rate: Similarly, it can be set to -5~-10℃ / min (e.g., from 125℃ to -40℃) to avoid internal condensation due to excessive cooling (it needs to be combined with humidity control, such as cooling to above the dew point first and then continuing to cool).

[0050] Test objectives: To observe the hardware stability of the SSD under rapid temperature changes (e.g., whether solder joints detach due to thermal expansion and contraction, and whether interfaces have poor contact). To monitor the instantaneous performance fluctuations of NAND flash memory (e.g., whether there is a sudden increase in read / write error rate at high temperatures, and whether write latency spikes due to slower charge migration at low temperatures).

[0051] 2. Slow temperature rise / fall mode (simulating gradual environmental changes), rate: 0.5~2℃ / min (e.g., rising from 25℃ to 85℃ takes 30~120 minutes), more closely resembling the adjustment capabilities of natural environments or device cooling systems. Test objective: To evaluate the long-term thermal adaptability of the SSD (e.g., the sustained computing power of the controller and the stability of DRAM under continuous high temperatures). To capture the linear / non-linear relationship between temperature and performance (e.g., "random read / write latency increases by X% for every 10℃ increase in temperature"), providing data support for thermal design.

[0052] Both modes require setting the "number of cycles" (e.g., 3-5 cycles) to simulate the cumulative effect of repeated temperature changes. The SSD's heat dissipation efficiency is recorded simultaneously: using temperature sensor data from the controller / NAND, the "difference between ambient temperature and chip temperature" is calculated to evaluate the effectiveness of its heat dissipation design (e.g., heat sink, packaging materials).

[0053] Step 202: In the core monitoring points of dynamic voltage testing, voltage fluctuation mode: waveform design: in addition to step fluctuations (such as from 12V→10.2V→13.8V→12V, each voltage point is held for 5 minutes), sinusoidal fluctuations (frequency 0.1~1Hz, simulating low-frequency noise of the power grid) or random pulses (such as instantaneous drop to 80% of the nominal value, lasting for 10ms, simulating power supply interference).

[0054] Coverage: ±15% exceeds the voltage tolerance range of conventional commercial equipment (usually ±5%~±10%). It is suitable for industrial / automotive grade SSD testing. The undervoltage protection (UVLO) and overvoltage protection (OVLO) thresholds of the SSD need to be confirmed in advance to avoid triggering a hard shutdown during testing.

[0055] Key metrics to record: Response latency: Distinguish between "read latency", "write latency" and "command response latency" (such as the processing time of NVMe's Admin commands and I / O commands). Voltage fluctuations may cause unstable power supply to the main controller, which in turn prolongs the command parsing time.

[0056] Data write success rate: Verify the integrity of the written data through checksums (such as CRC32), and pay special attention to whether there are "false successes" under low voltage (the controller returns that the write is complete, but the NAND is not actually stored correctly) or NAND overprogramming under high voltage (causing data flipping).

[0057] Power consumption linkage: Records real-time current changes during voltage fluctuations and calculates power consumption (P=U). I) Evaluate the SSD's power consumption control logic during abnormal voltage conditions (such as whether it actively reduces frequency for protection).

[0058] Step 203: In the coupled test design of composite stress scenarios, the combination logic of composite stresses needs to be designed based on the actual application scenario using a "temperature-voltage" coupling mode. For example: High temperature + high voltage: Simulates equipment heat dissipation failure and power supply abnormality (such as power overload in a computer room during summer). Low temperature + low voltage: Simulates insufficient battery power supply in outdoor low temperature environments (such as vehicle equipment starting in winter). Dynamic temperature change + dynamic voltage: For example, while the temperature rises at 2℃ / min, the voltage fluctuates with a ±15% sine wave, which is closer to complex working conditions.

[0059] In the core data acquisition and analysis dimensions, coupled data on temperature response and voltage fluctuation are analyzed: the correlation between "voltage fluctuation amplitude" and "chip temperature change rate" is analyzed (e.g., whether increased power consumption of the main controller under high voltage leads to a sudden temperature rise). The risk of "thermal runaway" under extreme coupled conditions is recorded (e.g., whether high temperature + high voltage triggers the SSD's overheat protection, and whether the response time of the protection mechanism is within a safe range).

[0060] I / O Performance and Error Retransmission: Apply mixed I / O loads (e.g., 70% random reads + 30% sequential writes, QD=16) and monitor the fluctuations in throughput and latency (e.g., whether performance degradation exceeds 20% due to combined stress). Statistical analysis of error retransmissions at the link layer (e.g., PCIe) and protocol layer (e.g., NVMe): Link layer: Retransmissions due to CRC errors and data loss reflect the impact of the environment on signal integrity. Protocol layer: Retransmissions due to command timeouts and data verification failures reflect the stability of internal SSD data processing.

[0061] The data processing system needs to be configured with "abnormal warning thresholds" (such as more than 10 retransmissions within 5 minutes or a sudden increase in latency of 50%). When a warning is triggered, the system can automatically pause the test or adjust stress parameters (such as temporarily reducing temperature / voltage) to prevent hardware damage. A "stress-performance" correlation graph (such as a three-dimensional curve of temperature-voltage-latency) should be generated to pinpoint the SSD's "vulnerable zone" (such as the area with the greatest performance fluctuation at 60℃ +13.8V).

[0062] Stress application sequence: First, perform single stress tests (steps 201 and 202) to determine the basic tolerance range of the SSD, and then design boundary conditions for composite stress (such as avoiding the direct combination of extreme temperature and extreme voltage, which may lead to damage in the early stages of testing).

[0063] Data time alignment: In complex scenarios, parameters change rapidly, so it is necessary to ensure the timestamp accuracy (≤1ms) of temperature, voltage, I / O performance, and erroneous data; otherwise, it will be difficult to trace the root cause of the anomaly. Before testing, the performance baseline of the SSD under "normal temperature (25℃) + nominal voltage" should be recorded as a reference standard for performance degradation under complex stress.

[0064] Figure 4 yes Figure 1 The flowchart for step 3 is as follows: Figure 4 As shown, step 3 includes: step 301, querying the solid-state drive under test that has undergone dynamic temperature change testing within the same temperature range over a preset time range; step 302, adding simulated traffic or industrial vibrations to the test environment of the solid-state drive under test, with a vibration frequency of 10Hz to 50Hz and a vibration amplitude of 0.5g to 5g; step 303, performing specific types of I / O operation mode tests, including sequential read / write, random read / write (4KQD32), and mixed load operations on the solid-state drive under test.

[0065] Step 301: In the screening and baseline calibration of the SSDs under test, the precise definition of "same temperature range" requires clear understanding of the temperature control logic within the "preset time range": If it is a constant temperature test (e.g., at three fixed temperature points of -20℃, 25℃, and 70℃, each lasting 4 hours), it is necessary to ensure that the temperature fluctuation within the chamber does not exceed ±1℃ to prevent temperature drift from interfering with the comparison of test results. If it is a narrow range of dynamic temperature change (e.g., slowly fluctuating between 50℃ and 60℃, with a temperature change rate of 0.2℃ / min), the temperature change curve needs to be recorded in detail. This will help eliminate interference from small temperature changes when analyzing the impact of vibration on I / O performance later. Prioritize SSDs that show "no hardware failures and no abnormalities in SMART key indicators (such as the number of remapped sectors and the number of CRC errors)" as described in Step 201, to avoid distorted vibration test results due to hidden damage caused by previous temperature and voltage tests.

[0066] Within the target temperature range, conduct vibration-free I / O performance testing (test mode consistent with the I / O mode in step 303), and record benchmark data such as throughput, latency, and IOPS. For example, in a vibration-free environment at 25℃, the 4K QD32 random read IOPS is 100k and the latency is 0.3ms. These data will be used as the performance comparison benchmark for subsequent vibration tests.

[0067] Step 302: Matching vibration parameters with the actual scenario. For passenger vehicle (chassis) scenarios, the vibration frequency range is typically 10Hz~30Hz, the vibration amplitude (acceleration) is between 0.5g~2g, and the vibration direction must include both vertical and horizontal directions to simulate the vibration generated when a vehicle travels over speed bumps or bumpy roads. For industrial machinery (such as pumps and motors) scenarios, the vibration frequency is mostly between 20Hz~50Hz, the vibration amplitude is between 1g~3g, and the vibration direction covers both axial and radial directions to simulate the continuous mechanical vibration during equipment operation. For rail transit (carriage) scenarios, the vibration frequency is generally between 15Hz~40Hz, the vibration amplitude reaches 2g~5g, and the vibration direction includes both longitudinal and vertical directions to simulate the impact vibration generated when a train starts and brakes. It is recommended to use triaxial vibration (simultaneous vibration of the X-axis, Y-axis, and Z-axis), as this method is closer to the installation state of SSDs in actual devices. For example, an in-vehicle SSD may simultaneously withstand vertical road bumps and horizontal centrifugal forces from steering.

[0068] The installation method for SSDs in actual applications must be strictly replicated, such as using original screws and anti-vibration pads for fixing. This avoids excessive shaking due to loose fixing or deformation of the casing due to excessive fixing, which could compress the internal chips. The temperature chamber must be vibration-resistant, or a vibration table should be placed inside the temperature chamber to ensure that the temperature remains stable during vibration (e.g., the temperature fluctuation inside the temperature chamber during vibration does not exceed ±2℃), preventing the vibration from causing the temperature chamber's airflow to shift and leading to localized temperature anomalies. It is recommended to set the vibration duration in stages (e.g., 2 hours, 4 hours, 8 hours) and record the performance degradation trend of the SSD under different vibration durations. For example, after 4 hours of vibration, does the random read latency increase from 0.3ms to 0.5ms? This will help assess the cumulative impact of long-term vibration on the SSD.

[0069] Step 303: Test parameters and objectives for the three I / O modes must clearly define the specific configuration for each I / O mode to ensure repeatable and comparable tests: 1. Sequential read / write test: Block size can be selected as 128MB or 1GB, queue depth is set to 8 or 16, and read / write ratio is set to 100% read and 100% write respectively. Verify the impact of vibration on the stability of large file transfers, such as log file writing in industrial scenarios and video recording in vehicle scenarios. Focus on whether there are problems such as sudden drop in throughput or write interruption. Example: Using a 128MB block for sequential write test, the throughput is 500MB / s without vibration. If the throughput drops to 400MB / s with fluctuations exceeding 10% during vibration, it is necessary to analyze whether the vibration causes instability in NAND signal transmission.

[0070] Random read / write test (4K QD32): The block size is fixed at 4K, and the queue depth is set to 32 (to simulate a high-load scenario). The read / write ratio is 100% read and 100% write. The impact of vibration on the random access performance of small files is evaluated, such as in scenarios like application startup in automotive systems and real-time data queries in industrial equipment. The focus is on monitoring latency fluctuations and IOPS attenuation. The "maximum, minimum, and average latency" are recorded. For example, the average latency is 0.3ms without vibration, and rises to 0.5ms and reaches a maximum of 1ms during vibration. Simultaneously, attention is paid to whether "latency spikes" (i.e., instantaneous latency exceeding 10ms) occur.

[0071] In mixed load operations, the parameters are as follows: block size uses a mixed mode (including 4K, 64K, and 128MB); read / write ratio can be set to 70% read + 30% write or 50% read + 50% write; queue depth is dynamically adjusted (range 1~32). This simulates complex load conditions in real-world applications, such as an in-vehicle infotainment system simultaneously performing navigation map reading, music playback, and log writing, to evaluate the overall stability of the SSD under multi-task concurrency and vibration. Example: Using a mixed load mode of 70% 4K QD16 random read + 30% 64K QD8 sequential write, monitor for any task priority disruptions, such as high-priority navigation data read latency being increased due to vibration.

[0072] In addition to basic I / O performance metrics, the following data should be recorded simultaneously: Hardware status: Monitor potential physical damage caused by vibration using SMART data. For example, an increase in "interface error count" may indicate poor contact in the PCIe interface due to vibration; an increase in "NAND block error rate" may indicate data transmission errors caused by loose chip solder joints. Link stability: Use a PCIe protocol analyzer to record the link error rate and reconnection count during vibration. For example, if the PCIe link reconnects once per hour during vibration, the mechanical stability of the interface needs to be checked. Power consumption fluctuations: Vibration may cause poor contact in the SSD power supply pins, posing a risk of momentary power loss. Therefore, the current waveform needs to be recorded to observe whether there is a sudden drop in current to 0 or current fluctuations exceeding ±20%. Anomaly triggering mechanism: Set performance and hardware anomaly thresholds in advance, such as "4K random read latency exceeding twice the baseline," "SMART interface error count ≥ 5 times," and "link reconnection count ≥ 3 times / hour." When these thresholds are reached, the system automatically pauses the test to prevent further damage to the SSD, and records the vibration parameters (such as frequency and amplitude) at this time to locate the "vulnerable vibration range."

[0073] Under the same temperature, tests were conducted stepwise according to either the "vibration frequency gradient (10Hz→20Hz→30Hz→40Hz→50Hz)" or the "vibration amplitude gradient (0.5g→1g→2g→3g→5g)" to clarify the "quantitative relationship between frequency / amplitude and performance degradation." For example, for every 1g increase in vibration amplitude, the average 4K random read latency increased by 0.1ms. After the vibration test, if conditions permit, the SSD can be disassembled to inspect its internal condition, checking for solder joint detachment, loose NAND / DRAM chips, and bent interface pins. The hardware damage was correlated with the test data for analysis; for example, bent interface pins may be related to an increase in the number of link reconnections. "Vibration parameter - I / O performance" correlation charts were generated, such as "4K QD32 random read IOPS change curve with vibration amplitude at 25℃" and "Latency fluctuation comparison chart at different temperatures during 50Hz vibration," to more intuitively demonstrate the performance boundaries of the SSD in coupled scenarios.

[0074] Step 303 includes: Step 3031, performing Zone switching operation and data migration test on the ZNS SSD in the solid-state drive under test; Step 3032, performing cache consistency and memory semantic operation test on the CXL SSD in the solid-state drive under test; Step 3033, performing random write operation on all types of SSDs using the fio tool, and frequently triggering the TRIM command to simulate extreme usage scenarios for high write amplification load test.

[0075] Targeting the characteristics of ZNS SSDs, Zone state management operations were performed, including proactive reclamation of idle Zones and write blocking simulation of fully loaded Zones, to verify its garbage collection efficiency under high load. Simultaneously, cross-Zone data migration tests were conducted, recording changes in read / write latency and bandwidth usage during the migration process. Combined with temperature and voltage fluctuations, the ZNS SSDs were subjected to composite stress, and the stability of its Zone management algorithm under high temperature, high humidity, and vibration coupling environments was continuously monitored. The impact of controller temperature rise on garbage collection trigger frequency was recorded, and the trend of NAND write amplification under voltage fluctuations was analyzed. DRAM cache hit rate and end-to-end latency data were simultaneously collected to evaluate the SSD's response consistency under different load modes. All parameters were uploaded to a data analysis platform in real time for building a fault prediction model. Through multi-dimensional data correlation analysis, the nonlinear relationship between the temperature rise rate of the ZNS SSD controller and write amplification under the superposition of high temperature and voltage fluctuation is identified; combined with the influence of mechanical stress introduced by vibration, its coupling effect on the contact stability and signal integrity of NAND flash chips is evaluated; based on the I / O performance degradation curve under long-term continuous operation, the adaptability of the Zone management strategy in complex working conditions is verified; finally, a reliability assessment report covering the effects of multiple physical fields such as heat, electricity and vibration is generated, providing data support for the application of solid-state drives in extreme environments.

[0076] Specifically, step 3031: The core features of the ZNS SSD are zone-based sequential read / write and host-side data management. Under vibration conditions, it is crucial to verify the stability of zone operations and the reliability of data migration. Test logic needs to be designed based on prior vibration parameters (10Hz~50Hz, 0.5g~5g) and temperature conditions.

[0077] Zone switching operation test parameters and scenario adaptation: First, create different types of Zones (such as Sequential Write Required Zone and Sequential Read Required Zone) using a ZNS management tool (such as znsadm). It is recommended that the number of Zones cover 50% of the total number of Zones on the SSD (e.g., if the total number of Zones is 1024, then create 512 test Zones). Under target temperatures (e.g., 25℃, 70℃) and vibration conditions (e.g., 20Hz / 1g, 50Hz / 5g), repeatedly execute Zone Activate, Zone Close, and Zone Reset operations. Each loop contains 100 switching commands, and a total of 10 loops are run.

[0078] Query Zone metadata (such as Zone Used Size and Zone State) in real time using tools to confirm whether "command execution was successful but the status is abnormal" (e.g., Zone remains active after being closed) occurs during vibration, thus preventing data corruption in the Zone management module due to vibration. Record the processing time of Zone on / off commands and compare it with the baseline when there is no vibration (e.g., Zone Activate delay is 1ms when there is no vibration). If the delay exceeds 5ms or command timeout occurs during vibration (e.g., exceeding 100ms), it is necessary to investigate whether the NAND signal transmission or the main control processing logic is interfered with by vibration. After Zone activation, write fixed pattern data (e.g., all zeros, random numbers), close and reactivate, and then read the verification to confirm whether vibration has caused data loss or tampering within the Zone.

[0079] Simulate a host-side data hot / cold migration scenario: Write "hot data" (high-frequency updates, e.g., one write per second) to some zones (e.g., 200 zones), and write "cold data" (only one write) to another zone (e.g., 200 zones). Under vibration, trigger the host to initiate a data migration command (migrating cold data to a low-performance zone, while retaining hot data in a high-performance zone). Maintain stable vibration parameters (e.g., 30Hz / 2g) during the migration process, while simultaneously applying a low-intensity I / O load (e.g., 10% 4K random read) to simulate concurrent operations in real-world applications.

[0080] Calculate the migration completion rate (100% success required), and compare the migration time with that without vibration (e.g., migrating 200GB of data takes 10 minutes without vibration). If the migration time increases by more than 30% during vibration, it is necessary to analyze whether the vibration caused a decrease in NAND read / write performance or excessive controller resource usage. After the migration is complete, perform CRC checks on all data to confirm that there are no lost or corrupted blocks; at the same time, check whether the source zone has been correctly cleared (confirmed via the TRIM command) to avoid residual invalid data occupying zone space after the migration due to vibration.

[0081] Step 3032: CXL SSD Test Architecture and Parameter Settings: Set up a CXL host-SSD test environment (e.g., the CPU is connected to the CXL SSD via a CXL 3.0 interface). Map the SSD's DRAM cache (e.g., 16GB) to a memory area accessible to the host. Conduct tests under target temperature (e.g., 50℃) and vibration conditions (e.g., 40Hz / 3g). Simulate multi-threaded concurrent access: Start two host threads. Thread 1 continuously writes to a specific address range in the cache (e.g., 0x10000~0x20000) (100 times per second), while thread 2 simultaneously reads from the same address range (100 times per second). Run continuously for 1 hour.

[0082] Compare the data written by thread 1 with the data read by thread 2 to ensure that each read result is consistent with the latest write result, avoiding "dirty reads" (reading old data) or "phantom reads" (reading non-existent data). If inconsistencies occur, investigate whether the signal integrity of the CXL link under vibration or the cache synchronization mechanism has failed. Trigger the host to initiate a cache refresh command (writing cached data to NAND), record the refresh time, and compare it with the baseline when there is no vibration (e.g., refreshing 1GB cache takes 500ms when there is no vibration). If the time exceeds 1s or refresh fails during vibration, analyze whether the vibration affects the command transmission efficiency of the CXL.mem interface. Record link errors (such as CRC errors, data loss) during the test using a CXL protocol analyzer. If the error count exceeds 1e-12, investigate the physical connection of the interface (e.g., whether the CXL slot is loose due to vibration) or signal attenuation issues.

[0083] The simulation program performs memory semantic operations on the CXL SSD, including Load (reading data from the SSD cache into the CPU register), Store (writing CPU data to the SSD cache), and atomic operations (such as Compare-and-Swap, CAS, comparing and swapping data in the cache). These operations are executed cyclically under a vibration environment (e.g., 25Hz / 1g), with each cycle consisting of 1000 Loads, 1000 Stores, and 100 CASes, for a total of 100 cycles. Simultaneously, CXL link bandwidth pressure is applied (e.g., other CXL devices occupy 50% of the link bandwidth) to simulate a real-world scenario where multiple devices share the CXL bus.

[0084] Ensure all memory semantic operations are 100% successful, with no timeouts (e.g., CAS operation timeouts exceeding 10ms) or incorrect results (e.g., data not updated as expected after a CAS operation). If failures occur, investigate whether the controller's processing logic for memory semantic instructions is affected by vibration. Record the latency of each operation (e.g., Load latency, Store latency), and statistically analyze the latency fluctuation range (e.g., an average Load latency of 100ns with a fluctuation of ±5ns when there is no vibration). If the fluctuation exceeds ±20ns during vibration, analyze whether the CXL link's latency jitter under vibration exceeds the design tolerance range. After the test, check the SSD cache memory space mapping table to confirm there are no address conflicts or space leaks (e.g., a memory address cannot be accessed again after an operation), to prevent vibration from causing abnormalities in the memory management module.

[0085] Step 3033: Common Tests for All SSD Types. For all SSDs (including traditional NVMe, ZNS, and CXL SSDs), simulate extreme write scenarios and verify the effectiveness of SSD write amplification control and TRIM commands under vibration conditions. Test design should incorporate the characteristics of the fio tool and pre-designed vibration parameters.

[0086] Random write mode was used, with a block size of 4K (simulating small file writes, which can easily lead to high write amplification), a queue depth of QD=64 (high load scenario), a read / write ratio of 100% write, and a test file size of 80% of the SSD capacity (e.g., 800GB test file for a 1TB SSD) to ensure coverage of most NAND blocks. TRIM command was enabled for frequent triggering: using the `trim=1` parameter of `fio`, a TRIM operation was triggered once after every 1GB of data was written (or the `fstrim` command was executed every 10 seconds via a script) to simulate a scenario where the host frequently reclaims invalid data. Temperature conditions sensitive to write amplification were selected (e.g., 70℃, as high temperatures accelerate NAND wear and amplify the impact of write operations), vibration parameters were set to medium-high intensity (e.g., 30Hz / 3g), and a continuous test duration of 8 hours was recommended (sufficient to observe the cumulative effect of write amplification).

[0087] Calculate the WAF (WAF = Total Write Bytes / Host Write Bytes) using SMART data from the SSD (such as "Total Write Bytes" and "Host Write Bytes"). Compare this WAF to the baseline without vibration (e.g., WAF = 1.2 without vibration). If the WAF exceeds 1.5 during vibration, it's necessary to analyze whether vibration causes frequent GC (garbage collection) triggers or TRIM instruction execution delays, thus increasing invalid writes. For ZNS SSDs, additional attention needs to be paid to Zone-level write amplification: use Zone metadata to statistically analyze the actual write volume within the Zone and the host requested write volume to confirm whether vibration exacerbates data fragmentation within the Zone, pushing up the Zone-level WAF.

[0088] During testing, the SSD's "TRIM command execution count" and "TRIM reclamation bytes" were checked periodically to confirm that the TRIM commands were executed 100% successfully (without execution failure counts) and that the number of reclaimed bytes matched the number of TRIM request bytes sent by the host (error ≤ 5%), preventing vibration from causing TRIM commands to be lost or incompletely executed. After the test, the SSD's available capacity was checked using a tool (such as nvmelist-ns) to confirm that the reclaimed invalid space had been correctly released and there was no capacity leakage (e.g., the difference in available capacity before and after the test should be close to the host's write volume).

[0089] Real-time monitoring of fio write throughput and latency, recording performance degradation trends (e.g., if the initial throughput is 500MB / s, does it drop below 400MB / s after 8 hours?). If the degradation is too rapid, it is necessary to analyze whether vibration accelerates NAND wear or causes excessive GC pressure on the controller. Simultaneously check key SMART metrics (e.g., "remaining lifetime percentage", "erase count", "remapped sector count") to ensure that there is no significant lifespan reduction after the test (e.g., remaining lifespan decreases by no more than 1%) or hardware damage (e.g., no new remapped sectors). This verifies the hardware reliability of the SSD under extreme write and vibration conditions.

[0090] If testing resources are limited, the order can be adjusted according to the principle of "prioritizing core scenarios." For example, in automotive-grade scenarios, priority should be given to ensuring the stability of ZNS SSD's Zone operation; in cloud computing scenarios, priority should be given to verifying the cache consistency of CXL SSD; and in general consumer-grade scenarios, the focus should be on testing the fio+TRIM load. Correlate the specific test data with the I / O performance data from step 303. For example, is the cache consistency error of CXL SSD related to the number of link reconnections recorded in step 303? Is the increase in WAF of ZNS SSD related to the increased Zone data migration time in step 3032? This will help pinpoint the root cause of the problem. If an anomaly occurs in a certain step (such as ZNS SSD Zone switching failure), the test should be repeated 2-3 times under the same environmental parameters to rule out accidental factors. If the problem is successfully reproduced, the vibration intensity or temperature can be reduced to gradually locate the "abnormal trigger threshold" (such as Zone operation starting to fail when the vibration amplitude exceeds 4g).

[0091] Figure 5 yes Figure 1 The flowchart for step 4 is as follows: Figure 5 As shown, step 4 includes: Step 401: During the test, SMART information, real-time power consumption, and link-level bit error rate are recorded in real time through the data acquisition system; Step 402: After the test, a full disk scan is performed according to a custom command, and the bad block distribution map and write amplification rate change trend are obtained based on the full disk scan results, and the information of newly added bad blocks is recorded; Step 403: The CRC check value recorded during writing is compared to verify the data integrity.

[0092] Step 401: In the initial ZNS SSD Zone operation, CXL SSD cache test, and fio load test of all SSDs, it is necessary to realize the synchronous recording of multi-dimensional parameters through the data acquisition system, and to combine the monitoring logic adapted to different SSD characteristics and vibration environment: For all SSDs, core health indicators need to be collected at a frequency of 1 second / time, including "Remaining Life", "Total Erase Count", "Reallocated Sectors", "CRC Error Count", and "Host Write / Read Bytes". These indicators can directly reflect the impact of vibration on the lifespan of SSD hardware and data transmission (such as vibration causing poor interface contact, which will increase the CRC error count).

[0093] Additional data collection is performed on "Zone Operation Failures" and "Zone Migration Errors" every 0.5 seconds to capture anomalies during Zone switching and migration under vibration (e.g., a sudden increase in Zone operation failures during 50Hz / 5g vibration requires investigation of NAND signal issues by correlating vibration parameters). "CXL Link Errors" and "Cache Sync Failures" are also collected with a focus on increasing the collection frequency to 0.1 seconds per instance. This is because the CXL interface is more sensitive to vibration, and high-frequency collection avoids missing transient link errors (e.g., millisecond-level CRC errors under 40Hz / 3g vibration).

[0094] SMART data is stored in categories of "test phase + environmental parameters" (e.g., "ZNS_ZoneTest_25℃_30Hz / 2g_20251107.csv"). Threshold warnings are set (e.g., ≥10 new remapping sectors, ≥5 CXL link errors per minute). When triggered, the vibration and temperature parameters at the corresponding time point are automatically marked for easy traceability.

[0095] A high-precision power analyzer (such as Keysight N6705B) was connected in series in the SSD power supply circuit to measure voltage (accuracy ±0.001V) and current (accuracy ±0.001A) to calculate real-time power consumption (P=U×I). The sampling rate was set to 1kHz to capture instantaneous power consumption fluctuations under vibration (e.g., if vibration causes poor contact of the power supply pins, the current may drop sharply in milliseconds). The peak power consumption when ZNS SSD Zone is activated (e.g., the peak power consumption of activating 1 Zone is 1.2W when there is no vibration, and rises to 1.5W when there is vibration, which needs to be analyzed to see if the main controller occupies additional resources due to vibration) and the power consumption changes when CXL SSD cache is refreshed (e.g., the power consumption of refreshing 1GB cache is stable at 0.8W when there is no vibration, and fluctuates by ±0.3W when there is vibration, which may be due to link instability causing repeated cache synchronization). In the high write load test of fio, compare the power consumption difference between no vibration (e.g., average power consumption of 3.5W at 70℃ without vibration) and vibration (average power consumption of 4.2W at 70℃ + 30Hz / 3g). If the difference exceeds 20%, it is necessary to investigate whether the vibration causes a decrease in NAND read and write efficiency and frequent triggering of the controller GC, thereby increasing power consumption.

[0096] If a sudden increase (e.g., exceeding twice the rated power) or a sudden decrease (e.g., dropping to 0W) occurs, immediately pause the test and check if the SSD has experienced a hardware short circuit (e.g., solder joints falling off) or power failure due to vibration, to avoid further damage.

[0097] Traditional NVMe / ZNS SSDs (PCIe links) use PCIe protocol analyzers (such as the LeCroy Summit Z5) connected between the host and the SSD to monitor the "Bit Error Rate (BER)," "Symbol Errors," and "Link Retries" of the PCIe Gen3 / 4 / 5 link. The BER monitoring accuracy needs to reach 1e-15 to capture weak signal attenuation under vibration.

[0098] CXL SSD (CXL Link) uses a CXL protocol analyzer (such as Keysight U4301A) to additionally monitor "CXL.mem Command Errors" and "Cache AccessTimeouts". Because CXL Link supports memory semantic operations, bit errors may directly lead to data consistency issues and require close attention.

[0099] Record the bit error rate (BER) changes at different vibration frequencies and amplitudes (e.g., BER = 1e-14 at 10Hz / 0.5g vibration, rising to 1e-10 at 50Hz / 5g), plot the "vibration parameter - BER" ​​curve, and locate the SSD's "link stability threshold" (e.g., BER exceeds 1e-12 when the vibration amplitude exceeds 4g, exceeding the protocol's upper limit of 1e-12). Observe the automatic repair performance after a link error occurs under vibration (e.g., whether the PCIe link reconnection time is ≤100ms, whether the CXL link can automatically restore cache synchronization). If the repair time is too long (e.g., exceeding 1s) or cannot be repaired, it is necessary to analyze whether the interface mechanical structure (e.g., PCIe slot tightness, CXL connector contact pressure) is suitable for the vibration scenario.

[0100] Step 402: After the test is completed (such as after the ZNS Zone test, CXL cache test, and fio load test are completed respectively), a full disk scan should be performed using custom commands and tools to quantify the long-term impact of vibration on the SSD storage medium: For general SSDs, use the nvme command-line tool to perform a full disk read scan (e.g., vme read / dev / nvme0n1 --start-block=0 --block-count=200000000, covering all blocks of the 1TB SSD), and at the same time record the read status (normal / error / timeout) of each block using a custom script.

[0101] ZNS SSDs, combined with ZNS features, perform "scan by Zone" (e.g., znsadm scan-zone --zone-id=0-1023) to record the block status within each Zone individually. Due to ZNS's Zone-level management features, bad blocks may be concentrated in Zones with frequent operations (e.g., Zones that repeatedly migrate data under vibration).

[0102] In addition to a full disk block scan, the CXL SSD also performs an additional scan of the host-mapped cache area (e.g., cxl mem-scan --address=0x100000000-0x200000000) to check for data residue or corruption in the cache blocks, preventing vibrations from causing cache data to fail to synchronize with the NAND.

[0103] The scan block size is set to 4K (consistent with the fio test, covering small file write scenarios), and the timeout is set to 100ms / block. If a block read times out or returns an error, it is marked as a "suspected bad block" and subsequently confirmed by a second read (to avoid misjudgment caused by a single vibration interference). The scan results are imported into a visualization tool (such as Matplotlib) to generate a "bad block location - block type" distribution map, marking the logical block address (LBA) to which the bad block belongs, the corresponding physical block (PBA), and the block type (such as ZNS hot data zone / cold data zone, CXL cache block / NAND block). It is observed whether the bad blocks are concentrated in specific areas (such as the high bad block density in the fio test area where frequent writes under vibration).

[0104] Compare the initial number of bad blocks before the test (recorded after a full disk scan before the test), and count the number of newly added bad blocks (e.g., 0 bad blocks before the test, 5 new bad blocks after the test). Combine this with the environmental parameter logs during the test to analyze the reasons for the new bad blocks: If the newly added bad blocks are concentrated in the test phase with vibration amplitude ≥4g, it may be due to vibration causing the NAND chip solder joints to desolder or physical damage to the storage unit; if the newly added bad blocks are concentrated in the Zone migration area of ​​the ZNS SSD, it is necessary to correlate with the migration error data in step 3031 to check whether the data writing error was caused by vibration during the migration process, thereby triggering the bad block marking.

[0105] For newly added "repairable bad blocks" (such as those repaired through remapping), execute the nvme format or znsadmrepair-zone command to confirm whether the bad blocks have been successfully replaced after repair. At the same time, check whether the number of remapped sectors has been updated synchronously to verify the effectiveness of the SSD's bad block management mechanism after vibration.

[0106] Based on the "host write bytes" and "total write bytes" recorded in step 401, calculate WAF (WAF = total write bytes / host write bytes) according to the test phase (e.g., every 2 hours), and generate a "test time - WAF" curve:

[0107] Compare the trends of all SSDs under no vibration (e.g., WAF stable at 1.2) and vibration (e.g., WAF increases from 1.2 to 1.6 when vibrating at 30Hz / 3g). If WAF continues to rise during vibration, it is necessary to analyze whether the vibration causes a decrease in GC efficiency (e.g., increased NAND read / write latency, requiring GC to repeatedly move data).

[0108] ZNS SSDs require additional calculation of "Zone-level WAF" (total bytes written to a Zone / bytes written to the host in that Zone). If the WAF of a hot data Zone (e.g., 1.8) is much higher than that of a cold data Zone (e.g., 1.1), it indicates that vibration has exacerbated the fragmentation of the hot data Zone, and the Zone data migration strategy needs to be optimized.

[0109] If the WAF suddenly spikes during a certain period (e.g., from 1.3 to 1.8 within 10 minutes), tracing back the SMART data and environmental parameters at the corresponding time point, if it is found that the CRC error count increases and the vibration amplitude increases from 2g to 5g during the same period, it can be determined that the vibration caused the data transmission error, which in turn triggered repeated writes and pushed up the WAF.

[0110] Step 403: Verify the data writing, storage, and reading process under vibration environment by comparing CRC checksums. Writing Phase: In steps 3031 (ZNS data writing), 3032 (CXL cache writing), and 3033 (fio random writing), a custom script generates a CRC32 checksum before data writing (e.g., calculates the CRC value for each 4K data block), and stores "Data Block LBA + CRC Value + Write Time + Environmental Parameters" in an independent database (e.g., SQLite). Example record format: LBA: 0x12345, CRC: 0xabcdef12, WriteTime: 2025-11-07 10:00:00, Env: 25℃_30Hz / 2g. Reading Phase: During the full scan in step 402, the CRC32 value is recalculated for each read data block, and the corresponding CRC value for the LBA at the time of writing is retrieved from the database for real-time comparison.

[0111] Verification Result Classification: Consistent: This indicates that the data was not tampered with during the write-store-read process, and vibration did not affect the data block. Inconsistent: Marked as "Data Corruption," record the corresponding LBA, read time, and environmental parameters (e.g., LBA: 0x67890, CRC_Mismatch: Write=0x12345678, Read=0x87654321, Env: 70℃_50Hz / 5g). Further analysis of the cause of corruption is required: If the corrupted data blocks are concentrated in the CXL cache area, it may be due to vibration causing data transmission errors in the CXL link; if the corrupted data blocks belong to the ZNS Zone migration area, it is necessary to correlate the migration error data in step 3031 to investigate whether data loss was caused by vibration during migration. Verification Failure (No Write CRC Value): This may be due to a missing CRC record during writing or a database failure. The write and verification of the corresponding area must be re-executed to ensure no data blocks are missed during verification.

[0112] If the SSD capacity is large (e.g., 4TB), a full CRC check will take a long time. A combined "sampling + full" strategy can be adopted: first, sample and verify 10% of the random LBAs. If the sampling pass rate is ≥99.9%, then perform a full check on the remaining LBAs. If the sampling pass rate is <99.9%, stop sampling immediately and perform a full check on all LBAs to avoid missing or corrupting data blocks.

[0113] For industrial / automotive grade SSDs that require long-term service, after the test, the SSD can be placed in a "normal temperature (25℃) + low vibration (10Hz / 0.5g)" environment for 72 hours, and then a full disk CRC check can be performed to verify whether potential data damage caused by vibration (such as NAND storage cell charge leakage) will appear after the resting period, ensuring the integrity of long-term data storage.

[0114] By correlating the real-time power consumption and link bit error rate from step 401 with the bad blocks and WAF data from step 402, a chain reaction of "sudden increase in power consumption → increase in link bit error rate → new bad blocks" can be observed, indicating that vibration caused unstable power supply, which in turn led to link errors and hardware damage. Integrating SMART acquisition, power consumption measurement, and CRC verification functions, an automated testing platform (e.g., based on Python + LabVIEW) can be developed to automate the entire process of "data acquisition - analysis - report generation," reducing human error (e.g., manual recording of CRC values ​​is prone to errors). After testing, a comprehensive report is generated, including "real-time monitoring curves (SMART / power consumption / bit error rate)," "bad block distribution map," "WAF trend map," and "CRC verification result statistics table," highlighting key anomalies (e.g., "CXL link bit error rate exceeds the standard during 50Hz / 5g vibration, causing CRC verification failures for 2 data blocks"), providing clear direction for SSD hardware optimization (e.g., strengthening interfaces, optimizing cache synchronization).

[0115] By analyzing the full-disk scan results and bad block growth rate, the durability performance of NAND flash memory under high write loads is evaluated; the performance degradation curve under frequent TRIM triggering scenarios is used to verify the SSD controller's ability to suppress write amplification; the error rate is statistically analyzed by comparing CRC checksums to confirm the reliability of the end-to-end data path; the collected power consumption, temperature, and bit error rate data are correlated and analyzed to identify the correlation between abnormal fluctuations and hardware aging; finally, the data from all testing phases are integrated to form a complete SSD reliability verification report. The SSD reliability verification report covers the stability performance of ZNS SSD under frequent zone switching and data migration, verifies the correctness of the cache consistency mechanism of CXL SSD in memory semantic operations, confirms the effective suppression of performance degradation by the controller of various SSDs under high write amplification loads; through comparison of multiple rounds of test data, a correlation model between bad block growth rate and write amplification rate is quantified, and an abnormal warning threshold based on temperature, power consumption, and bit error rate fluctuations is established.

[0116] Figure 6 yes Figure 1 The flowchart for step 5 is as follows: Figure 6As shown, step 5 includes: Step 501, establishing an anomaly detection model, training the anomaly detection model based on historical normal SSD data according to the isolated forest or autoencoder algorithm; Step 502, comparing the real-time recorded SMART data with the anomaly detection model, and calculating the health status score of the SSD under test based on the comparison results; Step 503, if the health status score is lower than the preset threshold, the SSD under test is marked as faulty, and fault prediction and root cause analysis are performed; Step 504, generating a health test report from the analysis results, including fault prediction results, data integrity verification results, and performance consistency evaluation results.

[0117] Step 501: Based on the dynamic nature of SSD data under vibration (e.g., SMART metrics fluctuate with vibration parameters) and type differences (ZNS / CXL SSD characteristic metrics differ), historical normal data must cover both "no-vibration baseline scenarios" and "normal scenarios under different vibration intensities" to ensure the model adapts to reasonable fluctuations caused by vibration. The basic dimensions include all common SMART metrics from Step 401 (remaining lifetime, erase count, number of remapped sectors, etc.), real-time power consumption (average power consumption, peak power consumption), and link bit error rate (BER, number of link reconnections). Each metric must correspond to an environmental parameter label (temperature / vibration frequency / amplitude) to facilitate subsequent association of vibration scenarios and metric changes. For ZNS SSDs, the characteristic dimensions are supplemented with "Zone operation success rate, Zone-level WAF" to avoid the model being insensitive to ZNS-specific anomalies (e.g., Zone switching failures) due to missing Zone management-related metrics; for CXL SSDs, "CXL link error count, cache synchronization success rate" are supplemented to ensure the capture of abnormal CXL interface performance under vibration (e.g., cache synchronization latency). For each SSD type (traditional NVMe / ZNS / CXL), at least 100 devices of the same model must be collected, covering 5 vibration intensities (10Hz / 0.5g~50Hz / 5g), accumulating 1000 hours of normal operation data. This ensures the diversity of vibration scenarios covered by the sample and avoids model "bias" towards a particular vibration intensity. It is suitable for detecting "abrupt anomalies" of SMART metrics (such as vibration causing 10 new remapped sectors in 1 hour, or a sudden increase in the number of CXL link errors). Because it does not require assumptions about data distribution, its efficiency in capturing sparse anomalies is higher than that of traditional clustering algorithms. For example, if an SSD experiences a sudden increase in the number of remapped sectors from 0 to 8 under 40Hz / 4g vibration, the isolated forest can quickly identify this "jump" as an anomaly.

[0118] Autoencoders are suitable for detecting "gradual anomalies" (such as a slow increase in WAF under vibration and a gradual increase in power consumption fluctuation). They learn the characteristic distribution of normal data through neural networks. Abnormal data cannot be effectively reconstructed, resulting in a high reconstruction error. For example, under 30Hz / 2g vibration, the WAF of an SSD increases from 1.2 to 1.8 month by month. The autoencoder can identify this abnormal trend by the continuous increase in reconstruction error.

[0119] Network structure design: Input layer dimension = number of filtered features (e.g., 12 dimensions) to ensure coverage of all key health indicators; Hidden layers adopt a "dimensionality reduction-dimensionality increase" structure (e.g., 12→6→3→6→12), with the middle 3 dimensions being a feature compression layer to learn the core patterns of the data—for example, the compression layer can extract the correlation pattern of "vibration amplitude-power consumption-bit error rate"; Activation functions are ReLU (hidden layer) and Sigmoid (output layer). ReLU can effectively alleviate the gradient vanishing problem, and Sigmoid ensures that the output value is in the [0,1] interval, matching the standardized features; The loss function uses mean squared error (MSE) to quantify the difference between the reconstructed value and the true value; The optimizer uses Adam (learning rate 0.001) to balance convergence speed and stability; During training, the model is grouped according to SSD type (e.g., ZNS SSDs are trained separately) to avoid the differences in characteristic indicators of different types of SSDs interfering with model learning—for example, the success rate of Zone operation in ZNS and the success rate of cache synchronization in CXL are not directly related, and training them together will reduce model accuracy.

[0120] The model fusion adopts a "parallel detection + weighted voting" mechanism. The isolation forest outputs the "anomaly probability" (0~1, the closer to 1, the higher the anomaly risk), and the autoencoder outputs the "reconstruction error rate" (0~1, the higher the error rate, the more obvious the anomaly). The comprehensive anomaly score is calculated with a weight of 6:4 (comprehensive score = 0.6 × anomaly probability + 0.4 × error rate). A score ≥0.7 is judged as an anomaly. This weight allocation highlights the advantages of the isolation forest in detecting sudden anomalies, while also taking into account the autoencoder's ability to capture trend anomalies, reducing the misjudgment of a single model.

[0121] A 30% subset of historical data is used as a validation set, containing both known normal data and artificially injected anomalous data (such as newly added bad blocks due to simulated vibration or CRC errors). This validates the model's accuracy (false positive rate for normal data ≤ 5%) and recall (false negative rate for anomalous data ≤ 3%). For example, injecting anomalous data such as "3 new bad blocks added under 50Hz / 5g vibration" indicates a successful recall if the model identifies it 100% of the time. A false positive rate of ≤ 5% for normal data indicates a successful accuracy. For every 50 newly added devices with normal operating data, the model parameters are retrained, especially supplementing with normal data from extreme vibration scenarios (such as 50Hz / 5g) to prevent misjudgments of new scenarios. For instance, initially, the model may not have encountered 50Hz / 5g data and might classify normal power fluctuations (such as 20% higher than normal temperature) as anomalous; supplementing with new data corrects this bias.

[0122] Step 502: Health Status Score Calculation. Combining anomaly detection scores with core SSD health indicators, an interpretable and comparable scoring system is designed. The first dimension is the "anomaly detection score," with a weight of 40%, which includes the probability of anomalies in the isolated forest and the autoencoder reconstruction error rate, comprehensively reflecting the degree to which data deviates from the normal distribution. In high-vibration scenarios, if the comprehensive score of this dimension is ≥0.5, even if other indicators are normal, it should be closely monitored, as this may indicate potential hidden anomalies (such as decreased link stability). The second dimension is the "hardware health status," with a weight of 30%, which includes the percentage of remaining lifetime, the number of remapped sectors, and the number of newly added bad blocks. If the remaining lifetime is <80% or the number of newly added bad blocks is ≥5, the score for this dimension is directly deducted by 30%. If the new remapped sectors are caused by vibration (e.g., new sectors appear when the vibration amplitude is ≥4g), the weight of this indicator within the dimension is increased by an additional 5%, thus highlighting the direct damage of vibration to the hardware. The third dimension is "Data Integrity," with a weight of 20%, including CRC checksum consistency rate and the number of corrupted blocks. If the CRC checksum consistency rate is less than 99.99%, 1 point is deducted for every 0.01% decrease (e.g., 2 points are deducted for a consistency rate of 99.97%). If the number of corrupted blocks is greater than or equal to 2 under vibration conditions (e.g., vibration frequency ≥ 30Hz), 10 points are deducted directly from this dimension, emphasizing the impact of vibration on data storage reliability. The fourth dimension is "Link and Power Consumption Stability," with a weight of 10%, including link error rate and power consumption fluctuation. If the link error rate (BER) is greater than 1e-12, or the power consumption fluctuation is greater than ±20%, 50% of the score is deducted from this dimension. For CXL SSDs, if the number of CXL link errors is greater than or equal to 3 times per hour, an additional 3 points are deducted from this dimension, because the CXL interface is more sensitive to vibration, and link anomalies directly affect memory semantic operations. At the same time, a weight adjustment mechanism is set up to dynamically adjust according to the application scenario: for example, in automotive-grade scenarios (high vibration risk, link stability directly affects driving safety), the weight of "link and power consumption stability" is increased to 20%; in industrial scenarios (data reliability is prioritized, such as log storage in industrial control), the weight of "data integrity" is increased to 30%.

[0123] Single-dimensional score calculation: Anomaly detection score dimension: First, calculate the base score using "Overall Score = 0.6 × Anomaly Probability + 0.4 × Error Rate", then calculate the final dimension score using "Dimension Score = 40 - 40 × Overall Score"—for example, if the overall score is 0.2, the dimension score = 40 - 40 × 0.2 = 32 points; if the overall score is 0.8 (high anomaly risk), the dimension score = 40 - 40 × 0.8 = 8 points. Hardware health status dimension: Calculated in three parts and then summed (minimum 0 points)—Remaining lifetime score = 15 × (Remaining lifetime % / 100) (e.g., 90% remaining lifetime, 13.5 points); Remapping sector score = 10 - (Number of newly remapping sectors × 1) (e.g., 2 newly added, 8 points); New bad block score = 5 - (Number of newly added bad blocks × 1) (e.g., 1 newly added, 4 points); The sum of the three parts (13.5 + 8 + 4 = 25.5 points) is the score for this dimension. Data integrity dimension: Calculated into two parts and summed (minimum 0 points) - CRC consistency rate score = 15 × (CRC consistency rate) (e.g., 99.98% consistency rate, 14.997 points); corrupt block score = 5 - (number of corrupt blocks × 2.5) (e.g., 1 corrupt block, 2.5 points); the sum of the two (14.997 + 2.5 ≈ 17.5 points) is the score for this dimension. Link and power consumption stability dimension: Calculated separately for two items and then summed (minimum 0 points) – BER score = 5 × (1 - BER / 1e-12). If BER ≤ 1e-12 (normal range), 5 points are awarded; if BER = 2e-12, 5 × (1 - 2e-12 / 1e-12) = 0 points. Power consumption fluctuation score = 5 × (1 - fluctuation amplitude / 20%). If fluctuation amplitude ≤ 20%, 5 points are awarded; if fluctuation amplitude = 30%, 5 × (1 - 30% / 20%) = -2.5 points (counted as 0 points). The sum of the two items (e.g., BER 5 points, power consumption fluctuation 3 points, total 8 points) is the score for this dimension. Total score calculation: The scores for the four dimensions are added together to obtain the final health status score – for example, anomaly detection 32 points + hardware health 25.5 points + data integrity 17.5 points + link power consumption 8 points = 83 points, indicating a good overall health status.

[0124] For scoring calibration and benchmark comparison, first calculate the average health score of the same model of SSD under the same vibration / temperature conditions—for example, under a vibration scenario of 25℃ / 30Hz / 2g, the average score of 100 SSDs of the same model is 85 points. If the SSD under test scores 73 points under this scenario (12 points lower than the average), even if it does not reach the preset threshold (such as 60 points), it should be marked as "potential risk" because its performance is significantly lower than the normal level of the same batch of devices. Compare the score change of the SSD under test before and after the test—for example, the score is 90 points before the test (without vibration benchmark), and the score is 75 points after 200 hours of 30Hz / 2g vibration test, a decrease of 15%. At this time, it is necessary to analyze the reason for the decrease. If it is mainly from the "hardware health status" dimension (such as the addition of 2 bad blocks), it is determined to be cumulative damage caused by vibration, and further assessment of long-term use risks is required.

[0125] Step 503: When the health score is lower than the preset threshold (e.g., 60 points for industrial-grade SSDs, 50 points for consumer-grade SSDs), it is necessary to combine the previous test data to locate the fault type and root cause, and classify the fault type (adapted to vibration coupling scenarios): Hardware damage: Characteristics: A sudden increase in the number of remapped sectors in a short period of time (e.g., ≥5 new sectors added within 1 hour), newly added bad blocks concentrated in a specific physical area (e.g., the LBA range corresponding to a certain NAND chip), a sudden drop in real-time power consumption (e.g., from 3W to below 0.5W), and these anomalies often occur in high vibration scenarios (vibration amplitude ≥4g, frequency ≥40Hz) - for example, in a 50Hz / 5g vibration test, the number of remapped sectors of a certain SSD increased from 0 to 8 within 10 minutes, while the power consumption dropped to 0.3W, which is consistent with the characteristics of hardware damage. Possible causes: Vibration causes the NAND chip solder joints to desolder (unable to supply power or transmit data normally), interface pins to bend (e.g., poor contact in the PCIe slot), physical damage to the NAND storage cell (vibration aggravates charge leakage, causing data to be unable to be retained).

[0126] Link Anomaly Category: Characteristics: Link Bit Error Rate (BER) consistently > 1e-12, CXL link error count ≥ 5 times / minute, PCIe link reconnection count ≥ 3 times / hour, and the anomaly is strongly correlated with vibration frequency—for example, the link reconnection count reaches 5 times / hour during 50Hz vibration, but only 1 time / hour during 30Hz vibration, indicating that the vibration frequency is close to the link resonant frequency, leading to signal instability. Possible Causes: Vibration causes poor contact of the PCIe / CXL interface (e.g., insufficient connector insertion / extraction force, resulting in brief disconnection during vibration), loose signal transmission lines (e.g., micro-cracks in traces on the PCB due to vibration), and the interface mechanical structure is not adapted to the vibration scenario (e.g., the slot is not reinforced, causing displacement during vibration).

[0127] Data consistency issues: Characteristics: CRC inconsistency rate > 0.01%, CXL cache synchronization failures ≥ 2 times / hour, ZNS Zone data migration errors (e.g., some data blocks fail verification after migration). These anomalies often occur in scenarios with combined "high vibration + high load"—for example, under 40Hz / 3g vibration, simultaneously running a mixed load of 70% random reads + 30% random writes, the CRC inconsistency rate rises to 0.03%. Possible causes: Vibration causes bit flipping during data transmission (e.g., signal interference changes 0 to 1), CXL cache data is not synchronized to NAND in time (vibration causes delay in cache synchronization instruction execution, and the host obtains old data when reading), ZNS Zone operation is interrupted (vibration causes the Zone Close instruction to not complete, resulting in incorrect data writing).

[0128] Performance degradation category: Characteristics: Write amplification factor (WAF) increases by >50% (e.g., from 1.2 to 1.8), random read / write latency increases by >30% (e.g., from 0.3ms to 0.4ms), throughput decreases by >20% (e.g., from 500MB / s to 400MB / s), and the degree of degradation intensifies with the duration of vibration—for example, WAF is 1.4 after 100 hours of vibration testing, rising to 1.7 after 200 hours, illustrating the cumulative impact of vibration on performance. Possible causes: Vibration leads to decreased garbage collection (GC) efficiency (increased NAND read / write latency, GC needs more time to move data), abnormal occupation of controller resources (e.g., frequent handling of link errors, insufficient computing power to schedule I / O), and accelerated NAND wear (vibration accelerates storage cell aging, resulting in slower read / write speeds).

[0129] Root cause analysis data correlation analysis: A correlation diagram of "abnormal indicators - environmental parameters" is drawn, overlaying abnormal indicators (such as the increase in remapping sectors) with corresponding vibration frequency, amplitude, temperature, and other parameters. For example, it is found that "the number of remapping sectors increases" only occurs when the vibration amplitude is ≥4g, and the increase doubles when the temperature is ≥70℃, thus identifying "high vibration + high temperature synergistically causing hardware damage" as the root cause. Comparing the time-series data from steps 401-403, the abnormal chain is traced along the time axis. For example, within a certain time period, the time series of "increased link error rate → CRC check failure → increased number of corrupted data blocks" completely overlaps, and the corresponding vibration parameter increases from 30Hz / 2g to 40Hz / 3g, indicating that the root cause is "vibration exacerbates link abnormalities, leading to data transmission errors."

[0130] Hardware disassembly verification: The faulty SSD is disassembled non-destructively, and the interface (PCIe / CXL slot), NAND chip solder joints, and DRAM chip fixation are observed using a microscope. If cracks are found on the NAND chip pin solder joints or obvious bending marks are found on the PCIe interface pins, it can be directly confirmed that "vibration caused physical damage to hardware" is the root cause. If no obvious physical damage is found after disassembly, further investigation of link or software level issues is required based on the data.

[0131] Simulated reproduction test: Repeat the test on a normal SSD of the same model under the same vibration parameters (such as frequency, amplitude, duration). If the same fault is reproduced (such as excessive link bit error rate, new remapped sectors), individual differences can be ruled out, and the root cause can be confirmed as "vibration parameters exceeding the SSD's design tolerance range". If the fault is not reproduced, the previous usage records of the faulty SSD need to be checked (such as whether it has experienced drops, high temperatures, or other damage) to avoid misjudging vibration as the only root cause.

[0132] Risk Level Classification: High Risk: For hardware damage-related failures (e.g., ≥10 new bad blocks, ≥8 new remapped sectors per month), serious problems such as disk failure and data loss are predicted to occur in the short term (within 1 month). It is recommended to immediately stop using the SSD and replace it. For example, if an SSD develops 12 new bad blocks after a vibration test, and the number of bad blocks is still slowly increasing, it is considered high risk. Medium Risk: For link anomaly-related failures (e.g., BER=1e-11, ≥2 link reconnection times / hour), intermittent read / write errors are predicted to occur (e.g., occasional inability to recognize the SSD, file read lag). It is recommended to optimize the interface fixing method (e.g., add anti-vibration pads, replace with a reinforced slot) and shorten the health monitoring cycle (e.g., change from weekly monitoring to daily monitoring). Low Risk: For performance degradation-related faults (such as a 30% increase in WAF and a 15% decrease in throughput), it is predicted that long-term use will shorten the SSD's lifespan (e.g., the original expected lifespan of 5 years may be shortened to 3 years), but there is no risk of data loss in the short term. It is recommended to reduce vibration intensity (e.g., from 40Hz / 3g to 30Hz / 2g) or reduce high-load operations (e.g., avoid write loads above 70%) to mitigate the rate of performance degradation. A "abnormal indicator-failure time" correlation model is established based on historical fault data, and quantitative relationships are derived through statistical analysis—for example, "5 new remapped sectors per month → remaining lifespan less than 50% after 3 months" and "link error rate = 1e-11 → first read / write error within 2 months"—and short-term risk predictions are based on this.

[0133] Step 504: Health Test Report Generation transforms test data, anomaly detection results, and fault analysis into intuitive content to meet the needs of different audiences (test engineers, product managers, and customers): Data integrity verification results clearly state the CRC checksum consistency rate (e.g., 99.98%), the number of corrupted data blocks (e.g., 2), and describe the vibration scenarios corresponding to the corrupted blocks (e.g., 1 occurred under 40Hz / 3g vibration, and 1 occurred under 50Hz / 5g vibration); it also describes the distribution characteristics of the corrupted blocks (e.g., whether they are concentrated on a single NAND chip or scattered across different physical areas). A table compares the number of corrupted blocks before and after testing (e.g., 0 before testing, 2 after testing), and a line graph shows the "CRC consistency rate as a function of vibration intensity" (horizontal axis: vibration amplitude 0.5g~5g, vertical axis: consistency rate 99.95%~100%), intuitively demonstrating the impact of vibration on data integrity.

[0134] The performance consistency assessment results record specific values ​​for throughput, latency, and WAF under different vibration scenarios. For example, under 30Hz / 2g vibration, the sequential write throughput is 500MB / s, the 4K QD32 random read latency is 0.3ms, and the WAF is 1.2; under 50Hz / 5g vibration, the sequential write throughput drops to 420MB / s, the random read latency increases to 0.45ms, and the WAF increases to 1.6. Simultaneously, the deviation rate from the non-vibration baseline (e.g., sequential write throughput of 550MB / s) is calculated (e.g., deviation rate of -23.6% at 50Hz / 5g). A line graph shows the relationship between "vibration frequency and throughput" (horizontal axis 10Hz~50Hz, vertical axis 400MB / s~550MB / s), and a radar chart compares the "performance dimension scores under different scenarios" (dimensions include throughput, latency, and WAF, with a maximum score of 10 points; 10 points for no vibration, 6 points for 50Hz / 5g), clearly showing the degree of performance degradation.

[0135] The anomaly detection and health score section describes the overall score of the anomaly detection model (e.g., 0.35, below the anomaly threshold of 0.7), listing the detailed scores for each dimension (e.g., anomaly detection 32 points, hardware health 28 points, data integrity 16 points, link power consumption 6 points), for a total score of 82 points. It also compares the score with the average score of the same model SSD in the same scenario (e.g., 85 points), illustrating the relative performance of the SSD under test (e.g., slightly below average, no obvious anomalies). A radar chart displays the score distribution across the four dimensions, and a line graph shows the "health score change over test time" (horizontal axis 0~200 hours, vertical axis 75~90 points), with anomaly trigger points marked on the curve (e.g., at 150 hours of testing, the score dropped from 85 to 80 points due to 40Hz / 3g vibration), facilitating the tracking of anomaly events.

[0136] Fault prediction and root cause analysis clearly define the fault risk level (e.g., low risk), predict the fault type (e.g., performance degradation), and provide root cause conclusions (e.g., 50Hz / 5g vibration leads to decreased GC efficiency, a 25% increase in WAF, and consequently, throughput degradation). Simultaneously, targeted optimization suggestions are proposed (e.g., reducing vibration amplitude to ≤3g, or optimizing the GC algorithm through firmware upgrades to reduce the impact of vibration on GC). A cause-and-effect diagram (fishbone diagram) is used to illustrate the logical chain of "vibration parameters → link latency → GC efficiency → increased WAF → decreased throughput," and a table is used to list "risk level - countermeasures - expected results" (e.g., low risk - optimized GC algorithm - WAF drops to 1.4 under 50Hz / 5g vibration, throughput increases to 460MB / s), allowing readers to clearly understand the risk response plan.

[0137] Based on the first embodiment, a second embodiment is proposed. In the second embodiment, step 1, test environment initialization, involves setting the test equipment parameters, including a temperature range of -40℃ to 125℃, a humidity range of 0% to 100%RH, a vibration frequency range of 10Hz to 200Hz, and a vibration amplitude range of 0.1g to 10g; installing the SSD DUT and embedding platinum resistance temperature sensors in key locations such as the SSD's controller chip, NAND flash memory chip, and dynamic random access memory (DRAM); and initializing the data acquisition system, including setting the data acquisition frequency to 1kHz, the data storage path to the local hard drive, and the anomaly detection model parameters to have 128 hidden layer nodes and 1000 iterations.

[0138] Step 2, the multi-stress coupling test phase, involves performing dynamic temperature change tests, including rapid and slow temperature rises and falls, with rates ranging from 0.5℃ / s to 5℃ / s. For example, the temperature is first raised from -40℃ to 85℃ at a rate of 5℃ / s, then maintained at 85℃ at a rate of 2℃ / s, then lowered to -20℃ at a rate of -5℃ / s, and finally maintained at -20℃ at a rate of 2℃ / s. During the temperature changes, a supply voltage fluctuation of ±5% to ±15% is applied simultaneously. For example, when the temperature rises to 70℃, the supply voltage fluctuation is ±10%. Real-time current and voltage data are recorded during the temperature changes and analyzed in real-time using a data processing system. The data processing system is programmed in Python and uses the `step` function from the matplotlib library to plot real-time curves.

[0139] Step 3, Steady-State Maintenance and Comprehensive Stress Loading Phase: Maintaining temperatures at high (65℃) and low (-15℃) for 15 minutes each; applying vibrations simulating a traffic environment at a frequency of 20Hz and an amplitude of 1g; performing specific types of I / O operation mode tests, including: for ZNS SSDs, performing Zone switching operations and data migration tests; performing 1 million random Zone switching operations at -10℃, with each Zone being 1GB in size; for CXL SSDs, performing cache consistency and memory semantic operation tests; performing 1 million read / write operations at 0℃, with each operation being 4KB in size; performing high write amplification load tests for all types of SSDs; and performing random writes using the fio tool at 25℃, with a write size of 4MB, continuously running for 30 minutes.

[0140] Step 4, Data Integrity Verification Phase: During the test, SMART information, real-time power consumption, link-level bit error rate, and other parameters are recorded in real time using a data acquisition system. The pySMART library (programmed in Python) is used to read SMART information, the RTL2832U chip is used to collect real-time power consumption, and an ophthalmic instrument link analyzer is used to collect the link-level bit error rate. After the test, a full scan is performed using a custom command provided by the manufacturer to record newly added bad block information. For example, for QLC NAND flash memory, the command "SMARTLOG -a -d 1" is used for scanning; the CRC checksum recorded during writing is compared to verify data integrity. The crc32 library (programmed in Python) is used to calculate the CRC32 checksum and compare it with the checksum saved during writing.

[0141] Step 5, Intelligent Diagnosis and Data Analysis Stage: An anomaly detection model is established using the Isolation Forest algorithm, trained based on historical normal SSD data. The Isolation Forest algorithm is implemented using the scikit-learn library in Python; the current SSD health status score is calculated in real time. The pandas library in Python is used to process the data, calculating the weights and scores of various indicators; if the health status score is below 0.8, fault prediction and root cause analysis are performed. The matplotlib library in Python is used to plot the health status change curve; a test report is generated, including fault prediction results, data integrity verification results, and performance consistency evaluation results. The ReportLab library in Python is used to generate a PDF test report.

[0142] Based on the first embodiment, a third embodiment is proposed. In the third embodiment, step 1, test environment initialization, involves setting test equipment parameters, including a temperature range of -45℃ to 130℃, a humidity range of 5% to 95%RH, a vibration frequency range of 15Hz to 180Hz, and a vibration amplitude range of 0.2g to 8g; installing the SSD DUT and embedding NTC thermistors in key locations such as the SSD's controller chip, NAND flash memory chip, and dynamic random access memory (DRAM); and initializing the data acquisition system, including setting the data acquisition frequency to 2kHz, the data storage path to a network storage device, and the anomaly detection model parameters to have 256 hidden layer nodes and 2000 iterations.

[0143] Step 2, Multi-stress Coupling Test Stage: Perform dynamic temperature change testing, including rapid and slow temperature rises and falls, with rates ranging from 0.2℃ / s to 4℃ / s. For example, first, raise the temperature from -45℃ to 90℃ at a rate of 2℃ / s, then maintain it at 90℃ at a rate of 1℃ / s, then lower it to -25℃ at a rate of -2℃ / s, and finally maintain it at -25℃ at a rate of 1℃ / s. During the temperature change process, apply a supply voltage fluctuation of ±3% to ±18%. For example, when the temperature rises to 75℃, the supply voltage fluctuation is ±12%. Record real-time current and voltage data during the temperature change process and perform real-time analysis using a data processing system. The data processing system is programmed in Matlab and uses the plot function to draw real-time curves.

[0144] Step 3, Steady-State Maintenance and Comprehensive Stress Loading Phase: Maintain high temperature (70℃) and low temperature (-10℃) for 10 minutes each; apply vibration simulating an industrial environment, with a vibration frequency of 30Hz and a vibration amplitude of 2g; perform specific types of I / O operation mode tests, including: for ZNS SSDs, perform Zone switching operations and data migration tests. At 0℃, perform 2 million random Zone switching operations, each Zone size being 2GB; for CXL SSDs, perform cache consistency and memory semantic operation tests. At 5℃, perform 2 million read / write operations, each operation size being 8KB; for all types of SSDs, perform high write amplification load tests. At 20℃, use the fio tool for random writes, with a write size of 8MB, running continuously for 45 minutes.

[0145] Step 4, Data Integrity Verification Phase: During the test, SMART information, real-time power consumption, and link-level bit error rate (BER) are recorded in real time using a data acquisition system. The smartmontools library (programmed in Python) is used to read SMART information, the ADS1115 chip is used to collect real-time power consumption, and the Keysight real-time analyzer is used to collect the link-level BER. After the test, a full scan is performed using a custom command provided by the manufacturer to record newly added bad block information. For example, for PLCNAND flash memory, the command "SMARTLOG -a -d 1" is used for scanning; the CRC checksum recorded during writing is compared to verify data integrity. The crc32 library (programmed in Python) is used to calculate the CRC32 checksum and compare it with the checksum saved during writing.

[0146] Step 5, Intelligent Diagnosis and Data Analysis Stage: An anomaly detection model is established using an autoencoder algorithm, trained based on historical normal SSD data. The autoencoder algorithm is implemented using the TensorFlow library in Python; the current SSD health status score is calculated in real time. The data is processed using the pandas library in Python, calculating the weights and scores of various indicators; if the health status score is below 0.7, fault prediction and root cause analysis are performed. The health status change curve is plotted using the matplotlib library in Python; a test report is generated, including fault prediction results, data integrity verification results, and performance consistency evaluation results. A PDF test report is generated using the ReportLab library in Python.

[0147] Based on the first embodiment, its application in data integrity and lifespan reliability under high load and temperature fluctuation environments was verified as follows: Equipment Installation: The ZNS SSD under test was installed in a temperature, humidity, and vibration combined test chamber and fixed with a special clamp to ensure the effectiveness of vibration transmission. Sensor Placement: PT1000 platinum resistance temperature sensors were fixed with high-temperature adhesive on the surface of the SSD's main controller chip package, the surface of the NAND flash memory chip package, and near the power management chip to accurately monitor the real-time temperature of key points. System Connection: The SSD was connected to an external host via a PCIe interface. The host powered the SSD through a programmable power supply that could accept commands to simulate voltage fluctuations. The data acquisition system communicated with the temperature sensor, the programmable power supply, and the host software to acquire data at a set frequency.

[0148] Test Procedure: Step 1: Test Environment Initialization: Set the test chamber parameters: Temperature cycling range is -40℃ to 90℃. This range is chosen to cover various extreme scenarios, from frigid environments to localized server overheating. Humidity is set to 90% RH (under non-condensing conditions) to accelerate potential electrochemical migration. Vibration parameters are set to a frequency of 20Hz and an amplitude of 1.5g to simulate typical vibrations generated by fans and nearby equipment in a server room. Initialize the data acquisition system: The acquisition frequency is set to 10 Hz to ensure the capture of rapid changes in electrical signals. The anomaly detection model selected is the Isolation Forest algorithm, and the model is pre-trained using historical data from a known and reliable SSD of the same model at room temperature.

[0149] Step 2: Multi-stress Coupling Test Phase (Dynamic Stress Period): Dynamic Temperature Change Test: Perform three cycles of rapid temperature changes. Each cycle includes: increasing from 25°C to 90°C at a rate of 8°C / min (approximately 8 minutes), holding at 90°C for 10 minutes; then decreasing to -40°C at a rate of 10°C / min (approximately 13 minutes), holding at -40°C for 10 minutes; and finally increasing back to 25°C at a rate of 8°C / min. Rapid temperature changes aim to examine the mechanical stress caused by the mismatch in thermal expansion coefficients between materials. Voltage Fluctuation Coupling: During the temperature changes (heating and cooling phases), the programmable power supply is synchronously controlled, causing the supply voltage to fluctuate by ±10% from the nominal 12V. This simulates the impact of power grid fluctuations or changes in power consumption of other components within the system on the SSD power supply stability.

[0150] Real-time monitoring and data acquisition: Throughout the entire process, the SSD's input current, core voltage, and readings from various temperature sensors are continuously recorded. The data acquisition system calculates the derivatives (rates of change) of current and temperature in real time to observe whether abnormal peaks occur under drastic temperature changes and voltage fluctuations.

[0151] Step 3: Steady-State Maintenance and Comprehensive Stress Loading Phase (Steady-State Stress Period): High-Temperature Steady-State Test: After reaching 90℃, maintain this temperature for 30 minutes. Simultaneously, start the vibration table (20Hz, 1.5g). High-Load I / O Test: Under high temperature and vibration conditions, apply a specific workload to the SSD via host commands: Zone Management Stress Test: Using fio tools or vendor-specific tools, continuously perform random Zone opening / closing operations at a frequency of 500 times per second for the entire 30 minutes. This aims to test the ZNS SSD's metadata management capabilities and FTL stability under harsh environments. Data Write Test: Sequentially write 4KB data blocks to the opened Zone, with the write queue depth set to 32 to maintain high write pressure. Low-Temperature Steady-State Test: Maintain at -40℃ for 20 minutes, and repeat the above vibration and I / O tests (but reduce the Zone operation frequency to 100 times per second, as controller performance may be limited at low temperatures).

[0152] Step 4: Data Integrity Verification Phase: Real-time Data Integrity Monitoring: During all write operations in Steps 2 and 3, the host driver calculates and appends a CRC32 checksum when sending each data block. Simultaneously, the checksum and Logical Block Address (LBA) are recorded. Post-Test Offline Verification: Full Disk Read Verification: After the test, all data written to the SSD is read out at room temperature, the CRC32 checksum is recalculated, and compared with the checksum recorded during writing. SMART Information Analysis: SMART parameters before and after the test are read and recorded, focusing on changes in "Media Wear Indicator," "Uncorrectable Error Count," and "Uncorrectable Error Count." Bad Block Scan: Vendor-specific diagnostic commands (such as NVMe Log Page related commands) are used to scan the entire disk storage unit, recording the number of newly added bad or weak blocks.

[0153] Step 5: Intelligent Diagnosis and Data Analysis Phase: Health Status Score: Multiple indicators collected throughout the test, including the maximum real-time temperature, current fluctuation variance, SMART error count increment, data verification failure rate, and bad block growth, are used to calculate a comprehensive health status score (HS) ranging from 0 to 1 using a weighted fusion algorithm (such as the analytic hierarchy process). Anomaly Diagnosis: Based on the isolated forest model, real-time analysis is performed on the collected time-series data (such as current waveforms and temperature curves). For example, if abnormal glitches are detected near a certain temperature point, the system will mark the event and associate it with the I / O operation log at that time, indicating a potential risk of "decreased stability of the power network at low temperatures." Report Generation: A test report is automatically generated. The report clearly states that the tested ZNS SSD achieved a 100% pass rate for data integrity verification throughout the test, with a comprehensive health status score of 0.92 (higher than the preset pass threshold of 0.75), but points out a significant increase in write latency at temperatures below -30℃. The conclusion is that this SSD has excellent reliability, but attention should be paid to its performance in extreme low-temperature environments.

[0154] Based on the first embodiment, this test focuses on SSDs supporting the CXL protocol applied to intelligent connected vehicles, emphasizing their cache coherency and functional stability under rapid temperature cycling and complex vibration. Test Preparation: Similar to Embodiment 1, but with the following key changes: Test Equipment: A motherboard supporting the CXL protocol is used. Sensor: An additional sensor is attached near the CXL connector to monitor the interface temperature. Vibration Profile: A measured vehicle driving vibration profile (frequency range 5-500Hz, random vibration) is used instead of fixed-frequency sinusoidal vibration to more realistically simulate the in-vehicle environment. Test Procedure (highlighting differences from Embodiment 1):

[0155] Step 2: Multi-stress Coupling Test Phase: Temperature Cycling: Employing a faster rate of temperature change to simulate a car's transition from engine shutdown to startup, or day-night temperature variations. For example, dropping from 85°C (simulating summer sun exposure) to -20°C (simulating a winter night) at a rate of 15°C / min, followed by a rapid recovery. The number of cycles is increased to 50 for accelerated life testing. Voltage Fluctuation: Simulating the characteristics of a car's power system, a load dump pulse (a brief high-voltage pulse) is superimposed on the voltage fluctuation (±12%).

[0156] Step 3: Steady-State Maintenance and Comprehensive Stress Loading Phase: I / O Testing Focus: Cache Consistency Test: The host CPU performs frequent read and write operations on the memory-mapped region of the CXL SSD. Simultaneously, a consistency protocol (such as CXL.cache) monitoring tool is used to check whether the consistency of cached data is compromised under vibration and temperature stress. For example, stress testing software is run to perform multi-core concurrent access to the same memory address to verify data correctness. Memory Semantic Operation Test: The functional correctness of the CXL.io and CXL.mem protocols is tested, such as performing a large number of atomic operations and doorbell register operations under high temperature to verify whether their response is timely and accurate.

[0157] Steps 4 and 5: Data Verification and Diagnosis: Verification Focus: In addition to data integrity, the emphasis is on functional errors, such as the number of cache consistency errors, the number of protocol timeout errors, and operating system blue screens or crashes. Diagnostic Model: An autoencoder is used for unsupervised anomaly detection. It is trained using timing information of a large number of CXL protocol link layer data packets under normal operating conditions. During testing, if abnormal message intervals or error code patterns occur, the autoencoder's reconstruction error will increase significantly, triggering an early warning that may indicate root causes such as "increased contact resistance of the connector due to vibration" or "controller logic error under high temperature."

[0158] Test Results: The report shows that after 50 temperature cycles, the tested CXL SSD exhibited no data integrity errors. However, during the high-temperature phase of the 35th cycle, a brief memory semantic operation timeout was detected. The intelligent diagnostic system identified the root cause as a transient power supply glitch and recommended adding a filter capacitor to the power supply design. The SSD received an overall score of 0.78, rated as "Acceptable but with room for design improvement."

[0159] This embodiment introduces a multi-stress coupling mechanism to comprehensively simulate multi-dimensional stress conditions such as temperature changes, voltage fluctuations, and vibration, fully reflecting the complex environment of solid-state drives in real-world application scenarios. This overcomes the limitations of traditional temperature cycling tests that only consider a single environmental stress, improving the comprehensiveness and accuracy of the test. Employing online real-time monitoring and intelligent diagnostic technology, it continuously monitors and collects data from multiple dimensions of the SSD, including physical health parameters, SMART information, and real-time power consumption, achieving full-process monitoring and dynamic analysis of the SSD during testing. This effectively solves the blindness problem of the traditional "post-test inspection" mode. Targeted test modes and evaluation criteria are designed according to different SSD types and application scenarios, specifically for QLC / PLC flash memory, ZNS SSDs, and Compute Express Link (CXL). Corresponding testing methods have been developed for emerging technologies and architectures such as SSDs, improving the relevance and applicability of testing. By introducing a dynamic temperature change rate testing mechanism, which combines rapid temperature rise and fall with slow temperature rise and fall, defects such as solder joint fatigue and chip cracking caused by mismatch in the thermal expansion coefficients of materials are effectively tested, improving the comprehensiveness and depth of testing. A comprehensive data integrity verification mechanism has been designed, which ensures that no silent errors occur in the data during the entire rigorous testing process by comparing the CRC checksum recorded during writing, effectively improving the reliability and accuracy of testing.

[0160] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0161] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0162] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for temperature cycling testing of solid-state drives based on multi-stress coupling, characterized in that, The method includes: Initialize the test environment, which includes setting the parameters of the test equipment, installing the solid-state drive under test, and initializing the data acquisition system; Determine the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing. First, perform a single stress test to determine the basic tolerance range of the SSD. Then, design the boundary conditions for composite stress and test the operating records of the SSD under test according to the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing. In the dynamic temperature change test, which maintains the test within a preset time range, the solid-state drive under test is subjected to an increased vibration frequency simulating environmental vibration, and a specific type of I / O operation mode test is performed; wherein, the specific type of I / O operation mode test includes: the solid-state drive under test performing sequential read / write, random read / write, and mixed load operations; Based on the data acquisition system, the SMART data, real-time power consumption, and link-level bit error rate output by the I / O operation mode are recorded in real time. The data processing system sets an abnormal warning threshold and automatically pauses the test or adjusts the stress parameters when the warning is triggered. An anomaly detection model is established. Based on historical normal SSD data, the anomaly detection model is trained using the isolated forest or autoencoder algorithm. During training, the model is grouped by SSD type. The real-time recorded SMART data is compared with the anomaly detection model. The health status score of the SSD under test is calculated based on the comparison results. The health status score is then analyzed, and the analysis results are used to generate a health test report.

2. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 1, characterized in that, The initialization of the test environment includes the steps of setting test equipment parameters, installing the solid-state drive under test, and initializing the data acquisition system. Initialize the test environment and set the test equipment parameters, including a temperature range of -40℃ to 125℃, a humidity range of 0% to 100%RH, a vibration frequency range of 10Hz to 200Hz, and a vibration amplitude range of 0.1g to 10g. Install the solid-state drive to be tested, and implant temperature sensors in at least the controller, NAND chip, and DRAM of the solid-state drive; Initialize the data acquisition system, including setting the data acquisition frequency, data storage path, and anomaly detection model parameters; Calibrate all sensors and test equipment to ensure that the measurement accuracy of temperature, humidity, vibration and electrical parameters meets the standards. After completing the initialization verification, start the subsequent test process.

3. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 1, characterized in that, The steps of determining the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing, and then testing the operating records of the solid-state drive under test based on the temperature range for dynamic temperature change testing and the voltage range for dynamic voltage testing, include: Perform dynamic temperature change testing, which includes two test modes: rapid temperature rise and fall, and slow temperature rise and fall. Perform dynamic voltage testing, fluctuating the voltage within ±15% of the nominal value, and simultaneously record the response latency and data write success rate of the solid-state drive under test under different voltage conditions; By combining temperature changes and voltage disturbances, a composite stress scenario is constructed. Under this composite stress scenario, the temperature response and voltage fluctuation coupled data of the solid-state drive under test are collected in real time, and the I / O performance fluctuations and error retransmission counts are recorded simultaneously. The data is then analyzed in real time through a data processing system.

4. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 1, characterized in that, The steps of performing a dynamic temperature change test within a preset time range, which involves increasing the vibration frequency of the solid-state drive under test to simulate environmental vibration and executing a specific type of I / O operation mode test, include: Query the solid-state drives under test that have undergone dynamic temperature change testing within the same temperature range over a preset time period; To simulate traffic or industrial vibrations in the test environment of the solid-state drive under test, the vibration frequency is increased from 10Hz to 50Hz and the vibration amplitude is increased from 0.5g to 5g. Perform tests on specific types of I / O operation modes.

5. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 4, characterized in that, The steps for performing specific types of I / O operation mode tests include: For the ZNS SSD in the solid-state drive under test, perform Zone on / off operation and data migration test; For the CXL SSD in the solid-state drive under test, perform cache consistency and memory semantic operation tests; For all types of SSDs, the fio tool was used to perform random write operations, and the TRIM command was frequently triggered to simulate extreme usage scenarios and conduct high write amplification load tests.

6. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 1, characterized in that, The steps of recording SMART data, real-time power consumption, and link-level bit error rate output by the data acquisition system in real time include: During the test, SMART information, real-time power consumption, and link-level bit error rate were recorded in real time through the data acquisition system. After the test, a full disk scan is performed according to the custom command. The bad block distribution map and write amplification trend are obtained from the full disk scan results, and the information of newly added bad blocks is recorded. Compare the CRC checksum recorded during writing to verify data integrity.

7. The solid-state drive temperature cycling test method based on multi-stress coupling according to claim 1, characterized in that, The steps of establishing an anomaly detection model, training the model based on historical normal SSD data using an isolated forest or autoencoder algorithm, comparing real-time recorded SMART data with the anomaly detection model, calculating a health status score for the SSD under test based on the comparison results, analyzing the health status score, and generating a health test report from the analysis results include: Establish an anomaly detection model and train it based on historical normal SSD data, using either the isolated forest or autoencoder algorithm. The real-time recorded SMART data is compared with the anomaly detection model, and the health status score of the solid-state drive under test is calculated based on the comparison results. If the health status score is lower than the preset threshold, the solid-state drive under test is marked as faulty, and fault prediction and root cause analysis are performed. The analysis results will generate a health test report, including failure prediction results, data integrity verification results, and performance consistency assessment results.

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