Methods, apparatus, electronic devices and readable storage media for unpredictable branch transformations

Abstract

This application provides a method, apparatus, electronic device, and computer-readable storage medium for transforming unpredictable branches. The method involves identifying a target instruction sequence from an instruction sequence; performing instruction transformation operations on the unpredictable branch instructions in the target instruction sequence to obtain transformed instructions, and using the branch judgment results of the unpredictable branch instructions as direction markers; adding the direction markers to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; and executing the transformed instructions and the adjusted instructions corresponding to the context instructions based on the values ​​of each direction marker. By identifying the target instruction sequence from the instruction sequence and adding direction markers to the adjusted instructions corresponding to the context instructions, processing all unpredictable branches can be avoided, reducing the number of dynamic instructions and algorithm complexity, thereby reducing pipeline conflicts and scheduling overhead.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and computer-readable storage medium for unpredictable branch transformation. Background Technology

[0002] Branch prediction is a technique in computer architecture used to improve the efficiency of instruction pipelines by predicting the branching path of a program to avoid pipeline stalls.

[0003] In modern processors, hard-to-predict (HTP) branches refer to conditional branch instructions with complex behavior patterns and poor historical regularity during program execution, whose jump direction is difficult to accurately predict using static or dynamic prediction strategies. Existing technologies for handling hard-to-predict branches can transform control flow into data dependencies through predicate-based instructions, and eliminate small-granular data-dependent branches in the program by attaching a predicate to each regular instruction.

[0004] However, predicated instructions increase the dependency on path length and the total number of dynamic instructions. In addition, when there are instructions in the branch path that cannot be predicated, it is difficult to reduce unpredictable branches and increase the complexity of transformations. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and computer-readable storage medium for unpredictable branch transformation, which can reduce the number of dynamic instructions and lower the complexity of the transformation algorithm.

[0006] In a first aspect, embodiments of this application disclose a method for unpredictable branch transformation, the method comprising:

[0007] Identify a target instruction sequence from an instruction sequence, the target instruction sequence including unpredictable branch instructions and context instructions of the unpredictable branch instructions;

[0008] An instruction transformation operation is performed on the unpredictable branch instructions in the target instruction sequence to obtain the transformed instructions, and the branch judgment result of the unpredictable branch instructions is used as a direction flag. The value of the direction flag is used to indicate whether the unpredictable branch instructions jump to the target address.

[0009] The direction identifier is added to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction;

[0010] Based on the values ​​of each of the direction markers, execute the transformed instruction and the adjusted instruction corresponding to the context instruction.

[0011] Secondly, embodiments of this application disclose a difficult-to-predict branch transformation device, the device comprising:

[0012] The identification module is used to identify the target instruction sequence from the instruction sequence;

[0013] The transformation module performs an instruction transformation operation on the unpredictable branch instructions in the target instruction sequence to obtain the transformed instructions, and uses the branch judgment result of the unpredictable branch instructions as a direction marker.

[0014] The adjustment module adds the direction identifier to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction;

[0015] The execution module executes the transformed instruction and the adjusted instruction corresponding to the context instruction, based on the values ​​of each of the direction markers.

[0016] Thirdly, embodiments of this application also provide an electronic device, including a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0017] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0018] The embodiments of this application have the following advantages:

[0019] This application discloses a method for transforming unpredictable branches. It identifies a target instruction sequence containing unpredictable branches, performs instruction transformation operations on the unpredictable branch instructions within the target instruction sequence, and uses the branch determination result of the unpredictable branch instructions as a direction marker. This direction marker is then added to the context instructions in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction. By identifying the target instruction sequence from multiple instruction sequences and performing transformation operations only on the unpredictable branch instructions within the target instruction sequence, excluding other unprocessable instruction sequences, the number of dynamic instructions can be reduced, thereby reducing pipeline conflicts and scheduling overhead. Furthermore, since the instruction transformation operation involves adding a direction marker to the context instructions, only one variable needs to be added, thus reducing the complexity of the transformation algorithm and improving processor performance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the steps of an embodiment of the unpredictable branch transformation method of the present invention;

[0022] Figure 2 This is a flowchart illustrating the steps of another embodiment of the unpredictable branch transformation method of the present invention;

[0023] Figure 3 This is a structural block diagram of a difficult-to-predict branch transformation device according to the present invention;

[0024] Figure 4 This is a structural block diagram of an electronic device provided by an example of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0027] Branch prediction is a key factor in the performance of modern microprocessors. In the event of a branch misprediction, if the branch jump direction is not known in advance, the pipeline must stop and wait for the result, causing microprocessors with high-capacity pipelines and large caches to stall. Branch misprediction can interrupt program flow, leading to pipeline resets and the need to refill caches from slow main memory. Unpredictable branches typically have branch conditions that depend on unpredictable external data or computation results, such as hash collisions, cryptographic algorithm judgments, and cyclic redundancy checks (CRC), as well as extremely low-bias branches and non-locally dependent branches. A branch can also be identified as unpredictable by analyzing the correlation between the branch instruction and the data value loaded by the preceding load instruction; if the branch condition is directly related to the result of historical data loading, the branch instruction is considered unpredictable.

[0028] Because even extremely low branch prediction accuracy can cause severe performance degradation in microprocessors, supplementary branch prediction circuitry, such as specialized branch predictors, is needed. These supplementary circuitry provide algorithms focused on predicting certain types of hard-to-predict (HTP) branches, predicting branch direction and target address in advance to keep the instruction pipeline running. If the prediction is correct, performance is significantly improved; if incorrect, a rollback is required, wasting time. These HTP branches can be caused by program structures that, for example, result in highly variable historical data used for branch prediction. Traditional branch predictors, such as local pattern matching branch predictors, cannot predict accurately because they rely on identifying capture position dependencies. Therefore, hard-to-predict branches can be addressed through compiler optimization, hardware improvements, and software-level optimizations. Software-level optimizations, compared to other methods, do not increase hardware costs and can continuously improve adaptability and accuracy through algorithmic optimization, thereby improving processor performance, such as instructions per cycle (IPC).

[0029] Instructions per cycle (IPC) is the average number of instructions executed per clock cycle, reflecting instruction level parallelism (ILP) and microarchitectural efficiency. Since pipeline flushing occurs due to misprediction, IPC can be improved to increase processor execution efficiency by increasing branch prediction accuracy.

[0030] The processor's job is to fetch, decode, and execute instructions. Instruction sequence processing includes the fetch, decode, execute, memory access, and write-back phases. An instruction is an operation command that the processor can recognize and execute; it is binary code stored in memory. A branch is a type of instruction that can change the normal sequential execution flow of a program. Normally, instructions are executed one after another. A branch instruction tells the processor that the next instruction to be executed is not the one following in sequence, but an instruction at a different address. A path refers to the sequence or trajectory of instructions that the program's instruction flow traverses during actual execution. Due to the existence of branch instructions, a program may have multiple instruction flows; the instructions contained in different instruction flows are called different execution paths.

[0031] The branch target address refers to the address of the next instruction to be executed when a branch instruction jumps to its execution (target address). This target address is typically calculated from the operands or registers of the branch instruction. It can be obtained through relative addressing, inter-register addressing, or inter-memory addressing.

[0032] Method Implementation Examples

[0033] Reference Figure 1 The diagram illustrates a step flowchart of an embodiment of a difficult-to-predict branch transformation method according to the present invention. The method may specifically include the following steps:

[0034] Step 101: Identify the target instruction sequence from the instruction sequence, the target instruction sequence including unpredictable branch instructions and the context instructions of the unpredictable branch instructions.

[0035] It should be noted that, firstly, the execution target of this branch transformation method needs to be selected. This can be done by selecting an instruction sequence containing unpredictable branches from multiple instruction sequences within the processor. The target instruction sequence can include unpredictable branch instructions and context instructions of unpredictable branch instructions. For example, the unpredictable branch instruction is a conditional branch instruction, and the context instructions are the instructions adjacent to the conditional branch instruction and related instructions.

[0036] For unpredictable branch transformation methods, the accuracy of selecting the target instruction sequence directly affects program performance and resource utilization efficiency.

[0037] Step 102: Perform an instruction transformation operation on the unpredictable branch instructions in the target instruction sequence to obtain the transformed instructions, and use the branch judgment result of the unpredictable branch instructions as a direction flag. The value of the direction flag is used to indicate whether the unpredictable branch instructions jump to the target address.

[0038] It should be noted that instruction transformation operations can be performed on unpredictable branch instructions in the target instruction sequence to obtain transformed instructions. Unpredictable branch instructions are those that are difficult to predict accurately during program execution through historical data or pattern matching. These instructions typically have the following characteristics: indirect jumps, control dependencies, and dynamic branches. Indirect jumps mean that the target address is determined by a register value, rather than directly by the PC (Program Counter) offset; control dependencies mean that the branch direction or target address needs to wait for the execution results of other instructions, making it impossible to predict in advance during the instruction fetch stage; dynamic branches mean that the branch direction or target address may be dynamically adjusted during program execution based on input data and environmental changes. For example, for input-type conditional branch instructions, instruction transformation operations can transform the conditional branch instruction into a comparison micro-instruction, thereby converting the original unpredictable branch instruction into other comparison-type micro-instructions. The transformed instruction is a micro-instruction. Because the transformation is performed only on unpredictable branch instructions, rather than on every line of instructions in the target instruction sequence, the complexity of the transformation algorithm can be reduced.

[0039] The branch judgment result of a difficult-to-predict branch instruction can be used as a direction flag. The branch judgment result indicates whether the branch judgment condition of the difficult-to-predict branch is true. The direction flag is a user-defined variable that can be stored in a general-purpose register. The value of the direction flag indicates whether the difficult-to-predict branch instruction should jump to the target address. The direction flag is a user-defined integer data, with a value of 1 or 0. 1 means that the difficult-to-predict branch must jump to the target address, and 0 means that the difficult-to-predict branch does not need to jump to the target address. The target address represents the next machine address to which the program counter automatically increments to jump to the next instruction. The accuracy of the target address is also crucial for branch prediction execution. The accuracy of target address prediction can be improved by optimizing indirect jumps, controlling dependencies, and dynamic branching techniques. Therefore, instead of adding a user-defined variable for the direction flag, only one register is added to store the user-defined variable, without adding more hardware devices or hardware interfaces, thus saving hardware costs.

[0040] Step 103: Add the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0041] It should be noted that the direction flag can be added to each context instruction in the target instruction sequence through instruction adjustment operations to obtain the adjusted instruction corresponding to each context instruction. The context instructions refer to some instructions adjacent to the unpredictable branch instruction, and can be multiple types of instructions following the unpredictable branch instruction, such as arithmetic instructions, access and store instructions, conditional branch instructions, jump instructions, etc. The direction flag is obtained from the transformation process in step 102 and is usually stored in the target register. The adjusted instruction corresponding to each context instruction can be formed by adding the direction flag after the opcode of each context instruction as a flag bit, while keeping other parameters unchanged. The processing of the adjusted instruction depends on the value of the direction flag; the value of the direction flag can be read to determine whether to execute the instruction. For example, when executing the adjusted instruction, if the direction flag is 1, the adjusted instruction is not executed; if the direction flag is 0, the adjusted instruction is executed sequentially.

[0042] Therefore, instruction transformation and adjustment operations are performed on the target instruction sequence to obtain a processed instruction sequence, which includes transformed instructions and adjusted instructions.

[0043] Each instruction in the processed instruction sequence includes a direction marker, thus completing the processing of the target instruction sequence. The processing of unpredictable branches can be accomplished by simplifying the transformation process.

[0044] Step 104: Execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the values ​​of each of the direction markers.

[0045] The direction flag can be a binary value, used to indicate whether a difficult-to-predict branch instruction jumps to the target address. Transformed instructions corresponding to difficult-to-predict branch instructions are executed unconditionally, while adjusted instructions corresponding to context instructions require different operations based on the direction flag value obtained from the instruction transformation. For example, when executing an adjusted instruction, if the read direction flag is 1, the adjusted instruction is not executed; if the read direction flag is 0, the adjusted instruction is executed sequentially. Executing the adjusted instruction means the instruction takes effect; taking effect refers to misprediction flushing, register value modification, and memory access. Branch instruction misprediction flushing refers to the process where, when the processor mispredicts the jump path or target address of a branch instruction, all instructions that have entered the pipeline but were executed based on the erroneous prediction are cleared, and instruction fetching restarts from the correct address. For arithmetic instructions, this can involve modifying register values, primarily implemented through the arithmetic logic unit. For load and store instructions, during the memory access phase, after calculating the target address, the processor can either read memory data into a register via the data bus or write register data to a specified address.

[0046] Therefore, by taking the value of the direction flag, the adjusted instructions corresponding to the context instructions are executed sequentially. This can transform dynamic branches into static sequential execution, ensuring that the computer executes the target instruction sequence sequentially and avoiding out-of-order operations from interfering with the effectiveness of the direction flag.

[0047] In this embodiment, the target instruction sequence is identified from the instruction stream, and instruction transformation processing is performed on the unpredictable branches included therein to obtain the transformed instructions and direction flags. The direction flags are then added to all branches except the unpredictable branches to generate the adjusted instructions. Therefore, by performing transformation operations only on the unpredictable branch instructions and adding only the direction flags to the context instructions, the number of dynamic instructions can be reduced, thereby reducing pipeline conflicts and scheduling overhead. Furthermore, by identifying the target instruction sequence from the instruction sequence, instruction transformation processing on a large number of instruction sequences is avoided, reducing the complexity of the transformation algorithm and improving the efficiency of instruction execution, thus improving the overall performance of the processor.

[0048] Reference Figure 2 The flowchart illustrates another embodiment of the unpredictable branch transformation method of the present invention, which specifically includes the following steps:

[0049] Step 201: Identify the target instruction sequence from the instruction sequence, wherein the target instruction sequence includes unpredictable branch instructions and context instructions of the unpredictable branch instructions.

[0050] For details of this step, please refer to step 101 above, which will not be repeated here.

[0051] Optionally, step 201 may include:

[0052] Sub-step 2011: Select an instruction sequence that includes the target instruction structure from the instruction sequence as the target instruction sequence.

[0053] The target instruction structure includes a difficult-to-predict conditional branch instruction, a context instruction, and a transfer instruction; the context instruction is located between the difficult-to-predict conditional branch instruction and the transfer instruction; the context instruction includes at least one of an operation instruction, a load instruction, a store instruction, and other conditional branch instructions besides the difficult-to-predict conditional branch instruction; and the target address is the address of the transfer instruction.

[0054] Specifically, conditional branches that rely on unpredictable external data are also considered unpredictable branches. These unpredictable conditional branches include unpredictable conditional branch instructions, context instructions, and jump instructions. Jump instructions are instructions in the instruction stream that change the program execution order or modify the program counter (PC) value; these include conditional jumps, unconditional jumps, function calls / returns, and indirect jumps. The target address is the memory address to which the jump instruction jumps; target addresses can be immediate, relative, register, or memory. Context instructions are located between unpredictable conditional branch instructions and jump instructions.

[0055] In this embodiment, an assembly language fragment under the Reduced Instruction Set Computer-Version 5 (RISC-V) architecture is used as an example, as shown below:

[0056] 10a5a: c299beqza3,10a60

[0057] 10a5c: 031f0963beqt5,a7,10a8e

[0058] 10a60: 97aaadda5,a5,a0

[0059] 10a62: 05b7fd63bgeu a5,s11,10abc<main+0x5a4>

[0060] It should be noted that this code is commonly used in loop control, conditional statements, and data processing. It executes the following logic:

[0061] Condition check: First, check if the value of register a3 is 0. If it is 0, jump directly to address 10a60 to calculate the address.

[0062] Alternative branch: If the value of register a3 is not 0, continue to check whether the values ​​of register t5 and a7 are equal. If they are, jump to address 10a8e.

[0063] Address calculation: At address 10a60, add the values ​​of register a5 and a0, and store the result back into a5.

[0064] Boundary check: Verify whether the value of register a5 exceeds the boundary represented by s11 through unsigned comparison. If it exceeds the boundary, jump to address 10abc (marked as offset 0x5a4 of the main function).

[0065] Optionally, step 201 may also include:

[0066] Sub-step 2012: Read the instruction sequence from the processor instruction buffer, which is located in the cache area between the instruction fetch unit and the decode unit.

[0067] Sub-step 2013: When the first line of instruction in the instruction sequence is a conditional branch instruction and the first line of instruction is separated from the branch instruction by at least one context instruction, the instruction sequence is identified as the target instruction sequence.

[0068] Regarding sub-steps 2012 and 2013, it should be noted that the processor instruction buffer is used to temporarily store instructions to be executed fetched from memory or cache. Located after the instruction fetch unit and before the decode unit, it decouples instruction fetching and decoding, improves parallelism, reduces blocking caused by waiting for instruction cache latency, and supports predictive execution. The instruction fetch unit fetches the next instruction to be executed from memory. The instruction fetch unit reads the instruction from the instruction cache based on the current PC address; if a branch instruction is encountered, the branch predictor is called to determine the next fetch address; the fetched instruction is placed in the instruction buffer to await decoding. The decode unit parses the instruction meaning, fetches operands, and prepares execution information. Parsing the instruction meaning means translating the binary machine code into instruction operation types (arithmetic / logical / memory access / jump, etc.); fetching operands means reading operands from the register file; preparing execution information means generating control signals. The execution unit performs arithmetic or address calculations and includes an arithmetic logic unit, a branch decision unit, a multiplier / divider, and an address calculator.

[0069] A matching pattern based on instruction structure type can be used to identify similar instruction sequences as target instruction sequences from the instruction sequence. In this type of instruction sequence, the first instruction is a conditional branch instruction, and there are other instructions between this conditional branch instruction and the jump instruction. These context instructions include at least one of arithmetic instructions, load instructions, store instructions, and other conditional branch instructions besides the aforementioned unpredictable branch instruction; the target address is the address to which the jump instruction proceeds.

[0070] Therefore, by reading instruction sequences from the processor's instruction buffer and selecting only those that satisfy a specific static program structure as the target instruction sequence for processing and decoding, the processor can effectively avoid reading the entire instruction sequence from the instruction stream, thus reducing unnecessary memory usage, decreasing the number of instructions processed, and improving processing efficiency.

[0071] Optionally, step 201 may include:

[0072] Sub-step 2014: Obtain instruction sequences from paths other than the critical path in the processor pipeline, where the critical path is the longest combinational logic path;

[0073] Sub-step 2015: Identify the target instruction sequence from the instruction sequences on the other paths.

[0074] It's important to note that the critical path in a pipeline is a concept in computer architecture that determines the shortest clock cycle (i.e., the highest frequency) and overall performance ceiling of the pipeline. The processor pipeline consists of five stages: fetch, decode, execute, memory access, and write-back. Each stage can be composed of several hardware components. The critical path refers to the longest logical delay path traversed by the signal from input to output within a given pipeline stage.

[0075] In this embodiment, during the actual execution of the program, the sequence or trajectory traversed by the instruction stream lies on a non-longest logical delay path. By obtaining instruction sequences from these instruction streams and identifying the target instruction sequence from these sequences, the instruction stream to be processed can be differentiated. Transformation processing is performed only on unpredictable branch instructions on non-critical paths, rather than on all unpredictable branch instructions on all paths. In other words, the longest path in the hardware design's combinational logic affects the processor's clock frequency and thus performance. Therefore, branch prediction can be advanced to the instruction stream selection stage during instruction fetching, and the logic structure can be simplified, thereby ensuring the processor's frequency and performance.

[0076] Optionally, step 201 may include:

[0077] Sub-step 2016: When refilling the microinstruction cache, obtain the instruction sequence from the microinstruction sequence already stored in the microinstruction cache;

[0078] Sub-step 2017: Identify the target instruction sequence from the instruction sequence.

[0079] Regarding sub-steps 2016 and 2017, it should be noted that microinstructions are the lowest-level instructions used internally by the processor controller to directly control the hardware to perform basic operations. Each microinstruction consists of a control signal field. Microinstructions are stored in microcode memory or control memory. The microinstruction buffer is a temporary cache area used to store microinstructions that have been fetched from microcode memory for quick use during the execution phase.

[0080] An opcode is a binary field in an instruction that defines a basic operation, such as addition, subtraction, or a jump operation. Operands are the objects to be operated on in the instruction; they can typically be register operands or immediate values. A decoder is a hardware module that translates binary instructions into internal processor control signals. After translating the instructions, the decoder sends them to the execution unit, which is responsible for performing the actual calculations according to the instructions.

[0081] When the contents of the microinstruction buffer become invalid or exhausted, a new sequence of microinstructions needs to be reloaded from the microcode memory or instruction decoding unit and added to the buffer. The microinstruction buffer is used to temporarily store instructions to be executed, fetched from memory or cache, reducing blocking caused by waiting for instruction cache latency and supporting predictive execution.

[0082] Refilling the microinstruction cache is a crucial recovery mechanism for processors when encountering branch prediction errors or cache misses during execution. When the trace cache misses or branch prediction fails, the processor needs to fetch instructions again from the L2 cache or main memory and use the microinstruction sequencer to convert complex IA-32 (Intel Architecture 32-bit) instructions into micro-operation code. By obtaining the target instruction sequence during this process, the performance penalty caused by the latency in obtaining the target instruction sequence can be effectively reduced, while avoiding the overhead of repeatedly decoding the same instructions.

[0083] Step 202: Perform an instruction transformation operation on the unpredictable branch instructions in the target instruction sequence to obtain the transformed instructions, and use the branch judgment result of the unpredictable branch instructions as a direction flag. The value of the direction flag is used to indicate whether the unpredictable branch instructions jump to the target address.

[0084] For details of this step, please refer to step 102 above, which will not be repeated here.

[0085] Optionally, step 202 further includes:

[0086] Sub-step 2021: Transform the unpredictable branch instructions in the target instruction sequence into transformed instructions, and use the branch judgment result of the unpredictable branch instructions as a direction marker. The transformed instructions are comparison operation micro-instruction type instructions, and the transformed instructions are used to calculate the branch judgment of the unpredictable branch.

[0087] It's important to note that comparison operation microinstructions are hardware-level commands directly executed by the processor control unit. Their core function is to compare two data values ​​using a subtraction operation and set a flag to reflect the result. The flag is set based on the comparison result for use by subsequent conditional branch instructions. Comparison operation microinstructions (e.g., cmp) belong to the arithmetic logic class of microinstructions. Modern processors improve comparison efficiency through parallel microinstruction streams, converting Complex Instruction Set Computer (CISC) instructions into RISC microoperations (μops).

[0088] Specifically, the target conditional branch instruction in the target instruction sequence can be converted into comparison operation micro-instructions to obtain the transformed instruction. The target conditional branch instruction is usually the first conditional branch instruction identified first; other conditional branch instructions nested within the first conditional branch will not undergo transformation. An example assembly language fragment from the Reduced Instruction Set Computer-Version 5 (RISC-V) architecture is shown below:

[0089] bne x2,x3,target

[0090] bne x5, x7, target2 (unrelated jump target)

[0091] target:

[0092] Logical explanation: Compare the values ​​in registers x2 and x3. If the values ​​in the two registers are not equal, the program counter jumps to the address specified by the target label to continue execution; compare the values ​​in registers x5 and x7. If they are not equal, jump to the target2 label.

[0093] The conditional branch instruction bne in unpredictable branches can be transformed into cmp to obtain the following instruction sequence:

[0094] cmp x2,x3,flag1

[0095] bne_flag flag1, x5, x7, target2 (irrelevant jump target)

[0096] target:

[0097] Logical description: Compare the values ​​of registers x2 and x3; store the comparison result in the flag1 register or variable; based on the comparison of flag1 and the register, if flag1 is true (indicating that x2 ≠ x3 in the previous comparison) and x5 ≠ x7, then jump to target2.

[0098] It should be noted that conditional branch instructions include: beq (Branch if Equal), bne (Branch if Not Equal), beqz (Branch if Equal Zero), and bnez (Branch if Not Zero). MIPS conditional branching is based on beq and bne, and jumps are achieved through register comparisons. Instruction translation replaces beqz with the cmp instruction.

[0099] Decoupling operations can improve pipeline throughput, and a flag mechanism enhances program flow control flexibility. The first conditional branch instruction performs a transformation operation, while the second conditional branch instruction immediately following it does not perform a transformation operation but instead performs a subsequent adjustment operation. That is, it transforms `bne` into `cmp`. Therefore, the `cmp` instruction can store the generated flag result in `flag1`, which can be easily shared by multiple subsequent instructions. This avoids redundant comparison operations, thereby improving program processing efficiency.

[0100] Optionally, step 202 may also include:

[0101] Sub-step 2022: When it is determined that the branch judgment condition carried by the unpredictable branch instruction is met, the first value is written into the direction flag. The first value is used to indicate that the adjusted instruction corresponding to each context instruction is not executed.

[0102] Sub-step 2023: When it is determined that the branch judgment condition carried by the unpredictable branch instruction is not met, the second value is written into the direction flag. The second value is used to indicate the adjusted instruction corresponding to the execution context instruction.

[0103] It should be noted that the branch conditions for unpredictable branch instructions are usually determined by both the instruction type and the hardware implementation. Condition judgment types include register comparisons, flag checks, and memory value dependencies. Memory value dependencies mean that the branch condition may indirectly depend on memory data, requiring the condition to wait for the data to become available before a decision can be made.

[0104] In this embodiment, during the transformation of unpredictable branches, instruction transformation operations can be performed according to the type of the unpredictable branch instruction. For unpredictable branch instructions carrying branch judgment conditions, the branch direction and target address are two key factors. When determining the branch direction, it is necessary to determine whether the branch judgment conditions carried by the unpredictable branch instruction are true. If the branch judgment conditions are true, a first value (e.g., 1) is written to the direction flag. In the instruction before transformation, 1 indicates that the instruction corresponding to the target address should be jumped to. In the instruction after transformation, 1 indicates that the adjusted instruction corresponding to each context instruction should not be executed. If the branch judgment conditions are not true, a second value (e.g., 0) is written to the direction flag. In the instruction before transformation, 0 indicates that the instruction corresponding to the target address should not be jumped to. In the instruction after transformation, 0 indicates that the adjusted instruction corresponding to each context instruction should be executed. Thus, by adding a flag as a flag bit, the detection of the flag bit can avoid relying on memory data reading, reducing the overhead and latency of unpredictable branch prediction failure.

[0105] Optionally, the method further includes:

[0106] Step 203: Extract the output value of the comparison result corresponding to the transformed instruction from the target register specified by the transformed instruction; the target register is used to store the comparison result;

[0107] Step 204: Store the output value of the comparison result into the flag register.

[0108] For steps 203 and 204, a read operation is performed on the target register specifying the storage output result of the transformed instruction of the unpredictable branch instruction, and the output value of the read result is stored in the flag register. The flag register is specifically set up to store the output value of the comparison result corresponding to the transformed instruction. The type of this output value can be numeric or Boolean.

[0109] Step 205: Add the direction identifier to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0110] For details of this step, please refer to step 103 above, which will not be repeated here.

[0111] Optionally, step 205 may also include:

[0112] Sub-step 2051: Read the comparison result from the flag register as a direction flag;

[0113] Sub-step 2052: Add the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0114] It should be noted that the flag register is a crucial register in the processor used to store operational status and control instruction execution; it is also known as the program status word. The basic results of the flag register include status flags and control flags. Its functions can include reflecting the characteristics of arithmetic / logic operation results, controlling program flow, and the processor's operating mode. Jumps can be triggered through combinations of flag bits to implement logic such as loops and conditional statements.

[0115] In this embodiment, the comparison result pre-stored in the flag register can be read out as a direction flag, and the direction flag can be added as a flag bit to each context instruction in the target instruction sequence, for example, after the opcode of the context instruction.

[0116] 10a5c: 031f0963beq_flag flag1,t5,a7,10a8e

[0117] flag1 refers to the status flag. If the flag is true (1), the branch is triggered. If the flag is false (0), the branch is not triggered. If flag1 is 1, the branch judgment is executed. If the values ​​of registers t5 and a7 are equal, the program jumps to address 10a8e to continue execution.

[0118] Step 206: Execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the values ​​of each of the direction markers.

[0119] For details of this step, please refer to step 104 above, which will not be repeated here.

[0120] Optionally, step 206 further includes:

[0121] Sub-step 2061: When the value of the direction indicator is the first value, only the transformed instruction is executed;

[0122] Sub-step 2062: When the value of the direction indicator is the second value, execute the transformed instruction and the adjusted instruction corresponding to the context instruction.

[0123] It should be noted that the direction indicator can take the value 0 or 1, or it can be extended to other integer values ​​to represent multiple states. The variable type of the direction indicator is not limited to numeric; it can also be a boolean type, and can be true or false.

[0124] In this embodiment, during the execution phase, the transformed instruction sequence of the target instruction sequence is executed. First, the transformed instruction corresponding to the unpredictable branch instruction is executed. Then, different operations can be performed on the transformed target instruction sequence based on different values ​​of the direction identifier. When the value of the direction identifier indicates that the jump condition of the unpredictable branch is met, the adjusted instruction corresponding to the context instruction is not executed; when the value of the direction identifier indicates that the jump condition of the unpredictable branch is not met, the adjusted instruction corresponding to the context instruction is executed.

[0125] Taking an assembly language fragment from the Reduced Instruction Set Computer (RISC) version 5 architecture as an example, as shown below:

[0126] 10a5a: c299beqza3,10a60

[0127] 10a5c: 031f0963beqt5,a7,10a8e

[0128] 10a60: 97aaadda5,a5,a0

[0129] 10a62: 05b7fd63bgeua5,s11,10abc<main+0x5a4>

[0130] Logical Explanation: First, check if the value of register a3 is 0. If it is 0, jump directly to address 10a60 for address calculation. If the value of register a3 is not 0, continue to check if the values ​​of register t5 and a7 are equal. If they are, jump to address 10a8e. At address 10a60, add the values ​​of register a5 and a0, and store the result back in a5. Finally, verify whether the value of register a5 is greater than the value of register s11 through an unsigned comparison. If it is, jump to address 10abc (marked as offset 0x5a4 of the main function).

[0131] After instruction transformation, the transformed instruction is:

[0132] 10a5a: c299cmpa3,zero,flag1

[0133] The adjusted instructions are as follows:

[0134] 10a5c: 031f0963beq_flag flag1,t5,a7,10a8e

[0135] 10a60: 97aaadda5,a5,a0

[0136] 10a62: 05b7fd63bgeua5,s11,10abc<main+0x5a4>

[0137] Logical explanation: First, check if the value of register a3 is 0, and store the comparison result in the flag1 register; if flag1 is true (a3=0) and t5=a7, skip the addition operation and jump directly to address 10a8e; otherwise, perform the addition operation a5 += a0, and then check if the value of register a5 is greater than or equal to the value of register s11 to decide whether to jump to address 10abc.

[0138] SPEC CPU 2006 is a CPU subsystem benchmark suite released by Standard Performance Evaluation Corporation (SPEC), primarily used to evaluate the integer and floating-point performance of processors.

[0139] After processing, the instructions were tested using the SPEC CPU 2006 test item mcf. The 0x10a5a branch prediction accuracy increased from 94.53% to 96.79%, and the misprediction rate per kilo-instructions (MPKI) decreased from 11.85 to 6.95.

[0140] In this embodiment, the target register can be the current program status register, the flag register can be any general-purpose register, and the output value of the comparison result can be 0 or 1, or true or false. `cmp<register1><register2><flag register>` compares the values ​​of register1 and register2 and stores the comparison result directly in the flag register. Since the result before and after the transformation is consistent, the conditional judgment logic of the instruction will not be changed.

[0141] In summary, the unpredictable branch transformation method provided in this application can perform transformation operations only on unpredictable branch instructions, add only the direction flag to the context instruction, reduce the number of dynamic instructions, thereby reducing pipeline conflicts and scheduling overhead, improving processor performance, and by identifying the target instruction sequence from the instruction sequence, avoid processing all unpredictable branches, thereby reducing the complexity of the transformation algorithm, improving the efficiency of instruction execution, and improving the overall performance of the processor.

[0142] Reference Figure 3 This invention illustrates a difficult-to-predict branch transformation device, which may specifically include the following modules:

[0143] The identification module 310 is used to identify the target instruction sequence from the instruction sequence;

[0144] The transformation module 320 is used to perform an instruction transformation operation on the unpredictable branch instructions in the target instruction sequence to obtain the transformed instructions, and use the branch judgment result of the unpredictable branch instructions as a direction marker.

[0145] The adjustment module 330 adds the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction;

[0146] The execution module 340 executes the transformed instruction and the adjusted instruction corresponding to the context instruction according to the values ​​of each of the direction markers.

[0147] Optionally, the identification module includes:

[0148] The first selection submodule is used to select an instruction sequence that includes the target instruction structure from the instruction sequence as the target instruction sequence.

[0149] Optionally, the identification module includes:

[0150] The first read submodule is used to read instruction sequences from the processor instruction buffer.

[0151] The second selection submodule is used to identify the instruction sequence as a target instruction sequence when the first line instruction in the instruction sequence is a conditional branch instruction and the first line instruction is separated from the branch instruction by at least one context instruction.

[0152] Optionally, the identification module includes:

[0153] The fetch submodule is used to fetch instruction sequences from paths other than the critical path of the processor pipeline.

[0154] The identification submodule is used to identify the target instruction sequence from the instruction sequences on the other paths.

[0155] Optionally, the transformation module includes:

[0156] The transformation submodule transforms the unpredictable branch instructions in the target instruction sequence into transformed instructions.

[0157] Optionally, the transformation module includes:

[0158] The first determining submodule, when determining that the branch judgment condition carried by the unpredictable branch instruction is true, writes the first value into the direction flag.

[0159] The second determining submodule, when it is determined that the branch judgment condition carried by the unpredictable branch instruction is not met, writes the second value into the direction flag.

[0160] Optionally, the adjustment module includes:

[0161] The second read submodule is used to read the direction flag from the flag register;

[0162] A submodule is added to add the direction identifier to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0163] Optionally, the execution module includes:

[0164] The first execution submodule is used to execute only the transformed instruction when the value of the direction indicator is the first value;

[0165] The second execution submodule is used to execute the transformed instruction and the adjusted instruction corresponding to the context instruction when the value of the direction indicator is the second value.

[0166] The device further includes:

[0167] The extraction module is used to extract the output value of the comparison result corresponding to the transformed instruction from the target register specified by the transformed instruction;

[0168] The storage module is used to store the output value of the comparison result into the flag register.

[0169] In summary, the unpredictable branch transformation device provided in this application can perform transformation operations only on unpredictable branch instructions, add only the direction identifier to the context instruction, reduce the number of dynamic instructions, thereby reducing pipeline conflicts and scheduling overhead, improving processor performance, and by identifying the target instruction sequence from the instruction sequence, avoid processing all unpredictable branches, thereby reducing the complexity of the transformation algorithm, improving the efficiency of instruction execution, and improving the overall performance of the processor.

[0170] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0171] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0172] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0173] Reference Figure 4 This is a structural block diagram of an electronic device for unpredictable branch transformations provided in an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the unpredictable branch transformation method of the aforementioned embodiment.

[0174] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0175] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0176] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0177] This invention also provides a non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform... Figure 1 The unpredictable branch transformation method is shown.

[0178] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0179] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0180] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0181] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0182] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0183] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0184] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0185] The present invention provides a detailed description of a method, apparatus, electronic device, and computer-readable storage medium for unpredictable branch transformation. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method of unpredictable branch transformation, comprising: The method comprises: identifying a target instruction sequence from an instruction sequence, the target instruction sequence comprising a difficult-to-predict branch instruction and context instructions of the difficult-to-predict branch instruction; performing an instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker, a value of the direction marker being used to indicate whether the difficult-to-predict branch instruction jumps to a target address; adding the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; executing the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker; the performing of the instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and the taking of a branch judgment result of the difficult-to-predict branch instruction as a direction marker, comprises: transforming the difficult-to-predict branch instruction in the target instruction sequence into a transformed instruction, the transformed instruction being a comparison operation microinstruction type instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker, the transformed instruction being used to calculate the branch judgment of the difficult-to-predict branch.

2. The method of claim 1, wherein, The identifying of a target instruction sequence from an instruction sequence comprises: selecting an instruction sequence comprising a target instruction structure as a target instruction sequence from an instruction sequence; wherein the target instruction structure comprises a difficult-to-predict branch instruction, context instructions and a transfer instruction; the context instructions are located between the difficult-to-predict branch instruction and the transfer instruction; the context instructions comprise at least one of an operation instruction, a load instruction, a store instruction and another conditional branch instruction other than the difficult-to-predict branch instruction; and the target address is an address of the transfer instruction.

3. The method of claim 1, wherein, The method further comprises: extracting an output value of a comparison result corresponding to the transformed instruction from a target register specified by the transformed instruction, the target register being used to store the output value of the comparison result; storing the output value of the comparison result into a flag register.

4. The method of claim 3, wherein, The adding of the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction comprises: reading the comparison result as a direction marker from the flag register; adding the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction.

5. The method of claim 1, wherein, The performing of the instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and the taking of a branch judgment result of the difficult-to-predict branch instruction as a direction marker, comprises: when it is determined that a branch judgment condition carried by the difficult-to-predict branch instruction is established, writing a first value into the direction marker, the first value being used to indicate that an adjusted instruction corresponding to each context instruction is not executed; when it is determined that the branch judgment condition carried by the difficult-to-predict branch instruction is not established, writing a second value into the direction marker, the second value being used to indicate that the adjusted instruction corresponding to the context instruction is executed.

6. The method of claim 5, wherein, The execution of the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker includes: When the value of the direction marker is a first value, only the transformed instruction is executed; When the value of the direction marker is a second value, the transformed instruction and the adjusted instruction corresponding to the context instruction are executed.

7. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: reading the instruction sequence from a processor instruction buffer, the instruction buffer being located in a cache area between a fetch unit and a decode unit; when a first instruction in the instruction sequence is a conditional branch instruction and the first instruction is separated from a transfer instruction by at least one context instruction, identifying the instruction sequence as the target instruction sequence.

8. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: obtaining the instruction sequence from a path other than a critical path of a processor pipeline, the critical path being a longest path of combinational logic; identifying the target instruction sequence from the instruction sequence on the other path.

9. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: when refilling a microinstruction cache, obtaining the instruction sequence from a microinstruction sequence stored in the microinstruction cache; identifying the target instruction sequence from the instruction sequence.

10. A branch prediction conversion apparatus characterized by comprising: The apparatus includes: an identifying module configured to identify a target instruction sequence from an instruction sequence; a transforming module configured to perform an instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and to use a branch judgment result of the difficult-to-predict branch instruction as a direction marker; an adjusting module configured to add the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; an execution module configured to execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker; the transforming module includes a transforming submodule, the transforming submodule is configured to transform the difficult-to-predict branch instruction in the target instruction sequence into the transformed instruction, the transformed instruction being a comparison operation microinstruction type of instruction, and to use the branch judgment result of the difficult-to-predict branch instruction as the direction marker.

11. An electronic device, comprising: include: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method of any one of claims 1 to 9.

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