A chip fault testing method and electronic device

Abstract

The application discloses a chip fault test method and electronic equipment, relates to the technical field of fault test, and is applied to a chip fault test system. The method comprises the following steps: a substrate signal control module generates a fault instruction corresponding to at least one to-be-tested function of a to-be-tested chip; a fault signal analysis module analyzes the generated fault instruction, obtains a fault type, and triggers the to-be-tested chip to enter a fault state based on the fault instruction; in response to the to-be-tested chip entering the fault state, register data and black box data are acquired; based on the register data, the black box data and the fault type, a test result is acquired; when the test result indicates that the to-be-tested function is normal, a fault recovery module cancels the fault state, and the test of the next to-be-tested function is circularly performed; when the test result indicates that the to-be-tested function is abnormal, the fault recovery module keeps the to-be-tested chip in the fault state. The application solves the problem of low chip fault test efficiency in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of fault testing, and in particular to a chip fault testing method and electronic equipment. BACKGROUND

[0002] The server voltage regulator (VR) black box is a core module for recording system operation logs and error information, and the integrity and accuracy of its data directly affect the fault diagnosis efficiency. The black box function verification needs to traverse each VR on the server board and all important error types.

[0003] Currently, the traditional VR black box function verification relies on manual simulation of error scenarios or passive waiting for real faults to occur, which has problems such as low error injection efficiency, incomplete scene coverage, difficulty in reproducing complex errors, and the like. Moreover, the artificially simulated faults are independent of each other and lack unified management. In related technologies, the protection threshold needs to be adjusted separately, and external hardware devices such as pull fixtures and voltage sources are used to create faults to trigger VR protection, and then verify whether the VR black box register value is correct. This method has a single error injection method, and the process of traversing each VR on the server motherboard is lengthy and tedious to operate, which not only is inefficient, but also leads to high labor costs.

[0004] Therefore, the related art has the technical problem of low chip fault testing efficiency. SUMMARY

[0005] The present application provides a chip fault testing method and electronic equipment to at least solve the problem of low chip fault testing efficiency in the related art.

[0006] The present application provides a chip fault testing method applied to a chip fault testing system, the testing system comprising a substrate signal control module, a fault signal analysis module, a register verification module, a fault recovery module, a chip to be tested, a register, and a black box. The chip to be tested internally includes the register and the black box, and the black box is used to record the state of the register. The method comprises:

[0007] The substrate signal control module generates a fault instruction corresponding to at least one function to be tested of the chip to be tested;

[0008] The fault signal analysis module analyzes the fault instruction generated by the substrate signal control module to obtain a fault type, and triggers the chip to be tested to enter a fault state based on the fault instruction;

[0009] In response to the chip under test entering the fault state, the register verification module acquires register data and black box data; wherein, the register data is used to characterize the internal state of the chip under test when it is faulty, and the black box data is used to characterize the fault events and fault information recorded by the black box;

[0010] The register verification module obtains the test results based on the register data, the black-box data, and the fault type;

[0011] When the test result indicates that the function under test is normal, the fault recovery module removes the fault state and executes the test of the next function under test in a loop;

[0012] When the test result indicates that the function under test is abnormal, the fault recovery module keeps the chip under test in the fault state.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of the test method for any of the above-described chip faults when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the test method for any of the above-described chip faults.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the test method for any of the above-described chip faults.

[0016] This application enables automated generation of fault commands, parsing of fault types, and verification of relevant data, achieving proactive triggering testing of multiple functions of the chip under test. Fault coverage and cyclic testing can be completed without manual intervention, which improves testing efficiency and the completeness of fault coverage while reducing manual operation costs. At the same time, the design of automatically restoring normal functions to advance testing and maintaining abnormal states for easy troubleshooting further simplifies the testing process, providing an efficient, convenient, and reliable solution for chip fault testing. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a chip fault testing system provided in an embodiment of this application;

[0019] Figure 2 This is one of the flowcharts illustrating a chip fault testing method provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram of a fault type provided in an embodiment of this application;

[0021] Figure 4 This is a second schematic flowchart of a chip fault testing method provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] This application provides a chip fault testing system, and the method is described in detail below with reference to the execution flow of the chip fault testing system. Figure 1 The diagram shown is a schematic of the structure of a chip fault testing system provided in this application embodiment. The chip fault testing system 100 includes: a substrate signal control module 101, a fault signal parsing module 102, a register verification module 103, a fault recovery module 104, a chip under test 105, a register 106, a black box 107, and an adjustment module 108.

[0026] The system includes a register and a black box, with the black box recording the register's state. A substrate signal control module 101 is connected to a fault signal analysis module 102, the other end of which is connected to the chip under test 105 and an adjustment module 108, and also to a register verification module 103. The chip under test 105 is connected to the adjustment module 108, which in turn is connected to the register verification module 103 and a fault recovery module 104. The register verification module 103 is connected to the fault recovery module 104, and the other end of the fault recovery module 104 is connected to the chip under test 105 and the substrate signal control module 101. This system is an integrated system for automatically injecting faults and verifying the black box's functionality.

[0027] The substrate signal control module 101 acts as the command initiator of the test system, and its core function is to generate standardized fault commands. The command types correspond to four key faults: overcurrent protection (OCP), overvoltage protection (OVP), undervoltage protection (UVP), and overtemperature protection (OTP). Each command corresponds one-to-one with a function under test in the chip 105. The substrate signal control module 101 can generate commands in a preset order to ensure full coverage of all functions under test, while simultaneously receiving feedback signals from the fault recovery module 104 to trigger the next round of testing or terminate the process.

[0028] The fault signal parsing module 102 is responsible for receiving fault commands from the substrate signal control module 101 and parsing them to obtain a clear fault type. Its core function is to link with the adjustment module 108, which converts the parsed commands into specific operation commands; that is, to drive the adjustment module 108 to adjust the corresponding protection threshold and sensor readings of the chip under test 105, triggering the fault without external hardware; at the same time, the fault signal parsing module 102 will synchronously transmit the parsed fault type to the register verification module 103.

[0029] The adjustment module 108 (also known as the VR dongle) executes the operation instructions of the fault signal analysis module 102: for different fault types, it adjusts the protection threshold of the chip under test 105; and simultaneously modifies the reading value of the internal sensor of the chip so that the reading value exceeds the adjusted threshold, thereby triggering the chip under test 105 to enter the corresponding fault state.

[0030] For example, for overcurrent protection faults, the OCP threshold can be lowered to 10% of the chip's full load current to ensure that it can be triggered by slight current fluctuations; for overtemperature protection faults, the OTP threshold can be set slightly above room temperature to lower the trigger threshold; for overvoltage protection faults, the OVP threshold can be lowered to be close to the normal output voltage; for undervoltage protection faults, the UVP threshold can be raised to be close to the normal output voltage.

[0031] The chip under test 105 (also known as the VR chip) is the test object, which includes register 106 and black box 107. The register 106 and black box 107 integrated inside the chip under test 105 are the fault data recording terminals.

[0032] Register 106 stores the internal real-time status data of the chip at the moment of failure, including the original physical parameters such as current value, voltage value, temperature value, and activation status of protection mechanism at the time of failure.

[0033] The black box 107 is specifically used to record structured information about fault events, including fault type identifier, fault occurrence time, associated chip module and other summary information, and will also record the state changes of register 106 in a synchronous manner.

[0034] The register verification module 103 obtains the test results through triple data comparison: it compares the original data of register 106 with the black box data of black box 107, i.e., the structured log, to verify the consistency of the records. For example, if the register displays a current of 12A, the black box should record an OCP overcurrent fault.

[0035] The above comparison results are compared with the fault type transmitted by the fault signal analysis module 102 to verify whether the actual triggered fault is consistent with the preset test target; if both comparisons are consistent, the function under test is normal; if either comparison is inconsistent, the function is abnormal, and the result is fed back to the fault recovery module 104.

[0036] The fault recovery module 104 performs two types of operations based on the result of the register verification module 103: If the test result is normal, it sends a fault clearance instruction to the chip under test 105 to restore it to normal working state, and at the same time feeds back a signal to the substrate signal control module 101 to trigger the generation of the next fault instruction and advance the cyclic test.

[0037] If the test result is abnormal: control the chip under test 105 to maintain the current fault state, so that technicians can troubleshoot the problem through register data and black box log.

[0038] This application provides a chip fault testing method. The method is described in detail below, combining the execution flow of the chip fault testing method with the aforementioned chip fault testing system. (Refer to...) Figure 2 The diagram shown is a flowchart illustrating the chip fault testing method provided in this application embodiment. The specific steps include the following:

[0039] S201. Generate a fault instruction corresponding to at least one function under test of the chip under test.

[0040] Specifically, the first step is to determine the core protection functions that the chip under test needs to verify, i.e. the functions to be tested. These typically include at least four basic and critical functions: overcurrent protection (OCP), overtemperature protection (OTP), overvoltage protection (OVP), and undervoltage protection (UVP).

[0041] For each function to be tested, the baseboard signal control module generates a standardized fault command based on a preset automated test sequence. For example, an OCP test command is generated for the overcurrent protection function, and an OTP test command is generated for the overtemperature protection function. Each command contains two core pieces of information: first, a fault type identifier, used by subsequent modules to identify the test target; and second, trigger parameter prompts, providing the fault signal analysis module with an operational basis.

[0042] Automated test sequences can be predefined in configuration files or dynamically issued by upper-level test management software, ensuring programmability and high coverage of the testing process. The substrate signal control module sends encapsulated fault commands to the subsequent fault signal parsing module via the system bus or communication interface, thereby initiating a complete automated test process.

[0043] In this embodiment, standardized fault instructions corresponding one-to-one with the core protection functions of the chip under test are generated by the substrate signal control module. This not only clarifies the precise targets for subsequent fault triggering and verification, but also ensures that key protection functions such as overcurrent, overtemperature, overvoltage, and undervoltage are not missed through the full-coverage and sequential instruction design. This lays the foundation for the automated loop of the entire test process, while avoiding instruction confusion or test blind spots caused by manual intervention, and greatly improving the standardization and overall efficiency of chip fault testing.

[0044] S202. Parse the fault command to obtain the fault type, and trigger the chip under test to enter the fault state based on the fault command.

[0045] Specifically, this step is performed by the fault signal parsing module. This module receives fault commands from the substrate signal control module, determines the specific fault type to be simulated in this test by parsing the fault code field inside the fault command, and then actively triggers the chip under test to enter the corresponding fault state by adjusting parameters, replacing the cumbersome traditional method that relies on external hardware; the fault types include at least: overcurrent protection fault, overtemperature protection fault, overvoltage protection fault, and undervoltage protection fault.

[0046] Specifically, the above S202 can be further refined into the following steps 2021 and 2022:

[0047] Step 2021: Determine the safety threshold and adjustment strategy based on the fault type.

[0048] Among them, the safety threshold, also known as the VR chip native protection threshold, is a safety threshold set at the factory. It can include: overcurrent protection threshold (OCP threshold), overtemperature protection threshold (OTP threshold), overvoltage protection threshold (OVP threshold), and undervoltage protection threshold (UVP threshold).

[0049] Based on the identified fault type, the fault signal analysis module retrieves the corresponding adjustment strategy from a pre-defined configuration library. This strategy clearly specifies the specific threshold objects to be adjusted, the adjustment direction, and the sensor readings that need to be modified accordingly.

[0050] For example, for overcurrent protection faults, the adjustment strategy could be to lower the overcurrent protection threshold and simultaneously increase the current sensor reading reported by the chip under test (DBT) so that the reading exceeds the newly set threshold. For overtemperature protection faults, the adjustment strategy could be to lower the overtemperature protection threshold and simultaneously increase the temperature sensor reading reported by the DBT so that the reading exceeds the newly set threshold. For overvoltage protection faults, the adjustment strategy could be to lower the overvoltage protection threshold and simultaneously increase the voltage sensor reading reported by the DBT so that the reading exceeds the newly set threshold. For undervoltage protection faults, the adjustment strategy could be to raise the undervoltage protection threshold and simultaneously lower the voltage sensor reading reported by the DBT so that the reading falls below the newly set threshold.

[0051] Figure 3 A schematic diagram of a fault type provided in an embodiment of this application, such as Figure 3 As shown, the fault types are mainly divided into four parts. When the fault is overcurrent protection (OCP), the OCP threshold and the current sensor reading of the VR chip need to be considered. To simulate the occurrence of the fault, no external hardware devices are used, so the OCP threshold and sensor reading need to be changed simultaneously. First, the OCP threshold is adjusted to an appropriate value using the adjustment module, for example, reduced to about 10% of the full load current. Then, the current sensor reading of the VR chip is adjusted so that the sensor reading is higher than this current, which triggers the overcurrent protection of the VR chip. After the VR chip fails, the register data exported by the adjustment module and the black box data are transmitted to the register verification module for comparison, and compared with the parsed fault signal to determine the fault type.

[0052] When the fault is over-temperature protection (OTP), the OTP threshold and the temperature sensor reading of the VR chip must be considered. To simulate the fault occurrence, external hardware devices such as hot air guns are not used for heating; therefore, both the OTP threshold and the sensor reading need to be changed simultaneously. First, the OTP threshold is adjusted to an appropriate value using the adjustment module, for example, by lowering it a few degrees Celsius above room temperature. Then, the temperature sensor reading of the VR chip is adjusted so that the reading exceeds this temperature, triggering the VR chip's over-temperature protection. After the VR chip faults, the register data exported by the adjustment module and the black-box data are transmitted to the register verification module for comparison. This comparison is then compared with the parsed fault signal to determine the fault type.

[0053] When the fault is overvoltage protection (OVP), two points need to be adjusted: the OVP threshold and the voltage sensor reading of the VR chip. Since external hardware devices such as a loading fixture are not used to simulate a fault, both the OVP threshold and the sensor reading need to be changed simultaneously. First, use the VR dongle to adjust the OVP threshold in the software to an appropriate value, such as directly lowering the OVP or adjusting it slightly higher than VID. Then, adjust the voltage sensor reading of the VR chip so that a reading higher than this voltage triggers the VR chip's overvoltage protection. After the chip faults, the register data exported by the VR dongle is compared with the black-box log to the register verification module, and then compared with the parsed fault signal to determine the fault type.

[0054] When the fault is undervoltage protection (UVP), it is necessary to consider adjusting the UVP threshold and the voltage sensor reading of the VR chip. To simulate the fault occurrence without external hardware, both the UVP threshold and the sensor reading need to be changed simultaneously. First, use the adjustment module to adjust the UVP threshold to an appropriate value, such as directly increasing UVP or adjusting UVP slightly below VID. Then, adjust the voltage sensor reading of the VR chip so that the reading is lower than this voltage, triggering the VR chip's undervoltage protection. After the VR chip faults, the register data exported by the adjustment module and the black-box data are transmitted to the register verification module for comparison, and then compared with the parsed fault signal to determine the fault type.

[0055] Step 2022: Based on the adjustment strategy, adjust the safety threshold and the sensor readings of the chip under test to trigger the chip under test to enter a fault state.

[0056] The sensor readings include at least current, voltage, and temperature values.

[0057] This step is implemented through the adjustment module. The fault signal parsing module sends specific operation commands to the adjustment module, which then performs the adjustment operation on the chip under test using a standard communication protocol.

[0058] The adjustment module writes the corresponding threshold into the register of the chip under test according to the adjustment strategy in step 2021; and simultaneously modifies the real-time reading of the corresponding sensor inside the chip to make it exceed the adjusted threshold.

[0059] For example, when testing for overcurrent, the current sensor reading is changed from the normal 5A to 2A (exceeding the adjusted OCP threshold of 1A), triggering overcurrent protection; when testing for overtemperature, the temperature sensor reading is changed from the normal 30℃ to 38℃ (exceeding the adjusted OTP threshold of 35℃), triggering overtemperature protection.

[0060] In this embodiment, by locking the corresponding safety threshold based on the fault type and formulating a targeted adjustment strategy, the target of fault triggering is clear and the operation is standardized, avoiding test chaos caused by blind adjustment. Based on the strategy, the safety threshold and sensor readings are adjusted by software to trigger the fault, without relying on external hardware such as load jigs and hot air guns. This simplifies the test operation, reduces hardware costs, and can simulate various fault scenarios such as overcurrent and overtemperature. It provides a controllable and reliable fault state for subsequent verification of the effectiveness of the chip protection function, and greatly improves the efficiency of fault triggering.

[0061] S203. In response to the chip under test entering a fault state, acquire register data and black box data.

[0062] Register data is used to characterize the internal state of the chip under test when it fails, including raw physical parameters such as current, voltage, and temperature values ​​at the time of the fault, as well as low-level information such as the activation status of the protection mechanism and timestamps. This data is a raw snapshot of the chip's fault state, directly reflecting the physical details of the moment of the fault. Black-box data is used to characterize the fault events and fault information recorded by the black box, including fault type identifier, fault occurrence time, associated chip module information, core parameter summary, etc. It is a structured extraction of fault events, which facilitates the rapid location of core fault information.

[0063] Specifically, once the chip under test is successfully triggered and enters a fault state, the test system immediately initiates the data acquisition process. The adjustment module directly reads the register data latched or updated by the chip's internal register array at the moment of the fault through its communication link with the chip under test; at the same time, the test system reads the fault log recorded by the black box, i.e., black box data.

[0064] S204. Obtain test results based on register data, black-box data, and fault type.

[0065] Specifically, the register verification module first compares register data with black-box data to verify whether the black-box records accurately reflect the actual fault state of the chip. Then, it compares the fault condition indicated by both data with preset fault types to verify whether the chip has triggered the expected protection function. This method, based on cross-verification of three types of data, forms a complete data loop of original state, record verification, and functional verification. This avoids misjudgments caused by a single data source and ensures that the test results directly reflect the true performance of the black-box and chip protection functions, providing authoritative evidence for subsequent fault handling.

[0066] S205. When the test result indicates that the function under test is normal, the fault status is cleared, and the test of the next function under test is executed in a loop.

[0067] This step, performed by the fault recovery module, is crucial for achieving automated testing cycles. Once the register verification module receives a normal test indication, the fault recovery module removes the fault status.

[0068] The fault recovery module, through the control and adjustment module, restores the safety threshold that was previously modified to trigger the fault to its normal default value or safe range, restores the previously modified sensor readings to values ​​that reflect the actual operating state of the chip, and sends a command to the chip under test to clear the fault state, causing it to exit the protection mode.

[0069] Once the test results indicate that the function under test is normal and the fault state is cleared, to ensure the system has fully recovered and is ready for the next test, the fault recovery module will obtain the output voltage of the chip under test through the adjustment module. When the output voltage is detected to be stable within the preset normal operating range, it is determined that the chip under test has recovered. After confirming that the chip under test has recovered, the fault recovery module sends a ready or test completed signal to the substrate signal control module. Upon receiving this signal, the substrate signal control module automatically retrieves the fault command corresponding to the next function under test from its preset test sequence and issues it, thereby initiating a new round of error injection, verification, and recovery process.

[0070] In this embodiment, when the test result is normal, the fault state is automatically lifted and the next functional test is executed in a loop. This ensures that the chip under test returns to normal working state through fault recovery, avoiding interference from the current fault with subsequent tests and guaranteeing the independence and accuracy of the test. Furthermore, the automated loop mechanism achieves sequential full coverage of all functions under test, such as overcurrent and overtemperature, without the need for manual intervention. This solves the problems of cumbersome and inefficient manual switching of test scenarios in traditional testing, significantly improving the overall testing efficiency while ensuring the integrity of the test. It provides continuous and smooth process support for the comprehensive verification of the chip's protection functions.

[0071] S206. When the test result indicates that the function under test is abnormal, keep the chip under test in a fault state.

[0072] Specifically, when the register verification module determines that the test result is abnormal, the test system will execute the reverse process. Upon receiving the indication of a test anomaly, the fault recovery module will not perform any recovery operations but will maintain the current fault state of the chip under test. At this time, the system will send a clear alarm signal to the upper-level system or test engineer through a preset communication interface. By maintaining the fault state, the chip's internal register configuration, sensor readings, and log records in the black box are frozen at the moment the fault occurred, providing complete and tamper-proof fault data for subsequent problem localization.

[0073] In this embodiment, when the test result indicates that the function under test is abnormal, the fault state of the chip under test is maintained, and the on-site environment and data at the time of the fault are completely preserved, avoiding the loss of key troubleshooting information due to automatic fault recovery; it provides technicians with real and undistorted fault scenario support to locate the root cause of the problem, and reduces the tedious operation of repeatedly triggering the fault, greatly improving the efficiency and pertinence of problem troubleshooting, and ensuring the closed-loop nature and reliability of chip fault testing.

[0074] In the above solution, by automatically generating fault commands, parsing fault types, and verifying relevant data, proactive triggering testing of multiple functions to be tested on the chip under test is realized. Fault coverage and cyclic testing can be completed without manual intervention, which not only improves testing efficiency and the completeness of fault coverage, but also reduces manual operation costs. At the same time, the design of automatically restoring normal functions to advance testing and maintaining abnormal states for easy troubleshooting further simplifies the testing process, providing an efficient, convenient, and reliable solution for chip fault testing.

[0075] As an extension and refinement of the above embodiments, refer to Figure 4 As shown, this application also provides a method for testing chip faults, the specific steps of which include the following:

[0076] S2041. Compare the register data with the black-box data to obtain the comparison result.

[0077] The register verification module parses the fault flag status in the register data and compares it with the fault cause recorded in the black box data to obtain the comparison result.

[0078] S2042. Determine whether the comparison result is consistent with the register data and the black box data.

[0079] If the comparison result shows that the register data and the black-box data are consistent, execute S2043; if the comparison result shows that the register data and the black-box data are inconsistent, execute S2046.

[0080] S2043. Compare the comparison results with the fault types to obtain the test results.

[0081] When the comparison result shows that the register data and the black box data are consistent, it indicates that the black box record matches the chip's underlying state. Based on this, the comparison result is compared with the fault type sent by the fault signal parsing module to obtain the test result and verify whether the fault actually triggered by the chip matches the test target.

[0082] S2044. Determine whether the test result is consistent with the comparison result and the fault type.

[0083] If the test result is consistent with the fault type, execute S2045; if the test result is inconsistent with the fault type, execute S2046.

[0084] S2045. The test result confirms that the function under test is normal.

[0085] When the test result is consistent with the comparison result and the fault type, it indicates that the chip protection function is working as expected. Based on this, it is determined that the test result shows that the function under test is normal.

[0086] S2046. The test result indicates that the function under test is abnormal.

[0087] When the comparison result shows that the register data and the black box data are inconsistent, it indicates that the black box's recording function itself is defective (e.g., missing or incorrect recording); based on this, the test result is determined to be an anomaly of the function under test.

[0088] When the test result is inconsistent with the comparison result and the fault type, it indicates that although the black box and register data are consistent, the recorded fault type is not the expected fault type, and there is an identification error; based on this, the test result is determined to be an abnormality of the function under test.

[0089] In this embodiment, a dual verification mechanism, which compares register data with black-box data and consistent results with fault types, ensures the authenticity of the black-box records and verifies the accuracy of the chip protection function triggering, forming a complete data closed loop. This layered verification logic solves the problem of misjudgment caused by a single data source in traditional testing. It not only improves the accuracy of test results but also quickly locates the problem link when the function is abnormal, providing a clear direction for subsequent fault investigation and greatly enhancing the reliability and efficiency of chip fault testing.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0091] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described chip fault test method embodiments.

[0092] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described chip fault test method embodiments when running.

[0093] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0094] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described chip fault testing method embodiments.

[0095] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described chip fault testing method embodiments.

[0096] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The present application provides a detailed description of a chip fault testing method and apparatus. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method of testing for a chip failure, characterized by, The application is applied to a test system for chip failure, and the test system comprises a substrate signal control module, a failure signal analysis module, a register verification module, a failure recovery module, a chip to be tested, a register and a black box; wherein the chip to be tested internally comprises the register and the black box, and the black box is used for recording the state of the register; the method comprises: The substrate signal control module generates a failure instruction corresponding to at least one function to be tested of the chip to be tested; The failure signal analysis module analyzes the failure instruction generated by the substrate signal control module, obtains a failure type, and triggers the chip to be tested to enter a failure state based on the failure instruction; In response to the chip to be tested entering the failure state, the register verification module acquires register data and black box data; wherein the register data is used for representing the internal state of the chip to be tested when the chip to be tested fails, and the black box data is used for representing the failure event and failure information recorded by the black box; The register verification module acquires a test result based on the register data, the black box data and the failure type; When the test result indicates that the function to be tested is normal, the failure recovery module cancels the failure state and cyclically executes the test of the next function to be tested; When the test result indicates that the function to be tested is abnormal, the failure recovery module keeps the chip to be tested in the failure state; Wherein, the register verification module acquires a test result based on the register data, the black box data and the failure type, comprising: the register verification module compares the register data with the black box data to obtain a comparison result; when the register data is consistent with the black box data, and the comparison result is consistent with the failure type, it is determined that the test result is that the function to be tested is normal; when the register data is consistent with the black box data, and the comparison result is inconsistent with the failure type, it is determined that the test result is that the function to be tested is abnormal; when the register data is inconsistent with the black box data, it is determined that the test result is that the function to be tested is abnormal.

2. The method of claim 1, wherein, The test system further comprises an adjustment module connected with the failure signal analysis module and the chip to be tested; the failure signal analysis module analyzes the failure instruction generated by the substrate signal control module to obtain a failure type, and triggers the chip to be tested to enter a failure state based on the failure instruction, comprising: The failure signal analysis module determines a safety threshold and an adjustment strategy based on the failure type; wherein the safety threshold at least comprises an overcurrent protection threshold, an overtemperature protection threshold, an overvoltage protection threshold and an undervoltage protection threshold; The adjustment module adjusts the safety threshold and the sensor reading value of the chip to be tested based on the adjustment strategy determined by the failure signal analysis module, so as to trigger the chip to be tested to enter the failure state; wherein the sensor reading value at least comprises a current value, a voltage value and a temperature value.

3. The method of claim 1, wherein, The test result indicates that the function to be tested is normal, the fault recovery module releases the fault state, and the test of the next function to be tested is executed in a loop, comprising: After the fault recovery module releases the fault state when the function to be tested is normal, it is determined whether the chip to be tested returns to normal; After the chip to be tested returns to normal, the test of the next function to be tested is executed in a loop.

4. The method of claim 3, wherein, After the fault recovery module releases the fault state when the function to be tested is normal, it is determined whether the chip to be tested returns to normal, comprising: Obtaining the output voltage of the chip to be tested; When the output voltage is within the normal range, it is determined that the chip to be tested returns to normal.

5. The method of claim 1, wherein, The fault types at least include overcurrent protection fault, overtemperature protection fault, overvoltage protection fault and undervoltage protection fault.

6. The method according to any one of claims 1 to 5, characterized in that, The adjusting module is connected with the register data verification module, and is used to send the register data obtained from the chip to be tested and the black box data to the register data verification module.

7. An electronic device, comprising: Comprising: A memory for storing a computer program; A processor for executing the computer program to realize the steps of the chip fault test method according to any one of claims 1 to 6.

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