An accurate behavior analysis system and method for a vivado synthesizer security state machine

Abstract

The application discloses a kind of accurate behavior analysis system and method for Vivado synthesizer security state machine, including training class management module, south gate access control management module, training apartment lock management module and system management module;The application realizes the integrated intelligent management of training center sign-in management, access control, attendance statistics by integrating face recognition technology and information management means.The linkage of training class management module and access control management module ensures that student face information is input once, and is used in multiple areas, reducing repetitive input work;Mobile phone end sign-off function combined with private network WiFi restriction not only facilitates student sign-off, but also avoids remote clocking cheating behavior;Real-time attendance reminder function enables class teacher to timely grasp student attendance, improving management efficiency.

Description

Technical Field

[0001] This invention relates to the field of FPGA testing technology, specifically to a precise behavior analysis system and method for the safety state machine of the Vivado synthesizer. Background Technology

[0002] Finite state machines are a widely used design method in digital logic circuit design. They can efficiently perform synchronous sequential logic processing and are a typical design approach for implementing complex processing flows. They are frequently used in programmable logic circuits such as FPGAs.

[0003] In applications with high safety requirements, such as aerospace, aviation, missile weapons, and nuclear power, single-event effects can occur due to external factors such as radiation and the space environment. Therefore, it is necessary to avoid errors or deadlocks when designing and using state machines. Previous research has mainly focused on protecting state machines in RTL code design, such as strengthening the protection of RAM contents through error correction and detection coding, using dual-redundant RAM blocks to detect state machine errors, and combining self-detection and triple modular redundancy to monitor and correct state machine errors.

[0004] When synthesizing RTL code, FPGA synthesizers perform a series of transformations and optimizations, including introducing state machine safety implementations. Liszewski et al. proposed a process using a constraint solver to reverse-engineer the synthesized gate-level netlist, but this method is cumbersome and cannot intuitively reflect the behavior of the synthesized state machine. Previous methods for logical equivalence analysis of finite state machines based on ASIC verification processes exist; however, these methods have limited application scope and do not consider the full state space situation of the state machine after Vivado synthesis with safety implementation settings.

[0005] Therefore, there is an urgent need for a system and method that can use formal logical equivalence to accurately analyze the gate-level implementation behavior of the Vivado synthesizer's safe state machine, so as to obtain an intuitive description of the behavior of the finite state machine in the full state space. Summary of the Invention

[0006] The purpose of this invention is to provide a precise behavior analysis system and method for the Vivado synthesizer's security state machine, in order to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a precise behavior analysis system for the Vivado synthesizer security state machine, comprising a gate-level netlist loading module, a state coding analysis module, an RTL code modification module, a logical equivalence verification module, and a behavior analysis module;

[0008] The gate-level netlist loading module is responsible for loading the gate-level netlist after the integrated layout and routing is completed, as the implementation design IMPL. The state machine in the IMPL has been implemented safely.

[0009] The state coding analysis module determines the coding method of the synthesized state machine and the number of register bits of the gate-level state machine based on the synthesis constraint settings and the synthesis report (vds) file output by Vivado.

[0010] The RTL code modification module modifies the definition and encoding settings of the state registers according to the gate-level state machine, and selects the corresponding module for configuration;

[0011] The logical equivalence verification module loads the RTL code as the reference design REF, performs matching, verification, and debugging operations, and realizes the logical equivalence verification between the REF and IMPL.

[0012] After successful verification, the behavior analysis module performs precise analysis of the behavior of the synthesized safety state machine by analyzing the RTL code.

[0013] Preferably, the matching operation of the logical equivalence verification module achieves the correspondence of all driving points and comparison points in REF and IMPL, with a focus on solving the correspondence of state machine registers; if a one-to-one correspondence cannot be achieved, the RTL code modification module is triggered to modify the RTL code again.

[0014] Preferably, the verification operation of the logical equivalence verification module traverses the state space formed by the driving points and checks whether each comparison point satisfies logical equivalence.

[0015] Preferably, the debugging operation of the logic equivalence verification module targets unequal comparison points, analyzes the pattern of the driving points, and combines methods such as gate-level simulation to infer the actual behavior of the gate-level circuit, triggering the RTL code modification module to modify the RTL code again until the verification is successful.

[0016] An analysis method for a precise behavioral analysis system for the Vivado synthesizer's security state machine includes the following steps:

[0017] Step 1: Load the gate-level netlist: The gate-level netlist loading module loads the gate-level netlist after synthesis, placement and routing, as the implementation design IMPL. The state machine in the IMPL has been safely implemented.

[0018] Step 2: Analyze State Coding: The state coding analysis module determines the coding method of the synthesized state machine and the number of register bits of the gate-level state machine based on the synthesis constraint settings and the synthesis report (vds) file output by Vivado.

[0019] Step 3: Modify RTL code: The RTL code modification module modifies the definition and encoding settings of the state registers according to the gate-level state machine. Select the appropriate module for configuration.

[0020] Step 4: Perform logical equivalence verification: The logical equivalence verification module loads the RTL code as the reference design REF;

[0021] Step 5: Analyze state machine behavior: The behavior analysis module analyzes and verifies the RTL code after successful verification, realizing an accurate analysis of the behavior of the synthesized safe state machine, and obtaining an intuitive description of the behavior of the finite state machine in the full state space, including the state transition function and output function after safety is achieved.

[0022] Preferably, step 4 includes the following sub-steps:

[0023] 1) Perform a matching operation to establish the correspondence between all driving points and comparison points in REF and IMPL, with a focus on resolving the correspondence between state machine registers; if a one-to-one correspondence cannot be achieved, return to step 3 to modify the RTL code;

[0024] 2) Perform verification operations, traverse the state space formed by the driving points, and check whether each comparison point satisfies logical equivalence;

[0025] 3) For unequal comparison points, perform debugging operations, analyze the pattern of the driving point, and combine the gate-level simulation method to infer the actual behavior of the gate-level circuit. Return to step 3 to modify the RTL code until the verification is successful.

[0026] Compared with the prior art, the beneficial effects of the present invention are:

[0027] This invention proposes a precise analysis method for the gate-level implementation behavior of state machines. Through a formal logical equivalence method, without using constraints such as state machine recoding, it achieves numerical comparisons of the entire state space of a secure state machine, accurately obtaining all gate-level behaviors. Based on the analysis results, the precise behaviors of four secure state machine implementations in the Vivado synthesizer can be clearly defined, providing key guidance for state machine design in high-security application scenarios. For example, it clarifies design considerations for different secure implementation modes, avoids the impact of uncertainties introduced during synthesis, and effectively improves the security and reliability of state machine design, possessing significant engineering application value. Attached Figure Description

[0028] Figure 1 This is a system schematic diagram of the present invention;

[0029] Figure 2 This is a flowchart of the method of the present invention. Detailed Implementation

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1-2 This invention provides a precise behavior analysis system and method for the secure state machine of the Vivado synthesizer, including a gate-level netlist loading module, a state coding analysis module, an RTL code modification module, a logical equivalence verification module, and a behavior analysis module;

[0032] The gate-level netlist loading module is responsible for loading the gate-level netlist after the integrated layout and routing are completed, which serves as the implementation design IMPL. The state machine in this IMPL has been safely implemented.

[0033] The state coding analysis module determines the coding method of the synthesized state machine and the number of register bits of the gate-level state machine based on the synthesis constraint settings and the synthesis report (vds) file output by Vivado.

[0034] The RTL code modification module modifies the definition and encoding settings of the state registers according to the gate-level state machine, and selects the appropriate module for configuration;

[0035] The logic equivalence verification module loads the RTL code as the reference design REF, performs matching, verification, and debugging operations, and realizes the logic equivalence verification between the REF and IMPL.

[0036] After successful verification, the behavior analysis module performs precise analysis of the behavior of the synthesized safety state machine by analyzing the RTL code.

[0037] The matching operation of the logical equivalence verification module achieves the correspondence between all driving points and comparison points in REF and IMPL, with a focus on the correspondence of state machine registers; if a one-to-one correspondence is not achieved, the RTL code modification module is triggered to modify the RTL code again.

[0038] The verification operation of the logical equivalence verification module traverses the state space formed by the driving points and checks whether each comparison point satisfies logical equivalence.

[0039] The debugging operation of the logic equivalence verification module targets unequal comparison points, analyzes the pattern of the driving points, and combines gate-level simulation and other methods to infer the actual behavior of the gate-level circuit. This triggers the RTL code modification module to modify the RTL code again until the verification is successful.

[0040] An analysis method for a precise behavioral analysis system for the Vivado synthesizer's security state machine includes the following steps:

[0041] Step 1: Load the gate-level netlist: The gate-level netlist loading module loads the gate-level netlist after synthesis, placement and routing, as the implementation design IMPL. The state machine in the IMPL has been safely implemented.

[0042] Step 2: Analyze State Coding: The state coding analysis module determines the coding method of the synthesized state machine and the number of register bits of the gate-level state machine based on the synthesis constraint settings and the synthesis report (vds) file output by Vivado.

[0043] Step 3: Modify RTL code: The RTL code modification module modifies the definition and encoding settings of the state registers according to the gate-level state machine. Select the appropriate module for configuration.

[0044] Step 4: Perform logical equivalence verification: The logical equivalence verification module loads the RTL code as the reference design REF and performs the following sub-steps:

[0045] 1) Perform a matching operation to establish the correspondence between all driving points and comparison points in REF and IMPL, with a focus on resolving the correspondence between state machine registers; if a one-to-one correspondence cannot be achieved, return to step 3 to modify the RTL code;

[0046] 2) Perform verification operations, traverse the state space formed by the driving points, and check whether each comparison point satisfies logical equivalence;

[0047] 3) For unequal comparison points, perform debugging operations, analyze the pattern of the driving point, and combine the gate-level simulation method to infer the actual behavior of the gate-level circuit. Return to step 3 to modify the RTL code until the verification is successful.

[0048] Step 5: Analyze state machine behavior: The behavior analysis module analyzes and verifies the RTL code after successful verification, realizing an accurate analysis of the behavior of the synthesized safe state machine, and obtaining an intuitive description of the behavior of the finite state machine in the full state space, including the state transition function and output function after safety is achieved.

[0049] Example:

[0050] Scene background:

[0051] A precise behavioral analysis was performed on the four safe state machine implementations in the Vivado synthesizer.

[0052] This invention provides a method for accurate behavioral analysis of the Vivado synthesizer's security state machine, comprising the following steps:

[0053] Step 1: Load the gate-level netlist: Code samples are selected from IWLS 2005 Benchmarks. There are 84 sets of design code in IWLS 2005 Benchmarks, divided into several code sample sets such as ICT99, ISCAS 85 and 89, OpenCores, Gaisler Research, and Faraday Technology Corporation. Design code containing state machines is selected as samples, covering both VHDL and Verilog languages. After synthesis, placement and routing by the Vivado synthesizer, the gate-level netlist loaded by the gate-level netlist loading module is used as the IMPL. The state machines in this netlist have been configured with four safe implementation modes: auto_safe_state, reset_state, power_on_state, and default_state.

[0054] Step 2: Analyze state coding: The state coding analysis module reads the comprehensive constraint file and the corresponding VDS comprehensive report, and determines that the state machine encoding method for each security implementation mode is binary coding. The number of register bits is determined according to the number of states, such as 8 states corresponding to 3 register bits.

[0055] Step 3: Modify RTL code: The RTL code modification module adjusts the code according to the gate-level state machine, including setting different reset and power-on states to reflect the differences between different options of the safety state machine. Different transition processing and output port operation statements are added to the default / others branches of the state transition case statements, unlike those for reset and power-on states. Logical control statements based on the current state are added outside the case statements to separate the output function. The output function includes determining whether the state is "equal to" or "not equal to". Similarly, to avoid optimizations caused by other reasons, logical control is added to directly operate the port.

[0056] Step 4: Perform logic equivalence verification: The logic equivalence verification module loads the modified RTL code as REF, first performs a matching operation to match the REF with the state machine registers and input / output ports of the IMPL; then it performs a verification operation to traverse the entire state space; for the inequivalent comparison points that appear, by debugging and analyzing the driving point pattern and combining it with gate-level simulation, it is found that the problem is caused by the optimization of the default branch logic. Return to step 3 to adjust the expression of the default branch in the RTL code, and repeat the iteration until the verification is successful.

[0057] Step 5: Analyze State Machine Behavior: The behavior analysis module analyzes the final gate-level precise behavior of the state machine implemented by the Vivado synthesizer for the four safe implementation synthesis attributes of the finite state machine: auto_safe_state, reset_state, power_on_state, and default_state. The following results can be obtained:

[0058]

[0059] This invention uses a formal logic equivalence verification method to accurately analyze the gate-level behavior of the Vivado synthesizer's secure state machine, providing clear guidance for state machine design in high-security scenarios and improving the security and reliability of state machine implementation.

[0060] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A system for accurate behavioral analysis of a Vivado synthesizer security state machine, comprising: The method comprises the following steps: The gate-level netlist loading module is responsible for loading the gate-level netlist after layout and routing, as the implementation design IMPL, and the state machine in the IMPL has completed the safety implementation of the state machine. The state code analysis module determines the encoding mode of the synthesized state machine and the register bit number of the gate-level state machine according to the synthesis constraint settings and the synthesis report vds file output by Vivado. The RTL code modification module modifies the definition and encoding settings of the state register according to the gate-level state machine, and selects the corresponding module for configuration. The logic equivalence verification module loads the RTL code as the reference design REF, and performs matching, verification and debugging operations to realize the logic equivalence verification of the REF and the IMPL. The behavior analysis module performs accurate analysis on the behavior of the synthesized safety state machine by analyzing the RTL code after successful verification.

2. The system for accurate behavioral analysis of a Vivado synthesizer security state machine of claim 1, wherein: The matching operation of the logic equivalence verification module realizes the correspondence of all driving points and comparison points in the REF and the IMPL, and focuses on solving the correspondence of the state machine register.

3. The system for accurate behavioral analysis of a Vivado synthesizer security state machine of claim 1, wherein: If one-to-one correspondence cannot be realized, the RTL code modification module is triggered to modify the RTL code again.

4. The system for accurate behavioral analysis of a Vivado synthesizer security state machine of claim 1, wherein: The verification operation of the logic equivalence verification module traverses the state space formed by the driving points, and checks whether each comparison point satisfies the logic equivalence.

5. The analysis method of a Vivado synthesizer security state machine oriented accurate behavior analysis system according to any one of claims 1-4, characterized in that: The debugging operation of the logic equivalence verification module analyzes the pattern of the driving point for the non-equivalent comparison point, and combines gate-level simulation and other methods to infer the real behavior of the gate-level circuit, triggers the RTL code modification module to modify the RTL code again until the verification is successful. The method comprises the following steps: Step 1, load the gate-level netlist: the gate-level netlist loading module loads the gate-level netlist after layout and routing, as the implementation design IMPL, and the state machine in the IMPL has completed the safety implementation of the state machine; Step 2, analyze the state code: the state code analysis module determines the encoding mode of the synthesized state machine and the register bit number of the gate-level state machine according to the synthesis constraint settings and the synthesis report vds file output by Vivado; Step 3, modify the RTL code: the RTL code modification module modifies the definition and encoding settings of the state register according to the gate-level state machine, and selects the corresponding module for configuration; Step 4, perform logic equivalence verification: the logic equivalence verification module loads the RTL code as the reference design REF; 6. The analysis method of a Vivado synthesizer security state machine-oriented accurate behavior analysis system according to claim 5, characterized in that: Step 5, analyze the state machine behavior: the behavior analysis module analyzes the RTL code after successful verification, realizes accurate analysis on the behavior of the synthesized safety state machine, obtains the intuitive description of the finite state machine behavior under the full state space, and includes the state transition function and the output function after safety implementation. The step 4 performs the following substeps: 1) perform matching operation to realize the correspondence of all driving points and comparison points in the REF and the IMPL, and focus on solving the correspondence of the state machine register; if one-to-one correspondence cannot be realized, return to step 3 to modify the RTL code; 2) Verification operation, traversing the state space composed of driving points, checking whether each comparison point meets the logic equivalence; 3) For the comparison points that are not equivalent, debugging operation is performed, analyzing the pattern of driving points, and combining with gate-level simulation method, inferring the real behavior of gate-level circuit, returning to step 3 to modify the RTL code until the verification is successful.

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