Method, system and device for reducing reading delay based on tts technology

Abstract

The application relates to the technical field of speech synthesis, in particular to a method, system and device for reducing reading delay based on TTS technology. The method comprises the following steps: acquiring audio data, sampling the audio data to obtain a discrete sampling signal; optimizing a cache queue according to the discrete sampling signal, and determining an optimal synthesis cache value according to the discrete sampling signal; adjusting a TTS model according to the optimal synthesis cache value; performing energy analysis on the discrete sampling signal to obtain an energy value of the sampling signal; when the energy value of the sampling signal is lower than an energy value threshold, judging that the sampling signal is a blank signal; when the energy value of the sampling signal is not lower than the energy value threshold, judging that the sampling signal is a non-blank signal; deleting the blank signal in the cache queue, and outputting the non-blank signal. The optimal synthesis cache value is set, and a blank data deletion algorithm is introduced, so that the reading delay of TTS is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of speech synthesis technology, and in particular to a method, system and device for reducing reading latency based on TTS technology. Background Technology

[0002] With the widespread adoption of smart devices, speech synthesis technology has been widely applied in numerous scenarios, such as intelligent voice assistants, audiobooks, and voice navigation. TTS (text-to-speech) technology can convert text into speech, providing users with a more convenient interaction method. In media channels, TTS reading performance is crucial for user experience. However, current technologies suffer from slow reading performance during media channel TTS reading, especially with high latency in short text speech synthesis, severely impacting user experience and the performance of related applications.

[0003] Through research and analysis of existing technologies, it was found that current speech synthesis technologies generally suffer from problems such as unreasonable synthesis buffer settings and improper processing of synthesized audio data when processing short texts. Many speech engines set large minimum synthesis buffers to ensure synthesis stability and compatibility. This leads to the filling of short texts with a large amount of invalid blank data, increasing synthesis time and playback latency. Simultaneously, in the audio playback stage, there is a lack of effective mechanisms for handling invalid blank data in the synthesized audio data, causing this invalid data to be played back, further prolonging the reading delay.

[0004] Testing on mainstream brand devices revealed a particularly significant latency issue with TTS (Text-to-Speech) reading through media channels, with latency reaching up to 200ms. This is unacceptable in scenarios requiring high voice response speed, such as real-time interaction. Therefore, an effective technical solution is needed to address the excessive latency of TTS reading through media channels, thereby improving the efficiency of speech synthesis and the user experience. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in related technologies. To this end, the present invention provides a method, system, and apparatus for reducing reading latency based on TTS technology, achieving the technical effect of significantly reducing TTS reading latency.

[0006] This invention provides a method for reducing reading latency based on TTS technology, comprising the following steps:

[0007] S1: Acquire audio data, sample the audio data, and obtain discrete sampled signals;

[0008] S2: Optimize the buffer queue based on the discrete sampling signal, and determine the optimal synthesized buffer value based on the discrete sampling signal;

[0009] S3: Adjust the TTS model according to the optimal synthesis cache value;

[0010] S4: Perform energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal;

[0011] S5: When the energy value of the sampled signal is lower than the energy value threshold, it is determined to be a blank signal; when the energy value of the sampled signal is not lower than the energy value threshold, it is determined to be a non-blank signal.

[0012] S6: Delete the blank signal from the buffer queue and output a non-blank signal.

[0013] According to the present invention, a method for reducing reading latency based on TTS technology is provided, wherein step S2 includes:

[0014] S21: Store the discrete sampled signal in a buffer queue and optimize the buffer queue;

[0015] S22: Determine the optimal synthesis buffer value based on the discrete sampled signal.

[0016] According to the present invention, a method for reducing reading latency based on TTS technology is provided, wherein step S21 includes:

[0017] S211: Create a buffer queue to store discrete sampled signals;

[0018] S212: The discrete sampled signals are stored in a buffer queue according to the first-in-first-out principle;

[0019] S213: Real-time detection of the cache queue status; accelerate speech synthesis when the amount of data in the cache queue is lower than the cache threshold.

[0020] S214: Periodically monitor the storage time of data in the cache queue, and delete audio data blocks that have been stored for longer than the threshold duration and have not been played from the cache queue.

[0021] According to the present invention, a method for reducing reading latency based on TTS technology is provided, wherein step S22 includes:

[0022] S221: Decrease the cache value of the cache queue by a fixed step size, perform speech synthesis test using text, and obtain the reading delay, number of synthesis errors, and number of program crashes corresponding to the cache value;

[0023] S222: Calculate the corresponding comprehensive evaluation value based on the reading delay, number of synthesis errors, and number of program crashes:

[0024]

[0025] in, For comprehensive evaluation, As the first weighting coefficient, To extend the reading time, This is the second weighting coefficient. To synthesize the number of errors, This is the third weighting coefficient. This represents the number of times the program crashed.

[0026] S223: The cache value corresponding to the smallest overall evaluation value is the optimal synthesized cache value.

[0027] According to the present invention, a method for reducing reading latency based on TTS technology is provided, wherein step S4 includes:

[0028] S41: The audio data frame sample value is obtained by using a window calculation for each frame in the discrete sampled signal;

[0029] S42: Calculate the energy value of the discrete sampled signal using the root mean square algorithm.

[0030]

[0031] in, The energy value of the sampled signal. For the number of samples, For the first Each audio data frame sample value, The sampling sequence number, .

[0032] According to the present invention, a method for reducing reading delay based on TTS technology, the method for deleting blank signals in step S6 includes: pointer operation deletion, data reconstruction deletion, data copying overwriting, and linked list node deletion.

[0033] According to the present invention, a method for reducing reading latency based on TTS technology is provided, wherein the sampling rate range in step S1 is set to 40kHz~48kHz and the quantization accuracy range is 12~24 bits.

[0034] According to the present invention, a method for reducing reading delay based on TTS technology is provided. The window function in step S41 includes Hanning window, Hamming window, rectangular window, Blackman window and Gaussian window, and the window size is set to a range of 512 to 2048 sampling points.

[0035] This invention also provides a reading latency reduction system based on TTS technology, comprising:

[0036] Data sampling module: used to acquire audio data, sample the audio data, and obtain discrete sampled signals;

[0037] Optimal synthesis buffer value calculation module: used to optimize the buffer queue based on the discrete sampled signal and determine the optimal synthesis buffer value;

[0038] TTS Model Adjustment Module: Used to adjust the TTS model according to the optimal synthesis cache value;

[0039] Energy value calculation module: Performs energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal;

[0040] Blank signal rejection module: used to determine a sampled signal as blank when its energy value is lower than the energy value threshold, and as a non-blank signal when its energy value is not lower than the energy value threshold;

[0041] Data output module: used to delete the blank signal in the buffer queue and output a non-blank signal.

[0042] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of a method for reducing reading latency based on TTS technology as described above.

[0043] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0044] This invention provides a method, system, and device for reducing reading latency based on TTS technology. By setting an optimal synthesis cache value and introducing a blank data deletion algorithm, the following effects are achieved:

[0045] 1. Reduced reading latency: Through innovative audio trimming algorithms and caching technology optimization, the TTS reading latency in the media channel has been successfully reduced from a maximum of 200ms to about 30ms, meeting the fastest reading latency performance of 25ms as specified in the speech engine SDK documentation. This makes speech synthesis smoother and more efficient in real-time interactive scenarios, greatly improving the user experience.

[0046] 2. Improved synthesis efficiency: The optimized speech engine's minimum buffer settings and audio clipping algorithm reduce the synthesis and transmission of invalid blank data, thereby improving the overall efficiency of speech synthesis and saving system resources and time costs.

[0047] 3. Enhanced system stability: The automatic memory reclamation algorithm effectively controls program crashes caused by memory leaks, enhances the stability and reliability of the system during long-term operation, and ensures the normal operation of applications.

[0048] 4. Strong compatibility: The optimization scheme of this invention has been tested and verified on major mainstream brand devices, and has good compatibility, which can be widely used in various smart devices and speech synthesis application scenarios.

[0049] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0051] Figure 1 This is a flowchart of a method for reducing reading delay based on TTS technology provided by the present invention.

[0052] Figure 2 This is a structural block diagram of a reading delay reduction device based on TTS technology provided by the present invention.

[0053] Figure 3 This is a schematic diagram of the electronic device provided by the present invention.

[0054] Figure label:

[0055] 101. Data sampling module; 102. Optimal synthesis buffer value calculation module; 103. TTS model adjustment module; 104. Energy value calculation module; 105. Blank signal removal module; 106. Data output module; 810. Processor; 820. Communication interface; 830. Memory; 840. Communication bus. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but cannot be used to limit the scope of this invention.

[0057] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0058] The following is combined Figures 1 to 3 This invention is described.

[0059] Example

[0060] like Figure 1 As shown, Figure 1 A flowchart for reducing reading latency based on TTS technology provided by the present invention includes the following steps:

[0061] S1: Acquire audio data, sample the audio data, and obtain discrete sampled signals;

[0062] S2: Optimize the buffer queue based on the discrete sampling signal, and determine the optimal synthesized buffer value based on the discrete sampling signal;

[0063] S3: Adjust the TTS model according to the optimal synthesis cache value;

[0064] S4: Perform energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal;

[0065] S5: When the energy value of the sampled signal is lower than the energy value threshold, it is determined to be a blank signal; when the energy value of the sampled signal is not lower than the energy value threshold, it is determined to be a non-blank signal.

[0066] S6: Delete the blank signal from the buffer queue and output a non-blank signal.

[0067] Specifically, step S2 includes:

[0068] S21: Store the discrete sampled signal in a buffer queue and optimize the buffer queue;

[0069] S211: Create a buffer queue to store discrete sampled signals. The size of the buffer queue is set according to the system memory resources and the average length of the audio data. When the application starts, a buffer queue is created to store the audio data after TTS synthesis. The size of the buffer queue is set reasonably according to the system memory resources and the average length of the audio data, for example, set to 512 to 2048 audio data blocks, with each data block being 512 to 2048 bytes in size.

[0070] S212: The discrete sampled signals are stored in the buffer queue according to the first-in, first-out (FIFO) principle; after the speech engine completes TTS synthesis, the synthesized audio data is stored in the buffer queue according to the FIFO principle. During storage, timestamps and data identifiers are added to each audio data block for subsequent reading and management.

[0071] S213: Real-time monitoring of the cache queue status. When the amount of data in the cache queue is lower than the cache threshold, speech synthesis is accelerated; when audio needs to be played, audio data blocks are read from the head of the cache queue for playback. During playback, the status of the cache queue is monitored in real time. If the amount of data in the cache queue is found to be lower than a certain threshold, such as 10% to 30%, the speech engine is promptly notified to perform new TTS synthesis to ensure playback continuity.

[0072] S214: Periodically monitor the storage time of data in the cache queue. For audio data blocks that have been stored for a longer period than a threshold and have not been played, remove them from the cache queue. Start a background thread to periodically monitor memory usage and the storage time of data in the cache queue, such as every 50-200 milliseconds. For audio data blocks that have been stored for a certain period, such as 3-10 seconds and have not been played, remove them from the cache queue and release the corresponding memory space. Simultaneously, log memory usage and reclamation operations for subsequent analysis and optimization.

[0073] This invention identifies the root cause of the problem as the minimum synthesis cache setting of the speech engine and optimizes this core issue. The speech engine SDK development documentation was consulted, and the minimum cache value was modified, gradually decreasing from the initial 1kb setting. During cache adjustments, speech synthesis performance was tested after each adjustment to assess the actual effect of reducing reading latency. Ultimately, after repeated testing, a range of 50-70b was established for the minimum synthesis cache. When the minimum cache value falls below this lower limit, the speech engine stops synthesizing text and frequently crashes with errors. Therefore, this range was determined to be the minimum synthesis cache value for the speech engine. By modifying the minimum cache value, the latency issue in short text reading under media channels was significantly improved.

[0074] S22: Determine the optimal synthesis buffer value based on the discrete sampled signal.

[0075] S221: Gradually reduce the cache value of the cache queue according to a certain step size, and conduct speech synthesis tests using text. Obtain the reading delay, number of synthesis errors, and number of program crashes corresponding to the cache value. After each adjustment, conduct speech synthesis tests using a large number of texts of different lengths and contents, including short texts and long texts. Record the speech synthesis effect, reading delay, and whether synthesis errors or program crashes occur in each test.

[0076] S222: Calculate the corresponding comprehensive evaluation value based on the reading delay, number of synthesis errors, and number of program crashes:

[0077]

[0078] in, For comprehensive evaluation, As the first weighting coefficient, To extend the reading time, This is the second weighting coefficient. To synthesize the number of errors, This is the third weighting coefficient. This represents the number of times the program crashed.

[0079] S223: The cache value corresponding to the smallest overall evaluation value is the optimal synthesized cache value.

[0080] In this invention, after repeated testing, 60b was determined to be the optimal minimum synthesis buffer value range. When the minimum buffer value is less than the lower limit of this range, the speech engine will experience synthesis errors and frequent crashes. However, when set within this range, the latency problem under the media channel is greatly improved in short text reading. Although there is still some latency when synthesizing text of 1 to 2 Chinese characters, the overall performance meets the optimization requirements.

[0081] For short text content synthesis, analysis of playback data revealed that the 200ms delay data packet contained a large portion of blank and invalid audio data. This invention innovatively proposes an automatic audio blank segmentation algorithm. Based on digital signal processing principles, this algorithm can accurately identify which parts of the synthesized audio data are invalid blank data and which parts are the actual synthesized text data that the program needs to play. In its implementation, the algorithm first samples and quantizes the audio data, converting the continuous audio signal into a discrete digital signal. Then, by setting appropriate thresholds and window functions, the digital signal is analyzed. For each audio data frame, its energy value is calculated; if the energy value is lower than the set threshold, the frame is determined to be blank and invalid audio data. By dynamically adjusting the window size and threshold parameters, the algorithm can dynamically and accurately identify the size and duration of blank audio data based on the length of the text content. After identifying blank and invalid audio data, the algorithm deletes it from the audio data, retaining only the valid synthesized audio data. After processing with this algorithm, the TTS reading delay has been reduced from 200ms to a certain range of 60-80ms.

[0082] Specifically, step S4 includes:

[0083] S41: The audio data frame sample value is calculated using a window for each frame in the discrete sampled signal; the window function includes Hanning window, Hamming window, rectangular window, Blackman window and Gaussian window, and the window size is set to a range of 512 to 2048 sampling points.

[0084] S42: Calculate the energy value of the discrete sampled signal using the root mean square algorithm.

[0085]

[0086] in, The energy value of the sampled signal. For the number of samples, For the first Each audio data frame sample value, The sampling sequence number, .

[0087] In this invention, after repeated testing, 50~70b was determined to be the optimal range for the minimum synthesis buffer value. When the minimum buffer value is less than the lower limit of this range, the speech engine will experience synthesis errors and frequent crashes. However, when set within this range, the latency problem under the media channel is greatly improved in short text reading. Although there is still some latency when synthesizing text with 1 to 2 Chinese characters, the overall performance meets the optimization requirements.

[0088] Table 1 Test Results of Mainstream Brand Equipment

[0089]

[0090] As shown in Table 1, the results of the experiments were conducted on mainstream brand devices. After comprehensive testing on various mainstream brand devices, the results demonstrate that the media channel TTS reading performance optimization scheme proposed in this invention can effectively reduce TTS reading latency, lowering it from a maximum of 200ms to approximately 30ms. This aligns with the speech engine SDK documentation's fastest reading latency of 25ms, significantly improving the efficiency and quality of speech synthesis and greatly enhancing the user experience.

[0091] like Figure 2 As shown, the present invention also provides a system for reducing reading latency based on TTS technology, comprising the following modules:

[0092] Data sampling module 101: used to acquire audio data, sample the audio data, and obtain discrete sampled signals;

[0093] Optimal synthesis buffer value calculation module 102: used to optimize the buffer queue based on the discrete sampled signal and determine the optimal synthesis buffer value;

[0094] TTS model adjustment module 103: used to adjust the TTS model according to the optimal synthesis cache value;

[0095] Energy value calculation module 104: Performs energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal;

[0096] Blank signal rejection module 105: used to determine a blank signal when the energy value of the sampled signal is lower than the energy value threshold; and to determine a non-blank signal when the energy value of the sampled signal is not lower than the energy value threshold.

[0097] Data output module 106: used to delete the blank signal in the buffer queue and output a non-blank signal.

[0098] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute a method for reducing reading latency based on TTS technology, the method including:

[0099] S1: Acquire audio data, sample the audio data, and obtain discrete sampled signals;

[0100] S2: Optimize the buffer queue based on the discrete sampling signal, and determine the optimal synthesized buffer value based on the discrete sampling signal;

[0101] S3: Adjust the TTS model according to the optimal synthesis cache value;

[0102] S4: Perform energy analysis on the discrete sampled signal to obtain the energy value of the sampled signal;

[0103] S5: When the energy value of the sampled signal is lower than the energy value threshold, it is determined to be a blank signal; when the energy value of the sampled signal is not lower than the energy value threshold, it is determined to be a non-blank signal.

[0104] S6: Delete the blank signal from the buffer queue and output a non-blank signal.

[0105] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0109] It should be noted that the embodiments of this disclosure can be implemented using hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a programmable memory or a data carrier such as an optical or electronic signal carrier.

[0110] Furthermore, although the operation of the methods of this disclosure is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. It should also be noted that the features and functions of two or more devices according to this disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided and embodied by multiple devices.

[0111] While this disclosure has been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the specific embodiments disclosed. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for reducing reading latency based on TTS technology, characterized in that, Includes the following steps: S1: Acquire audio data, sample the audio data, and obtain discrete sampled signals; S2: Optimize the buffer queue based on the discrete sampling signal, and determine the optimal synthesized buffer value based on the discrete sampling signal; Step S2 includes: S21: Store the discrete sampled signal in a buffer queue and optimize the buffer queue; Step S21 includes: S211: Create a buffer queue to store discrete sampled signals; S212: The discrete sampled signals are stored in a buffer queue according to the first-in-first-out principle; S213: Real-time detection of the cache queue status; accelerate speech synthesis when the amount of data in the cache queue is lower than the cache threshold. S214: Periodically monitor the storage time of data in the cache queue, and delete audio data blocks that have been stored for more than the threshold duration and have not been played from the cache queue. S22: Determine the optimal synthesis buffer value based on the discrete sampled signal; S3: Adjust the TTS model according to the optimal synthesis cache value; S4: Perform energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal; S5: When the energy value of the sampled signal is lower than the energy value threshold, it is determined to be a blank signal; when the energy value of the sampled signal is not lower than the energy value threshold, it is determined to be a non-blank signal. S6: Delete the blank signal from the buffer queue and output a non-blank signal.

2. The method for reducing reading latency based on TTS technology according to claim 1, characterized in that, Step S22 includes: S221: Decrease the cache value of the cache queue by a fixed step size, perform speech synthesis test using text, and obtain the reading delay, number of synthesis errors, and number of program crashes corresponding to the cache value; S222: Calculate the corresponding comprehensive evaluation value based on the reading delay, number of synthesis errors, and number of program crashes: in, For comprehensive evaluation, As the first weighting coefficient, To extend the reading time, This is the second weighting coefficient. To synthesize the number of errors, This is the third weighting coefficient. This represents the number of times the program crashed. S223: The cache value corresponding to the smallest overall evaluation value is the optimal synthesized cache value.

3. The method for reducing reading latency based on TTS technology according to claim 1, characterized in that, Step S4 includes: S41: The audio data frame sample value is obtained by using a window calculation for each frame in the discrete sampled signal; S42: Calculate the energy value of the discrete sampled signal using the root mean square algorithm. in, The energy value of the sampled signal. For the number of samples, For the first Each audio data frame sample value, The sampling sequence number, .

4. The method for reducing reading latency based on TTS technology according to claim 1, characterized in that, The methods for deleting blank signals in step S6 include: pointer operation deletion, data reconstruction deletion, data copying overwriting, and linked list node deletion.

5. The method for reducing reading latency based on TTS technology according to claim 1, characterized in that, In step S1, the sampling rate range is set to 40kHz~48kHz, and the quantization precision range is 12~24 bits.

6. The method for reducing reading latency based on TTS technology according to claim 4, characterized in that, The window functions in step S41 include Hanning window, Hamming window, rectangular window, Blackman window and Gaussian window, with the window size ranged from 512 to 2048 sampling points.

7. A system for reducing reading latency based on TTS technology, used to execute the method for reducing reading latency based on TTS technology as described in any one of claims 1 to 6, characterized in that, Data sampling module: used to acquire audio data, sample the audio data, and obtain discrete sampled signals; Optimal synthesis buffer value calculation module: used to optimize the buffer queue based on the discrete sampled signal and determine the optimal synthesis buffer value; TTS Model Adjustment Module: Used to adjust the TTS model according to the optimal synthesis cache value; Energy value calculation module: Performs energy analysis on the discrete sampled signal according to the adjusted TTS model to obtain the energy value of the sampled signal; Blank signal rejection module: used to determine a sampled signal as blank when its energy value is lower than the energy value threshold, and as a non-blank signal when its energy value is not lower than the energy value threshold; Data output module: used to delete the blank signal in the buffer queue and output a non-blank signal.

8. An electronic device, comprising a processor, a communication interface, a memory, and a communication bus, characterized in that, When the processor executes a computer program, it implements the steps of the method for reducing reading latency based on TTS technology as described in any one of claims 1 to 6.

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