Electronic load mode switching circuit, method and electronic load

Abstract

This application discloses a mode switching circuit, method, and electronic load for an electronic load. The circuit includes a control module, a switching module, one or more current loops, an upper limit control circuit, and a lower limit control circuit. A switching module is set at the non-inverting input of a first error amplifier in the current closed loop. The control module switches the input control quantity of the current closed loop through the switching module, thereby realizing the switching of the electronic load between constant current mode and other modes. Furthermore, the control module outputs an upper limit current control quantity to the second error amplifier of the upper limit control circuit and an lower limit current control quantity to the third error amplifier of the lower limit control circuit. By limiting the input control quantity of the current closed loop through the upper and lower limit control circuits, this application can reduce the probability of current overshoot or current drop during the switching process, achieving smooth switching of the electronic load and improving reliability and stability.

Description

Technical Field

[0001] This application relates to the field of power supply testing, and in particular to a mode switching circuit, method, and electronic load for an electronic load. Background Technology

[0002] Electronic loads are specialized instruments used to test power supply performance. When performing different power supply tests, electronic loads need to change their operating modes according to the type and operation of the power supply. Electronic loads have four basic operating modes: constant current, constant voltage, constant resistance, and constant power.

[0003] In related technologies, electronic loads switch between constant current mode and other modes, such as constant voltage mode and constant current mode, by controlling a switch to switch the input of voltage control quantity and current control quantity. However, the switching takes time, and there is no clear control quantity input in the loop during the switching process, which can easily lead to current runaway, causing overshoot or current drop.

[0004] In summary, electronic loads in related technologies suffer from low reliability and stability during mode switching. Summary of the Invention

[0005] This application proposes an electronic load mode switching circuit, method, and electronic load, which can reduce the probability of current overshoot or current drop during the switching process of the electronic load, realize smooth switching of the electronic load, and improve reliability and stability.

[0006] According to an embodiment of the first aspect of this application, the electronic load includes a power supply, and the mode switching circuit of the electronic load includes:

[0007] Control module;

[0008] A switching module, wherein the control module is connected to the first input terminal of the switching module for inputting a first control quantity, and the second input terminal of the switching module is used to input a second control quantity, wherein the first control quantity is a current control quantity, and the second control quantity is any one of a constant voltage control quantity, a constant power control quantity, or a constant resistance control quantity;

[0009] One or more current loops are provided, each current loop including a first error amplifier and a power transistor. The output of the switching module is connected to the non-inverting input of the first error amplifier, and the inverting input of the first error amplifier is used to input the current feedback signal of the current loop. The output of the first error amplifier is connected to the control terminal of the power transistor, the drain of the power transistor is connected to a power supply, and the source of the power transistor is grounded. The control module is connected to the control terminal of the switching module to control the input control quantity of the current loop to switch to a first control quantity or a second control quantity, so that the electronic load switches to a constant current mode or a target mode, where the target mode is any one of constant voltage, constant power, or constant resistance modes.

[0010] An upper limit control circuit is provided, comprising a second error amplifier, a first switching transistor, and a negative power supply terminal. The control module is connected to the inverting input of the second error amplifier for inputting the upper limit control quantity of the current. The output terminal of the second error amplifier is connected to the control terminal of the first switching transistor. One end of the first switching transistor is connected to both the non-inverting input of the second error amplifier and the non-inverting input of the first error amplifier. The other end of the first switching transistor is connected to the negative power supply terminal. The first switching transistor is a high-level active switching transistor.

[0011] The lower limit control circuit includes a third error amplifier, a second switching transistor, and a positive power supply terminal. The control module is connected to the inverting input of the third error amplifier to input the lower limit control quantity of the current. The output terminal of the third error amplifier is connected to the control terminal of the second switching transistor. One end of the second switching transistor is connected to the non-inverting input of the second error amplifier and the non-inverting input of the first error amplifier, respectively. The other end of the second switching transistor is connected to the positive power supply terminal. The second switching transistor is a low-level active switching transistor.

[0012] According to some embodiments of this application, the control module includes:

[0013] FPGA;

[0014] A first DAC, wherein the FPGA is connected to the first DAC for outputting a first control quantity;

[0015] A current sampling circuit is provided, which is used to sample the current of the current loop. The output terminal of the current sampling circuit is connected to the inverting terminal of the first error amplifier, and the output terminal of the current sampling circuit is connected to the current sampling terminal of the FPGA through the first ADC.

[0016] A voltage sampling circuit is provided, which is used to sample the voltage of the current loop. The output of the voltage sampling circuit is connected to the voltage sampling terminal of the FPGA through a second ADC.

[0017] The second DAC and the third DAC are connected to the FPGA, which is used to output an upper limit current control value and an lower limit current control value.

[0018] According to some embodiments of this application, the target mode is a constant pressure mode, and the control module further includes:

[0019] The fourth DAC, connected to the FPGA, is used to output voltage control quantities;

[0020] The fourth error amplifier has its non-inverting input connected to the output of the second DAC, the voltage sampling circuit connected to the inverting input of the fourth error amplifier, and its output connected to the second input of the switching module.

[0021] According to some embodiments of this application, the target mode is a constant power mode, and the control module further includes:

[0022] The multiplier has its output terminal connected to the first input terminal of the current sampling circuit, its voltage sampling circuit connected to the second input terminal of the multiplier, and its output terminal connected to the second input terminal of the switching module.

[0023] According to some embodiments of this application, the target mode is a constant resistance mode, the switching module includes a switch, a first DAC, and a reference power supply terminal, and the control module includes:

[0024] FPGA, the FPGA being connected to the input of the first DAC,

[0025] A voltage sampling circuit is provided, wherein the voltage sampling circuit is used to sample the voltage of the current loop, the output terminal of the voltage sampling circuit is connected to the voltage sampling terminal of the FPGA through a second ADC, the output terminal of the voltage sampling circuit is connected to the first input terminal of the switch, the reference power supply terminal is connected to the second input terminal of the switch, and the output terminal of the switch is connected to the reference voltage terminal of the first DAC.

[0026] A current sampling circuit is provided, which is used to sample the current of the current loop. The output terminal of the current sampling circuit is connected to the inverting terminal of the first error amplifier, and the output terminal of the current sampling circuit is connected to the voltage sampling terminal of the FPGA through the first ADC.

[0027] The second DAC and the third DAC are connected to the FPGA, which is used to output an upper limit current control value and an lower limit current control value.

[0028] According to some embodiments of this application, the upper limit control circuit further includes:

[0029] The first capacitor is connected to the inverting input of the second error amplifier through the first capacitor.

[0030] And / or, the lower limit control circuit further includes:

[0031] The output terminal of the third error amplifier is connected to the inverting terminal of the third error amplifier via the second capacitor.

[0032] The electronic load control method according to a second aspect of this application, applied to the control module described in the first aspect embodiment, includes the following steps:

[0033] Obtain a mode switching instruction, which is used to instruct the electronic load to switch to constant current mode or target mode;

[0034] Obtain the current parameters of the electronic load, and based on these parameters, determine the upper and lower current limits during the switching process.

[0035] Wherein, when the mode switching command instructs the electronic load to switch from constant current mode to target mode, the current parameter is a current sample value;

[0036] When the mode switching command instructs the electronic load to switch from the target mode to the constant current mode, the current parameter is the current set value;

[0037] According to the mode switching command, the switching module is controlled to switch the electronic load to constant current mode or target mode, and the upper limit current control quantity is output according to the upper limit current value, and the lower limit current control quantity is output according to the lower limit current value.

[0038] According to some embodiments of this application, obtaining the upper and lower current limits during the switching process based on current parameters includes:

[0039] Obtain current sampling error parameters and current setting error parameters. The current sampling error parameters are used to indicate the error between the actual current sampling value and the current sampling reading value of the electronic load. The current setting error parameters are used to indicate the error between the current setting value and the actual current value of the electronic load.

[0040] The upper limit and lower limit of the current are calculated based on the current sampling error parameter, the current setting error parameter, and the current parameter.

[0041] An electronic load according to a third aspect of this application includes the mode switching circuit of the electronic load described above.

[0042] The mode switching circuit, method, and electronic load according to the embodiments of this application have at least the following beneficial effects:

[0043] In this embodiment, a switching module is set at the non-inverting input of the first error amplifier in the current closed loop. The control module switches the input control quantity of the current closed loop through the switching module, thereby realizing the switching of the electronic load between constant current mode and other modes. Furthermore, the control module outputs an upper current limit control quantity to the second error amplifier of the upper limit control circuit and an lower current limit control quantity to the third error amplifier of the lower limit control circuit. When the input control quantity of the current closed loop is higher than the upper current limit control quantity during switching, the second error amplifier outputs a high level, the first switch is turned on, and the input control voltage of the current closed loop is quickly pulled down through the negative power supply. When the input control quantity of the current closed loop is lower than the lower current limit control quantity during switching, the third error amplifier outputs a low level, the second switch is turned on, and the input control voltage of the current closed loop is quickly pulled up through the positive power supply. This application, by limiting the input control quantity of the current closed loop through the upper and lower limit control circuits, can reduce the probability of current overshoot or current drop during the switching process of the electronic load, realize smooth switching of the electronic load, and improve reliability and stability.

[0044] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0045] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0046] Figure 1 This is a schematic block diagram of the mode switching circuit of the electronic load in the embodiments of this application;

[0047] Figure 2 This is a circuit diagram of the constant current / constant voltage switching circuit in the embodiments of this application;

[0048] Figure 3 This is a circuit diagram of the constant current and constant power switching circuit in the embodiments of this application;

[0049] Figure 4 This is a circuit diagram of the constant current and constant resistance switching circuit in the embodiments of this application;

[0050] Figure 5 This is a flowchart of the electronic load control method in the embodiments of this application. Detailed Implementation

[0051] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0052] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0053] In the description of this application, "multiple" refers to two or more. The use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or the order in which the technical features are indicated.

[0054] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0055] Reference Figure 1 As shown, an electronic load mode switching circuit includes a power supply, and the electronic load mode switching circuit includes:

[0056] Control module;

[0057] The switch module and the control module are connected to the first input terminal of the switch module for inputting a first control quantity, and the second input terminal of the switch module is used to input a second control quantity. The first control quantity is a current control quantity, and the second control quantity is any one of constant voltage control quantity, constant power control quantity, or constant resistance control quantity.

[0058] One or more current loops are provided, each current loop including a first error amplifier and a power transistor. The output of a switching module is connected to the non-inverting input of the first error amplifier, and the inverting input of the first error amplifier is used to input the current feedback signal of the current loop. The output of the first error amplifier is connected to the control terminal of the power transistor, the drain of the power transistor is connected to the power supply, and the source of the power transistor is grounded. A control module is connected to the control terminal of the switching module to switch the input control quantity used to control the current loop to either a first control quantity or a second control quantity, so that the electronic load switches to a constant current mode or a target mode. The target mode is any one of constant voltage, constant power, or constant resistance modes.

[0059] The upper limit control circuit includes a second error amplifier, a first switching transistor, and a negative power supply terminal. The control module is connected to the inverting input of the second error amplifier to input the upper limit control quantity of the current. The output terminal of the second error amplifier is connected to the control terminal of the first switching transistor. One end of the first switching transistor is connected to both the non-inverting input and the non-inverting input of the second error amplifier. The other end of the first switching transistor is connected to the negative power supply terminal. The first switching transistor is a high-level active switching transistor.

[0060] The lower limit control circuit includes a third error amplifier, a second switching transistor, and a positive power supply terminal. The control module is connected to the inverting input of the third error amplifier to input the lower limit control quantity of the current. The output terminal of the third error amplifier is connected to the control terminal of the second switching transistor. One end of the second switching transistor is connected to the non-inverting input of the second error amplifier and the non-inverting input of the first error amplifier, respectively. The other end of the second switching transistor is connected to the positive power supply terminal. The second switching transistor is a low-level active switching transistor.

[0061] In this embodiment, a switching module is set at the non-inverting input of the first error amplifier in the current closed loop. The control module switches the input control quantity of the current closed loop through the switching module, thereby realizing the switching of the electronic load between constant current mode and other modes. Furthermore, the control module outputs an upper current limit control quantity to the second error amplifier of the upper limit control circuit and an lower current limit control quantity to the third error amplifier of the lower limit control circuit. When the input control quantity of the current closed loop is higher than the upper current limit control quantity during switching, the second error amplifier outputs a high level, the first switch is turned on, and the input control voltage of the current closed loop is quickly pulled down through the negative power supply. When the input control quantity of the current closed loop is lower than the lower current limit control quantity during switching, the third error amplifier outputs a low level, the second switch is turned on, and the input control voltage of the current closed loop is quickly pulled up through the positive power supply. This application, by limiting the input control quantity of the current closed loop through the upper and lower limit control circuits, can reduce the probability of current overshoot or current drop during the switching process of the electronic load, realize smooth switching of the electronic load, and improve reliability and stability.

[0062] The control module described above can use an FPGA, MCU, DSP or other logic controller as the main controller, and output control quantities through several DAC modules, and then sample voltage and current signals through an ADC. Alternatively, a chip with built-in DAC and ADC ports can be used.

[0063] The aforementioned current loop refers to the circuit that implements current control. The current loop in an electronic load is the core mechanism for achieving precise load current control, and its core function is to maintain current stability through feedback regulation. Its working principle is based on closed-loop control: the load current is detected in real time through a current sampling resistor, the actual current value is compared with the set value, an error signal is generated using a first error amplifier, and then the current is controlled by adjusting the analog value of the power transistor's gate voltage, thereby dynamically changing the load's power consumption capacity. In this embodiment, a MOSFET is used as the power transistor, but other power devices can also be used.

[0064] It should be understood that there can be one or more current loops, and connecting multiple current loops in parallel can increase the power of the electronic load.

[0065] The aforementioned switch module is used to switch between the first and second control quantities. The switch module can be a simple dual-channel switch, or it can include a DAC or other auxiliary circuitry. Users can configure different specific circuits for the switch module depending on the target mode.

[0066] It should be noted that in constant current mode, the input control quantity of the current loop is the first control quantity, i.e., the current control quantity output by the control module. This current control quantity can be a user-preset current setting or a current setting calculated based on a predetermined scenario and algorithm. In constant voltage mode, the input control quantity of the current loop is the voltage setting value output by the control module. In constant power mode, the input control quantity of the current loop is the constant power control quantity, obtained by multiplying the current sampling signal and the voltage sampling signal. In constant resistance mode, the input control quantity of the current loop is the constant resistance control quantity output by the control module.

[0067] The aforementioned upper limit control circuit functions to acquire the voltage of the input control quantity of the current loop and pull it down when it exceeds the upper limit control quantity. Specifically, the upper limit control quantity is output by the control module. The second error amplifier compares the input control quantity of the current loop (input at the non-inverting input) with the upper limit control quantity. When the input control quantity of the current loop is lower than the upper limit control quantity, the second error amplifier outputs a low level. Since the first switch is active high, it is cut off at this time, and the input control quantity of the current loop is not affected by the negative power supply. When the input control quantity of the current loop is higher than the upper limit control quantity, the second error amplifier outputs a low level, the first switch is turned on, and the input control voltage of the current closed loop is quickly pulled down through the negative power supply.

[0068] The aforementioned lower limit control circuit functions to acquire the voltage of the input control quantity of the current loop and pull it down when it exceeds the lower current limit control quantity. Specifically, the lower current limit control quantity is output by the control module. The third error amplifier compares the input control quantity of the current loop (input at the non-inverting input) with the lower current limit control quantity. When the input control quantity of the current loop is higher than the lower current limit control quantity, the third error amplifier outputs a high level. Since the second switch is active low, it is cut off at this time, and the input control quantity of the current loop is not affected by the positive power supply. When the input control quantity of the current loop is lower than the lower current limit control quantity, the third error amplifier outputs a low level, the second switch is turned on, and the input control voltage of the current closed loop is quickly pulled up through the positive power supply.

[0069] For example, the first switching transistor can be an NMOS transistor, an NPN transistor, or other switching devices that are turned on at a high level and turned off at a low level, and the second switching transistor can be a PMOS transistor, a PNP transistor, or other switching devices that are turned on at a low level and turned off at a high level.

[0070] It should be noted that the voltage corresponding to the negative power supply only needs to be lower than the voltage corresponding to the minimum DAC value that the control module can output. Similarly, the voltage corresponding to the positive power supply only needs to be lower than the voltage corresponding to the maximum DAC value that the control module can output. In this embodiment, the negative and positive power supplies are directly connected to the positive and negative power supplies of any operational amplifier.

[0071] It should be noted that the upper and lower current control values ​​can be preset by the user or calculated by the control module according to a specific algorithm. The specific values ​​of the upper and lower current control values ​​can be set to a range based on the current before switching. For example, the upper and lower limits of the current can be set to 95% to 105% or 90% to 110% of the sampled current before switching.

[0072] By limiting the current in the current loop during the switching process using the circuit described above, overshoot and drop during the switching process can be effectively reduced, ensuring the normal operation of the electronic load and the accuracy of the data during the test.

[0073] In some implementations, the control module may include:

[0074] FPGA;

[0075] The first DAC is connected to the FPGA to output the first control quantity.

[0076] The current sampling circuit is used to sample the current in the current loop. The output of the current sampling circuit is connected to the inverting input of the first error amplifier. The output of the current sampling circuit is connected to the current sampling input of the FPGA through the first ADC.

[0077] The voltage sampling circuit is used to sample the voltage of the current loop. The voltage sampling circuit includes a differential amplifier AMP3. The two ends of the differential amplifier AMP3 are connected to the power supply terminal VBUS and the ground terminal respectively to obtain the voltage of the current loop. The output terminal of the differential amplifier AMP3 is connected to the voltage sampling terminal of the FPGA through the second ADC.

[0078] The second DAC and the third DAC are connected to the FPGA. The second DAC is used to control the upper limit of the output current, and the third DAC is used to control the lower limit of the output current.

[0079] In this embodiment, the control module uses an FPGA as the core controller to achieve synchronous logic control. Utilizing the FPGA's synchronization capability, upper and lower limit control, mode switching, and electronic load function control can be performed simultaneously, improving reliability. Furthermore, the FPGA outputs current control quantities through a first DAC, and current sampling and negative feedback are achieved through a current sampling circuit. Voltage sampling is achieved through a voltage sampling circuit, and the upper and lower current limit control quantities are output through a second and third DAC.

[0080] refer to Figure 2 As shown, in this embodiment, there are multiple current loops. The current sampling circuit includes multiple current sampling resistors R1, multiple differential amplifiers AMP1, and an adder AMP2. Each current loop corresponds to a current sampling resistor R1 and a differential amplifier AMP1. The current sampling resistor R1 is connected in series between the MOSFET Q1 and the ground terminal. The differential amplifier AMP1 is connected across the current sampling resistor R1 to obtain the voltage across the current sampling resistor R1. The current of the current loop can be obtained through the voltage-resistance ratio. The output of the differential amplifier AMP1 is connected to the inverting input of the first error amplifier EA1 in the corresponding current loop to achieve negative feedback. On the other hand, the outputs of all differential amplifiers AMP1 are connected to the adder AMP2 to accumulate the current of all loops. The output of the adder AMP2 is connected to the current sampling terminal of the FPGA through the first ADC, so that the FPGA can obtain the total current of the electronic load. Of course, in addition to the above mode, the current sampling circuit can also connect the output of each differential amplifier AMP1 to the FPGA through an ADC, so that the FPGA can obtain the current of each loop. It should be understood that when there is only one current loop, the partial current equals the total current, so there is no need to configure an adder.

[0081] In this embodiment, the differential amplifier AMP3 samples the voltage of the current loop and then inputs it to the voltage sampling terminal of the FPGA through the second ADC. Since the current loops are connected in parallel, the voltages of all current loops are equal.

[0082] In some implementations, the target mode is a constant voltage mode, and the control module further includes:

[0083] The fourth DAC is connected to the FPGA for output voltage control.

[0084] The fourth error amplifier has its non-inverting input connected to the output of the second DAC, the voltage sampling circuit connected to the inverting input of the fourth error amplifier, and the output of the fourth error amplifier connected to the second input of the switching module.

[0085] In this embodiment, the generation of constant voltage control quantity can be achieved through the fourth error amplifier and the second DAC, enabling the electronic load to switch between constant current mode and constant voltage mode.

[0086] For details, please refer to Figure 2 The diagram shows the switching circuit for constant current and constant voltage modes of an electronic load. The FPGA is connected to the inverting input of the fourth error amplifier EA4 via the fourth DAC. The fourth error amplifier EA4 is a voltage error amplifier, and its non-inverting input is connected to the output of the differential amplifier AMP3 to obtain the voltage of the current loop, i.e., the load voltage. The fourth error amplifier EA4 outputs an error signal based on the voltage control quantity and the actual voltage, which is used as a constant voltage control quantity input to switch S1. When switch S1 switches to the constant voltage mode, the current loop controls the conduction of MOSFET Q1 through the control quantity of the fourth error amplifier EA4, thereby controlling the voltage at the power supply terminal VBUS. When switching to the constant current mode, the first DAC outputs a current control quantity to the first error amplifier to control the conduction of MOSFET Q1, thereby controlling the current in the current loop.

[0087] Specifically, the upper limit control circuit includes a second error amplifier EA2, a first switching transistor K1, and a positive power supply terminal V+. The FPGA is connected to the inverting input of the second error amplifier EA2 through a second DAC. The output of the second error amplifier EA2 is connected to the gate of the first switching transistor K1. The source of the first switching transistor K1 is connected to the positive power supply terminal V+, and the drain is connected to the non-inverting input of the second error amplifier EA2 and the non-inverting input of the first error amplifier EA1, respectively. The other end of the first switching transistor K1 is connected to the positive power supply terminal V+. The first switching transistor K1 is an NPN transistor.

[0088] The lower limit control circuit includes a third error amplifier EA3, a second switch K2, and a negative power supply terminal V-. The FPGA is connected to the inverting input of the third error amplifier EA3 through a third DAC. The output of the third error amplifier EA3 is connected to the gate of the second switch K2. The source of the second switch K2 is connected to the non-inverting input of the second error amplifier EA3 and the non-inverting input of the first error amplifier EA1, respectively. The drain of the second switch K2 is connected to the negative power supply terminal V-. The second switch K2 is a PNP transistor.

[0089] For example, the switching process of the constant voltage and constant current circuit is as follows:

[0090] Let Vprog be the voltage at the non-inverting input of the first error amplifier EA1, Vdac2 be the output voltage of the second DAC, and Vdac3 be the output voltage of the third DAC. During the switching process of switch S1, when Vprog is lower than the lower current limit Vdac3, the second error amplifier EA2 is reverse-biased, and the gate voltage of the second switch K2 is lower than the positive power supply V+. The second switch K2 is turned on, pulling Vprog up through the positive power supply V+ until the voltage equals Vdac3. At this point, the second error amplifier EA2 reaches equilibrium, and Vprog is clamped to the value of Vdac3. When Vprog is higher than the lower current limit Vdac3, the second error amplifier EA2 is forward-biased, the gate voltage of the second switch K2 equals the positive power supply V+, the second switch K2 is turned off, and Vprog is unaffected.

[0091] When the Vprog voltage is higher than the upper current limit Vdac3, the first error amplifier EA1 becomes forward biased, the gate voltage of the first switch K1 is higher than the negative power supply V-, the first switch K1 turns on, and the negative power supply V- begins to pull Vprog low until the voltage equals Vdac2, at which point the first error amplifier EA1 reaches equilibrium, and Vprog is clamped to the value of Vdac2. When the Vprog voltage is lower than the lower current limit Vdac2, the first error amplifier EA1 becomes reverse biased, the gate voltage of the first switch K1 equals the negative power supply V-, the first switch K1 turns off, and Vprog is unaffected.

[0092] In some implementations, the target mode is a constant power mode, and the control module may further include:

[0093] The multiplier has its current sampling circuit output connected to its first input, its voltage sampling circuit connected to its second input, and its output connected to the second input of the switching module.

[0094] In this embodiment, the current sample value and the voltage sample value are multiplied by a multiplier to obtain the constant power control quantity, so that the electronic load can achieve constant power control.

[0095] For details, please refer to Figure 3 As shown, the two input terminals of multiplier EA5 are connected to the output terminals of differential amplifier AMP3 and adder AMP2 respectively to obtain voltage and current sampling values. The output terminal of multiplier EA5 is connected to one input terminal of switch S1. Switching between constant current mode and constant power mode can be achieved by switching switch S1.

[0096] The current limiting process during the switching process of a constant current and constant power circuit is the same as that of a constant current and constant voltage circuit, and will not be described in detail here.

[0097] In some implementations, the target mode is a constant resistance mode, the switching module includes a switch, a first DAC, and a reference power supply terminal, and the control module includes:

[0098] The FPGA is connected to the input of the first DAC.

[0099] The voltage sampling circuit is used to sample the voltage of the current loop. The output of the voltage sampling circuit is connected to the voltage sampling terminal of the FPGA through the second ADC. The output of the voltage sampling circuit is connected to the first input terminal of the switch. The reference power supply terminal is connected to the second input terminal of the switch. The output of the switch is connected to the reference voltage terminal of the first DAC.

[0100] The current sampling circuit is used to sample the current in the current loop. The output of the current sampling circuit is connected to the inverting input of the first error amplifier. The output of the current sampling circuit is connected to the voltage sampling input of the FPGA through the first ADC.

[0101] The second DAC and the third DAC are connected to the FPGA. The second DAC is used to control the upper limit of the output current, and the third DAC is used to control the lower limit of the output current.

[0102] In this embodiment, the voltage sample is used as the input reference voltage of the first DAC by switching, so that the electronic load can achieve constant resistance control.

[0103] For details, please refer to Figure 4 As shown, the voltage sampling circuit includes a differential amplifier AMP3. One input terminal of switch S1 is connected to the reference voltage source Vref, and the other input terminal is connected to the output terminal of differential amplifier AMP3. The two ends of differential amplifier AMP3 are connected to the power supply terminal VBUS and the ground terminal respectively to obtain the voltage of the current loop.

[0104] The working principle of a constant resistance circuit is as follows:

[0105] When switch S1 is in position 2, the electronic load is in constant current mode. At this time, the reference voltage of the first DAC is Vref. The FPGA outputs a set DAC value to the DAC module, and the DAC module outputs a voltage corresponding to the DAC value to the non-inverting input of the first error amplifier EA1, realizing a constant current closed loop with negative feedback. When switch S1 is in position 1, the reference voltage of the first DAC is the output voltage of the differential amplifier AMP3. The FPGA outputs different DAC values ​​to derive different resistors, realizing a constant resistance circuit.

[0106] The current limiting process during the switching process of the constant current constant resistance circuit is the same as that of the constant current constant voltage circuit, and will not be described in detail here.

[0107] In some implementations, the upper limit control circuit further includes:

[0108] The first capacitor is connected to the inverting input of the second error amplifier through the first capacitor.

[0109] And / or, the lower limit control circuit also includes:

[0110] The output of the third error amplifier is connected to the inverting input of the third error amplifier through the second capacitor.

[0111] In this embodiment, by connecting a capacitor in series between the output terminal and the inverting terminal of the second and third error amplifiers, the response speed of the current upper and lower limit control can be improved.

[0112] refer to Figure 5 As shown, this application also relates to an electronic load control method applied to a control module, comprising the following steps:

[0113] S101. Obtain the mode switching instruction. The mode switching instruction is used to instruct the electronic load to switch to constant current mode or target mode.

[0114] S102. Obtain the current parameters of the electronic load;

[0115] S103. Obtain the upper and lower current limits during the switching process based on the mode switching command and current parameters.

[0116] In the case where the mode switching command instructs the electronic load to switch from constant current mode to target mode, the current parameter is the current sample value;

[0117] When the mode switching command instructs the electronic load to switch from the target mode to the constant current mode, the current parameter is the current set value;

[0118] S104. Control the switch module to switch the electronic load to constant current mode or target mode according to the mode switching command, and output the upper limit current control quantity according to the upper limit current value and the lower limit current control quantity according to the lower limit current value.

[0119] In this embodiment, a mode switching command is first obtained, followed by the current parameters of the electronic load. Based on the mode switching command and the current parameters, the upper and lower current limits during the switching process are obtained. Finally, the switching module is controlled to switch the electronic load to constant current mode or target mode according to the mode switching command. Furthermore, an upper current limit control quantity is output based on the upper current limit, and a lower current limit control quantity is output based on the lower current limit. This application can reduce the probability of current overshoot or current drop during the switching process of the electronic load, achieving smooth switching of the electronic load and improving reliability and stability.

[0120] Specifically, taking the switching between constant voltage and constant current modes as an example, when the electronic load starts to draw load, it obtains a mode switching command through human-machine interaction, i.e., the constant current or constant voltage mode, set values, and other parameters, and starts drawing load current. When the control module receives the mode switching command, it calculates the current range to be maintained based on the obtained current value and the parameters of the target mode, or sets a percentage N based on experience. If switching from constant current mode to constant voltage mode, the upper and lower limits are set to N% above and below the current current; if switching from constant voltage mode to constant current mode, the upper and lower limits are set to N% above and below the target current value. Simultaneously, it starts switching switch S1 and outputs the set current control value. In this embodiment, an FPGA is used to process data and control the DAC, ensuring that this control process is short enough, generally below the nanosecond level, thus preventing current overshoot and drop during the switching process. After the switching is completed, the upper and lower current limits return to their default values, which can be set to the maximum and minimum values ​​of the electronic load current range.

[0121] In some implementations, obtaining the upper and lower current limits during the switching process based on current parameters may include:

[0122] Obtain the current sampling error parameter and the current setting error parameter. The current sampling error parameter is used to indicate the error between the actual current sampling value and the current sampling reading value of the electronic load. The current setting error parameter is used to indicate the error between the current setting value and the actual current value of the electronic load.

[0123] The upper and lower limits of the current are calculated based on the current sampling error parameters, the current setting error parameters, and the current parameters.

[0124] In this embodiment, the current sampling error parameter and the current setting error parameter are first obtained. Then, the upper limit value and the lower limit value of the current are calculated based on the current sampling error parameter, the current setting error parameter, and the current parameter. The upper limit value and the lower limit value of the current are calculated based on the current sampling error and the current setting error of the electronic load. Then, current limiting control is performed during the switching process based on the upper limit value and the lower limit value, which can further reduce the probability of current fluctuations, ensure the smoothness and stability of the current during the switching process, and achieve seamless switching.

[0125] Specifically, the current sampling error parameters include the current sampling accuracy value, the current sampling slope value, and the current sampling zero-point offset value; the current setting error parameters include the current setting accuracy value, the current setting slope value, and the current setting zero-point offset value.

[0126] The expression for the upper limit of current is:

[0127] Imax=(K1×I1+B1)×(1+a%)×(1+b%)-B2} / K2;

[0128] The expression for the lower limit of current is:

[0129] Imin=(K1×I1+B1)×(1-a%)×(1-b%)-B2} / K2;

[0130] Where Imax is the upper limit of current, I1 is the current sampled value before switching, a is the current sampling accuracy value, K1 is the sampling slope value, B1 is the current sampling zero offset value, Imin is the lower limit of current, b is the current setting accuracy value, K2 is the current setting slope value, and B2 is the current setting zero offset value.

[0131] In this embodiment, the upper limit and lower limit of the current are calculated by the current sampling accuracy value, the current sampling slope value, the current sampling zero-point offset value, the current setting accuracy value, the current setting slope value, and the current setting zero-point offset value. Then, current limiting control is performed during the switching process based on the upper limit and lower limit of the current, which can further reduce the probability of current fluctuations, ensure the smoothness and stability of the current during the switching process, and achieve seamless switching.

[0132] Specifically, the current sampling accuracy value 'a', sampling slope value K1, and current sampling zero-point offset value B1 are obtained through sampling calibration of the electronic load. The current sampling accuracy value reflects the sampling precision, the sampling slope value refers to the linear control slope of the current sampling, and the current sampling zero-point offset value refers to the zero-point offset of the current sampling. By calibrating, the current sampling accuracy value 'a', sampling slope value K1, and current sampling zero-point offset value B1 can reflect the error between the actual sampled value and the sampled reading value of the electronic load. Similarly, the current setting accuracy value 'b', current setting slope value K2, and current setting zero-point offset value B2 are obtained through calibration of the output setting of the electronic load. The current setting accuracy value reflects the precision of the set current. By calibrating, the current setting accuracy value 'b', current setting slope value K2, and current setting zero-point offset value B2 can reflect the error between the user's current setting value received by the electronic load and the actual current value.

[0133] Specifically, taking the constant current to constant voltage switch as an example, the actual current sampling value before the switch, i.e., the value collected by the first ADC, is I1. Through calibration, it can be known that the sampling value read by the electronic load is Id = K1 × I1 + B1, with a readback accuracy of a%. Similarly, through calibration, it is known that when the setting value of the second DAC is V2, the actual value of the upper limit of the electronic load current is Iup = K2 × V2 + B2, with a setting accuracy of b%. Therefore, the upper limit of the current Imax = {Iup(1 + b%) - B2} / K2 = {(K1 × I1 + B1) × (1 + a%) × (1 + b%) - B2} / K2, and similarly, the lower limit of the current Imin = {(K1 × I1 + B1) × (1 - a%) × (1 - b%) - B2} / K2.

[0134] This application also relates to an electronic load, including the mode switching circuit of the electronic load described in the above embodiments.

[0135] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A mode switching circuit for an electronic load, characterized in that, The electronic load includes a power supply, and the mode switching circuit of the electronic load includes: Control module; A switching module, wherein the control module is connected to the first input terminal of the switching module for inputting a first control quantity, and the second input terminal of the switching module is used to input a second control quantity, wherein the first control quantity is a current control quantity, and the second control quantity is any one of a constant voltage control quantity, a constant power control quantity, or a constant resistance control quantity; One or more current loops are provided, each current loop including a first error amplifier and a power transistor. The output of the switching module is connected to the non-inverting input of the first error amplifier, and the inverting input of the first error amplifier is used to input the current feedback signal of the current loop. The output of the first error amplifier is connected to the control terminal of the power transistor, the drain of the power transistor is connected to a power supply, and the source of the power transistor is grounded. The control module is connected to the control terminal of the switching module to control the input control quantity of the current loop to switch to a first control quantity or a second control quantity, so that the electronic load switches to a constant current mode or a target mode, where the target mode is any one of constant voltage, constant power, or constant resistance modes. An upper limit control circuit includes a second error amplifier, a first switching transistor, and a negative power supply terminal. The control module is connected to the inverting input of the second error amplifier to input the upper limit control quantity of the current. The output terminal of the second error amplifier is connected to the control terminal of the first switching transistor. One end of the first switching transistor is connected to both the non-inverting input and the non-inverting input of the second error amplifier. The other end of the first switching transistor is connected to the negative power supply terminal. The first switching transistor is a high-level active switching transistor. The lower limit control circuit includes a third error amplifier, a second switching transistor, and a positive power supply terminal. The control module is connected to the inverting input of the third error amplifier to input the lower limit control quantity of the current. The output terminal of the third error amplifier is connected to the control terminal of the second switching transistor. One end of the second switching transistor is connected to the non-inverting input of the second error amplifier and the non-inverting input of the first error amplifier, respectively. The other end of the second switching transistor is connected to the positive power supply terminal. The second switching transistor is a low-level active switching transistor. The control module switches the electronic load mode using an electronic load control method, which includes the following steps: Obtain a mode switching instruction, which is used to instruct the electronic load to switch to constant current mode or target mode; Obtain the current parameters of the electronic load; The upper and lower current limits during the switching process are obtained based on the mode switching command and current parameters. Wherein, when the mode switching command instructs the electronic load to switch from constant current mode to target mode, the current parameter is a current sample value; When the mode switching command instructs the electronic load to switch from the target mode to the constant current mode, the current parameter is the current set value; According to the mode switching command, the switching module is controlled to switch the electronic load to constant current mode or target mode. Furthermore, the upper limit current control quantity is output to the upper limit control circuit according to the upper limit current value, and the lower limit current control quantity is output to the lower limit control circuit according to the lower limit current value.

2. The mode switching circuit for the electronic load according to claim 1, characterized in that, The control module includes: FPGA; A first DAC, wherein the FPGA is connected to the first DAC for outputting a first control quantity; A current sampling circuit is provided, which is used to sample the current of the current loop. The output terminal of the current sampling circuit is connected to the inverting terminal of the first error amplifier, and the output terminal of the current sampling circuit is connected to the current sampling terminal of the FPGA through the first ADC. A voltage sampling circuit is provided, which is used to sample the voltage of the current loop. The output of the voltage sampling circuit is connected to the voltage sampling terminal of the FPGA through a second ADC. The second DAC and the third DAC are connected to the FPGA, which is used to output an upper limit current control value and an lower limit current control value.

3. The mode switching circuit for the electronic load according to claim 2, characterized in that, The target mode is a constant pressure mode, and the control module further includes: The fourth DAC, connected to the FPGA, is used to output voltage control quantities; The fourth error amplifier has its non-inverting input connected to the output of the second DAC, the voltage sampling circuit connected to the inverting input of the fourth error amplifier, and its output connected to the second input of the switching module.

4. The mode switching circuit for the electronic load according to claim 2, characterized in that, The target mode is a constant power mode, and the control module further includes: The multiplier has its output terminal connected to the first input terminal of the current sampling circuit, its voltage sampling circuit connected to the second input terminal of the multiplier, and its output terminal connected to the second input terminal of the switching module.

5. The mode switching circuit for the electronic load according to claim 1, characterized in that, The target mode is a constant resistance mode. The switching module includes a switch, a first DAC, and a reference power supply terminal. The control module includes: FPGA, the FPGA being connected to the input of the first DAC, A voltage sampling circuit is provided, wherein the voltage sampling circuit is used to sample the voltage of the current loop, the output terminal of the voltage sampling circuit is connected to the voltage sampling terminal of the FPGA through a second ADC, the output terminal of the voltage sampling circuit is connected to the first input terminal of the switch, the reference power supply terminal is connected to the second input terminal of the switch, and the output terminal of the switch is connected to the reference voltage terminal of the first DAC. A current sampling circuit is provided, which is used to sample the current of the current loop. The output terminal of the current sampling circuit is connected to the inverting terminal of the first error amplifier, and the output terminal of the current sampling circuit is connected to the voltage sampling terminal of the FPGA through the first ADC. The second DAC and the third DAC are connected to the FPGA, which is used to output an upper limit current control value and an lower limit current control value.

6. The mode switching circuit for the electronic load according to claim 1, characterized in that, The upper limit control circuit also includes: The first capacitor is connected to the inverting input of the second error amplifier through the first capacitor. And / or, the lower limit control circuit further includes: The output terminal of the third error amplifier is connected to the inverting terminal of the third error amplifier via the second capacitor.

7. The mode switching circuit for the electronic load according to claim 1, characterized in that, The step of obtaining the upper and lower current limits during the switching process based on current parameters includes: Obtain current sampling error parameters and current setting error parameters. The current sampling error parameters are used to indicate the error between the actual current sampling value and the current sampling reading value of the electronic load. The current setting error parameters are used to indicate the error between the current setting value and the actual current value of the electronic load. The upper limit and lower limit of the current are calculated based on the current sampling error parameter, the current setting error parameter, and the current parameter.

8. An electronic load, characterized in that, The mode switching circuit includes the electronic load as described in any one of claims 1 to 7.

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