Three-phase input phase correction method based on zero-crossing timestamp

Abstract

The invention relates to the technical field of electronic power, and discloses a three-phase input phase correction method based on a zero crossing point timestamp, which is used for improving the efficiency and accuracy of phase detection. The three-phase input phase correction method based on the zero crossing point timestamp comprises the following steps: acquiring a synchronous sampling signal of three-phase voltage; detecting a zero-crossing timestamp of the first phase voltage based on the sampling signal; acquiring instantaneous values of the second phase voltage and the third phase voltage at a moment corresponding to the zero crossing point timestamp; judging the phase sequence according to the positive-negative relation of the instantaneous values of the second phase voltage and the third phase voltage; and if the phase sequence is determined to be the reverse phase sequence, adjusting the mapping relation of the PWM output signal to realize phase adaptive correction.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and in particular to a three-phase input phase correction method based on zero-crossing timestamps. Background Technology

[0002] Currently, phase sequence detection in the production and commissioning of power electronic equipment mainly relies on manual operation. Technicians need to use instruments such as oscilloscopes to check the voltage waveforms of each phase one by one, relying on manual observation and comparison to identify phase sequence problems caused by wiring errors. This traditional method has obvious drawbacks: low detection efficiency, which severely restricts the pace of mass production; its accuracy depends entirely on the operator's skill level and experience, posing a significant risk of human error; furthermore, manual detection is difficult to standardize, and different operators may arrive at different judgments, making it difficult to guarantee product quality consistency. Therefore, there is an urgent need to develop a technical solution that can automatically identify and correct phase sequence to overcome the inherent limitations of manual detection. Summary of the Invention

[0003] This invention provides a three-phase input phase correction method based on zero-crossing timestamps to solve the problems of low detection efficiency and insufficient reliability caused by reliance on manual detection in the prior art.

[0004] The first aspect of this invention provides a three-phase input phase correction method based on zero-crossing timestamps, comprising: acquiring synchronous sampling signals of three-phase voltages; detecting the zero-crossing timestamp of a first-phase voltage based on the sampling signals; acquiring the instantaneous values ​​of a second-phase voltage and a third-phase voltage at the time corresponding to the zero-crossing timestamp; determining the phase sequence according to the positive and negative relationship between the instantaneous values ​​of the second-phase voltage and the third-phase voltage; and if the phase sequence is determined to be reversed, adjusting the mapping relationship of the PWM output signal to achieve phase adaptive correction.

[0005] In one feasible implementation, the step of detecting the zero-crossing timestamp of the first phase voltage based on the sampled signal includes: comparing the current sampled value of the first phase voltage with the previous sampled value in real time; when the previous sampled value is not less than a preset zero threshold and the current sampled value is less than the zero threshold, determining that a zero-crossing point from positive to negative has occurred; and recording the time when the zero-crossing point occurs as the zero-crossing timestamp.

[0006] In one feasible implementation, obtaining the instantaneous values ​​of the second phase voltage and the third phase voltage at the time corresponding to the zero-crossing timestamp includes: triggering an interrupt when the zero-crossing timestamp of the first phase voltage is detected using a pre-set timer; and in the interrupt service routine, reading the sampled values ​​of the second phase voltage and the third phase voltage at the time corresponding to the zero-crossing timestamp from the sampling registers corresponding to the second phase voltage and the third phase voltage, wherein the sampled values ​​are the instantaneous values ​​of the corresponding phase voltages at the zero-crossing timestamp.

[0007] In one feasible implementation, determining the phase sequence based on the positive and negative relationship between the instantaneous values ​​of the second phase voltage and the third phase voltage includes: comparing the instantaneous value of the second phase voltage with a preset zero threshold to determine its positive and negative state; comparing the instantaneous value of the third phase voltage with the zero threshold to determine its positive and negative state; and determining the phase sequence of the three-phase system based on the combination relationship between the positive and negative states of the second phase voltage and the third phase voltage.

[0008] In one feasible implementation, determining the phase sequence of the three-phase system based on the combination of the positive and negative states of the second phase voltage and the third phase voltage includes: when the instantaneous value of the second phase voltage is positive and the instantaneous value of the third phase voltage is negative, the system is determined to be in a positive phase sequence; when the instantaneous value of the second phase voltage is negative and the instantaneous value of the third phase voltage is positive, the system is determined to be in a reverse phase sequence; when the instantaneous values ​​of the second phase voltage and the third phase voltage are both positive or both negative, the current phase sequence determination is determined to be invalid.

[0009] In one feasible implementation, the step of adjusting the mapping relationship of the PWM output signal to achieve phase adaptive correction if the phase sequence is determined to be reverse includes: reconfiguring the logical correspondence between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third phase voltage to be mapped to the second phase.

[0010] In one feasible implementation, the reconfiguration of the logical correspondence between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third phase voltage to be mapped to the second phase, includes: exchanging the configuration parameters of the second and third phase output channels in the output mapping register of the PWM controller; or exchanging the control signal output targets of the second and third phases in the PWM duty cycle calculation module; while keeping the mapping relationship between the first phase PWM output channel and the first phase voltage unchanged.

[0011] A second aspect of the present invention provides a three-phase input phase correction method and apparatus based on zero-crossing timestamps, comprising: a first acquisition module for acquiring synchronous sampling signals of three-phase voltages; a detection module for detecting the zero-crossing timestamp of a first-phase voltage based on the sampling signals; a second acquisition module for acquiring instantaneous values ​​of a second-phase voltage and a third-phase voltage at the time corresponding to the zero-crossing timestamp; a judgment module for judging the phase sequence based on the positive and negative relationship between the instantaneous values ​​of the second-phase voltage and the third-phase voltage; and a correction module for adjusting the mapping relationship of the PWM output signal to achieve phase adaptive correction if the phase sequence is determined to be reversed.

[0012] In one feasible implementation, the detection module is specifically used to: compare the current sampled value of the first phase voltage with the previous sampled value in real time; when the previous sampled value is not less than a preset zero threshold and the current sampled value is less than the zero threshold, determine that a zero-crossing point from positive to negative has occurred; and record the time when the zero-crossing point occurs as a zero-crossing point timestamp.

[0013] In one feasible implementation, the second acquisition module is specifically used to: trigger an interrupt when the zero-crossing timestamp of the first phase voltage is detected using a pre-set timer; in the interrupt service routine, read the sampled values ​​of the second phase voltage and the third phase voltage at the time corresponding to the zero-crossing timestamp from the sampling registers corresponding to the second phase voltage and the third phase voltage, wherein the sampled values ​​are the instantaneous values ​​of the corresponding phase voltage at the time of the zero-crossing timestamp.

[0014] In one feasible implementation, the judgment module includes: a first comparison unit, used to compare the instantaneous value of the second phase voltage with a preset zero threshold to determine its positive or negative state; a second comparison unit, used to compare the instantaneous value of the third phase voltage with the zero threshold to determine its positive or negative state; and a judgment unit, used to determine the phase sequence of the three-phase system based on the combination relationship between the positive and negative states of the second phase voltage and the third phase voltage. In one feasible implementation, the judgment unit is specifically used to: determine the system as having a positive phase sequence when the instantaneous value of the second phase voltage is positive and the instantaneous value of the third phase voltage is negative; determine the system as having a reverse phase sequence when the instantaneous value of the second phase voltage is negative and the instantaneous value of the third phase voltage is positive; and determine the current phase sequence judgment as invalid when the instantaneous values ​​of the second phase voltage and the third phase voltage are both positive or both negative. In one feasible implementation, the correction module includes: a configuration unit, configured to reconfigure the logical correspondence between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third phase voltage to be mapped to the second phase.

[0015] In one feasible implementation, the configuration unit is specifically used to: exchange the configuration parameters of the second-phase and third-phase output channels in the output mapping register of the PWM controller; or exchange the control signal output targets of the second-phase and third-phase in the PWM duty cycle calculation module; and keep the mapping relationship between the first-phase PWM output channel and the first-phase voltage unchanged. A third aspect of the present invention provides an electronic device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor invokes the instructions in the memory to cause the electronic device to execute the above-described three-phase input phase correction method based on zero-crossing timestamps.

[0016] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the above-described three-phase input phase correction method based on zero-crossing timestamps.

[0017] The technical solution provided by this invention involves acquiring synchronous sampling signals of three-phase voltages; detecting the zero-crossing timestamp of the first-phase voltage based on the sampling signals; acquiring the instantaneous values ​​of the second-phase and third-phase voltages at the time corresponding to the zero-crossing timestamp; determining the phase sequence based on the positive and negative relationship of the instantaneous values ​​of the second-phase and third-phase voltages; and adjusting the mapping relationship of the PWM output signal to achieve phase adaptive correction if the phase sequence is determined to be reversed. In this embodiment, by capturing the zero-crossing timestamp of the first-phase voltage in real time and synchronously acquiring the instantaneous values ​​of the other two phase voltages at that specific moment, phase sequence determination can be completed quickly and accurately based solely on the positive and negative relationship of the instantaneous values ​​of the two phase voltages. This method does not rely on additional phase detection hardware circuitry. When reverse phase sequence is detected, phase adaptive correction can be achieved by dynamically adjusting the mapping relationship of the PWM output signal. Compared to manual oscilloscope detection, this phase sequence determination response time is significantly shortened, effectively solving the problem of phase sequence disorder caused by wiring errors, while also greatly improving production debugging efficiency and system reliability, and reducing hardware costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the three-phase input phase correction method based on zero-crossing timestamps in this invention. Figure 2 This is a schematic diagram of another embodiment of the three-phase input phase correction method based on zero-crossing timestamps in this invention. Figure 3 This is a schematic diagram of an embodiment of the three-phase input phase correction method device based on zero-crossing timestamps in this invention. Figure 4This is a schematic diagram of another embodiment of the three-phase input phase correction method device based on zero-crossing timestamps in this invention; Figure 5 This is a schematic diagram of one embodiment of the electronic device in this invention. Detailed Implementation

[0019] This invention provides a three-phase input phase correction method based on zero-crossing timestamps. By coordinating the analysis of zero-crossing timestamps and instantaneous voltage values, the method achieves automatic phase sequence identification and correction, significantly improving the efficiency and accuracy of phase detection.

[0020] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] It is understood that the executing entity of this invention can be a three-phase input phase correction device based on zero-crossing timestamps, or it can be a terminal or a server; the specific implementation is not limited here. This embodiment of the invention will be described using a server as an example.

[0022] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the three-phase input phase correction method based on zero-crossing timestamps in this invention includes: 101. Obtain the synchronous sampling signal of the three-phase voltage; By configuring the microcontroller's high-speed analog-to-digital converter (ADC) module, the three-phase input voltage is synchronously acquired at a sampling frequency of no less than 25kHz. Specifically, the ADC trigger mechanism needs to be set to ensure that the sampling times of the three-phase voltages are strictly aligned to avoid phase measurement errors caused by sampling time deviations. During sampling, the raw voltage signal needs to be properly preprocessed, including signal conditioning, anti-aliasing filtering, and level biasing, to adapt the signal amplitude to the ADC's input range. The acquired digital quantity is transferred to the storage area in real time via DMA technology, forming a continuous three-phase voltage data stream. The accurate implementation of this process provides a reliable data foundation for subsequent zero-crossing detection, and its synchronization performance directly determines the accuracy of the entire phase correction system.

[0023] 102. Detect the zero-crossing timestamp of the first phase voltage based on the sampled signal; The zero-crossing moment of the first-phase voltage is captured by digital signal processing technology. The sampling sequence of the first-phase voltage is continuously monitored, and a sliding window comparison method is used to determine the zero-crossing point: when two adjacent sampled values ​​meet the condition that the previous value is not less than the zero threshold and the current value is less than the zero threshold, a zero-crossing point from positive to negative is determined. During the detection process, the zero threshold is usually set to the median value of the ADC range to accommodate different voltage references. Once a zero-crossing point is identified, the count value of a high-precision timer is immediately read, and this timestamp will be used as the reference time for subsequent processing. This digital detection method overcomes the temperature drift problem of traditional analog circuits, ensuring the accuracy and stability of the timestamp.

[0024] 103. At the time corresponding to the zero-crossing timestamp, obtain the instantaneous values ​​of the second-phase voltage and the third-phase voltage; After determining the zero-crossing timestamp of the first phase, the instantaneous voltage values ​​of the second and third phases at that moment are obtained. This step is implemented through an interrupt service mechanism. When a zero-crossing is detected, an interrupt handler is triggered, and the sampled values ​​of the other two phases are synchronously read from the ADC result buffer. Since the three-phase voltage sampling is performed synchronously, these instantaneous values ​​accurately reflect the actual state of each phase voltage at the zero-crossing moment. To ensure the validity of the data, the system also includes a data verification mechanism to eliminate abnormal sampled values ​​caused by interference. These instantaneous values ​​constitute the key basis for phase sequence determination, and their accuracy directly affects the reliability of the entire correction system.

[0025] 104. Determine the phase sequence based on the sign relationship between the instantaneous values ​​of the second-phase voltage and the third-phase voltage; The instantaneous values ​​of the second and third phase voltages are compared with the zero threshold to determine their respective polarity states. According to the basic principles of three-phase power systems, in the case of a positive phase sequence, when the first phase crosses zero, the second phase voltage should be positive and the third phase voltage should be negative; while in the case of a reverse phase sequence, the polarity relationship is exactly the opposite. The phase sequence state can be determined through simple logical judgment. To enhance anti-interference capability, this method can also include a continuous verification mechanism, requiring consistent judgment results over multiple cycles before finally confirming the phase sequence. This design effectively avoids misjudgments caused by instantaneous interference.

[0026] 105. If the phase sequence is determined to be reversed, the mapping relationship of the PWM output signal is adjusted to achieve phase adaptive correction.

[0027] In Vienna PFC rectifiers, pulse width modulation (PWM) signals are used to control the turn-on and turn-off timing of power switches. When the system detects an inverted phase sequence, it automatically initiates an adjustment process for the PWM output mapping relationship. This step is achieved through software reconfiguration without changing the hardware connections. Specifically, this involves modifying the output mapping table of the PWM controller, outputting the PWM signal originally corresponding to the second phase to the third phase power switch, and simultaneously outputting the third phase PWM signal to the second phase power switch. This dynamic remapping technology ensures that even with an incorrect input phase sequence, the system's internal control logic maintains the correct phase relationship. The entire adjustment process is completed within milliseconds, achieving true online adaptive correction and significantly improving the system's fault tolerance and engineering applicability.

[0028] In this embodiment of the invention, by capturing the zero-crossing timestamp of the first phase voltage in real time and simultaneously acquiring the instantaneous values ​​of the other two phase voltages at that specific moment, phase sequence determination can be completed quickly and accurately simply based on the positive and negative relationship of the instantaneous values ​​of the two phase voltages. This method does not rely on additional phase detection hardware circuits. When reverse phase sequence is detected, phase adaptive correction can be achieved by dynamically adjusting the mapping relationship of the PWM output signal. Compared with the manual oscilloscope detection method, the phase sequence determination response time is significantly shortened. This not only effectively solves the problem of phase sequence disorder caused by wiring errors, but also greatly improves production debugging efficiency and system reliability, and reduces hardware costs.

[0029] Please see Figure 2 Another embodiment of the three-phase input phase correction method based on zero-crossing timestamps in this invention includes: 201. Obtain the synchronous sampling signal of the three-phase voltage; 202. Detect the zero-crossing timestamp of the first phase voltage based on the sampled signal; The current sampled value of the first phase voltage is compared with the previous sampled value in real time. When the previous sampled value is not less than the preset zero threshold and the current sampled value is less than the zero threshold, a zero-crossing point from positive to negative is determined to have occurred. The time when the zero-crossing point occurs is recorded as the zero-crossing point timestamp.

[0030] In the specific implementation of zero-crossing detection, a circular storage buffer is established to manage the sampling data sequence. During each ADC interrupt service routine execution, the microcontroller stores the latest conversion result of the first phase voltage into the current sampling register, and simultaneously transfers the sampling value from the previous interrupt cycle to the historical data register. A fixed threshold comparison method is used for zero-crossing discrimination. This zero-value threshold is preset to the corresponding voltage zero-point reference value based on the ADC range characteristics. When the value in the historical register is not less than the zero-value threshold, and the value in the current sampling register is less than the zero-value threshold, a zero-crossing event from the positive half-cycle to the negative half-cycle is accurately determined. At this time, the processor immediately responds, reads the current count value of the high-precision timer, marks the timestamp as the precise moment of the zero-crossing, and stores it in non-volatile memory. To improve the accuracy of the timestamp, the inherent delay of the ADC sample-and-hold circuit and the interrupt response time can be calculated, and these fixed deviations can be compensated and corrected in real time. A sliding window filtering algorithm is also used, requiring three consecutive sampling points to meet the zero-crossing condition before the event is finally confirmed as valid. This mechanism effectively suppresses false triggering caused by power grid harmonics and random interference, ensuring a stable and reliable zero-crossing time reference.

[0031] 203. At the time corresponding to the zero-crossing timestamp, obtain the instantaneous values ​​of the second-phase voltage and the third-phase voltage; Using a pre-set timer, an interrupt is triggered when the zero-crossing timestamp of the first phase voltage is detected. In the interrupt service routine, the sampled values ​​of the second and third phase voltages at the corresponding zero-crossing timestamps are read from the sampling registers corresponding to the second and third phase voltages. The sampled values ​​are the instantaneous values ​​of the corresponding phase voltages at the zero-crossing timestamps.

[0032] A time reference unit is established by configuring a high-precision timer module. When the first phase voltage zero-crossing event is detected, the hardware comparator immediately generates a trigger signal, which is directly connected to the processor's high-speed interrupt input port. After the interrupt service routine completes context saving within three clock cycles, it first accesses the result buffer of the analog-to-digital converter (ADC). It then reads the sampling registers of the second and third phase voltage channels in batches via direct memory access. Because the ADC uses synchronous sampling technology, the sampling times of each channel are strictly aligned, so the acquired sampled values ​​accurately correspond to the instantaneous voltage state at the zero-crossing point of the first phase. To ensure data integrity, the ADC status flag is checked before the read operation to confirm that the conversion is complete and the data is valid. The read raw sampled values ​​are stored in a designated double-buffer structure after offset calibration and gain compensation for use by subsequent phase sequence determination algorithms. The entire interrupt handling process is optimized at the assembly level to ensure that all operations are completed within ten microseconds, thereby accurately capturing the true instantaneous values ​​of each phase voltage at the zero-crossing point.

[0033] 204. Compare the instantaneous value of the second phase voltage with the preset zero threshold to determine its positive or negative state; The instantaneous sampled value of the second-phase voltage is rapidly compared with a preset zero-value reference threshold. This comparison is directly executed by the processor's arithmetic logic unit. When the instantaneous sampled value of the second-phase voltage is greater than the zero-value threshold, the voltage state is marked as positive and the corresponding flag in the status register is set. When the instantaneous sampled value is less than the zero-value threshold, it is marked as negative and the corresponding flag is cleared. To ensure reliability, three consecutive sampling comparison operations are performed. If the three results are consistent, the final state is confirmed. This redundant verification mechanism effectively eliminates misjudgments caused by occasional interference. The final determined positive or negative state information is stored in a specific state variable.

[0034] 205. Compare the instantaneous value of the third-phase voltage with the zero threshold to determine its positive or negative state; The comparison process for the third-phase voltage is similar to that for the second-phase voltage: the instantaneous sampled value of the third-phase voltage is quickly compared with a preset zero-value reference threshold. This comparison is directly executed by the processor's arithmetic logic unit. When the instantaneous sampled value of the third-phase voltage is greater than the zero-value threshold, the voltage state of that phase is marked as positive and the corresponding flag bit in the status register is set; when the instantaneous sampled value of the third-phase voltage is less than the zero-value threshold, it is marked as negative and the corresponding flag bit is cleared. To ensure reliability, three consecutive sampling comparison operations are performed. If the three results are consistent, the final state is confirmed. This redundancy check mechanism effectively eliminates misjudgments caused by occasional interference. The final determined positive or negative state information is stored in a specific state variable.

[0035] 206. Determine the phase sequence of a three-phase system based on the combination relationship between the positive and negative states of the second-phase voltage and the third-phase voltage; When the instantaneous value of the second phase voltage is positive and the instantaneous value of the third phase voltage is negative, the system is determined to be in positive phase sequence; when the instantaneous value of the second phase voltage is negative and the instantaneous value of the third phase voltage is positive, the system is determined to be in reverse phase sequence; when the instantaneous values ​​of the second phase voltage and the third phase voltage are both positive or both negative, the current phase sequence determination is deemed invalid.

[0036] When the second-phase status flag is detected to be in a positive polarity state while the third-phase status flag is in a negative polarity state, the phase sequence determination module immediately outputs a positive phase sequence confirmation signal and updates the phase sequence status register to the normal phase sequence mode. When the second-phase status flag is detected to be in a negative polarity state while the third-phase status flag is in a positive polarity state, the phase sequence determination module generates a reverse phase sequence alarm signal and marks the phase sequence status register as an abnormal phase sequence mode. If two phase status flags are both positive or both are both negative, the phase sequence determination module marks the current judgment as invalid and initiates a retry mechanism. To improve the reliability of the judgment results, the phase sequence judgment results within five consecutive power grid cycles must be completely consistent. Any inconsistent judgments during this period will cause the confirmation counter to be reset and recounted. Only when the number of consecutive confirmations reaches a set threshold will the final phase sequence judgment result be adopted by the system and used for subsequent phase correction control. This multi-verification mechanism effectively avoids misjudgments caused by voltage distortion or transient interference, ensuring the accuracy of phase sequence determination and the stability of system operation.

[0037] 207. If the phase sequence is determined to be reversed, the logical correspondence between the PWM output signal and the three-phase input voltage is reconfigured. The PWM output signal originally mapped to the second phase voltage is changed to be mapped to the third phase, and the PWM output signal originally mapped to the third phase voltage is changed to be mapped to the second phase.

[0038] In the output mapping register of the PWM controller, exchange the configuration parameters of the second and third phase output channels; or in the PWM duty cycle calculation module, exchange the control signal output targets of the second and third phases; keep the mapping relationship between the first phase PWM output channel and the first phase voltage unchanged.

[0039] Once the system confirms a reverse phase sequence, the phase correction module immediately initiates a dynamic remapping process for the PWM output signal. This process involves modifying the hardware configuration registers of the PWM controller to switch signal channels. Specifically, the configuration parameters of the second-phase output channel are written to the third-phase mapping register, and vice versa. At the software level, the output target of the PWM duty cycle calculation module is adjusted synchronously, redirecting the control signal originally sent to the second-phase power switch to the third phase, and vice versa. The entire remapping process ensures that the first-phase PWM output channel maintains its original mapping relationship, only logically swapping the two phases with phase misalignment. After the mapping adjustment, a closed-loop verification is automatically performed, confirming the correction effect by real-time monitoring of the corrected phase relationship. If the verification fails, a re-correction mechanism is triggered. This hardware-software collaborative mapping adjustment method can complete phase adaptive correction within milliseconds, effectively eliminating phase sequence disorder caused by external wiring errors, while maintaining continuous and stable operation of the power circuit.

[0040] In this embodiment of the invention, three-phase voltage signals are acquired through synchronous sampling technology, and the instantaneous values ​​of each phase voltage are captured based on the zero-crossing timestamp. The positive and negative state combinations of the instantaneous voltage values ​​of the second and third phases are used to automatically identify the phase sequence. When an inverse phase sequence is determined, the output channels of the second and third phases are interchanged by dynamically reconfiguring the logical mapping relationship of the pulse width modulation output signals, thereby achieving phase adaptive correction. This method requires no external hardware detection circuit. Compared with manual oscilloscope detection, the phase sequence judgment response time is significantly shortened, solving the problem of phase sequence disorder caused by wiring errors. This significantly improves production debugging efficiency and system reliability, while effectively reducing hardware and manual maintenance costs.

[0041] The above describes the three-phase input phase correction method based on zero-crossing timestamps in the embodiments of the present invention. The following describes the three-phase input phase correction device based on zero-crossing timestamps in the embodiments of the present invention. Please refer to [link / reference]. Figure 3 One embodiment of the three-phase input phase correction device based on zero-crossing timestamps in this invention includes: The first acquisition module 301 is used to acquire the synchronous sampling signal of the three-phase voltage; Detection module 302 is used to detect the zero-crossing timestamp of the first phase voltage based on the sampled signal; The second acquisition module 303 is used to acquire the instantaneous values ​​of the second phase voltage and the third phase voltage at the time corresponding to the zero-crossing timestamp; The judgment module 304 is used to determine the phase sequence based on the positive and negative relationship between the instantaneous values ​​of the second phase voltage and the third phase voltage; The correction module 305 is used to adjust the mapping relationship of the PWM output signal to achieve phase adaptive correction if the phase sequence is determined to be reverse.

[0042] In this embodiment of the invention, by capturing the zero-crossing timestamp of the first phase voltage in real time and simultaneously acquiring the instantaneous values ​​of the other two phase voltages at that specific moment, phase sequence determination can be completed quickly and accurately simply based on the positive and negative relationship of the instantaneous values ​​of the two phase voltages. This method does not rely on additional phase detection hardware circuits. When reverse phase sequence is detected, phase adaptive correction can be achieved by dynamically adjusting the mapping relationship of the PWM output signal. Compared with the manual oscilloscope detection method, the phase sequence determination response time is significantly shortened. This not only effectively solves the problem of phase sequence disorder caused by wiring errors, but also greatly improves production debugging efficiency and system reliability, and reduces hardware costs.

[0043] Please see Figure 4 Another embodiment of the three-phase input phase correction device based on zero-crossing timestamps in this invention includes: The first acquisition module 301 is used to acquire the synchronous sampling signal of the three-phase voltage; Detection module 302 is used to detect the zero-crossing timestamp of the first phase voltage based on the sampled signal; The second acquisition module 303 is used to acquire the instantaneous values ​​of the second phase voltage and the third phase voltage at the time corresponding to the zero-crossing timestamp; The judgment module 304 is used to determine the phase sequence based on the positive and negative relationship between the instantaneous values ​​of the second phase voltage and the third phase voltage; The correction module 305 is used to adjust the mapping relationship of the PWM output signal to achieve phase adaptive correction if the phase sequence is determined to be reverse.

[0044] Optionally, the detection module 302 can be specifically used for: The current sampled value of the first phase voltage is compared with the previous sampled value in real time. When the previous sampled value is not less than the preset zero threshold and the current sampled value is less than the zero threshold, a zero-crossing point from positive to negative is determined to have occurred. The time when the zero-crossing point occurs is recorded as the zero-crossing point timestamp.

[0045] Optionally, the second acquisition module can be specifically used for: Using a pre-set timer, an interrupt is triggered when the zero-crossing timestamp of the first phase voltage is detected. In the interrupt service routine, the sampled values ​​of the second and third phase voltages at the corresponding zero-crossing timestamps are read from the sampling registers corresponding to the second and third phase voltages. The sampled values ​​are the instantaneous values ​​of the corresponding phase voltages at the zero-crossing timestamps.

[0046] Optionally, the judgment module 304 includes: The first comparison unit 3041 is used to compare the instantaneous value of the second phase voltage with a preset zero threshold to determine its positive or negative state. The second comparison unit 3042 is used to compare the instantaneous value of the third phase voltage with the zero threshold to determine its positive or negative state; The judgment unit 3043 is used to determine the phase sequence of the three-phase system based on the combination relationship between the positive and negative states of the second phase voltage and the third phase voltage. Optionally, the decision unit 3043 can be specifically used for: When the instantaneous value of the second phase voltage is positive and the instantaneous value of the third phase voltage is negative, the system is determined to be in positive phase sequence; when the instantaneous value of the second phase voltage is negative and the instantaneous value of the third phase voltage is positive, the system is determined to be in reverse phase sequence; when the instantaneous values ​​of the second phase voltage and the third phase voltage are both positive or both negative, the current phase sequence determination is deemed invalid. Optionally, the calibration module 305 includes: Configuration unit 3051 is used to reconfigure the logical correspondence between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third phase voltage to be mapped to the second phase.

[0047] Optionally, configuration unit 3051 can be specifically used for: In the output mapping register of the PWM controller, exchange the configuration parameters of the second and third phase output channels; or in the PWM duty cycle calculation module, exchange the control signal output targets of the second and third phases; keep the mapping relationship between the first phase PWM output channel and the first phase voltage unchanged. In this embodiment of the invention, three-phase voltage signals are acquired through synchronous sampling technology, and the instantaneous values ​​of each phase voltage are captured based on the zero-crossing timestamp. The positive and negative state combinations of the instantaneous voltage values ​​of the second and third phases are used to automatically identify the phase sequence. When an inverse phase sequence is determined, the output channels of the second and third phases are interchanged by dynamically reconfiguring the logical mapping relationship of the pulse width modulation output signals, thereby achieving phase adaptive correction. This method requires no external hardware detection circuit. Compared with manual oscilloscope detection, the phase sequence judgment response time is significantly shortened, solving the problem of phase sequence disorder caused by wiring errors. This significantly improves production debugging efficiency and system reliability, while effectively reducing hardware and manual maintenance costs.

[0048] above Figure 3 and Figure 4 The three-phase input phase correction device based on zero-crossing timestamps in this embodiment of the invention will be described in detail from the perspective of modular functional entities. The electronic device in this embodiment of the invention will be described in detail from the perspective of hardware processing.

[0049] See Figure 5 As shown, the electronic device includes a processor 500 and a memory 501. The memory 501 stores machine-executable instructions that can be executed by the processor 500. The processor 500 executes the machine-executable instructions to implement the above-described three-phase input phase correction method based on zero-crossing timestamps.

[0050] Furthermore, Figure 5 The electronic device shown also includes a bus 502 and a communication interface 503. The processor 500, the communication interface 503 and the memory 501 are connected via the bus 502.

[0051] The memory 501 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 503 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 502 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0052] The processor 500 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 500 or by instructions in software form. The processor 500 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 501. The processor 500 reads the information in memory 501 and, in conjunction with its hardware, completes the method steps of the aforementioned embodiment.

[0053] The present invention also provides an electronic device, the computer device including a memory and a processor, the memory storing computer-readable instructions, which, when executed by the processor, cause the processor to perform the steps of the three-phase input phase correction method based on zero-crossing timestamps described in the above embodiments.

[0054] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the three-phase input phase correction method based on zero-crossing timestamps.

[0055] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0056] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0057] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A zero-crossing time-stamp based three-phase input phase correction method, characterized in that, The three-phase input phase correction method based on zero-crossing point timestamp comprises: obtaining a synchronous sampling signal of three-phase voltage; detecting a zero-crossing point timestamp of a first-phase voltage based on the sampling signal; obtaining instantaneous values of a second-phase voltage and a third-phase voltage at a time corresponding to the zero-crossing point timestamp; judging a phase sequence according to a positive-negative relationship of the instantaneous values of the second-phase voltage and the third-phase voltage; if the phase sequence is determined to be reverse, adjusting a mapping relationship of a PWM output signal to realize adaptive phase correction.

2. The zero-crossing time-stamped three-phase input phase correction method of claim 1, wherein, The method for detecting the zero-crossing point timestamp of the first-phase voltage based on the sampling signal comprises: comparing a current sampling value of the first-phase voltage with a previous sampling value in real time; when the previous sampling value is not less than a preset zero value threshold and the current sampling value is less than the zero value threshold, determining that a zero-crossing point from positive to negative occurs; recording a time when the zero-crossing point occurs as the zero-crossing point timestamp.

3. The zero-crossing time-stamped three-phase input phase correction method of claim 1, wherein, The method for obtaining the instantaneous values of the second-phase voltage and the third-phase voltage at the time corresponding to the zero-crossing point timestamp comprises: triggering an interrupt by using a pre-set timer when the zero-crossing point timestamp of the first-phase voltage is detected; in an interrupt service program, reading sampling values of the second-phase voltage and the third-phase voltage at the time corresponding to the zero-crossing point timestamp from sampling registers corresponding to the second-phase voltage and the third-phase voltage, the sampling values being instantaneous values of the corresponding phase voltages at the time of the zero-crossing point timestamp.

4. The zero-crossing time-stamped three-phase input phase correction method of claim 1, wherein, The method for judging the phase sequence according to the positive-negative relationship of the instantaneous values of the second-phase voltage and the third-phase voltage comprises: comparing the instantaneous value of the second-phase voltage with the preset zero value threshold to determine a positive-negative state thereof; comparing the instantaneous value of the third-phase voltage with the zero value threshold to determine a positive-negative state thereof; determining the phase sequence of the three-phase system based on a combination relationship of the positive-negative states of the second-phase voltage and the third-phase voltage.

5. The zero-crossing time-stamped three-phase input phase correction method of claim 4, wherein, The method for determining the phase sequence of the three-phase system based on the combination relationship of the positive-negative states of the second-phase voltage and the third-phase voltage comprises: when the instantaneous value of the second-phase voltage is positive and the instantaneous value of the third-phase voltage is negative, determining that the system is in a positive phase sequence; when the instantaneous value of the second-phase voltage is negative and the instantaneous value of the third-phase voltage is positive, determining that the system is in a reverse phase sequence; when the instantaneous values of the second-phase voltage and the third-phase voltage are both positive or both negative, determining that the current phase sequence determination is invalid.

6. The zero-crossing time-stamp based three-phase input phase correction method according to any one of claims 1-5, characterized in that, The method for adjusting the mapping relationship of the PWM output signal to realize adaptive phase correction comprises: reconfiguring a logical correspondence relationship between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second-phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third-phase voltage to be mapped to the second phase.

7. The zero-crossing time-stamped three-phase input phase correction method of claim 6, wherein, The method for reconfiguring the logical correspondence relationship between the PWM output signal and the three-phase input voltage, changing the PWM output signal originally mapped to the second-phase voltage to be mapped to the third phase, and changing the PWM output signal originally mapped to the third-phase voltage to be mapped to the second phase comprises: exchanging configuration parameters of second-phase and third-phase output channels in an output mapping register of a PWM controller; Or in the PWM duty cycle calculation module, exchange the control signal output target of the second phase and the third phase; The mapping relationship between the first phase PWM output channel and the first phase voltage is kept unchanged.

8. A zero-crossing time-stamp based three-phase input phase correction device, characterized in that, The three-phase input phase correction device based on zero-crossing point timestamp comprises: A first acquisition module is configured to acquire a synchronous sampling signal of a three-phase voltage; A detection module is configured to detect a zero-crossing point timestamp of a first phase voltage based on the sampling signal; A second acquisition module is configured to acquire instantaneous values of a second phase voltage and a third phase voltage at a time corresponding to the zero-crossing point timestamp; A judgment module is configured to determine a phase sequence according to a positive-negative relationship between the instantaneous values of the second phase voltage and the third phase voltage; A correction module is configured to adjust a mapping relationship of a PWM output signal to realize phase adaptive correction if the phase sequence is determined to be reverse.

9. An electronic device, comprising: The electronic device comprises a memory and at least one processor, and the memory stores instructions; The at least one processor invokes the instructions in the memory, so that the electronic device executes the three-phase input phase correction method based on zero-crossing point timestamp as claimed in any one of claims 1-7.

10. A computer-readable storage medium having stored thereon instructions, the instructions comprising, The instructions are executed by the processor to implement the three-phase input phase correction method based on zero-crossing point timestamp as claimed in any one of claims 1-7.

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