Distributed battery sensor synchronization network

Abstract

The invention discloses a distributed battery sensor synchronization network, which is characterized in that closed-loop network data is updated after data output by a relay unit returns to the relay unit, and the relay unit extracts a reference clock from the closed-loop network data and synchronizes the clock of the relay unit with the reference clock. Therefore, each relay unit can calculate data and command delay according to own address (position) and perform time compensation to finish synchronous detection.

Description

Technical Field

[0001] This invention relates to a distributed battery sensor synchronization network, belonging to the field of battery management. Background Technology

[0002] Distributed battery systems require real-time monitoring of each battery's status via sensor networks, specifically monitoring its voltage, current, and temperature. Existing sensor networks, such as... Figure 1 As shown, it includes a gateway connected in a daisy chain and multiple battery sensor relay units (subsequent detection "relay units"). Each relay unit is connected to a battery or battery module, collects the battery's status parameters, and uploads all collected status parameters to the host computer through the gateway.

[0003] exist Figure 1 In the network, each daisy chain unit sends data using protocols such as SPI / UART and uses asynchronous communication. The operating frequency of each node unit is different due to process deviations and other reasons, making it impossible to achieve accurate synchronous detection. Summary of the Invention

[0004] This invention provides a distributed battery sensor synchronization network, which solves the problems disclosed in the background art.

[0005] According to one aspect of this disclosure, a distributed battery sensor synchronization network is provided, characterized in that it includes a gateway constituting a closed-loop network and multiple relay units; each relay unit receives closed-loop network data containing its own data transmitted at the previous moment, extracts a reference clock from the closed-loop network data, synchronizes its own high-frequency clock with the reference clock, and uses the frequency and frequency division of the synchronized high-frequency clock as the reference operating frequency for all its digital circuits and switching circuits; updates its own data transmitted at the previous moment in the closed-loop network data with its own data to be transmitted at the current moment, and multiplexes it into the corresponding time slot in the closed-loop network data before transmission.

[0006] In some embodiments of this disclosure, the static bias current of the analog circuitry in all relay units is consistent.

[0007] In some embodiments of this disclosure, the relay unit uses a phase-locked loop (PLL) to synchronize its high-frequency clock with a reference clock; extracting the reference clock from the closed-loop network data includes: filtering the closed-loop network data, replacing all 0s with 1s in the filtered closed-loop network data, and filtering and attenuating jitter after passing through the PLL feedback loop to obtain a stable reference clock in the closed-loop network.

[0008] In some embodiments of this disclosure, updating the data sent by the user in the previous moment in the closed-loop network data to the data to be sent by the user in the current moment, and reusing it in the corresponding time slot in the closed-loop network data, includes: reading the data sent by the user in the previous moment from the closed-loop network data, updating the data sent by the user in the previous moment to the data to be sent by the user in the current moment, and reusing it in the corresponding time slot in the closed-loop network data.

[0009] In some embodiments of this disclosure, before reading data or after multiplexing data, jitter attenuation processing is performed on the closed-loop network data according to the synchronized high-frequency clock.

[0010] In some embodiments of this disclosure, before transmitting the multiplexed closed-loop network data, the relay unit performs "0" and "1" signal judgment on the closed-loop network data, modulates the judged signal with a synchronized high-frequency clock, and transmits the modulated signal according to the synchronized high-frequency clock; wherein the "1" signal is modulated into a waveform suitable for closed-loop network transmission.

[0011] In some embodiments of this disclosure, a power amplifier is used to amplify the signal before transmitting the modulated signal.

[0012] In some embodiments of this disclosure, the power amplifier is a Class AB power amplifier. The static bias current is input to the Class AB power amplifier as a reference current after being controlled by the static current, and the static current of the output stage of the Class AB power amplifier is controlled by the reference current.

[0013] In some embodiments of this disclosure, the output of the power amplifier is also connected to an impedance matching circuit.

[0014] In some embodiments of this disclosure, the reference clock in the closed-loop network is the clock of the gateway or the clock of any relay unit.

[0015] The beneficial effects achieved by this invention are as follows: 1. After the data output by the relay unit returns to itself, it updates the closed-loop network data. The relay unit extracts a reference clock from the closed-loop network data and synchronizes its own high-frequency clock with the reference clock. In this way, each relay unit can calculate the data and command delays based on its own address (location) and perform time compensation to complete synchronization detection. 2. After the data output by the relay unit returns to itself, it updates the closed-loop network data. The transmission code stream of each relay unit is consistent, making the driving power consumption of all relay units consistent. The relay unit extracts a reference clock from the closed-loop network data, synchronizes its own high-frequency clock with the reference clock, and uses the frequency and frequency division of the synchronized high-frequency clock as the reference operating frequency of all its digital circuits and switching circuits. This makes the dynamic power consumption of the digital circuits and switching circuits of all relay units consistent. The analog circuits of the relay units use a consistent static bias current, making the static power consumption of the analog circuits of all relay units consistent. The power consumption of all relay units in this invention is close to consistent, ensuring the power balance of the distributed battery. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an existing sensor network; Figure 2 This is a schematic diagram of the structure of a distributed battery sensor synchronization network; Figure 3 This is a schematic diagram of the relay unit structure; Figure 4 A schematic diagram of the clock extraction circuit for data recovery; Figure 5 Waveforms for filtering, shaping, and reference clock; Figure 6 This is a schematic diagram of a jitter attenuation circuit; Figure 7 This is a waveform reshaping diagram. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0018] Unless otherwise stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0019] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0020] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0021] It should be noted that similar symbols and letters in the following figures represent similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0022] To address the problem of synchronous detection in distributed battery sensor synchronization networks, this disclosure proposes a distributed battery sensor synchronization network.

[0023] Figure 2 This is a schematic diagram of one embodiment of the distributed battery sensor synchronization network disclosed herein, including a gateway and multiple relay units, which constitute a closed-loop network. The relay units are externally connected to batteries to receive status parameters such as battery voltage, current, and temperature. The gateway is externally connected to a host computer, which can read closed-loop network data (i.e., data transmitted in the closed-loop network) in real time through the gateway.

[0024] To achieve synchronization detection, the relay unit receives closed-loop network data containing its own data transmitted in the previous moment, extracts the reference clock from the closed-loop network data, synchronizes its own high-frequency clock with the reference clock, and uses the frequency and frequency division of the synchronized high-frequency clock as the reference operating frequency for all its digital circuits and switching circuits. The relay unit updates its own data transmitted in the closed-loop network data in the previous moment with its own data to be transmitted in the current moment, and reuses the updated data in the closed-loop network data, that is, reuses it in the corresponding time slot in the closed-loop network data. In this way, each relay unit can calculate the data and command delay according to its own address (location) and perform time compensation to complete the synchronization detection.

[0025] It should be noted that the reference clock can be the gateway's clock or the clock of any relay unit; the relay unit's clock can be an internally generated clock or an external reference clock, such as a clock provided by a host computer or an external clock circuit. Both the relay unit and the gateway use this clock as the reference for sending and receiving data.

[0026] It should be noted that, in Figure 1In this network, each daisy-chain unit sends data to the gateway and then terminates, resulting in inconsistent data streams and power consumption among the relay units. Each battery sensor relay unit uses its own internal clock for data sampling, leading to inconsistent power consumption in the digital circuitry within each unit. Furthermore, manufacturing variations in the daisy-chain unit cause inconsistent static bias currents, resulting in inconsistent static power consumption. Therefore, this structure suffers from inconsistent power consumption among relay units, leading to uneven power consumption in the distributed battery network.

[0027] To achieve consistent power consumption, in some embodiments, the static bias current of the analog circuitry in all relay units is set to be consistent.

[0028] Since the data output by the relay unit updates the closed-loop network data after returning to itself, the transmission code stream of each relay unit is consistent, resulting in consistent drive power consumption for all relay units. The relay unit extracts the reference clock from the closed-loop network data, synchronizes its own high-frequency clock with the reference clock, and uses the frequency and frequency division of the synchronized high-frequency clock as the reference operating frequency for all its digital circuits and switching circuits, making the dynamic power consumption of the digital circuits and switching circuits of all relay units consistent. The analog circuits of the relay units adopt a consistent static bias current, making the static power consumption of the analog circuits of all relay units consistent. Therefore, the power consumption of all relay units in the network is nearly consistent, ensuring the power balance of the distributed batteries.

[0029] It should be noted that the static bias current is a reference current with a stable value IR. It can be generated by an internal reference source and an external precision resistor through current-to-voltage conversion, or it can be calibrated through internal processes, testing trimming, etc.

[0030] It should be noted that the existing relay unit includes a signal acquisition circuit, a line receiver, a clock extraction circuit, and a line transmitter. In order to achieve the above-mentioned function of consistent power consumption, certain improvements have been made to the existing structure, specifically improvements to the line receiver, the clock extraction circuit, and the line transmitter.

[0031] like Figure 3 As shown, the signal acquisition circuit mainly includes a processor and multiple acquisition branches connected to the processor. Each acquisition branch includes a PGA (Programmable Array of Generic Amplifiers) and an ADC (Analog-to-Digital Converter) connected in series. The input of the PGA receives and amplifies the acquired state parameters. The ADC performs analog-to-digital conversion on the acquired state parameters and transmits the converted parameters to the processor. The processor performs data filtering, processing, and storage functions, and also controls the state machine (similar to the program control of a microcontroller, which automatically controls the chip to switch between various states). The processor receives the clock output from the clock extraction circuit and uses the frequency of this clock as the operating frequency.

[0032] The line receiver mainly includes a signal reception and determination circuit, a data recovery and clock extraction circuit, and a data demultiplexing circuit.

[0033] The signal receiving and determination circuit receives closed-loop network data, which is an analog signal. It needs to be amplified in analog form, and then peak detection and comparison are performed to determine the data "0" and "1". After digital filtering, a series of digital code streams "1" and "0" are obtained.

[0034] The data recovery clock extraction circuit filters the output signal of the signal receiving and judgment circuit to remove noise and glitches, making the edges of the "1" data more certain. It extracts the reference clock in the closed-loop network from the filtered data. Specifically, it replaces all 0s with 1s in the filtered closed-loop network data and filters and attenuates the jitter after passing it through the phase-locked loop feedback loop to obtain a stable reference clock in the closed-loop network.

[0035] It should be noted that the closed-loop network data includes data from each relay unit. The data of these relay units are arranged in a certain time slot (position or mark). The data demultiplexing circuit is used to read the data or commands related to itself, or its own closed-loop data (i.e., the data it sent at the previous moment) from the closed-loop network data after data recovery. The output of the data demultiplexing circuit is sent to the processor of the signal acquisition circuit for verification through a buffer, and to the line transmitter through a buffer.

[0036] It should be noted that the recovered closed-loop network data may have significant jitter. Therefore, before the data demultiplexing circuit reads the data, jitter attenuation processing can be performed on the recovered closed-loop network data (i.e., the filtered data mentioned above) based on the synchronized high-frequency clock. Specifically, the data with large jitter is read out by a stable clock to form a data stream with smaller and more stable jitter.

[0037] Specifically, jitter attenuation circuitry can be used for jitter reduction. This jitter attenuation circuitry can be integrated between the data recovery clock extraction circuit and the data demultiplexing circuit. (See...) Figure 6 The jitter attenuation circuit includes a first-in-first-out (FIFO) data buffer and a digital phase-locked loop (DPLL). It stores data with large jitter in the data buffer (FIFO) and then reads it out by a stable high-frequency clock, so that the recovered data is synchronized with the extracted stable high-frequency clock. The depth of the buffer determines the jitter attenuation performance.

[0038] like Figure 4 and 5As shown, the clock extraction circuit contains a clock generator with a frequency of approximately Fdata (which is also the data transmission rate). Specifically, it uses an oscillator within the phase-locked loop (PLL) with a frequency defined around Fdata. After multiplying by N, a high-frequency clock is generated, expressed as Fs = N×Fdata, where N is generally an integer, such as 16. This high-frequency clock serves as the input clock for the data recovery clock extraction circuit, which uses Fs as its operating frequency. The output of the data comparison and judgment is used as a digital signal. After passing through a high-speed digital filter to remove noise, the rising edge of the "1" is determined to identify the position of the data "1" and the position of the "0", thus obtaining the filtered data. During data recovery, all data "0"s in the filtered data are replaced with "1", generating a reference clock. This clock signal is filtered for jitter in the PLL and multiplied by N to generate a high-frequency clock. The reference clock is synchronized with the high-frequency clock of the relay unit. The synchronized high-frequency clock is then sent to all digital circuits and switching circuits in the relay unit.

[0039] The data recovery clock extraction circuit of each relay unit ensures that the clock and operating frequency of each node are consistent. This ensures that the transmission delay (the time interval from receiving the signal to outputting the signal) of each node is consistent, being an integer multiple N0 of the high-frequency clock period Fs, denoted as T. d0 =N0 / F, where F is Fs or a frequency division of Fs, depending on the accuracy requirements, T d0 Let T be the transmission delay of a node. Assuming the closed-loop network has n nodes, the total delay of the entire closed-loop network is T. dt =n*T d0 Let the delay time for translating and executing the broadcast detection command be M0 times F cycles, and T dCOM =M0*F, when the host computer or gateway issues a command, the delay time for the k-th node to receive the command is T. dk =(k-1)*T d0 Therefore, the insertion wait time T at the kth node is... kwait =T dt -T dk Then, the total time from when the k-th node issues a command to when it executes the detection is T. kex =T dk +T kwait +T dCOM = T dk + T dt -T dk +T dCOM = T dk + T dCOM This enables synchronous detection. Generally, the transmission delay of cables is negligible. However, if the cable is very long, the cable delay must be considered, affecting T... dk T dtCalibration compensation is sufficient; the time resolution is 1 / F, and the highest resolution is 1 / Fs.

[0040] The line transmitter includes a multiplexer, a 0 / 1 signal discrimination circuit, a waveform shaping circuit, a power amplifier, and an impedance matching circuit.

[0041] The multiplexer obtains its own data to be transmitted at the current moment from the processor of the signal acquisition circuit through a buffer, extracts the closed-loop network data containing its own data transmitted at the previous moment from the data demultiplexing circuit through a buffer, extracts the data transmitted at the previous moment from the closed-loop network data and updates it with its own data to be transmitted at the current moment, and multiplexes it into the corresponding time slot in the closed-loop network data.

[0042] It should be noted that multiplexing involves inserting local real-time data into the closed-loop network data according to the corresponding time slot positions. In this way, the data of each relay node (including the gateway) is arranged and transmitted in the closed-loop network data according to the corresponding time slot positions.

[0043] If a jitter attenuation circuit is not integrated between the data recovery clock extraction circuit and the data demultiplexing circuit, the multiplexed data may have significant jitter. Therefore, after multiplexing the data, jitter attenuation processing can be performed on the multiplexed closed-loop network data based on the synchronized high-frequency clock. Specifically, the jitter attenuation circuit can be integrated between the multiplexer and the 0 / 1 signal judgment circuit, so that the data transmitted by the line is stable with low jitter and synchronized with the reference clock. In other words, the jitter attenuation circuit is integrated between the data recovery clock extraction circuit and the data demultiplexing circuit, or between the multiplexer and the 0 / 1 signal judgment circuit.

[0044] The 01 signal judgment circuit is used to judge the "0" and "1" signals of the closed-loop network data. There are two main types of 01 signal judgment. At the receiving end, the amplitude of the analog signal input voltage is compared with the reference level. If it is higher than the reference level, it is a high level "1" and lower than the reference level "0". Then there is the digital filter judgment, which mainly uses a high-frequency clock to determine the width of the high level. If it is too narrow, it is a glitch, and if it is too wide, it is "1". The circuit filters out noise in the judgment signal and determines the position of the rising or falling edge of the digital "1".

[0045] The waveform shaping circuit determines whether the closed-loop network data "0" or "1" signal to be transmitted is to be modulated by a synchronized high-frequency clock.

[0046] It should be noted that waveform shaping uses a synchronized high-frequency clock to modulate a "1" data waveform. The "1" signal is modulated into a waveform suitable for closed-loop network transmission, including controlling the rising and falling edge speeds, the width of the high level, etc., thereby controlling the harmonic components of the waveform to achieve good EMI / EMC performance and power efficiency. The shaped waveform can be a square wave, a half-sine wave, a sine wave, etc., which can be set according to the actual application. The "0" data is modulated to a "0" level. Since a high-frequency clock is a reference clock that is N times the frequency, a waveform can be depicted using N points. For example, when Fdata = 2MHz, the period is 0.5µs, and N = 16, the 0.5µs is divided into 16 equal parts, each part being 0.5µs / 16, t1, t2, ..., t16 = 0.5 / 16µs. The amplitude of each time slot is 1×V01 = V01, 1×V02 = V02, ..., 1×V16 = V16. This forms the waveform of a data "1". Figure 7 The purpose of waveform shaping is to convert the transmitted signal into a waveform that is easy to transmit through the channel (communication line), with smaller bandwidth and higher harmonic components, thus achieving good EMI / EMC performance. For the data "0", the amplitude of each time slot is 0×V01=0, 0×V02=0, ..., 0×V16=0, which is the waveform of a data "0", which is actually a 0 level.

[0047] A power amplifier is used to amplify the power of a modulated signal, and the output of the amplified signal is output through an impedance matching circuit.

[0048] It should be noted that, in order to improve driving efficiency, the power amplifier adopts a Class AB power amplifier, and the static bias current is input to the Class AB power amplifier as a reference current. At the same time, the static bias current controls the static current of the output stage of the Class AB power amplifier through a static current control circuit.

[0049] It should be noted that, in Figure 3 In the circuit, the static bias current is mainly output to the signal acquisition circuit, power management / reference power supply circuit, signal receiving and judgment circuit, waveform shaping circuit and power amplifier.

[0050] Based on the synchronized clock and static bias current, the waveform of the data output by the 01 data signal judgment circuit is shaped. By inserting an impedance matching circuit at the output of the power amplifier, the power is reduced by half compared to the method of inserting an external impedance matching resistor, thereby improving the transmission efficiency and the EMI / EMC performance of the relay unit.

[0051] It should be noted that, as a node or gateway providing a reference clock, after receiving data, it continues to send data using its local clock, and the extracted clock can be used to determine the system's status.

[0052] It should be noted that in a closed-loop network, any node (relay unit and gateway) can read data from all nodes in the network. Since the voltage levels of each node are inconsistent, the communication connection can be isolated, such as by capacitor or transformer isolation, or it can be wireless communication, but the transmitted signal must contain clock information.

[0053] If baseband transmission is used, its encoding method should meet the following requirements: (1) It should not contain DC and should have as few low-frequency components as possible; (2) It should contain rich timing information so that timing signals can be extracted from the received code stream; (3) The main lobe width of the power spectrum should be narrow to save transmission bandwidth; (4) It should not be affected by the statistical characteristics of the information source, that is, it should be able to adapt to changes in the information source; (5) It should have inherent error detection capability, that is, the code pattern should have a certain regularity so that macroscopic detection can be performed; (6) The encoding and decoding should be simple to reduce communication delay and cost. Commonly used codes include AMI, HDB3, and CMI codes.

[0054] The closed-loop network described above can achieve synchronous detection, and the power consumption of all relay units is nearly consistent, ensuring the power balance of the distributed batteries.

[0055] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A distributed battery sensor synchronization network, characterized in that, It includes a gateway constituting a closed-loop network and multiple relay units; the relay unit receives closed-loop network data containing its own data transmitted at the previous moment, extracts the reference clock in the closed-loop network from the closed-loop network data, synchronizes its own high-frequency clock with the reference clock, and uses the frequency and frequency division of the synchronized high-frequency clock as the reference operating frequency of all its digital circuits and switching circuits; it updates its own data transmitted at the previous moment in the closed-loop network data with its own data to be transmitted at the current moment, and multiplexes it into the corresponding time slot in the closed-loop network data before transmitting it.

2. The distributed battery sensor synchronization network according to claim 1, characterized in that, The static bias current of the analog circuits in all relay units is consistent.

3. The distributed battery sensor synchronization network according to claim 1, characterized in that, In the relay unit, a phase-locked loop is used to synchronize its own high-frequency clock with the reference clock; Extracting the reference clock from the closed-loop network data includes: The closed-loop network data is filtered by replacing all 0s with 1s. After passing through a phase-locked loop feedback loop for filtering and attenuation of jitter, a stable reference clock is obtained in the closed-loop network.

4. The distributed battery sensor synchronization network according to claim 1, characterized in that, The data is updated from the previous time step to the current time step of the closed-loop network data, and then reused in the corresponding time slot of the closed-loop network data, including: The data sent by the user in the previous moment is retrieved from the closed-loop network data, updated to the data to be sent in the current moment, and reused in the corresponding time slot in the closed-loop network data.

5. The distributed battery sensor synchronization network according to claim 4, characterized in that, Before reading data or after reusing data, jitter attenuation processing is performed on the closed-loop network data based on the synchronized high-frequency clock.

6. The distributed battery sensor synchronization network according to claim 1, characterized in that, In the relay unit, before sending the multiplexed closed-loop network data, the closed-loop network data is judged by "0" and "1" signals. The judged signals are modulated by a synchronized high-frequency clock, and the modulated signals are sent according to the synchronized high-frequency clock. Among them, the "1" signal is modulated into a waveform suitable for closed-loop network transmission.

7. The distributed battery sensor synchronization network according to claim 6, characterized in that, Before transmitting the modulated signal, a power amplifier is used to amplify the signal.

8. The distributed battery sensor synchronization network according to claim 7, characterized in that, The power amplifier adopts a Class AB power amplifier. The static bias current is input into the Class AB power amplifier as a reference current after being controlled by the static current. The static current of the output stage of the Class AB power amplifier is controlled by the reference current.

9. The distributed battery sensor synchronization network according to claim 7 or 8, characterized in that, The output of the power amplifier is also connected to an impedance matching circuit.

10. The distributed battery sensor synchronization network according to claim 1, characterized in that, The reference clock in a closed-loop network is the clock of the gateway or the clock of any relay unit.

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