A back contact structure of a stacked battery and a method of manufacturing the same, and a photovoltaic cell

Abstract

The application provides a back contact structure of a laminated battery, a preparation method of the back contact structure and a photovoltaic cell. The back contact structure of the laminated battery comprises a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polycrystalline silicon transfer layer which are sequentially stacked. The content of germanium in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer. The lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer. The application effectively reduces the lattice mismatch degree and improves the battery conversion efficiency by optimizing the carrier transfer and interface characteristics.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of photovoltaic cells, and relates to a back contact structure of a stacked cell, in particular to a back contact structure of a stacked cell, a preparation method thereof and a photovoltaic cell. BACKGROUND

[0002] BC cells (Back-Contact Solar Cell) are widely used in electrical devices due to their high conversion efficiency, low resistance, and high short-circuit current. However, the preparation process of BC cells is complex, the cost is high, and the material requirements are high. In BC cells such as TBC (TOPCon Back Contact cell) or IBC (Interdigitated Back Contact), the polysilicon layer serves as the core functional layer for carrier transport and passivation. The uniformity and density of the polysilicon layer directly affect the conversion efficiency of the cell. Currently, LPCVD (Low Pressure Chemical Vapor Deposition) is a commonly used process for preparing polysilicon layers. High-speed deposition mode (deposition rate > 5 nm / min) is often used to improve productivity and improve film quality. However, high-speed airflow can easily form turbulence at the edge of the reaction furnace cavity, causing gas direct blowing effect, which reduces the density of the polysilicon layer at the edge of the substrate, forming a visible white edge, and also easily causing substrate warping. In addition, turbulence disturbance causes deposition rate fluctuations, which also leads to a decrease in film thickness uniformity. Defects on the surface of the film layer cause a decrease in local minority carrier lifetime, resulting in an increase in contact resistance, which in turn reduces the conversion efficiency of the cell. In addition, increasing the deposition temperature significantly increases the engineering heat budget, leading to an increase in cell preparation cost and a decrease in economic benefit.

[0003] To improve the problems in the film preparation process, the existing technology usually adopts a multi-step deposition method, but the process complexity increases significantly, and the crystallization in the polysilicon layer preparation process easily causes interface defects, which reduces the film quality. In addition, interface defects exist in the stacked structure, which increases the recombination loss, even exceeding 20% Voc loss. The energy band mutation between functional layers causes carrier transport impedance, with a conduction band step > 0.3 eV, which adversely affects the electrical performance. Therefore, researchers have improved the doping atoms, such as using carbon-doped amorphous silicon, but this easily leads to an increase in light absorption loss. There are also laser annealing processes to improve the interface, but due to the process window of only ± 5℃, the effect is not good.

[0004] Therefore, how to improve the interface quality of the functional layers in the back contact structure of the cell to improve the electrical performance of the cell is crucial for the further development of BC cells. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application aims to provide a back contact structure of a stacked battery, a preparation method thereof and a photovoltaic cell, which alleviates the lattice mismatch problem between different functional layers by forming a lattice constant gradient structure, forms a continuous conductive structure, realizes band control, and reduces the interface barrier.

[0006] To achieve this purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a back contact structure of a stacked battery, which comprises a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polycrystalline silicon transfer layer arranged in sequence.

[0008] The germanium content in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer.

[0009] The lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer.

[0010] The present application adds a dense silicon germanium crystallization layer between the tunneling oxide layer and the amorphous silicon buffer layer, reduces the band offset, forms a continuous band structure, improves the carrier tunneling capability, and the lattice constant gradient structure of the silicon germanium crystallization layer realizes stress buffering, greatly reduces the lattice mismatch degree of the tunneling oxide layer and silicon, reduces the interface defect density, and alleviates the problem of composite loss.

[0011] As a preferred technical solution of the present application, the germanium content in the silicon germanium crystallization layer is 5at.% to 25at.%, for example, it can be 5at.%, 6at.%, 7at.%, 8at.%, 9at.%, 10at.%, 11at.%, 12at.%, 13at.%, 14at.%, 15at.%, 18at.%, 20at.%, 22at.%, or 25at.%, etc., but is not limited to the listed values, other values not listed in this range are also applicable.

[0012] As a preferred technical solution of the present application, the lattice constant of the silicon germanium crystallization layer increases in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer.

[0013] As a preferred technical solution of the present application, the lattice constant of the silicon germanium crystallization layer changes in a range of 0.543 to 0.548 nm, for example, it can be 0.543 nm, 0.544 nm, 0.545 nm, 0.546 nm, 0.547 nm, or 0.548 nm, but is not limited to the listed values, other values not listed in this range are also applicable.

[0014] The present application controls the gradual change range of the lattice constant within the above range, so that the lattice constant gradually increases from the tunneling oxide layer to the amorphous silicon buffer layer, forming a transition, which can match the amorphous silicon and effectively reduce the lattice mismatch degree.

[0015] As a preferred technical solution of the present application, the amorphous silicon buffer layer is an intrinsic amorphous silicon layer or a lightly doped amorphous silicon layer.

[0016] As an embodiment of the present application, when the amorphous silicon buffer layer is a lightly doped amorphous silicon layer, the doping concentration is 3×10 20 ~4.5×10 20 atoms / cm 3 , for example, it can be 3×10 20 atoms / cm 3 , 3.2×10 20 atoms / cm 3 , 3.4×10 20 atoms / cm 3 , 3.5×10 20 atoms / cm 3 , 3.6×10 20 atoms / cm 3 , 3.8×10 20 atoms / cm 3 , 4.0×10 20 atoms / cm 3 , 4.2×10 20 atoms / cm 3 , or 4.5×10 20 atoms / cm 3 , but is not limited to the listed values, and other values not listed in this range are also applicable.

[0017] As an embodiment of the present application, the polycrystalline silicon transfer layer is an N-type heavily doped polycrystalline silicon layer or a P-type heavily doped polycrystalline silicon layer.

[0018] As an embodiment of the present application, the doping concentration of the polycrystalline silicon transfer layer is 4×10 20 ~5×10 20 atoms / cm 3 , for example, it can be 4.0×10 20 atoms / cm 3 , 4.1×10 20 atoms / cm 3 , 4.2×10 20 atoms / cm 3 , 4.3×10 20 atoms / cm3 , 4.4 x 10 20 atoms / cm 3 , 4.5 x 10 20 atoms / cm 3 , 4.6 x 10 20 atoms / cm 3 , 4.7 x 10 20 atoms / cm 3 , or 5 x 10 20 atoms / cm 3 and so on, but are not limited to the listed values, and other values not listed within the range are also applicable.

[0019] As a preferred technical solution of the present application, the thickness of the tunneling oxide layer is 0.5-2 nm, for example, it can be 0.5 nm, 0.8 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, or 2.0 nm, etc., but is not limited to the listed values, and other values not listed within the range are also applicable.

[0020] As an embodiment of the present application, the thickness of the silicon germanium crystallization layer is 10-18 nm, for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, or 18 nm, etc., but is not limited to the listed values, and other values not listed within the range are also applicable.

[0021] As an embodiment of the present application, the thickness of the amorphous silicon buffer layer is 80-120 nm, for example, it can be 80 nm, 85 nm, 90 nm, 96 nm, 100 nm, 107 nm, 110 nm, 115 nm, or 120 nm, etc., but is not limited to the listed values, and other values not listed within the range are also applicable.

[0022] As an embodiment of the present application, the thickness of the polysilicon transfer layer is 80-150 nm, for example, it can be 80 nm, 85 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, etc., but is not limited to the listed values, and other values not listed within the range are also applicable.

[0023] In a second aspect, the present application provides a preparation method of the back contact structure of the stacked battery of the first aspect, and the preparation method comprises: providing a silicon substrate, and growing a tunneling oxide layer on the surface of the silicon substrate by a thermal oxidation method.

[0024] A silicon germanium crystallization layer is formed on the surface of the tunneling oxide layer by low pressure chemical vapor deposition.

[0025] A low temperature vapor deposition is performed on the surface of the silicon germanium crystallization layer to form an amorphous silicon buffer layer.

[0026] A high temperature crystallization treatment is then performed to obtain a polycrystalline silicon transfer layer.

[0027] The present application adopts low pressure chemical vapor deposition to prepare a dense silicon germanium crystallization layer, and then forms an amorphous silicon buffer layer and a polycrystalline silicon transfer layer through a low temperature-high temperature two-step deposition process, thereby reducing interface defects, improving film quality, and effectively reducing production cost budget.

[0028] As a preferred technical solution of the present application, the oxygen partial pressure of the thermal oxidation method is 8.2 kPa to 10 kPa, for example, it can be 8.2 kPa, 8.24 kPa, 8.5 kPa, 8.6 kPa, 8.7 kPa, 9.0 kPa, 9.3 kPa, 9.6 kPa, 9.8 kPa or 10 kPa, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0029] As an embodiment of the present application, the oxygen flow rate of the thermal oxidation method is 35,000 to 50,000 sccm, for example, it can be 35,000 sccm, 37,500 sccm, 38,000 sccm, 39,500 sccm, 40,000 sccm, 42,000 sccm, 43,500 sccm, 45,000 sccm, 45,500 sccm, 48,000 sccm or 50,000 sccm, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0030] As an embodiment of the present application, the growth temperature of the thermal oxidation method is 550 to 680℃, for example, it can be 550℃, 570℃, 585℃, 600℃, 620℃, 635℃, 640℃, 650℃, 660℃ or 680℃, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0031] As an embodiment of the present application, the growth time of the thermal oxidation method is 10 to 20 minutes, for example, it can be 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes, 15 minutes, 16 minutes, 17 minutes, 18 minutes, 19 minutes or 20 minutes, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0032] As one embodiment of the present application, the reaction gas of the low pressure chemical vapor deposition method includes GeH4and SiH4.

[0033] As one embodiment of the present application, the adding ratio of GeH4to SiH4is 1:(7~10), for example, it can be 1:7.0, 1:7.5, 1:8.0, 1:8.2, 1:8.5, 1:8.8, 1:9.0, 1:9.3, 1:9.5 or 1:10, etc., but not limited to the listed values, other values not listed in the range are also applicable.

[0034] As one embodiment of the present application, the flow rate of GeH4is 20~40sccm, for example, it can be 20sccm, 24sccm, 25sccm, 27sccm, 30sccm, 31sccm, 35sccm or 40sccm, etc., but not limited to the listed values, other values not listed in the range are also applicable.

[0035] As one embodiment of the present application, the flow rate of SiH4is 140~280sccm, for example, it can be 140sccm, 150sccm, 160sccm, 180sccm, 185sccm, 200sccm, 210sccm, 220sccm, 240sccm, 250sccm or 280sccm, etc., but not limited to the listed values, other values not listed in the range are also applicable.

[0036] As one embodiment of the present application, the deposition temperature of the low pressure chemical vapor deposition method is 450~550℃, for example, it can be 450℃, 460℃, 470℃, 480℃, 490℃, 500℃, 510℃, 520℃, 530℃ or 550℃, etc., but not limited to the listed values, other values not listed in the range are also applicable.

[0037] By controlling the deposition temperature within the above range, the present application can inhibit the crystal island growth, ensure the continuity of the film layer, avoid the formation of holes or defects, and cause the lattice mismatch.

[0038] As one embodiment of the present application, the deposition pressure of the low pressure chemical vapor deposition method is 15~30Pa, for example, it can be 15Pa, 17Pa, 20Pa, 21Pa, 23Pa, 25Pa, 26Pa, 27Pa, 28Pa or 30Pa, etc., but not limited to the listed values, other values not listed in the range are also applicable.

[0039] The present application can guarantee the compactness of the silicon germanium crystallization layer, improve the band matching, optimize the carrier transmission, improve the photoelectric conversion efficiency of the battery, simplify the operation difficulty, and reduce the process cost.

[0040] As an embodiment of the present application, the deposition rate of the low-pressure chemical vapor deposition method is 1.2-2.5 nm / min, for example, it can be 1.2 nm / min, 1.3 nm / min, 1.4 nm / min, 1.5 nm / min, 1.6 nm / min, 1.7 nm / min, 1.8 nm / min, 2.0 nm / min, 2.2 nm / min, 2.4 nm / min or 2.5 nm / min, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0041] As an embodiment of the present application, the deposition time of the low-pressure chemical vapor deposition method is 6-10 min, for example, it can be 6.0 min, 6.5 min, 7.0 min, 7.5 min, 8.0 min, 8.5 min, 8.7 min, 9.0 min, 9.5 min or 10 min, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0042] As a preferred technical solution of the present application, the deposition temperature of the low-temperature vapor deposition is 470-570℃, for example, it can be 470℃, 480℃, 490℃, 500℃, 510℃, 520℃, 530℃, 540℃, 550℃ or 570℃, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0043] As an embodiment of the present application, the deposition flow rate of the low-temperature vapor deposition is 400-500 sccm, for example, it can be 400 sccm, 415 sccm, 425 sccm, 440 sccm, 450 sccm, 460 sccm, 470 sccm, 480 sccm, 490 sccm or 500 sccm, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0044] As an embodiment of the present application, the deposition rate of the low-temperature vapor deposition is 2-3 nm / min, for example, it can be 2 nm / min, 2.1 nm / min, 2.2 nm / min, 2.3 nm / min, 2.4 nm / min, 2.5 nm / min, 2.6 nm / min, 2.7 nm / min, 2.8 nm / min or 3 nm / min, etc., but not limited to the listed values, other values not listed in this range are also applicable.

[0045] As one embodiment of the present application, the temperature of the high-temperature crystallization process is 580-620℃, for example, it can be 580℃, 585℃, 590℃, 595℃, 600℃, 605℃, 610℃, 615℃, 618℃ or 620℃, but not limited to the listed values, other values not listed in the range are also applicable.

[0046] As one embodiment of the present application, the flow rate of the high-temperature crystallization process is 250-350sccm, for example, it can be 250sccm, 260sccm, 270sccm, 280sccm, 290sccm, 300sccm, 310sccm, 320sccm, 330sccm or 350sccm, but not limited to the listed values, other values not listed in the range are also applicable.

[0047] As one embodiment of the present application, the deposition rate of the high-temperature crystallization process is 2.5-3.5nm / min, for example, it can be 2.5nm / min, 2.6nm / min, 2.7nm / min, 2.8nm / min, 3nm / min, 3.2nm / min or 3.5nm / min, but not limited to the listed values, other values not listed in the range are also applicable.

[0048] As one embodiment of the present application, the crystallization temperature rising rate of the high-temperature crystallization process is 8-13℃ / s, for example, it can be 8.0℃ / s, 8.5℃ / s, 9.0℃ / s, 9.7℃ / s, 10.0℃ / s, 10.8℃ / s, 11.0℃ / s, 11.5℃ / s, 12.0℃ / s, 12.4℃ / s or 13.0℃ / s, but not limited to the listed values, other values not listed in the range are also applicable.

[0049] By adjusting the crystallization temperature rising rate, the present application can effectively inhibit germanium segregation, ensure the uniformity of film composition and structure, and improve the electrical performance.

[0050] In a third aspect, the present application provides a photovoltaic cell, which comprises the back contact structure of the laminated cell of the first aspect.

[0051] The present application constructs a four-layer functional film stack structure on the back of the cell, reduces interface recombination, improves carrier migration ability, reduces electrical loss, and improves the conversion efficiency of the cell.

[0052] Compared with the prior art, the present application has the following beneficial effects:

[0053] The application provides a back contact structure of a laminated battery, a preparation method thereof and a photovoltaic cell. 2 The lattice mismatch degree is effectively reduced, the interface potential barrier is reduced to 0.05 eV, the interface recombination rate is reduced to 200 cm / s, the carrier mobility is increased to 35 cm BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 A schematic diagram of the back contact structure of the laminated battery provided for the embodiment 1 of the application.

[0055] Figure 2 A schematic diagram of the back contact structure of the laminated battery provided for the comparative example 1 of the application.

[0056] 1-silicon substrate; 2-tunneling oxide layer; 3-polysilicon transfer layer; 4-silicon germanium crystallization layer; and 5-amorphous silicon buffer layer. DETAILED DESCRIPTION

[0057] It should be understood that, in the description of the application, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In the description of the application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0058] The technical solutions of the application will be further described below in conjunction with the drawings and through specific embodiments.

[0059] In one specific embodiment, the application provides a back contact structure of a laminated battery, comprising a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polysilicon transfer layer which are sequentially stacked. The germanium content in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer, and the lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer.

[0060] The back contact structure of the stacked battery in the present application is arranged on at least one side surface of the silicon substrate, the surface of the silicon substrate is smooth, and has a low conductivity, and the type and thickness of the silicon substrate are not specifically limited in the present application, and can be adjusted according to actual needs by those skilled in the art. For example, the silicon substrate can be an N-type Czochralski monocrystalline silicon wafer or a P-type monocrystalline silicon wafer, and the thickness can be between 30 and 180 μm.

[0061] The tunneling oxide layer in the present application is a thin film of silicon oxide grown on the surface of the silicon substrate, and the thickness is between 0.5 and 2 nm, preferably 0.8 to 1.2 nm, which plays a passivation role and reduces the interface recombination rate, which is beneficial to improve the electrical performance of the battery.

[0062] The germanium content in the silicon germanium crystallization layer in the present application can be 5 at.% to 25 at.%, which increases in the direction from the tunneling oxide layer to the amorphous silicon buffer layer, forming a continuous conduction band structure, which can reduce the conduction band offset, so that the tunneling probability of the carrier exceeds 90%, reduces the energy loss, reduces the interface potential barrier from 0.3 eV of the traditional battery to 0.05 eV, and effectively enhances the stability. At the same time, the lattice constant of the silicon germanium crystallization layer increases in the direction from the tunneling oxide layer to the amorphous silicon buffer layer, specifically, the lattice constant of the silicon germanium crystallization layer is in the range of 0.543 to 0.548 nm, forming a lattice constant gradient structure, which relieves the lattice mismatch between the tunneling oxide layer and the silicon, and reduces the mismatch degree from 7% of the traditional battery to 1.2%. Further, the thickness of the silicon germanium crystallization layer is 10 to 18 nm.

[0063] The amorphous silicon buffer layer in the present application can be an intrinsic amorphous silicon layer or a lightly doped amorphous silicon layer, which can buffer thermal stress, inhibit interface defects, and further reduce the interface recombination rate to less than 3 fA / cm 2 . The intrinsic amorphous silicon layer refers to a pure amorphous material without doping other atoms. The atomic doping concentration in the lightly doped amorphous silicon layer is 3×10 20 ~4.5×10 20 atoms / cm 3 , which can be N-type doping or P-type doping commonly used in the art, including but not limited to any one or a combination of at least two of phosphorus, boron or carbon. Further, the thickness of the amorphous silicon buffer layer can be 80 to 120 nm.

[0064] The polycrystalline silicon transfer layer in the present application is an N-type heavily doped polycrystalline silicon layer or a P-type heavily doped polycrystalline silicon layer, and the specific doping concentration is 4×10 20 ~5×10 20 atoms / cm 3, for providing carrier lateral transport channel, increasing lateral conductivity, which is more than 100 S / cm. Wherein, the doping atoms include but are not limited to any one or combination of at least two of phosphorus, boron or carbon which are well known to those skilled in the art. Further, the thickness of the polysilicon transport layer is 80-150 nm.

[0065] Compared with the conventional back contact structure, the present application inserts the silicon germanium crystallization layer and the amorphous silicon buffer layer between the tunneling oxide layer and the polysilicon transport layer, so that the interface recombination rate is reduced to 200 cm / s, the carrier mobility is increased to 35 cm 2 / V·s, and the battery conversion efficiency is significantly improved.

[0066] In another embodiment, the present application provides a preparation method of the back contact structure of the laminated battery described in one embodiment, which comprises:

[0067] Step one: providing a silicon substrate, and growing a tunneling oxide layer on the surface of the silicon substrate by thermal oxidation method.

[0068] The surface of the silicon substrate needs to be smooth and flat. The silicon substrate can be sequentially subjected to double-sided polishing treatment and RCA standard cleaning. Both of them adopt the treatment process commonly used in the art, which can reduce the surface roughness of the silicon substrate and reduce the interface defects.

[0069] The thermal oxidation method is a process commonly used in the art, which grows an oxide film on the surface of the silicon substrate by chemical reaction of oxygen and the silicon substrate at a certain temperature. The specific treatment process can be adjusted by those skilled in the art according to actual needs. The thermal oxidation method process parameters are as follows: oxygen partial pressure is 8.2-10 kPa, oxygen flow is 35000-50000 sccm, growth temperature is 550-680℃, and growth time is 10-20 min. By controlling the process parameters of thermal oxidation treatment, the present application can obtain a dense and extremely thin silicon oxide film, which ensures that the tunneling oxide layer has a low interface density.

[0070] Step two: forming a silicon germanium crystallization layer on the surface of the tunneling oxide layer by low pressure chemical vapor deposition method.

[0071] The low-pressure chemical vapor deposition method is a process commonly used in the art to make reaction gas react at a lower pressure and temperature, and then deposit on the substrate surface to form a thin film. The specific process parameters are as follows: the reaction gas used includes GeH4 and SiH4, the addition ratio of GeH4 and SiH4 is 1:(7-10), the flow rate of GeH4 is 20-40sccm, and the flow rate of SiH4 is 140-280sccm. The deposition temperature of the low-pressure chemical vapor deposition method is 450-550℃, the deposition pressure is 15-30Pa, the deposition rate is 1.2-2.5nm / min, and the deposition time is 6-10min. The thin film deposition in the above low-pressure and low-temperature environment can guarantee the denseness of the film, inhibit island growth, ensure the quality of the thin film, and control the deposition rate of the reaction gas in a lower range, thereby reducing the interface defect density and improving the denseness of the film layer.

[0072] Step three: low-temperature vapor deposition is performed on the surface of the silicon germanium crystallization layer to form an amorphous silicon buffer layer.

[0073] The low-temperature vapor deposition is a process of forming a thin film on the substrate surface by using a chemical vapor deposition method in a low-temperature environment, and the process parameters are as follows: the deposition temperature is 470-570℃, the deposition flow rate is 400-500sccm, and the deposition rate is 2-3nm / min. By controlling the process parameters of low-temperature vapor deposition, the defect density of the interface between the silicon germanium crystallization layer and the amorphous silicon buffer layer is reduced,

[0074] Step four: high-temperature crystallization treatment is then performed to form a polycrystalline silicon transfer layer, thereby obtaining a back contact structure.

[0075] The high-temperature crystallization treatment is a process commonly used in the art, which first forms an amorphous thin film on the substrate surface by using a chemical vapor deposition method in a high-temperature environment, and then rearranges the atoms inside the amorphous thin film by heat annealing treatment to convert it into an ordered polycrystalline state. The process parameters are as follows: the temperature is 580-620℃, the flow rate is 250-350sccm, the deposition rate is 2.5-3.5nm / min, and the crystallization temperature rising rate is 8-13℃ / s. By controlling the process parameters of high-temperature crystallization treatment, the oxygen atom diffusion depth is greatly reduced, and the crystallization temperature rising rate is maintained within the above range, which can inhibit germanium segregation and improve the uniformity of the film layer.

[0076] Compared with the traditional high-temperature deposition method (deposition in an 800℃ environment), the low-temperature-high-temperature two-step deposition process of the present application greatly reduces the process complexity and also reduces the process thermal budget by 40%.

[0077] In another specific embodiment, the present application provides a back contact structure of a stacked cell, which is used in a photovoltaic cell, and a method for manufacturing the same.

[0078] Embodiment 1

[0079] The present embodiment provides a back contact structure of a stacked cell and a method for manufacturing the same. Figure 1 As shown in FIG. 1, the back contact structure is arranged on the surface of a silicon substrate 1, and includes a tunneling oxide layer 2, a silicon-germanium crystallization layer 4, an amorphous silicon buffer layer 5 and a polycrystalline silicon transport layer 3 arranged in sequence. The silicon substrate 1 is an N-type straight-drawn single crystal silicon wafer with a resistivity of 10 Ω·cm and a thickness of 135 μm. The thickness of the tunneling oxide layer 2 is 1.5 nm. The thickness of the silicon-germanium crystallization layer 4 is 12 nm, and the germanium content in the silicon-germanium crystallization layer 4 is 5 at.% to 15 at.% and increases gradually from the tunneling oxide layer 2 to the amorphous silicon buffer layer 5, and the lattice constant of the silicon-germanium crystallization layer 4 changes in the range of 0.543 nm to 0.548 nm and changes gradually from the tunneling oxide layer 2 to the amorphous silicon buffer layer 5. The amorphous silicon buffer layer 5 is an intrinsic amorphous silicon layer with a thickness of 100 nm. The polycrystalline silicon transport layer 3 is an N-type heavily doped polycrystalline silicon layer doped with boron with an atomic doping concentration of 5×1019 atoms / cm3 and a thickness of 100 nm. 20 atoms / cm 3 , and a thickness of 100 nm.

[0080] The method for manufacturing the back contact structure of the stacked cell provided in the present embodiment includes the following steps.

[0081] (1) Providing a silicon substrate 1, and performing double-side polishing and RCA standard cleaning on the silicon substrate 1 in sequence.

[0082] (2) Growing silicon oxide on the surface of the silicon substrate 1 by a thermal oxidation method to obtain the tunneling oxide layer 2, and the process parameters are as follows: oxygen partial pressure is 8.6 kPa, oxygen flow rate is 40,000 sccm, growth temperature is 610 ℃, and growth time is 15 min.

[0083] (3) Forming the silicon-germanium crystallization layer 4 on the surface of the tunneling oxide layer 2 by a low-pressure chemical vapor deposition method, and the reaction gas used includes GeH4 and SiH4, the addition ratio of GeH4 to SiH4 is 1:9, the flow rate of GeH4 is 30 sccm, the flow rate of SiH4 is 270 sccm, the deposition temperature is 500 ℃, the deposition pressure is 20 Pa, the deposition rate is 1.5 nm / min, and the deposition time is 8 min.

[0084] (4) Low-temperature vapor deposition is performed on the surface of the silicon germanium crystallization layer 4 to form an amorphous silicon buffer layer 5, and the process parameters are as follows: the deposition temperature is 520°C, the deposition flow is 440sccm, and the deposition rate is 1.5nm / min.

[0085] (5) High-temperature crystallization treatment is then performed on the surface of the amorphous silicon buffer layer 5 to form a polycrystalline silicon transfer layer 3, thereby obtaining a back contact structure, and the process parameters are as follows: the temperature is 600°C, the flow is 300sccm, the deposition rate is 3nm / min, and the crystallization temperature rising rate is 10°C / s.

[0086] Example 2

[0087] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that, in the step (3) of the preparation method, the deposition temperature is 450°C, the deposition pressure is 15Pa, and the deposition rate is 2.5nm / min, and the remaining steps and process parameters are the same as those of the embodiment 1.

[0088] In the embodiment, the deposition temperature, the deposition pressure and the deposition rate and the like process parameters of the low-pressure chemical vapor deposition are adjusted, so that not only the island growth is inhibited, but also the uniformity of the film edge and the center is improved, and the density of the film layer is ensured.

[0089] Example 3

[0090] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that, in the step (3) of the preparation method, the deposition temperature is 550°C, the deposition pressure is 30Pa, and the deposition rate is 1.2nm / min, and the remaining steps and process parameters are the same as those of the embodiment 1.

[0091] In the embodiment, the deposition temperature, the deposition pressure and the deposition rate and the like process parameters of the low-pressure chemical vapor deposition are adjusted, so that not only the island growth is inhibited, but also the uniformity of the film edge and the center is improved, and the density of the film layer is ensured.

[0092] Example 4

[0093] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that, in the step (3) of the preparation method, the deposition rate is 6nm / min, and the remaining steps and process parameters are the same as those of the embodiment 1.

[0094] In the embodiment, the deposition rate set in the low-pressure chemical vapor deposition process is too high, and turbulence is easily formed in the deposition process, so that the density and the uniformity of the film edge are reduced, and then the battery conversion efficiency is adversely affected.

[0095] Example 5

[0096] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that in the step (3) of the preparation method, the preparation of the silicon germanium crystallization layer adopts a plasma enhanced chemical vapor deposition method, and the deposition temperature is 350 DEG C, and the remaining steps and process parameters are the same as those of the embodiment 1.

[0097] The compactness of the silicon germanium crystallization layer prepared in the embodiment is lower than that of the embodiment 1, which easily leads to an increase in the number of interface defects, and affects the conversion efficiency of the battery.

[0098] Embodiment 6

[0099] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that in the step (4) of the preparation method, the deposition temperature of the amorphous silicon buffer layer is 800 DEG C, and the remaining steps and process parameters are the same as those of the embodiment 1.

[0100] The embodiment adopts a high-temperature deposition method to prepare the amorphous silicon buffer layer, and the thermal budget is much higher than that of the preparation method of the embodiment 1.

[0101] Embodiment 7

[0102] The embodiment provides a back contact structure of a laminated battery and a preparation method thereof, and the difference from the embodiment 1 is that the amorphous silicon buffer layer 5 adopts a lightly doped amorphous silicon layer with a doping concentration of 4x10 20 atoms / cm 3 , and the remaining structure, steps and process parameters are the same as those of the embodiment 1.

[0103] The embodiment optimizes the carrier transport and interface characteristics, effectively reduces the lattice mismatch degree, improves the carrier mobility, and further improves the battery conversion efficiency.

[0104] Comparative example 1

[0105] The comparative example provides a back contact structure of a laminated battery and a preparation method thereof, as shown in the formula (I), and the difference from the embodiment 1 is that the silicon germanium crystallization layer and the amorphous silicon buffer layer are not arranged, and the remaining structure, preparation method steps and process parameters are the same as those of the embodiment 1. Figure 2 The application respectively adopts the back contact structures provided in the embodiment 1 to 7 and the comparative example 1 to manufacture photovoltaic cells, and the performance of the photovoltaic cells is tested.

[0106] (1) The open circuit voltage (Voc) and the fill factor (FF) of the photovoltaic cells are detected respectively, and the results are shown in Table 1.

[0107] Table 1

[0108]

[0109] ​

[0110] (2) The application uses quasi-steady-state photoconductance method to test the minority carrier lifetime of the photovoltaic cell (test the center and four edge points of the film layer respectively), and the results are shown in Table 2.

[0111] Table 2

[0112]

[0113] (3) The application respectively performs TEM analysis on the photovoltaic cells prepared by using the example 1 and the comparative example 1, and the results are shown in Table 3.

[0114] Table 3

[0115]

[0116] As can be seen from Table 1, Table 2 and Table 3, compared with the traditional structure, the open circuit voltage and the fill factor of the photovoltaic cell with the back contact structure provided by the application are improved. Compared with the interface between the traditional tunneling oxide layer and the polycrystalline silicon transmission layer, the interface defect density and the oxygen atom diffusion depth between the silicon germanium crystallization layer and the amorphous silicon buffer layer of the application are significantly reduced, which greatly improves the cell electrical performance.

[0117] The applicant declares that the above is only a specific embodiment of the application, but the protection scope of the application is not limited thereto. It should be understood by those skilled in the art that any changes or replacements within the technical scope disclosed by the application can be easily thought of by any person skilled in the art, and all fall within the protection scope and disclosure scope of the application.

Claims

1. A back contact structure for a stacked battery, characterized by, The back contact structure of the stacked battery comprises a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polysilicon transfer layer arranged in sequence. The germanium content in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer. The lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer.

2. The back contact structure of a stacked battery according to claim 1, wherein The germanium content in the silicon germanium crystallization layer is 5at.%-25at.%.

3. The back contact structure of a stacked cell according to claim 1 or 2, characterized by, The lattice constant of the silicon germanium crystallization layer increases in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer.

4. The back contact structure of a stacked battery according to claim 3, wherein The lattice constant of the silicon germanium crystallization layer ranges from 0.543nm to 0.548nm.

5. The back contact structure of a stacked battery of claim 1, wherein, The amorphous silicon buffer layer is an intrinsic amorphous silicon layer or a lightly doped amorphous silicon layer. And / or, when the amorphous silicon buffer layer is a lightly doped amorphous silicon layer, the doping concentration is 3 x 1015 atoms / cm3 to 4.5 x 1015 atoms / cm3. 20 4.5 x 1015 atoms / cm3. 20 3 x 1015 atoms / cm3. 3 3 x 1015 atoms / cm3. The polysilicon transfer layer is an N-type heavily doped polysilicon layer or a P-type heavily doped polysilicon layer. and / or the doping concentration of the polysilicon transmission layer is 4 x 1018 atoms / cm3. 20 5 x 1018 atoms / cm3 20 5 x 1018 atoms / cm3 3 .

6. The back contact structure of a stacked cell battery of claim 1 or 5, wherein, The thickness of the tunneling oxide layer is 0.5-2nm. The thickness of the silicon germanium crystallization layer is 10-18nm. The thickness of the amorphous silicon buffer layer is 80-120nm. The thickness of the polysilicon transfer layer is 80-150nm.

7. A method of producing a back contact structure of a stacked cell as claimed in any one of claims 1 to 6, characterized by, The preparation method comprises: providing a silicon substrate, growing a tunneling oxide layer on the surface of the silicon substrate by a thermal oxidation method; forming a silicon germanium crystallization layer on the surface of the tunneling oxide layer by a low-pressure chemical vapor deposition method; forming an amorphous silicon buffer layer on the surface of the silicon germanium crystallization layer by a low-temperature vapor deposition method; then performing a high-temperature crystallization treatment to obtain a polysilicon transfer layer.

8. The method of claim 7, wherein the method further comprises: The oxygen partial pressure of the thermal oxidation method is 8.2kPa-10kPa. The oxygen flow rate of the thermal oxidation method is 35000-50000sccm. The growth temperature of the thermal oxidation method is 550-680℃. The growth time of the thermal oxidation method is 10-20min. The reaction gas of the low-pressure chemical vapor deposition method comprises GeH4 and SiH4. The addition ratio of GeH4 to SiH4 is 1:(7-10). The flow rate of GeH4 is 20-40sccm, and the flow rate of SiH4 is 140-280sccm. The deposition temperature of the low-pressure chemical vapor deposition method is 450-550℃. The deposition pressure of the low-pressure chemical vapor deposition method is 15-30Pa. The deposition rate of the low-pressure chemical vapor deposition method is 1.2-2.5nm / min. The deposition time of the low-pressure chemical vapor deposition method is 6-10min.

9. The method of claim 8, wherein the method further comprises: The deposition temperature of the low-temperature vapor deposition is 470-570℃. The deposition flow rate of the low-temperature vapor deposition is 400-500sccm. The deposition rate of the low-temperature vapor deposition is 2-3nm / min. The temperature of the high-temperature crystallization treatment is 580-620℃. The flow rate of the high-temperature crystallization treatment is 250-350sccm. The deposition rate of the high-temperature crystallization treatment is 2.5-3.5nm / min. And / or, the high-temperature crystallization process has a crystallization temperature increase rate of 8-13℃ / s.

10. A photovoltaic cell, characterized by, The photovoltaic cell comprises a back contact structure of the laminated cell according to any one of claims 1-6.

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