Fin type light-emitting display device with piezoresistive sensing function and preparation method of fin type light-emitting display device

Abstract

The invention discloses a fin type light-emitting display device with a piezoresistive sensing function and a preparation method of the fin type light-emitting display device. The device comprises a driving back plate and a plurality of pixel units on the driving back plate, each pixel unit integrates red, green and blue light-emitting sub-pixels and a pressure sensing sub-pixel, each sub-pixel comprises a stacked structure of an anode, a semiconductor device, a transparent conductive layer and a metal connecting layer, the semiconductor device is a fin type field effect transistor of a trench gate structure, and the transparent conductive layer is a transparent conductive layer. Specifically, the grid can be an L-shaped grid or a double-layer step grid, so that the driving capability and the voltage resistance are effectively improved; the pressure sensing sub-pixel adopts a hollow silicon structure and is connected with a P-type monocrystalline silicon sensing film in combination with a tungsten through hole, so that high-sensitivity and high-reliability pressure sensing is realized. RGB sub-pixels are integrated with a vacuum low-temperature bonding technology through mass transfer. According to the invention, real monolithic integration of display and touch sensing is realized, high-resolution and high-brightness display and real-time pressure sensing functions are realized, and meanwhile, the display device has the advantages of low manufacturing cost and high reliability.

Description

Technical Field

[0001] This invention relates to the field of intelligent integrated device technology, and in particular to a fin-type light-emitting display device equipped with piezoresistive sensing function and its manufacturing method. Background Technology

[0002] With the rapid development of display technology, consumers have put forward higher requirements for the interactive experience of smart terminal devices. They not only pursue higher display resolution, brightness and contrast, but also expect the devices to achieve more sensitive and integrated tactile feedback and pressure sensing functions. At present, the mainstream solution to realize display and touch functions is to separately stack a pressure sensing layer outside the display panel or attach an independent pressure sensor. This mechanical stacking solution has obvious limitations: (1) it increases the overall thickness and manufacturing cost of the device, which runs counter to the development trend of thinner and lighter electronic devices; (2) the separate design of display and sensing systems results in long signal transmission paths, long response times and low reliability.

[0003] Existing integrated solutions mostly use traditional planar MOSFETs or simple trench gate structures as the driving transistors for pixels. However, as pixel sizes continue to shrink to the micrometer level, traditional planar structures face problems such as insufficient driving current, slow response speed, and increased power consumption, making it difficult to meet the demands of high-resolution, high-refresh-rate displays.

[0004] Although existing solutions attempt to integrate piezoresistive pressure sensors with display pixels on the same chip, they typically suffer from the following drawbacks: (a) poor compatibility between the sensor structure and the display pixel's driving circuitry, requiring complex additional process steps, leading to decreased yield and increased costs; (b) sensors are mostly simple diaphragm structures with limited sensitivity and reliability; (c) the electrical connections of sensors typically use traditional metal interconnects, which are prone to fatigue fracture under repeated pressure deformation, resulting in poor stability; (d) the integration of LED chips often employs high-temperature bonding processes, causing thermal damage to the already formed sensitive sensor structure and driving circuitry, affecting device performance and lifespan.

[0005] Furthermore, the layout and structural design of pressure sensing sub-pixels in existing technologies often fail to achieve efficient and compact collaborative optimization with the driving backplane of display pixels. This either sacrifices the aperture ratio of the display area or limits the performance of the sensor, making it difficult to achieve both high-performance display and accurate pressure sensing on a single chip. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a fin-type light-emitting display device with piezoresistive sensing function. This is because the existing display and pressure sensing technologies are mostly stacked separately, resulting in bulky devices, slow response, high cost, insufficient driving performance, complex sensor integration process, poor reliability, and difficulty in achieving high-performance monolithic integration.

[0007] The technical solution adopted by this invention to solve its technical problem is: a fin-type light-emitting display device equipped with a piezoresistive sensor function, comprising a driving backplate and a plurality of pixel units formed on the driving backplate, each pixel unit comprising a red light-emitting sub-pixel, a green light-emitting sub-pixel, a blue light-emitting sub-pixel and a pressure-sensing sub-pixel, each sub-pixel comprising an anode, a semiconductor device, a metal connection layer and a transparent conductive layer stacked sequentially, the anode being electrically connected to the driving backplate; the semiconductor device is a fin-type field-effect transistor with a trench gate structure, and the pressure-sensing sub-pixel further comprises: A hollow silicon structure disposed on the transparent conductive layer; A silicon dioxide layer disposed on the hollow silicon structure; A P-type silicon layer disposed on the silicon dioxide layer; A P-type monocrystalline silicon sensing film is bonded and fixed on the P-type silicon layer, and the P-type monocrystalline silicon sensing film is provided with a piezoresistive electrode. The conductive vias penetrate the P-type silicon layer, the silicon dioxide layer, and the hollow silicon structure. The conductive vias are filled with tungsten, with the lower end of the tungsten connected to the transparent conductive layer and the upper end connected to the piezoresistive electrode.

[0008] The use of finned field-effect transistors with trench gate structures as driving devices improves the switching speed and driving capability of pixel units, meeting the requirements of high-resolution and high-refresh-rate displays. Meanwhile, the pressure-sensing sub-pixels adopt a hollow silicon structure and tungsten through-holes to achieve efficient and stable conversion and transmission of mechanical deformation and electrical signals. Tungsten's excellent anti-electromigration and filling ability ensure the reliability of the connection under repeated pressure, while the bonding process enables heterogeneous integration of high-performance pressure-sensitive films.

[0009] According to one embodiment of the present invention, the semiconductor device includes a semiconductor substrate, an epitaxial layer located on the substrate, and a P-well region, an N+ region, and a P+ region formed in the epitaxial layer by ion implantation.

[0010] According to one embodiment of the present invention, the trench gate structure of the semiconductor device is L-shaped, including a first gate segment located at the bottom of the trench and a second gate segment located on the sidewall of the trench.

[0011] While reducing gate leakage current, it further enhances the control capability of the channel, thereby achieving lower power consumption and higher drive stability in specific application scenarios.

[0012] According to one embodiment of the present invention, the bottom of the trench gate structure of the semiconductor device is a two-step structure, and the bottom gate is respectively disposed on the first step surface and the second step surface at the bottom of the trench.

[0013] By actively controlling the electric field, the breakdown voltage is increased through the field plate effect, and the gate-drain capacitance is reduced through the shielding effect, thereby achieving faster switching speed and lower switching losses.

[0014] According to one embodiment of the present invention, the red light-emitting sub-pixel, the green light-emitting sub-pixel and the blue light-emitting sub-pixel further include a P-pad layer, a P-GaN layer, a multiple quantum well layer, an n-GaN layer and an N-pad layer sequentially disposed on the transparent conductive layer, and the red light-emitting sub-pixel, the green light-emitting sub-pixel and the blue light-emitting sub-pixel are all micro LED chips integrated on the transparent conductive layer by mass transfer and vacuum cryogenic bonding.

[0015] The red, green, and blue light-emitting sub-pixels are micro-LED chips, integrated through mass transfer and vacuum cryogenic bonding technology. Micro-LEDs themselves have excellent display characteristics such as high brightness, high contrast, and long lifespan. Mass transfer technology enables high-precision and high-efficiency batch integration of micro-pixels. The vacuum cryogenic bonding process avoids thermal damage to the fabricated fin field-effect transistors and sensitive pressure sensor structures, ensuring the overall device yield and reliability.

[0016] According to one embodiment of the present invention, the device further includes an interlayer dielectric layer filled between semiconductor devices, a common cathode disposed on the interlayer dielectric layer and electrically connected to each sub-pixel through an electrode trench disposed thereon, and a thin film encapsulation layer covering the common cathode.

[0017] The interlayer dielectric layer provides excellent electrical isolation and mechanical support; the common cathode provides a common low-resistance current return path for all light-emitting sub-pixels, ensuring the uniformity of display brightness; the thin-film encapsulation layer effectively isolates the core light-emitting and sensing structures from water and oxygen in the environment, greatly improving the service life and long-term stability of the entire device.

[0018] A method for manufacturing a fin-type light-emitting display device with piezoresistive sensing function as described above is also provided, comprising the following steps: S1a. Several anodes are formed on the drive backplate; S2a. A heavily doped N-type gallium nitride substrate layer and a lightly doped N-type gallium nitride drift layer are sequentially grown on each anode; S3a. Pattern a highly doped N-type gallium nitride substrate and a lightly doped N-type gallium nitride drift layer, deposit an interlayer dielectric layer and perform chemical mechanical polishing; S4a. Perform ion implantation to form a P-well region, and then implant ions again to form N+ and P+ regions; S5a. Etch L-shaped grooves; S6a. A gate oxide layer is grown using thermal oxidation and high-density plasma chemical vapor deposition processes, followed by deposition of a polysilicon gate, and then growth of an isolation layer; S7a. Deposit a metal bonding layer, then deposit a transparent conductive layer, grow an interlayer dielectric layer, and perform chemical mechanical polishing. S8a. Integrates RGB LED chips using mass transfer and vacuum cryogenic bonding technology; S9a. A hollow silicon structure, a silicon dioxide layer, and a P-type silicon layer are fabricated in the pressure sensing sub-pixel area. Conductive vias are etched and filled with tungsten. A P-type polycrystalline silicon sensing film with a piezoresistive electrode is bonded and fixed. S10a. Form a common cathode and encapsulation layer.

[0019] A method for manufacturing a fin-type light-emitting display device with piezoresistive sensing function as described above is also provided, comprising the following steps: S1b. Several anodes are formed on the drive backplate; S2b. A heavily doped N-type gallium nitride substrate layer and a lightly doped N-type gallium nitride drift layer are sequentially grown on each anode; S3b. Patterned highly doped N-type gallium nitride substrate and lightly doped N-type gallium nitride drift layer, deposited interlayer dielectric layer and chemically mechanically polished flat; S4b. Perform ion implantation to form a P-well region, and then implant ions again to form N+ and P+ regions; S5b. Etch a groove on the bottom double-stepped surface; S6b. A gate oxide layer is grown using thermal oxidation and high-density plasma chemical vapor deposition processes, followed by deposition of a polysilicon gate, and then growth of an isolation layer; S7b. Deposit a metal bonding layer, then deposit a transparent conductive layer, grow an interlayer dielectric layer, and perform chemical mechanical polishing to smooth it out; S8b. Integrates RGB LED chips using mass transfer and vacuum cryogenic bonding technology; S9b. A hollow silicon structure, a silicon dioxide layer, and a P-type silicon layer are fabricated in the pressure sensing sub-pixel area. Through holes are etched and filled with tungsten. A sensing film with a piezoresistive electrode is bonded and fixed. S10b. Form a common cathode and encapsulation layer.

[0020] According to one embodiment of the present invention, the bonding process is a low-temperature bonding process under vacuum, with a bonding temperature below 400°C.

[0021] Temperature limits were imposed on the bonding process to prevent high temperatures from degrading the performance and damaging the reliability of the fabricated precision semiconductor structure, thus ensuring the success and high yield of the entire integration process.

[0022] According to one embodiment of the present invention, the conductive via is formed by deep silicon etching and filled with tungsten by chemical vapor deposition.

[0023] Deep silicon etching can achieve high aspect ratio through-hole etching to meet the vertical interconnect requirements within tiny pixels; while chemical vapor deposition can perfectly fill such deep holes with tungsten without holes or gaps, forming a reliable connection with low resistance and high mechanical strength, ensuring high-fidelity transmission of pressure signals.

[0024] The beneficial effects of this invention are: The trench gate structure of the fin field-effect transistor has higher current driving capability, faster switching speed and excellent short-channel control characteristics, which enables each pixel unit to be driven faster and more accurately, providing a hardware foundation for achieving high resolution, high brightness and high contrast display effects, and meeting the needs of the high-end display market. By integrating a piezoresistive sensing unit containing a hollow silicon structure and tungsten through-holes as a sub-pixel into each pixel unit, real-time and accurate sensing of external pressure is achieved. The hollow structure enhances the stress concentration effect and improves sensitivity. The excellent conductivity and anti-electromigration properties of the tungsten through-holes ensure the stability and durability of electrical signal transmission, avoid the fatigue problem of traditional metal wires under repeated deformation, and greatly improve the reliability of the sensor. The display driver, light-emitting unit, and pressure sensor are fabricated and integrated on the same semiconductor process line, eliminating the need for an additional sensor layer, simplifying the system architecture, reducing the overall thickness and manufacturing cost, and improving production efficiency and yield through optimized pixel arrangement and mature CMOS compatible process. The vacuum low-temperature bonding technology used ensures that the integration of Micro-LED chips and piezoresistive films will not cause thermal damage to the previously prepared fin field-effect transistor precision drive circuit and sensitive sensor structure, thus guaranteeing the performance and long-term reliability of each functional unit. The provided L-shaped gate and double-step gate and other fin field-effect transistor structures offer optional optimization paths for different application scenarios, making the design more flexible and enabling targeted improvement of the overall performance of pixels. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0027] Figure 2 This is a schematic diagram of step 1 in Embodiment 1 of the present invention.

[0028] Figure 3 This is a schematic diagram of step 2 in Embodiment 1 of the present invention.

[0029] Figure 4 This is a schematic diagram of step 3 in Embodiment 1 of the present invention.

[0030] Figure 5 This is a schematic diagram of step 4 in Embodiment 1 of the present invention.

[0031] Figure 6 This is a schematic diagram of step 5 in Embodiment 1 of the present invention.

[0032] Figure 7 This is a schematic diagram of step 6 in Embodiment 1 of the present invention.

[0033] Figure 8 This is a schematic diagram of step 7 in Embodiment 1 of the present invention.

[0034] Figure 9 This is a schematic diagram of step 8 in Embodiment 1 of the present invention.

[0035] Figure 10 This is a schematic diagram of step 9 in Embodiment 1 of the present invention.

[0036] Figure 11 This is a schematic diagram of step 10 in Embodiment 1 of the present invention.

[0037] Figure 12 This is a current density diagram during operation of Embodiment 1 of the present invention.

[0038] Figure 13 This is an electric field intensity diagram during the operation of Embodiment 1 of the present invention.

[0039] Figure 14 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0040] Figure 15 This is a schematic diagram of step 1 in embodiment 2 of the present invention.

[0041] Figure 16 This is a schematic diagram of step 2 in Embodiment 2 of the present invention.

[0042] Figure 17 This is a schematic diagram of step 3 in embodiment 2 of the present invention.

[0043] Figure 18 This is a schematic diagram of step 4 in embodiment 2 of the present invention.

[0044] Figure 19 This is a schematic diagram of step 5 in Embodiment 2 of the present invention.

[0045] Figure 20 This is a schematic diagram of step 6 in embodiment 2 of the present invention.

[0046] Figure 21 This is a schematic diagram of step 7 in embodiment 2 of the present invention.

[0047] Figure 22 This is a schematic diagram of step 8 in Embodiment 2 of the present invention.

[0048] Figure 23 This is a schematic diagram of step 9 in embodiment 2 of the present invention.

[0049] Figure 24 This is a schematic diagram of step 10 in Embodiment 2 of the present invention.

[0050] Figure 25 This is the current density diagram during operation of Embodiment 2 of the present invention.

[0051] Figure 26 This is an electric field intensity diagram during the operation of Embodiment 2 of the present invention.

[0052] Figure 27 These are diagrams of the optimized pixel arrangement schemes of Embodiment 1 and Embodiment 2 of the present invention.

[0053] Figure 28 These are the driving circuit diagrams for Embodiment 1 and Embodiment 2 of the present invention.

[0054] In the diagram: 1. Driving backplane; 2. Red light-emitting sub-pixel; 3. Green light-emitting sub-pixel; 4. Blue light-emitting sub-pixel; 5. Pressure sensing sub-pixel; 6. Anode; 7. Semiconductor device; 8. Transparent conductive layer; 9. Metal interconnect layer; 10. Interlayer dielectric layer; 11. Common cathode; 12. Thin film encapsulation layer; 51. Hollow silicon structure; 52. Silicon dioxide layer; 53. P-type silicon layer; 54. P-type single crystal silicon sensing film; 55. Tungsten; 71. Semiconductor substrate; 72. Epitaxial layer; 73. P-well region; 74. N+ region; 75. P+ region; 76. Trench; 77. Gate oxide layer; 78. Polysilicon gate; 79. Isolation layer; 100. P-pad layer; 200. P-GaN layer; 300. Multiple quantum well layer; 400. n-GaN layer; 500. N-pad layer. Detailed Implementation

[0055] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0056] Example 1 like Figure 1 As shown, a fin-type light-emitting display device with a piezoresistive sensor function includes a driving backplate 1 and multiple pixel units formed on the driving backplate 1. Each pixel unit includes a red light-emitting sub-pixel 2, a green light-emitting sub-pixel 3, a blue light-emitting sub-pixel 4, and a pressure-sensing sub-pixel 5. Each sub-pixel includes an anode 6, a semiconductor device 7, a metal interconnect layer 9, and a transparent conductive layer 8 stacked sequentially. The anode 6 is electrically connected to the driving backplate 1. The semiconductor device 7 is a fin-type field-effect transistor with a trench gate structure, including a semiconductor substrate 71, an epitaxial layer 72 located on the substrate, and a P-well region 73, an N+ region 74, and a P+ region 75 formed in the epitaxial layer by ion implantation. The trench gate structure of the semiconductor device 7 is L-shaped, including a first gate segment located at the bottom of the trench 76 and a second gate segment located on the sidewall of the trench 76.

[0057] The red light-emitting sub-pixel 3, the green light-emitting sub-pixel 4, and the blue light-emitting sub-pixel 5 also include a P-pad layer 100, a P-GaN layer 200, a multi-quantum well layer 300, an n-GaN layer 400, and an N-pad layer 500 sequentially disposed on the transparent conductive layer 8. Furthermore, the red light-emitting sub-pixel 3, the green light-emitting sub-pixel 4, and the blue light-emitting sub-pixel 5 are all micro LED chips integrated on the transparent conductive layer 8 through mass transfer and vacuum cryogenic bonding.

[0058] The pressure sensing sub-pixel 5 also includes a hollow silicon structure 51, a silicon dioxide layer 52, a P-type silicon layer 53, a P-type monocrystalline silicon sensing film 54, and a conductive via. The hollow silicon structure 51 is disposed on the transparent conductive layer 8, the silicon dioxide layer 52 is disposed on the hollow silicon structure 51, the P-type silicon layer 53 is disposed on the silicon dioxide layer 52, and the P-type monocrystalline silicon sensing film 54 is bonded to the P-type silicon layer 53. The P-type monocrystalline silicon sensing film 54 is provided with a piezoresistive electrode. The conductive via penetrates the P-type silicon layer 53, the silicon dioxide layer 52, and the hollow silicon structure 51. The conductive via is filled with tungsten 55. The lower end of the tungsten 55 is connected to the transparent conductive layer 8, and the upper end is connected to the piezoresistive electrode.

[0059] The fin-type light-emitting display device equipped with a piezoresistive sensor also includes an interlayer dielectric layer 10 filled between semiconductor devices 7, a common cathode 11 disposed on the interlayer dielectric layer 10 and electrically connected to each sub-pixel through an electrode groove disposed thereon, and a thin film encapsulation layer 12 covering the common cathode 11.

[0060] The method for preparing the fin-type light-emitting display device with piezoresistive sensor function as described in Example 1 includes the following steps: Step 1: As Figure 2 As shown, several anodes 6 are formed on the drive backplate 1; Step 2: As Figure 3As shown, a highly doped N-type gallium nitride substrate layer (semiconductor substrate 71) and a lightly doped N-type gallium nitride drift layer (epitaxy layer 72) are sequentially grown on each anode 6. Step 3: As Figure 4 As shown, a patterned highly doped N-type gallium nitride substrate and a lightly doped N-type gallium nitride drift layer are formed, and an interlayer dielectric layer 10 is deposited and then chemically and mechanically polished. Step 4: As Figure 5 As shown, ion implantation is performed to form a P-well region 73, and ion implantation is performed again to form an N+ region 74 and a P+ region 75. Step 5: As Figure 6 As shown, L-shaped trenches 76 are etched; Step 6: As Figure 7 As shown, a gate oxide layer 77 is grown using thermal oxidation and high-density plasma chemical vapor deposition processes, followed by deposition of a polysilicon gate 78. Step 7: As Figure 8 As shown, a metal interconnect layer 9 is deposited, followed by a transparent conductive layer 8, an interlayer dielectric layer 10 is grown, and then chemically and mechanically polished. Step 8: As Figure 9 As shown, RGB LED chips are integrated using mass transfer and vacuum cryogenic bonding technologies; Step 9: As Figure 10 As shown, a hollow silicon structure 51, a silicon dioxide layer 52, and a P-type silicon layer 53 are fabricated in the pressure sensing sub-pixel 5 area. Conductive vias are etched and filled with tungsten 55. A P-type single-crystal silicon sensing film 54 with a piezoresistive electrode is bonded and fixed. Step 10: As Figure 11 As shown, a common cathode 11 and an encapsulation layer 12 are formed, and the purple arrow in the figure indicates the direction of current.

[0061] The trench grid image sensor device with display function prepared by the above method has the following current density and electric field strength during operation: Figure 12 and Figure 13 As shown, the device exhibits good conduction characteristics in the on state. The electric field distribution inside the device is uniform and the peak electric field is located in the design expected region, which helps to improve the breakdown voltage and reliability of the device and achieves excellent withstand voltage performance, thus meeting the application requirements of high-performance power semiconductor devices.

[0062] Example 2 The difference from Example 1 is as follows: Figure 14 As shown, the bottom of the trench gate structure of the semiconductor device 7 is a two-step structure, with the bottom gates respectively disposed on the first step surface and the second step surface of the bottom surface of the trench 76.

[0063] The method for preparing the fin-type light-emitting display device with piezoresistive sensor function as described in Example 2 includes the following steps: Step 1: As Figure 15 As shown, several anodes 6 are formed on the drive backplate 1; Step 2: As Figure 16 As shown, a highly doped N-type gallium nitride substrate layer (semiconductor substrate 71) and a lightly doped N-type gallium nitride drift layer (epitaxy layer 72) are sequentially grown on each anode 6. Step 3: As Figure 17 As shown, a patterned highly doped N-type gallium nitride substrate and a lightly doped N-type gallium nitride drift layer are formed, and an interlayer dielectric layer 10 is deposited and then chemically and mechanically polished. Step 4: As Figure 18 As shown, ion implantation is performed to form a P-well region 73, and ion implantation is performed again to form an N+ region 74 and a P+ region 75. Step 5: As Figure 19 As shown, the groove 76 on the bottom double-step surface is etched; Step 6: As Figure 20 As shown, a gate oxide layer 77 is grown using thermal oxidation and high-density plasma chemical vapor deposition processes, followed by the deposition of a polysilicon gate 78, and then the growth of an isolation layer 79. Step 7: As Figure 21 As shown, a metal interconnect layer 9 is deposited, followed by a transparent conductive layer 8, an interlayer dielectric layer 10 is grown, and then chemically and mechanically polished. Step 8: As Figure 22 As shown, RGB LED chips are integrated using mass transfer and vacuum cryogenic bonding technologies; Step 9: As Figure 23 As shown, a hollow silicon structure 51, a silicon dioxide layer 52, and a P-type silicon layer 53 are fabricated in the pressure sensing sub-pixel 5 area. Conductive vias are etched and filled with tungsten 55. A P-type single-crystal silicon sensing film 54 with a piezoresistive electrode is bonded and fixed. Step 10: As Figure 24 As shown, a common cathode 11 and an encapsulation layer 12 are formed, and the purple arrow in the figure indicates the direction of current.

[0064] The trench grid image sensor device with display function prepared by the above method has the following current density and electric field strength during operation: Figure 25 and Figure 26 As shown, the device exhibits high current handling capability in the on-state, demonstrating excellent conduction characteristics. The electric field intensity distribution shows that the internal electric field of the device is effectively modulated, with the peak electric field located in the expected region of the structural design. This further promotes the improvement of conduction performance while ensuring high breakdown voltage, significantly optimizing power conversion efficiency and reliability, making it particularly suitable for power semiconductor devices in integrated electronic applications.

[0065] Compared to traditional planar MOSFETs, the trench-gate finned field-effect transistor (FET) has a channel perpendicular to the substrate surface, allowing for a wider channel width per unit area. This significantly increases the drive current, meeting the high-instantaneous current requirements of high-brightness Micro-LED displays. Simultaneously, the three-sided trench-enclosed structure of the gate provides superior channel control capabilities, effectively suppressing short-channel effects and maintaining low leakage current and high on / off ratios even during pixel miniaturization, laying the foundation for high-resolution, high-contrast displays. Specifically, the L-shaped gate structure in Embodiment 1 achieves segmented electric field control by dividing the gate into bottom and sidewall segments. In the double-step gate structure of Embodiment 2, the two gates located on different step surfaces can be independently optimized. The gate on the higher step acts as the main gate, controlling the channel, while the gate on the lower step serves as a shielding gate.

[0066] A hollow silicon structure 51 is used as a stress concentrator. When external pressure is applied to the thin-film encapsulation layer 12, the force is transmitted to the underlying P-type single-crystal silicon sensing film 54, causing it to bend. The hollow structure concentrates this deformation mainly in the corresponding area of ​​the sensing film, amplifying the local stress and thus improving the sensitivity of the pressure sensor. Tungsten 55 has excellent conductivity, an extremely high melting point, and excellent resistance to electromigration. The tungsten 55 vias filled using CVD technology achieve perfect, gap-free filling, ensuring low resistance and high mechanical strength of the electrical connection. The thermal expansion coefficient mismatch between the Micro-LED chip and the silicon-based driver backplane 1 means that traditional high-temperature bonding will generate huge thermal stress, leading to chip cracking or performance degradation. A low-temperature bonding process below 400°C effectively avoids thermal damage, ensuring the integrity of the Micro-LED's luminous efficiency and the driving transistor's performance. The vacuum environment prevents oxidation and improves the quality and consistency of the bonding interface. The common cathode 11 provides a unified low-resistance current return path for all Micro-LED pixels, simplifying wiring, reducing voltage drop, and ensuring high brightness uniformity across the entire display panel. The thin-film encapsulation layer 12 completely isolates the light-emitting and sensing units from external water and oxygen, ensuring the device's lifespan.

[0067] The optimized pixel arrangement schemes of Embodiment 1 and Embodiment 2 are as follows: Figure 27As shown, a pixel includes a red emitting sub-pixel R, a green emitting sub-pixel G, a blue emitting sub-pixel B, and a pressure-sensing sub-pixel S. Spatially, a square has four vertices, each containing the pressure-sensing sub-pixel S and the blue emitting sub-pixel B at the two opposite vertices, and the red emitting sub-pixel R and the green emitting sub-pixel G at the remaining two vertices. The side length of the square is equal to the pixel width. Four clusters of red emitting sub-pixels R, green emitting sub-pixels G, and blue emitting sub-pixels B or pressure-sensing sub-pixels S are grouped together and share a single mask opening. Grouping four sub-pixels (R, G, B, S) together and sharing a single mask opening means that when manufacturing color filters or certain general-purpose layers, the patterning of all four sub-pixels can be completed in a single photolithography process. This significantly reduces the number of photomask uses and process steps, directly lowering manufacturing costs and improving production efficiency.

[0068] Example 1 and Example 2 are combined as follows Figure 28 The driving circuit shown can improve the performance and reliability of the display, and has the advantages of high integration, low power consumption, high speed and good stability, making it widely applicable.

[0069] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A fin-shaped light-emitting display device with a piezoresistive sensor function, comprising a driving backplane (1) and a plurality of pixel units formed on the driving backplane (1), each of the pixel units comprising a red light-emitting sub-pixel (2), a green light-emitting sub-pixel (3), a blue light-emitting sub-pixel (4) and a pressure sensing sub-pixel (5), each of the sub-pixels comprising an anode (6), a semiconductor device (7), a metal connecting layer (9) and a transparent conductive layer (8) stacked in sequence, the anode (6) being electrically connected to the driving backplane (1); characterized in that: The semiconductor device (7) is a fin field effect transistor with a trench gate structure, and the pressure sensing sub-pixel (5) further comprises: a hollow silicon structure (51) disposed on the transparent conductive layer (8); a silicon dioxide layer (52) disposed on the hollow silicon structure (51); a P-type silicon layer (53) disposed on the silicon dioxide layer (52); a P-type single crystal silicon sensing film (54) bonded and fixed on the P-type silicon layer (53), the P-type single crystal silicon sensing film (54) being provided with a piezoresistive electrode; and a conductive via penetrating through the P-type silicon layer (53), the silicon dioxide layer (52) and the hollow silicon structure (51), the conductive via being filled with tungsten (55), the lower end of the tungsten (55) being connected to the transparent conductive layer (8), and the upper end being connected to the piezoresistive electrode.

2. The fin-type light emitting display device according to claim 1, wherein: The semiconductor device (7) comprises a semiconductor substrate (71), an epitaxial layer (72) on the substrate, and a P-well well region (73), an N+ region (74) and a P+ region (75) formed in the epitaxial layer by ion implantation.

3. The fin-type light emitting display device according to claim 1 or 2, wherein: The trench gate structure of the semiconductor device (7) is L-shaped, comprising a first gate segment at the bottom of the trench (76) and a second gate segment on the sidewall of the trench (76).

4. The fin-type light emitting display device according to claim 1 or 2, wherein: The bottom of the trench gate structure of the semiconductor device (7) is a two-step structure, and the bottom gate is respectively arranged on the first step surface and the second step surface at the bottom of the trench (76).

5. The fin-type light emitting display device according to claim 1, wherein: The red light emitting sub-pixel (2), the green light emitting sub-pixel (3) and the blue light emitting sub-pixel (4) further comprise a P-pad layer (100), a P-GaN layer (200), a multi-quantum well layer (300), an n-GaN layer (400) and an N-pad layer (500) sequentially disposed on the transparent conductive layer, and the red light emitting sub-pixel (2), the green light emitting sub-pixel (3) and the blue light emitting sub-pixel (4) are all micro-LED chips integrated on the transparent conductive layer (8) by mass transfer and vacuum low-temperature bonding.

6. The fin-type light emitting display device according to claim 1, wherein: It further comprises an interlayer dielectric layer (10) filled between the semiconductor devices (7), a common cathode (11) disposed on the interlayer dielectric layer (10) and electrically connected to each sub-pixel through an electrode groove provided thereon, and a thin film encapsulation layer (12) covering the common cathode (11).

7. A method of manufacturing a fin-type light emitting display device having a piezoresistive sensing function according to any one of claims 1, 2, 3, 5 and 6, characterized by, The method comprises the following steps: S1a. Forming a plurality of anodes (6) on the driving backplane (1); S2a. Growing a high-doped N-type gallium nitride substrate layer and a lightly-doped N-type gallium nitride drift layer on each anode (6) in sequence; S3a. Patterning the high-doped N-type gallium nitride substrate layer and the lightly-doped N-type gallium nitride drift layer, depositing an interlayer dielectric layer (10) and performing chemical mechanical polishing to flatten; S4a. Forming a P-well well region (73) by ion implantation, and then forming an N+ region (74) and a P+ region (75) by ion implantation again; S5a. Etching an L-shaped trench (76); S6a. Growing a gate oxide layer (77) using a thermal oxidation method and a high-density plasma chemical vapor deposition process, then depositing a polysilicon gate (78), and then growing an isolation layer (79); S7a. Depositing a metal connecting layer (9), then plating a transparent conductive layer (8), growing an interlayer dielectric layer (10) and performing chemical mechanical polishing to flatten; S8a. Integrating RGB LED chips using mass transfer and vacuum low-temperature bonding technology; S9a. In the pressure sensing sub-pixel (5) area, a hollow silicon structure (51), a silicon dioxide layer (52), a P-type silicon layer (53) are made, a conductive via is etched and filled with tungsten (55), and a P-type single crystal silicon sensing film (54) with a pressure resistance electrode is bonded and fixed; S10a. Forming a common cathode (11) and a packaging layer (12).

8. A method for manufacturing a fin-type light emitting display device having a piezoresistive sensing function according to any one of claims 1, 2, 4, 5 and 6, characterized by, The method comprises the following steps: S1b. Forming a plurality of anodes (6) on a driving backplane (1); S2b. Growing a high-doped N-type gallium nitride substrate layer and a lightly-doped N-type gallium nitride drift layer on each anode (6) in sequence; S3b. Patternizing the high-doped N-type gallium nitride substrate layer and the lightly-doped N-type gallium nitride drift layer, depositing an interlayer dielectric layer (10) and performing chemical mechanical polishing to flatten; S4b. Forming a P-well (73) by ion implantation, and then forming an N+ region (74) and a P+ region (75) by ion implantation again; S5b. Etching a trench (76) with a double-step bottom; S6b. Growing a gate oxide layer (77) using a thermal oxidation method and a high-density plasma chemical vapor deposition process, then depositing a polysilicon gate (78), and then growing an isolation layer (79); S7b. Depositing a metal connecting layer (9), then plating a transparent conductive layer (8), growing an interlayer dielectric layer (10) and performing chemical mechanical polishing to flatten; S8b. Integrating RGB LED chips using mass transfer and vacuum low-temperature bonding technology; S9b. In the pressure sensing sub-pixel (5) area, a hollow silicon structure (51), a silicon dioxide layer (52), a P-type silicon layer (53) are made, a conductive via is etched and filled with tungsten (55), and a P-type single crystal silicon sensing film (54) with a pressure resistance electrode is bonded and fixed; S10b. Forming a common cathode (11) and a packaging layer (12).

9. The method of claim 7 or 8, wherein the method further comprises: forming a plurality of first electrodes on the substrate; forming a plurality of second electrodes on the substrate; and forming a plurality of third electrodes on the substrate. The bonding process is a low-temperature bonding process in a vacuum environment, and the bonding temperature is lower than 400°C.

10. The method of claim 7 or 8, wherein the method further comprises: forming a plurality of first electrodes on the substrate; forming a plurality of second electrodes on the substrate; and forming a plurality of third electrodes on the substrate. The conductive via is formed by a deep silicon etching process and filled with tungsten (55) by a chemical vapor deposition process.

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