Carrier loop based on integral discrete bilinear transformation of loop filter and tracking method

Abstract

The invention discloses a carrier loop based on integral discrete bilinear transformation of a loop filter and a tracking method, belongs to the technical field of satellite navigation receiver signal processing, and designs a loop filter core architecture in which a third-order frequency-locked loop and a third-order phase-locked loop are connected in parallel and cooperatively work. The filter receives a frequency error and a phase error which are obtained by calculating baseband I and Q signals, the frequency-locked loop branch circuit integrates the frequency error through a discrete integrator realized based on a bilinear transformation method and then converts the frequency error into a phase auxiliary quantity, and the phase auxiliary quantity and the output of the phase-locked loop branch circuit are added to jointly control the numerically-controlled oscillator. According to the invention, the high dynamic stress tolerance capability of the frequency-locked loop and the high-precision tracking advantage of the phase-locked loop are combined, so that the carrier loop can quickly and stably track high dynamic signals while keeping high tracking precision, and the reliability and performance of a receiver in a complex environment are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology for satellite navigation receivers, and in particular to a carrier loop and tracking method based on the integral discrete bilinear transform of a loop filter. Background Technology

[0002] The purpose of the carrier loop is to make the replicated carrier signal consistent with the received satellite carrier signal, thereby completely stripping the carrier from the satellite signal through the mixing mechanism, so that the received signal is down-converted from the intermediate frequency to the baseband signal. If the replicated carrier is inconsistent with the received carrier, the carrier in the received signal cannot be completely stripped, the received signal cannot be down-converted to the true baseband, and the autocorrelation amplitude obtained by code loop correlation will also be weakened.

[0003] To completely remove the carrier from the digital intermediate frequency (IF) input signal and downconvert it from IF to baseband, the carrier loop must contain a mixer. If the carrier loop detects the phase difference between its replicated carrier and the input carrier and adjusts the phase of the replicated carrier accordingly to keep them in sync, this type of carrier loop is called a phase-locked loop (PLL). If the carrier loop detects the frequency difference between its replicated carrier and the input carrier and adjusts the frequency of the replicated carrier accordingly to keep them in sync, this type of carrier loop is called a frequency-locked loop (FLL). However, based on the system transfer function in the carrier loop, the design and implementation of the loop filter is a decisive factor in the stability and reliability of the loop.

[0004] Existing carrier loop technology has the following defects and shortcomings: 1. A standalone frequency-locked loop (LLL) aims to maintain frequency consistency between its replicated carrier and the received carrier, but does not require them to maintain phase consistency. Although LLLs have a relatively wide noise bandwidth, good dynamic performance, and can more robustly tolerate high dynamic stress from users as well as interference from radio frequency, multipath, and ionospheric storms, and are not sensitive to data bit transitions, their signal tracking is slightly less tight, the loop noise is higher, the output carrier phase measurement is less accurate, and because LLLs track the frequency of the signal, the bit error rate during data demodulation is higher.

[0005] 2. A standalone phase-locked loop (PLL) uses a narrow noise bandwidth, which can track the signal more closely, and the output carrier phase measurement is quite accurate. The demodulated data bit error rate is also low. However, it has poor tolerance to dynamic stress. When the noise is strong or the required loop bandwidth is high, the PLL may have difficulty locking onto the signal.

[0006] Due to the significant technical limitations of both phase-locked loops (PLLs) and frequency-locked loops (FLLs), existing technologies often employ combined loops or higher-order loop structures to balance dynamic performance and tracking accuracy. However, traditional second-order PLLs still exhibit tracking errors under frequency ramp-up inputs, while higher-order loops are complex to design and prone to stability issues during discretization, especially in digital intermediate frequency (IF) processing systems, where the discretization method of the loop filter directly affects the loop's stability and convergence performance.

[0007] Therefore, there is an urgent need for a new type of carrier tracking loop structure that can achieve stable and accurate carrier tracking in high dynamic environments, while also possessing good noise suppression capabilities and ease of digital implementation. Summary of the Invention

[0008] The purpose of this invention is to solve the problems existing in the prior art and to provide a carrier loop and tracking method based on the integral discrete bilinear transform of a loop filter. The objective of this invention is achieved through the following technical solution: Firstly, a carrier loop based on the integral discrete bilinear transform of a loop filter is provided, including: A mixer is used to multiply the input digital intermediate frequency signal with the in-phase and quadrature components output by a digitally controlled oscillator to generate I and Q signals. The PN code module generates a local PN code and is used to capture the PN code in the digital intermediate frequency signal; A pseudo-code peak correlator is used to multiply and correlate the input I and Q signals with the local PN code to determine precise code element synchronization; A Gaussian integral filter is used to perform Gaussian filtering on the correlated I and Q signals. The loop frequency difference estimation module is used to estimate the loop frequency deviation in real time based on the Gaussian filtered baseband I and Q signals. The difference frequency trapezoidal integrator module is used to smooth and filter the frequency calculated by the loop in order to obtain a stable coarse phase difference.

[0009] The loop phase difference estimation module is used to estimate the loop phase deviation in real time based on the Gaussian filtered baseband I and Q signals; The loop filter adopts a structure in which a third-order frequency-locked loop and a third-order phase-locked loop work together. The output of the frequency-locked loop is converted into a phase deviation auxiliary phase-locked loop after discrete integration. The integral operation in the loop filter is discretized through bilinear transformation. This module is also the core module of the loop. The numerically controlled oscillator, regulated by the control signal output from the loop filter, generates a replicated carrier signal.

[0010] In some embodiments, the PN code module is further configured to: The optimal correlation peak is found based on the Gaussian filtered baseband I and Q signals to assist in accurate phase tracking of the carrier.

[0011] In some embodiments, the bilinear transformation is used to convert the continuous-time Laplace transform of the integral into a discrete-time form using a bilinear transformation model. The specific transformation formula is as follows: Where s is the Laplace variable, Ts Let z be the sampling period, and z be the Z-transform variable.

[0012] In some embodiments, the loop filter specifically includes: The phase-locked loop processing branch has its input connected to the output of the loop phase difference estimation module and is used to process the phase deviation signal. The frequency-locked loop processing branch has its input connected to the output of the loop frequency difference estimation module and is used to process the frequency deviation signal. An adder, the input of which is connected to the output of the phase-locked loop processing branch and the frequency-locked loop processing branch respectively, and its output is used as the total output of the loop filter; The frequency-locked loop processing branch includes at least one discrete integrator for integrating the frequency deviation into an auxiliary control quantity in the form of a phase deviation, so as to add it to the output of the phase-locked loop processing branch in the adder.

[0013] Secondly, a carrier tracking method based on the integral discrete bilinear transform of a loop filter is provided, including the following steps: S1. Receives digital intermediate frequency signals and performs mixing processing; S2. Perform PN code correlation and Gaussian integral filtering; S3. Calculate the frequency deviation and phase deviation; S4. The deviation signal is processed by the loop filter of the third-order phase-locked loop assisted by the third-order frequency-locked loop; S5. Control the numerically controlled oscillator to generate a replicated carrier, thereby achieving carrier tracking and locking.

[0014] It should be further noted that the technical features corresponding to the above embodiments can be combined or substituted with each other to form new technical solutions without conflict.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. It achieves the optimal combination of dynamic tracking performance and static tracking accuracy. By employing an innovative architecture that combines a third-order frequency-locked loop (FLL) and a third-order phase-locked loop (PLL) with a discrete-integral bilinear transform (DIB) loop filter, this invention successfully leverages the complementary advantages of both loop types. The FLL branch, with its wide noise bandwidth, can quickly respond to and track high-order frequency changes (such as acceleration and jerk) caused by high dynamic stress in the signal, playing a "coarse tracking" role and ensuring the loop's acquisition speed and dynamic range. The PLL branch, building upon this foundation, performs "fine tracking," utilizing its narrowband characteristics to precisely lock the signal phase, thereby outputting high-precision carrier phase measurements and achieving low-error-rate data demodulation. This collaborative mechanism fundamentally solves the problems of poor dynamic performance and easy lockout with a single PLL, and low tracking accuracy with a single FLL.

[0016] 2. Improved the stability and robustness of the loop under high dynamic stress. Because the third-order frequency-locked loop can track the frequency ramp signal without steady-state error, experimental data shows that in a high dynamic scenario with the receiver frequency offset set to 2000Hz, the frequency control word output of the loop filter can quickly converge to a stable state, proving that the entire loop locking process is fast and stable. This makes the present invention particularly suitable for high-dynamic application environments such as aviation, aerospace, and high-speed vehicles.

[0017] 3. Superior noise performance was achieved through high-order loop design and discretization optimization. This invention employs a third-order loop structure, which, compared to the common second-order loop, offers more adjustable parameters (such as characteristic frequency, damping coefficient, and third-order parameters a3 and b3), providing greater design freedom for optimizing loop noise bandwidth and suppressing various noise interferences. By reasonably setting parameters (e.g., setting the phase-locked loop noise bandwidth to 135Hz and the frequency-locked loop to 320Hz), an optimal balance can be achieved between tracking accuracy and noise suppression. Furthermore, the integral operation in the loop filter is discretized using the bilinear transform method. This method avoids frequency aliasing, maintains the stability of the continuous system, and ensures that the performance of the digitally implemented filter is highly consistent with the theoretical design, further improving the overall noise immunity of the system.

[0018] 4. The hardware implementation structure is clear and facilitates digital integration. The loop filter structure proposed in this invention consists of basic multipliers, adders, and registers, representing a typical parallel pipelined digital logic, highly suitable for implementation in digital chips such as FPGAs or ASICs. This hardware structure is well-defined and regular, easy to design, verify, and integrate into modern fully digital software receivers, possessing high engineering practical value and promising industrialization prospects. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of the carrier ring of the present invention; Figure 2 This is a flowchart of the carrier tracking method of the present invention; Figure 3 This is a schematic diagram of the loop filter of the present invention; Figure 4 This is a block diagram of the Laplace transform of the third-order loop filter of the present invention; Figure 5 This is a schematic diagram illustrating the implementation of the discrete bilinear transform of the integral in this invention; Figure 6 This is a schematic diagram of the convergence process of the loop filter output of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0022] In view of the technical problems pointed out in the background art, the present invention provides the following embodiments: In one exemplary embodiment, such as Figure 1 As shown, the carrier loop based on the integral discrete bilinear transform of the loop filter includes: A mixer is used to multiply the input digital intermediate frequency signal with the in-phase and quadrature components output by a digitally controlled oscillator to generate I and Q signals. The PN code module generates local PN codes and is used to capture the PN codes in the input signal. A pseudo-code peak correlator is used to multiply and correlate the input I and Q signals with the local PN code to determine precise code element synchronization; A Gaussian integral filter is used to perform Gaussian filtering on the correlated I and Q signals. The loop frequency difference estimation module is used to estimate the loop frequency deviation in real time based on the Gaussian filtered baseband I and Q signals. The difference frequency trapezoidal integrator module is used to perform trapezoidal integral filtering on the frequency calculated by the loop in order to obtain a stable coarse phase difference.

[0023] The loop phase difference estimation module is used to estimate the loop phase deviation in real time based on the Gaussian filtered baseband I and Q signals; The loop filter adopts a structure in which a third-order frequency-locked loop and a third-order phase-locked loop work together. The output of the frequency-locked loop is converted into a phase deviation auxiliary phase-locked loop after discrete integration. The integral operation in the loop filter is discretized through bilinear transformation. This module is also the core module of the loop. The numerically controlled oscillator, regulated by the control signal output from the loop filter, generates a replicated carrier signal.

[0024] Specifically, the carrier loop tracking method is as follows: Figure 2 As shown, it specifically includes: 1. The input signal of the designed carrier loop is a digital intermediate frequency signal. The intermediate frequency signal is multiplied by the in-phase component and the quadrature component of the NCO output to obtain the quadrature I and Q signals after mixing.

[0025] 2. The result after mixing is multiplied and correlated with the PN code module generated inside the receiver. The purpose of this step is to align the local PN code with the received intermediate frequency PN code so that the subsequent integration and filtering can generate a correlation peak.

[0026] 3. The I and Q branch results after correlation are respectively fed into Gaussian integral filters for Gaussian integral filtering to filter out high-frequency components generated by mixing and retain the baseband complex signal. The integrated and accumulated result is then sent to the PN code module. The PN code module determines whether to shift the local PN code based on the correlation peak after integration until the optimal correlation peak is found and the shift stops.

[0027] 4. Simultaneously, the baseband I and Q components after Gaussian integral filtering are sent to the loop frequency difference estimation module (frequency discriminator), frequency integration module, and loop phase difference estimation module (phase discriminator).

[0028] Figure 3 This is a block diagram of the architecture of the high-order frequency discriminator loop and the high-order phase discriminator loop working together inside the loop filter. The input of this block diagram is the frequency difference estimation result fd(n) and the phase difference estimation result Pd(n) of the loop. After the loop period is calculated, the output of the loop filter directly controls the digital NCO, thereby recovering the carrier of the pure intermediate frequency signal, and starting carrier tracking based on this.

[0029] The core technical solution lies in the design of the loop filter. The system function of the phase-locked loop (PLL) shows that the loop filter essentially determines the loop's performance. The stability of the entire loop is highly correlated with the design of the loop filter; therefore, the core technology of this invention lies in the design of the loop filter. Generally, first-order and second-order PLLs are theoretically unconditionally stable. However, first-order PLLs cannot track frequency step excitations and frequency ramp excitations. Second-order PLLs are often used in receivers, but they produce tracking deviations under frequency ramp excitations. Therefore, this design uses a third-order loop. A third-order loop can not only track frequency ramp signals with zero deviation, but also offers better freedom in noise performance optimization due to the larger number of loop parameters.

[0030] Furthermore, in addition to using a third-order phase-locked loop, a frequency-locked loop is also used. The frequency-locked loop assists the third-order phase-locked loop, enabling the frequency-locked loop in the entire combined loop to track the higher-order components of the signal that correspond to high dynamic stress during signal changes. Ultimately, the entire loop's tracking and locking of the signal becomes easier and more stable.

[0031] Figure 3 The discrete implementation of the loop filter is given. The output frequency difference of the frequency discriminator enters through the frequency-locked loop processing branch and is multiplied by the characteristic frequencies of the first-order and second-order (quadratic) frequency-locked loop branches, respectively. The results of the multiplication are then multiplied by the loop update period T. S The quadratic branch enters the first-stage discrete integrator module of the phase-locked loop (PLL) processing branch for the first integration. The first-order frequency-locked loop (FLL) branch then enters the second-stage discrete integrator block of the PLL processing branch. Finally, the frequency difference component of the lower branch undergoes two common discrete integrations with the third-order PLL branch of the upper branch, ultimately outputting the frequency control word of the external numerically controlled oscillator. The phase difference output of the phase detector enters the loop through the PLL processing branch. The frequency difference in the FLL processing branch is converted into a phase difference through internal discrete integration. This constitutes a new loop implementation structure where the FLL processing branch assists the PLL processing branch. Verification shows that this design can fully leverage the advantages of both the FLL and PLL, making signal tracking and locking easier.

[0032] Furthermore, the third-order Laplace transform of the loop filter is as follows: Figure 4 As shown, a third-order loop can track a frequency ramp-up input signal without bias, making it suitable for tracking loop designs in high-dynamic-range applications. Furthermore, it has more parameters, offering greater freedom in noise performance optimization. Figure 5 As shown, the continuous-time Laplace transform of the integral is transformed into a discrete-time form through a bilinear transform model. This completes the bilinear transform of the loop filter.

[0033] In one example, the sampling rate at the intermediate frequency (IF) is 61.44 MHz, the center frequency of the IF is 15.36 MHz, the transmit / receive frequency offset is set to 2000 Hz, and the loop parameters in the diagram are set as follows: a_2 = 2ξ, ζ is the damping coefficient with a value of 0.7071, ωnf, ωn is the characteristic frequency of the frequency-locked loop branch, Ts is the update period of the loop, K is the adjustable loop gain, which is set to 4 here. Here, b3 is the characteristic frequency of the phase-locked loop branch, b3 is a third-order loop intrinsic parameter, taken as 1.7 in the design, and a3 is also a third-order loop intrinsic parameter, taken as 1.3 in the design. The loop noise bandwidth of the frequency-locked loop is 320 Hz in this design, and the loop noise bandwidth of the phase-locked loop is 135 Hz in this design. This design can track the received frequency offset within at least 2000 Hz. Figure 6 As shown, the frequency control word output by the third-order auxiliary third-order loop filter gradually converges to a stable state during the entire loop tracking process, indicating that the entire loop gradually and rapidly tends to converge and stabilize, verifying the stability and reliability of this innovative architecture.

[0034] In summary, this invention designs a carrier loop architecture with a loop filter as its core, consisting of a high-order frequency-locked loop and a high-order phase-locked loop operating in parallel and collaboratively. The core of this novel loop architecture is the implementation of the Laplace integrator in the loop filter using a highly efficient discrete bilinear transform architecture. Furthermore, the loop filter in this architecture simultaneously receives the loop frequency estimate difference and phase estimate difference calculated in real time from the baseband I and Q signals, which are used as the inputs to the loop frequency perturbation parameter and loop phase perturbation parameter after discretization by the Laplace integrator in the loop filter, respectively. This architecture allows for rapid tuning of the phase change of the entire loop through real-time frequency changes, significantly improving the loop's response speed. Moreover, under this architecture, the loop bandwidth can be easily adjusted through internal parameter tuning of the loop filter, better adapting to environmental noise under different channels and significantly improving the noise immunity of the entire carrier loop.

[0035] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A carrier loop based on the integral discrete bilinear transform of a loop filter, characterized in that, include: A mixer is used to multiply the input digital intermediate frequency signal with the in-phase and quadrature components output by a digitally controlled oscillator to generate I and Q signals. The PN code module generates a local PN code and is used to capture the PN code in the digital intermediate frequency signal; A pseudo-code peak correlator is used to multiply and correlate the input I and Q signals with the local PN code to determine precise code element synchronization; A Gaussian integral filter is used to perform Gaussian filtering on the correlated I and Q signals. The loop frequency difference estimation module is used to estimate the loop frequency deviation in real time based on the Gaussian filtered baseband I and Q signals. The difference frequency trapezoidal integrator module is used to smooth and filter the frequency calculated by the loop in order to obtain a stable coarse phase difference; The loop phase difference estimation module is used to estimate the loop phase deviation in real time based on the Gaussian filtered baseband I and Q signals; The loop filter adopts a structure in which a third-order frequency-locked loop and a third-order phase-locked loop work together. The output of the frequency-locked loop is converted into a phase deviation-assisted phase-locked loop after discrete integration. The integral operation in the loop filter is discretized through bilinear transformation. The numerically controlled oscillator, regulated by the control signal output from the loop filter, generates a replicated carrier signal.

2. The carrier loop based on the integral discrete bilinear transform of the loop filter according to claim 1, characterized in that, The PN code module is also used for: The optimal correlation peak is found based on the Gaussian filtered baseband I and Q signals to assist in accurate phase tracking of the carrier.

3. The carrier loop based on the integral discrete bilinear transform of the loop filter according to claim 1, characterized in that, The bilinear transformation is used to convert the continuous-time Laplace transform of the integral into a discrete-time form using a bilinear transformation model. The specific transformation formula is as follows: ； Where s is the Laplace variable, Ts Let z be the sampling period, and z be the Z-transform variable.

4. The carrier loop based on the integral discrete bilinear transform of the loop filter according to claim 1, characterized in that, The loop filter specifically includes: The phase-locked loop processing branch has its input connected to the output of the loop phase difference estimation module and is used to process the phase deviation signal. The frequency-locked loop processing branch has its input connected to the output of the loop frequency difference estimation module and is used to process the frequency deviation signal. An adder, the input of which is connected to the output of the phase-locked loop processing branch and the frequency-locked loop processing branch respectively, and its output is used as the total output of the loop filter; The frequency-locked loop processing branch includes at least one discrete integrator for integrating the frequency deviation into an auxiliary control quantity in the form of a phase deviation, so as to add it to the output of the phase-locked loop processing branch in the adder.

5. A carrier tracking method based on the integral discrete bilinear transform of a loop filter, characterized in that, Includes the following steps: S1. Receives digital intermediate frequency signals and performs mixing processing; S2. Perform PN code correlation and Gaussian integral filtering; S3. Calculate the frequency deviation and phase deviation; S4. The deviation signal is processed by the loop filter of the third-order phase-locked loop assisted by the third-order frequency-locked loop; S5. Control the numerically controlled oscillator to generate a replicated carrier, thereby achieving carrier tracking and locking.

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