Storage access device, storage access method, and electronic device

Abstract

This disclosure provides a storage access device, a storage access method, and an electronic device. The storage access device includes: a physical address processing module configured to, in response to obtaining a first physical address, process a second physical address based on the first physical address processing and preset physical address processing rules, wherein the first physical address is determined based on a first access request; and a storage array access module configured to perform an access operation on the storage array based on the second physical address in accordance with the first access request. The first physical address includes multiple different address fields, and the preset physical address processing rules include processing rules determined based on the response latency characteristics of the storage array to each address field. The second physical address corresponds one-to-one with the first physical address, and the number of address bits in the second physical address is the same as that in the first physical address. This storage access device can reduce the response latency of the storage array to the first access request.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically to a memory access device, a memory access method, and an electronic device. Background Technology

[0002] As computing system performance improves, the demands on storage access response speeds become increasingly stringent. If the read / write speed of the storage medium cannot match the request frequency, access conflicts and waiting queues will occur, leading to storage response latency. Therefore, storage access rate is a key bottleneck restricting computing system performance. Summary of the Invention

[0003] At least one embodiment of this disclosure also provides a storage access device, which includes a physical address processing module and a storage array access module. The physical address processing module is configured to, in response to obtaining a first physical address, process a second physical address based on the first physical address processing and a preset physical address processing rule, wherein the first physical address is determined based on a first access request. The storage array access module is configured to perform an access operation of the first access request on the storage array based on the second physical address. The first physical address includes multiple different address fields, the preset physical address processing rule includes processing rules determined based on the response latency characteristics of the storage array to each address field, the second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as the number of address bits of the first physical address.

[0004] At least one embodiment of this disclosure provides a storage access method, the storage access method comprising: in response to obtaining a first physical address, processing based on the first physical address and a preset physical address processing rule to obtain a second physical address, wherein the first physical address is determined based on a first access request; performing an access operation of the first access request on a storage array based on the second physical address; wherein the first physical address includes multiple different address fields, the preset physical address processing rule includes processing rules determined based on the response latency characteristics of the storage array to each address field, the second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as the number of address bits of the first physical address.

[0005] At least some embodiments of this disclosure also provide an electronic device, which includes the storage access device and storage array provided in any embodiment of this disclosure. Attached Figure Description

[0006] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0007] Figure 1 A flowchart illustrating how a processor handles an access request is shown.

[0008] Figure 2 A block diagram of a computer system including a storage access device is shown, according to at least one embodiment of the present disclosure.

[0009] Figure 3 An exemplary memory organization diagram of a DRAM storage array provided in at least one embodiment of the present disclosure is shown.

[0010] Figure 4 Examples of address fields corresponding to a first physical address provided in at least one embodiment of this disclosure are shown.

[0011] Figure 5 An exemplary flowchart of a storage access method provided in at least one embodiment of the present disclosure is shown.

[0012] Figure 6 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0013] Figure 7 A schematic structural diagram of a general-purpose graphics processor (GPGPU) provided in at least one embodiment of the present disclosure is shown.

[0014] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0016] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0017] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0018] In a computer system, when a processor receives an access request, it first generates a virtual address (i.e., a logical address) based on the access request, and then completes the translation from virtual address to physical address through a page table (PTE). For example, when a general-purpose computing on graphics processing units (GPGPU) performs the translation from virtual address to physical address, it relies on the collaboration of the GPGPU memory management unit (MMU / GMMU), address translators (such as the translation lookaside buffer (TLB)), and software (such as page tables and drivers).

[0019] For example, after obtaining a physical address, the processor uses the physical address to index the multi-level caches (such as L1, L2, and L3) inside the processor. If a cache hit occurs inside the processor, the physical address is used to directly retrieve the cache tag; if a cache miss occurs, the processor needs to continue accessing the memory.

[0020] Figure 1 A flowchart illustrating how a processor handles an access request is shown.

[0021] like Figure 1As shown, taking the access request processed by the processor as a data read request as an example, the data read process includes the following steps S01-S07. It should be noted that the processor here can also be replaced by other processing devices or units with information processing capabilities. For example, for a multi-core processor, the processor here can also be replaced by one of the processor cores.

[0022] Step S01: The processor (or processor core) outputs the virtual address of the target data or instruction of the access request to the address translator 101 (TLB), which translates the virtual address into a physical address. The processor then determines whether the target data or instruction of the access request is in the first-level cache (e.g., L1 Cache). The access request can be a data or instruction read request; for example, the address translator 101 stores page tables for address translation.

[0023] Step S02: If the target data or instruction of the access request exists in the first-level cache, retrieve the target data or instruction of the access request from the first-level cache, and send the target data or instruction of the access request to the processor through the following step S07.

[0024] Step S03: If the target data or instruction of the access request does not exist in the first-level cache, then request a storage item from the missed address cache (MAB) 102 and allocate the storage item to the above access request.

[0025] Step S04: Cache miss 102 requests the target data or instruction of the access request from the next level cache (e.g., the second-level cache, L2 Cache) based on the storage item.

[0026] Step S05: The next level cache retrieves the target data or instruction of the access request and returns the target data or instruction of the access request to the cache of the missed address.

[0027] like Figure 1 As shown, if the target data or instruction of the access request is stored in the second-level cache, the second-level cache retrieves the target data or instruction from the second-level cache. If the target data or instruction of the access request is not stored in the second-level cache, the second-level cache can retrieve the target data or instruction from the storage located at the next level below the second-level cache. For example, the storage located at the next level below the second-level cache can be a third-level cache (L3Cache), a fourth-level cache (e.g., the last-level cache), or memory (e.g., DRAM), etc.

[0028] Step S06: Cache miss 102. The target data or instruction of the access request is written to the first-level cache. For example, after memory returns the target data, it can be filled into the processor's internal cache (e.g., L1 Cache) so that subsequent accesses can hit the processor's internal cache.

[0029] Step S07: The first-level cache provides the target data or instruction of the access request to the processor for further processing.

[0030] For a processor (or processor core), the first level cache, the second level cache and the last level cache within the processor are usually static random access memory (SRAM), while for memory outside the processor (such as main memory), dynamic random access memory (DRAM) is usually used.

[0031] When an access request corresponds to multiple consecutive missed physical addresses, the memory's response to those consecutive physical addresses is crucial. For example, DRAM-related technical standards (such as DDR5) specify various timing constraints for memory responses to physical addresses.

[0032] For example, when consecutive physical address access requests are made for the same bank group, and these physical addresses are mapped to the same bank group, the timing constraint of the Four Activation Window (tFAW) must be followed. The tFAW parameter indicates that within a specified time window, a maximum of four banks in the same bank group are allowed to be in row active state simultaneously. This is to prevent overload and current fluctuations in the internal power distribution network of the bank group due to excessive parallel activation.

[0033] For example, when consecutive physical address access requests for the same bank point to different rows within the same bank, the memory controller must adhere to the timing constraints of Row Cycle Time (tRC). The access request must first perform a precharge operation on the currently active row, then activate the target row and execute the corresponding read / write command. Here, Row Cycle Time (tRC) includes Row-to-Row Delay (tRRD) and Row Precharge Time (tRP).

[0034] Therefore, under the timing constraints of memory's response to physical addresses, the response latency of memory for consecutive accesses will increase to varying degrees depending on the different access overhead states of the memory during actual operation (such as access to the same memory bank or access to the same group of memory banks). This not only reduces the effective bandwidth of the memory and increases the memory's response latency, but also further affects the overall access performance of the computing system.

[0035] At least one embodiment of this disclosure provides a storage access device, which includes a physical address processing module and a storage array access module. The physical address processing module is configured to, in response to obtaining a first physical address, process it based on the first physical address and preset physical address processing rules to obtain a second physical address, wherein the first physical address is determined based on a first access request. The storage array access module is configured to perform an access operation on the storage array based on the second physical address in accordance with the first access request. The first physical address includes multiple different address fields, and the preset physical address processing rules include processing rules determined based on the response latency characteristics of the storage array to each address field. The second physical address corresponds one-to-one with the first physical address, and the number of address bits in the second physical address is the same as that in the first physical address.

[0036] In the memory access apparatus of the above embodiments of this disclosure, the physical address processing module processes the first physical address determined by the first access request according to a preset processing rule, including the response latency characteristics of each address field of the memory array, to obtain a second physical address. This allows the processing of the original first physical address into a second physical address without changing the timing constraints of the memory array's response to the physical address. This minimizes the timing constraints that would increase the memory array's response latency caused by the input physical address. Consequently, when the memory array access module uses a second physical address that corresponds one-to-one with the first physical address and has the same number of address bits to access the memory array, the response latency of the memory array to the first access request is reduced, and the overall access performance of the computing system is improved. Furthermore, in some embodiments, the integrated circuit (e.g., a chip) includes the memory access apparatus of the above embodiments of this disclosure, which can improve the efficiency of accessing the memory array (DRAM) without modifying the chip structure and running program.

[0037] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same parts described in different drawings.

[0038] Figure 2 A block diagram of a computer system including a storage access device is shown, according to at least one embodiment of the present disclosure.

[0039] like Figure 2 As shown, the computer system 100 includes a processor 10, a cache 20, a storage access device 200, and a storage array 50, wherein the storage access device 200 includes a physical address processing module 30 and a storage array access module 40.

[0040] When computer system 100 receives an access request (e.g., a first access request), processor 10 can determine a first physical address through virtual address mapping. For example, processor 10 can be any processing circuit with processing capabilities implemented in hardware or firmware, and can include a single processing core (also called a computing core) or multiple processing cores. For example, processor 10 can be a central processing unit (CPU) or a coprocessor, a microcontroller unit (MCU), or a digital signal processor (DSP); for example, a coprocessor can be an artificial intelligence processor such as a general-purpose computing on graphics processing units (GPGPU), an accelerator (e.g., a graphics accelerator or digital signal processing unit), a graphics processing unit (GPU), etc., or a programmable logic array or any other processor with instruction execution capabilities, etc., and the embodiments of this disclosure are not limited thereto.

[0041] After receiving the first physical address from the processor 10, cache 20 can match the physical address with a tag RAM composed of random-access memory (RAM). In the event of a cache hit, data is read from the data array (SRAM array); in the event of a cache miss, the first physical address is provided to the memory access device 200 of the memory array 50. Cache 20 can be a Level 1 cache, Level 2 cache, or a higher-level cache (e.g., the last level cache (LLC)) in the computer system 100, used to improve the response speed of access requests and overall efficiency in the computer system 100.

[0042] For example, without configuring cache 20, processor 10 can also directly provide the first physical address to storage access device 200.

[0043] In some embodiments of this disclosure, the physical address processing module 30 in the storage access device 200 is configured to, in response to obtaining a first physical address, process a second physical address based on the first physical address processing and a preset physical address processing rule, wherein the first physical address is determined based on a first access request.

[0044] The storage array access module 40 is configured to perform an access operation of the storage array 50 based on the second physical address and a first access request.

[0045] Here, the first physical address includes multiple different address fields, and the preset physical address processing rules include processing rules determined based on the response latency characteristics of each address field of the storage array 50. The second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as that of the first physical address.

[0046] For example, the storage array access module 40 can be a memory controller, or it can be an access control module located inside the memory and physically isolated from the storage array 50 in the memory.

[0047] In some embodiments of this disclosure, the storage array 50 may be a memory, such as a semiconductor memory cell. For example, the memory may be any memory with storage function, such as dynamic random access memory (DRAM), random access memory (RAM), or static random access memory (SRAM). For example, it may be the outermost storage in a GPGPU, low power double data rate synchronous dynamic random access memory (LPDDR), etc. This disclosure does not limit this.

[0048] The following detailed description uses storage array 50 as an example of dynamic random access memory (DRAM).

[0049] Figure 3 An exemplary memory organization diagram of a DRAM storage array provided in at least one embodiment of the present disclosure is shown.

[0050] like Figure 3 As shown, the storage array 50 includes control logic 501, address register 502, row decoder 503, column decoder 504, sensitive amplifier 505, data buffer 506, memory bank 0~X and memory bank 0~Y (X and Y are positive integers).

[0051] Control logic 501 is configured to receive external access requests and command signals, and address register 502 is configured to parse the input physical address (e.g., first physical address / second physical address) to determine each address field. Then, the corresponding memory group and / or memory can be selected based on the memory group address field and / or memory address field in the address field. For example, after parsing the memory group address field, a gating mechanism can be used to select the target memory group; after parsing the memory address field, a gating mechanism can be used to select the target memory.

[0052] Subsequently, the row address is sent to the row decoder 503 of the corresponding memory bank to activate the target row (i.e., word line) in the memory array; the column address is sent to the column decoder 504 of the memory bank to locate the target column (i.e., bit line), thereby locking the specific storage bit in the memory array through the cross-linking of the row address field and the column address field.

[0053] Subsequently, the weak signal of the storage capacitor is detected and amplified by the built-in sensitive amplifier 505 of each storage unit, and finally the data is matched with the external bus rate and transmitted bidirectionally via the data buffer 506.

[0054] For example, storage array 50 includes multiple banks or at least one bank group, each bank group including multiple banks; for example, multiple different address fields include at least two of the following address fields: address field of bank group, address field of bank, row address field, and column address field.

[0055] Figure 4 Examples of address fields corresponding to a first physical address provided in at least one embodiment of this disclosure are shown.

[0056] For example, the storage hierarchy of a storage array may include bank groups, banks, rows, and columns; each bank group includes multiple banks, each bank includes multiple rows, and each row includes multiple columns. The first physical address is an N-bit binary address Addr[N-1:0], which uses a segmented address mapping mechanism to access different storage levels of the DRAM, where N is a positive integer.

[0057] For example, for each address bit (i.e. bit) of the first physical address Addr01[N-1:0], the bits located at positions (m+h+k+n) to (m+h+k+1) (i.e., Addr01[m+h+k+n:m+h+k+1]) can be used as the row address field Row[n:0] of the target storage row to be activated within the bank.

[0058] The bits located at positions (m+h+k) to (h+k+1) (i.e., Addr01[m+h+k:h+k+1]) can be used as the Bank Group[m:0] address field for selecting the target bank group in the storage array.

[0059] The bits at positions (h+k) to (k+1) (i.e., Addr01[h+k:k+1]) can be used as the bank address field Bank[h:0] for selecting the target bank within the selected bank group.

[0060] Each bit at position (k) to (0) (i.e., Addr01[k:0]) can be used as the column address field Col[k:0] for selecting the target data column in the activated row buffer, where m, h, k and n are all integers.

[0061] It should be noted that, Figure 4 The bit field allocation of the address field of the first physical address shown is only an exemplary address field segmentation mapping method. The actual system can be flexibly configured according to performance optimization requirements. For example, the mapping relationship between the row address field, memory bank address field, memory bank group address field, and column address field and the physical address can be adjusted as needed, and this disclosure does not impose any limitations on this.

[0062] Since the second physical address corresponds one-to-one with the first physical address, and the number of bits in the second physical address is the same as the number of bits in the first physical address, then the second physical address is used as... Figure 4 When the first physical address is processed, the second physical address is Addr02[N-1:0].

[0063] For example, the address fields of the second physical address obtained by processing according to the preset physical address processing rules correspond to the address fields of the first physical address.

[0064] For example, for each address bit (i.e. bit) of the second physical address Addr02[N-1:0], the (m+h+k+n)th bit to the (m+h+k+1)th bit corresponds to the row address field Row[n:0]; the (m+h+k)th bit to the (h+k+1)th bit corresponds to the bank group address field Bank Group[m:0]; the (h+k)th bit to the (k+1)th bit corresponds to the bank address field Bank[h:0]; and the (k)th bit to the (0)th bit corresponds to the column address field Col[k:0].

[0065] Furthermore, since the second physical address corresponds one-to-one with the first physical address, and the first physical address is determined based on the first access request and corresponds one-to-one with the first access request, the second physical address also corresponds one-to-one with the first access request.

[0066] The preset physical address processing rules include processing rules determined based on the response latency characteristics of each address field of the storage array. The response latency characteristics of each address field vary because different address fields correspond to different timing constraints. That is, after obtaining the address fields based on a physical address, when the storage array responds to access requests based on each address field, the storage array will generate different response latency characteristics for each address field according to the timing constraints corresponding to each address field.

[0067] In other words, the preset physical address processing rules can be used to process each address field according to the corresponding physical address processing rules based on the different response latency characteristics generated by the storage array for each address field.

[0068] The following is based on Figure 4 Taking the first physical address accessing the storage array as an example, this illustrates that the storage array generates different response latency characteristics for each address field.

[0069] For example, after determining the bank group address field BankGroup[m:0], bank address field Bank[h:0], row address field Row[n:0], and column address field Col[k:0] of the corresponding access memory array based on the first physical address, the memory controller can first determine the target bank group Bank GroupA in the memory array based on the bank group address field Bank Group[m:0]. According to the timing constraint four-activation window (tFAW) for accessing the memory array corresponding to the bank group address field, if four banks in bank group A are already activated before accessing the target bank group Bank GroupA based on the bank group address field Bank Group[m:0], the response latency for accessing the first physical address will increase. For example, tFAW is typically around 30 nanoseconds, and the response latency for accessing the first physical address will increase by at least 30 nanoseconds.

[0070] For example, in target memory bank Bank GroupA, the target memory bank BankA is determined based on the memory bank address field Bank[h:0]. According to the timing constraint row cycle time (tRC) for accessing the memory array corresponding to the memory bank address field, when accessing based on the memory bank address field Bank[h:0], if another memory row is already active in the current target memory bank BankA, the current row needs to be activated and pre-charged. This increases the response latency for accessing the first physical address. For example, tRC is typically around 45 nanoseconds, increasing the response latency for accessing the first physical address by at least 45 nanoseconds.

[0071] For example, when accessing the target row RowA in the target storage BankA based on the row address field Row[n:0], if RowA has already been activated in the previous access (that is, the target row RowA is the same as the currently activated row), the response delay of the first physical address access caused by the aforementioned row cycle time (tRC) can be saved, and column access can be directly entered.

[0072] For example, for the target row RowA that has been activated, the memory controller sends a column read / write command to the target row buffer based on the column address field Col[k:0] to complete the data access. When accessing based on the column address field Col[k:0], if the consecutive column accesses always point to the same memory bank group or memory bank and the row address field remains unchanged, the switching overhead of memory bank group, memory bank or row can be avoided when performing consecutive column accesses, thereby reducing the response latency.

[0073] Therefore, in order to minimize the response latency of the storage array to the physical address, different processing is required for different address fields.

[0074] Next, continue with Figure 4 Taking the first physical address shown as an example, this paper explains how the physical address processing module processes the first physical address based on preset physical address processing rules to obtain the second physical address.

[0075] In some embodiments of this disclosure, the preset physical address processing rules include a first processing rule and a second processing rule. The first processing rule is used to process a first address field that makes the response latency characteristic decrease as the value changes, and the second processing rule is used to process a second address field that makes the response latency characteristic decrease as the value remains unchanged.

[0076] For example, the first processing rule can be used to handle the following access scenarios where address field A (representing any first address field) exists: Scenario 1, when another address field B changes, changing address field A will also reduce response latency. For example, changing the bit value of the row address field Row[n:0] while changing the bit value of the bank address field Bank[h:0] will reduce latency; Scenario 2, changing address field A as much as possible will reduce response latency. For example, frequently changing the bit value of Bank Group[m:0].

[0077] For example, the second processing rule can be used to handle the following access scenarios where address field C (representing any second address field) exists: Scenario 3, when another address field D changes, keeping address field C unchanged will reduce response latency, for example, when switching the bit value of column address field Col[k:0], it is not desirable for the bit value of bank address field Bank[h:0] to change; Scenario 4, keeping address field C unchanged as much as possible will reduce response latency, for example, keeping the bit value of row address field Row[n:0] unchanged as much as possible.

[0078] For example, when the corresponding values ​​of the Bank Group address field [m:0] and the Bank address field [h:0] change, the response latency caused by the four active window (tFAW) or row cycle time (tRC) can be avoided to some extent. Therefore, the response latency of these two address fields decreases as their values ​​change. In other words, the Bank Group address field and the Bank address field are the first address fields and can be processed using the first processing rule. That is, sequentially reading different Bank Groups in the DRAM array will have higher bandwidth than sequentially reading the same Bank Group in the DRAM.

[0079] For example, when the corresponding fetch of the row address field Row[n:0] changes, it will increase the response latency caused by the row cycle time (tRC) to some extent.

[0080] For example, when the corresponding fetch pointer of the column address field Col[k:0] changes, any change in the row address field, bank address field, or bank group address field will result in varying degrees of response latency. Only when the column address field changes while the other address fields remain unchanged will the response latency of the storage array caused by the change in the column address field be the lowest.

[0081] To minimize response latency, it is desirable to keep the row address field and column address field unchanged as much as possible. That is, the row address field and column address field can be used as the second address field, and the second processing rule can be applied.

[0082] It should be noted that whether each address field in the first physical address belongs to the first address field or the second address field can be dynamically determined based on different access situations of the storage array accessed by the physical address, rather than a fixed classification of a certain address field.

[0083] For example, when it is identified that the first physical address is different from the previously accessed physical address, the storage address field Bank[h:0] and the previously accessed physical address both point to the target storage bank BankA, but the target row pointed to by the row address field Row[n:0] has changed, since accessing different target rows of the same storage bank will increase the response latency caused by row cycle time (tRC), the storage address field Bank[h:0] can be identified as the first address field whose response latency decreases as the value changes.

[0084] For example, if the bank address field Bank[h:0] and the previously accessed physical address both point to the target bank BankA, but the target column pointed to by the column address field Col[k:0] has changed, since the response latency will be minimized when accessing different columns consecutively if the value of the bank address field does not change, the bank address field Bank[h:0] can be identified as a second address field that reduces the response latency as long as its value remains unchanged.

[0085] It should be noted that the specific address fields referred to by the first address field and the second address field may vary depending on the architecture of the storage array. For example, for a storage array without a storage group architecture, the physical address used to access the storage array does not contain a storage group address field; for example, for a storage array that further includes a storage rank or storage channel architecture, the physical address used to access the storage array will also contain a corresponding address field, and this disclosure does not impose any restrictions on this.

[0086] For example, when processing the first physical address, after identifying each address field of the first physical address, the physical address processing rules applicable to each address field can be determined.

[0087] In some embodiments of this disclosure, the physical address processing module 30 is further configured to: perform a first processing operation on at least each bit in the first address field based on a first processing rule to determine the bit value at the corresponding bit position in the second physical address; and / or, perform a second processing operation on at least each bit in the second address field based on a second processing rule to determine the bit at the corresponding bit position in the second physical address.

[0088] For example, a bit position is used to indicate the location of a bit or several bits within the entire physical address.

[0089] For example, for the row address field Row[n:0] formed by the bits at positions (m+h+k+n) to (m+h+k+1) in the first physical address, the second processing operation corresponding to the second processing rule can be performed on each bit of the row address field Row[n:0] to determine the bit value of each bit at position (m+h+k+n) to (m+h+k+1) in the second physical address.

[0090] For example, for the Bank Group[m:0] memory group address field corresponding to each bit position from (m+h+k) to (h+k+1) in the first physical address, the first processing operation corresponding to the first processing rule can be performed on each bit of the Bank Group[m:0] memory group address field to determine the bit value of each bit position from (m+h+k) to (h+k+1) in the second physical address.

[0091] For example, for the storage address field Bank[h:0] which is formed by the bits at positions (h+k) to (k+1) in the first physical address, the first processing operation corresponding to the first processing rule can be performed on each bit of the storage address field Bank[h:0] to determine the bit value of each bit at position (h+k) to (k+1) in the second physical address.

[0092] For example, for the column address field Col[k:0] formed by the bits at positions (k) to (0) in the first physical address, the second processing operation corresponding to the second processing rule can be performed on each bit of the row address field Row[n:0] to determine the bit value of each bit at position (k) to (0) in the second physical address.

[0093] It should be noted that in the above examples, each address field was processed according to the corresponding physical address processing rules. However, in practice, it is advisable to first identify whether the first and second address fields meet the response latency requirements for accessing the storage array. If the target storage bank of the first address field Bank[h:0] of the first physical address is BankA, while the target storage bank of the previously accessed physical address is BankB, that is, the value of this storage bank address field has changed relative to the previous physical address. In this case, the first processing operation for this storage bank address field is unnecessary. Similarly, for the second address field, if it is identified that this field is the same as the corresponding address field of the previous access, such as the target row of both accesses being RowA, then the second processing operation is also unnecessary.

[0094] In some embodiments of this disclosure, the physical address processing module 30 is further configured to: determine a first sequence corresponding to the first object bit based on a first processing rule; determine the bit value of the bit in the second physical address that is in the same position as the first object bit based on a first calculation result of the first sequence; and / or, determine a second sequence corresponding to the second object bit in the second address field based on a second processing rule; and determine the bit value of the bit in the second physical address that is in the same position as the second object bit based on a second calculation result of the second sequence.

[0095] For example, when performing a first processing operation on each bit of a first address field, a first sequence corresponding to the bit to be processed (the first object bit) in the first address field can be determined first. This first sequence is a sequence generated according to a first processing rule. For example, the sequence length (i.e., the number of bits) of the first sequence can be the same as the number of bits of the first physical address, or it can be different from the number of bits of the first physical address.

[0096] For example, when performing the first processing operation on the bit at position (h+k) of the first address field Bank[h:0], the first sequence (e.g., 101010) corresponding to the bit at position (h+k) can be determined. The first calculation result is obtained by calculating the sequence 101010, for example, which is 1. At this time, it can be determined that the bit value of the bit at position (h+k) of the second physical address is also 1.

[0097] For example, when performing a second processing operation on each bit of a second address field, a second sequence corresponding to the bit to be processed (the second object bit) in the second address field can be determined first. This second sequence is a sequence generated according to a second processing rule. For example, the length of this second sequence can be the same as the number of bits in the first physical address, or it can be different from the number of bits in the first physical address.

[0098] For example, when performing a second processing operation on the bit at position (m+h+k+n) of the second address field Row[n:0], a second sequence (e.g., 0000) corresponding to the bit at position (m+h+k+n) can be determined. The second calculation result is obtained by calculating the sequence 0000, which is, for example, 0. At this time, it can be determined that the bit value of the bit at position (m+h+k+n) in the second physical address is 0.

[0099] For example, the calculation method for the first sequence and / or the second sequence can be bitwise operations, fixed bit extraction, statistical voting, etc., and this disclosure does not limit the specific calculation method.

[0100] In some embodiments of this disclosure, the first calculation result is determined based on the XOR hash calculation of the first sequence, and the second calculation result is determined based on the XOR hash calculation of the second sequence.

[0101] For example, a bitwise XOR hash calculation can be performed on the first sequence or the second sequence to obtain the first calculation result or the second calculation result.

[0102] For example, both the first sequence and the second sequence have the same number of address bits as the first physical address. For example, the first sequence can be represented as Hash_config1_x[N-1:0] and the second sequence can be represented as Hash_config2_x[N-1:0].

[0103] In some embodiments of this disclosure, the physical address processing module 30 is further configured to: configure a first basic sequence as a sequence including a first bit value and a second bit value according to a first processing rule, and determine a first sequence according to a mapping processing rule and the first basic sequence; and / or, configure a second basic sequence as a sequence including only the first bit value according to a second processing rule, and determine a second sequence according to a mapping processing rule and the second basic sequence.

[0104] For example, in order for the value of the first address field processed according to the first processing rule to change after processing, the first processing rule may include configuring the first basic sequence as a sequence of mixed 0 (first bit value) and 1 (second bit value), for example, the sequence may be generated by randomly mixing 0 and 1.

[0105] For example, in order to ensure that the value of the second address field processed according to the second processing rule does not change after processing, the second processing rule may include configuring the second basic sequence as a sequence that only includes 0 (the first bit value).

[0106] When processing the same address field corresponding to the first physical address, if the first basic sequence is directly used as the first sequence of the bit bits of the object, or the second basic sequence is directly used as the second sequence of the bit bits of the object, there will be duplicates between the first sequences corresponding to each bit of the same address field, or duplicates between the second sequences. This will result in the calculated second physical address not being able to correspond one-to-one with the first physical address.

[0107] The uniqueness of each first sequence or each second sequence in the processing of the corresponding address field can be maintained through mapping rules. For example, after determining all the basic sequences corresponding to the address field, it is possible to check whether there are duplicates among the basic sequences, and to adjust the values ​​of the duplicate sequences until there are no duplicates. For example, the duplicate sequences can be adjusted with random values.

[0108] Alternatively, in order to maintain uniqueness while also following certain rules.

[0109] For example, in some embodiments of this disclosure, the mapping processing rules are configured to configure bits in the first base sequence that have the same bit position as the first object bit as the second bit value to determine the first sequence; and / or, configure bits in the second base sequence that have the same bit position as the second object bit as the second bit value to determine the second sequence.

[0110] For example, take a first physical address with 8 bits, Addr01[7:0]=10110101, for example, Addr01[7:5]= Row[3:0]=101, Addr01[4:3]= Bank Group[1:0]=10, Addr01[2:2]= Bank[0:0]=1, Addr01[1:0]= Col[1:0]=01.

[0111] For example, for the first address field Bank Group[1:0], the first basic sequence of the object bits BankGroup[1:1] in this field can be determined as Hash_config1_4[7:0]=01010101, and the first basic sequence of Bank Group[0:0] is Hash_config1_3[7:0]=01010101. To avoid the two first basic sequences being the same, since the bit position of BankGroup[1:1] in the first physical address is the 4th bit, Hash_config1_4[4:4] can be set to 1 (the second bit value); and since the bit position of Bank Group[0:0] in the first physical address is the 3rd bit, Hash_config1_3[3:3] can be set to 1. Thus, the first sequence of Bank Group[1:1] can be determined as Hash_config1_4[7:0]=01010101, and the first sequence of Bank Group[0:0] is Hash_config1_3[7:0]=01011101.

[0112] In other words, based on the above rules, the first sequences corresponding to each bit in the memory block address field of the first physical address are no longer the same, thus maintaining the uniqueness of each first sequence.

[0113] Since the method for configuring the bit position that is the same as that of the bit position of the second object in the second basic sequence as the second bit value is the same as the method for processing the first basic sequence described above, it will not be repeated here.

[0114] In some embodiments of this disclosure, the mapping processing rule is further configured to adjust the fourth sequence bit and / or the third sequence bit to a first bit value in response to both the fourth sequence bit in the third sequence and the third sequence bit in the fourth sequence being the second bit value; wherein, the third sequence is the sequence corresponding to the third object bit in the first physical address, and the fourth sequence is the sequence corresponding to the fourth object bit in the first physical address; the fourth sequence bit is the bit in the third sequence that has the same bit position as the fourth object bit, and the third sequence bit is the bit in the fourth sequence that has the same bit position as the third object bit.

[0115] For example, for the sequence of object bits Addr01[6:6] in the first physical address Addr01[7:0] (the third sequence), Hash_config_6[7:0]=01110001, and the sequence of object bits Addr01[5:5] (the fourth sequence), Hash_config_5[7:0]=01110101. Since Hash_config_6[5:5]=1 (the second bit value) in the third sequence and Hash_config_5[6:6]=1 (the second bit value) in the fourth sequence, in order to ensure the one-to-one correspondence between the second physical address and the first physical address obtained in subsequent processing, Hash_config_6[5:5] can be set to 0 (the first bit value), or Hash_config_5[6:6] can be set to 0; or, both Hash_config_6[5:5] and Hash_config_5[6:6] can be set to 0.

[0116] It should be noted that the third sequence and the fourth sequence can both be the first sequence obtained based on the first processing rule, or they can both be the second sequence obtained based on the second processing rule, or one of the third sequence and the fourth sequence belongs to the first sequence and the other sequence belongs to the second sequence. This disclosure does not restrict which processing rule the third sequence and the fourth sequence are obtained based on.

[0117] The aforementioned verification rules further ensure the uniqueness of the second physical address mapped from the first or second calculation result obtained through XOR hashing. Therefore, after processing each address field according to the corresponding physical address processing rules, using the processed second physical address for storage array access not only reduces storage array latency but also guarantees the correctness of storage array access based on the second physical address.

[0118] Figure 5 An exemplary flowchart of a storage access method provided in at least one embodiment of the present disclosure is shown.

[0119] like Figure 5 As shown, the storage access method is executed by the processor and includes the following steps S10 and S20.

[0120] Step S10: In response to obtaining the first physical address, process the second physical address based on the first physical address processing and the preset physical address processing rules.

[0121] Step S20: Perform the access operation of the first access request on the storage array based on the second physical address.

[0122] The first physical address is determined based on the first access request; the first physical address includes multiple different address fields, and the preset physical address processing rules include processing rules determined based on the response latency characteristics of each address field of the storage array; the second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as that of the first physical address.

[0123] For example, the preset physical address processing rules include a first processing rule and a second processing rule. The first processing rule is used to process a first address field that makes the response latency characteristic decrease as the value changes, and the second processing rule is used to process a second address field that makes the response latency characteristic decrease as the value remains unchanged.

[0124] In some embodiments of this disclosure, the above-described storage access method further includes: performing a first processing operation on at least each bit in the first address field based on a first processing rule to determine the bit value at the corresponding bit position in the second physical address; and / or performing a second processing operation on at least each bit in the second address field based on a second processing rule to determine the bit at the corresponding bit position in the second physical address.

[0125] In some embodiments of this disclosure, the storage access method further includes: determining a first sequence corresponding to a first object bit based on a first processing rule; determining the bit value of a bit in a second physical address that is in the same position as the bit of the first object bit based on a first calculation result of the first sequence; and / or determining a second sequence corresponding to a second object bit in a second address field based on a second processing rule; and determining the bit value of a bit in a second physical address that is in the same position as the bit of the second object bit based on a second calculation result of the second sequence.

[0126] In some embodiments of this disclosure, the storage access method further includes: configuring a first basic sequence as a sequence including a first bit value and a second bit value according to a first processing rule, and determining a first sequence according to a mapping processing rule and the first basic sequence; and / or configuring a second basic sequence as a sequence including only the first bit value according to a second processing rule, and determining a second sequence according to a mapping processing rule and the second basic sequence.

[0127] In some embodiments of this disclosure, the mapping processing rules are configured to: configure the bits in the first base sequence that have the same bit position as the first object bit as the second bit value to determine the first sequence; and / or configure the bits in the second base sequence that have the same bit position as the second object bit as the second bit value to determine the second sequence.

[0128] In some embodiments of this disclosure, the mapping processing rule is further configured to adjust the fourth sequence bit or the third sequence bit to a first bit value in response to both the fourth sequence bit in the third sequence and the third sequence bit in the fourth sequence being the second bit value; wherein, the third sequence is the sequence corresponding to the third object bit in the first physical address, and the fourth sequence is the sequence corresponding to the fourth object bit in the first physical address; the fourth sequence bit is the bit in the third sequence that has the same bit position as the fourth object bit, and the third sequence bit is the bit in the fourth sequence that has the same bit position as the third object bit.

[0129] In some embodiments of this disclosure, the first calculation result is determined based on the XOR hash calculation of the first sequence, and the second calculation result is determined based on the XOR hash calculation of the second sequence.

[0130] For example, a storage array may include multiple storage cells or at least one group of storage cells, each group of storage cells including multiple storage cells; multiple different address fields may include at least two of the following: an address field for the group of storage cells, an address field for the storage cell, a row address field, and a column address field.

[0131] The technical effects of the storage access method in the above embodiments of this disclosure are the same as those of the storage access device described above, and therefore will not be repeated here.

[0132] Figure 6 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0133] At least one embodiment of this disclosure also provides an electronic device, such as Figure 6 As shown, the electronic device 300 includes the storage access device 200 and storage array 50 described in at least one of the above embodiments.

[0134] In some embodiments of this disclosure, the electronic device 300 further includes a processor core configured to determine a first physical address based on a first access request. For example, the processor core could be... Figure 2 The processor core in processor 10.

[0135] The following explanation uses any one of the cores in the GPGPU as an example in the processor core of electronic device 300.

[0136] Figure 7 A schematic structural diagram of a general-purpose graphics processor (GPGPU) provided in at least one embodiment of the present disclosure is shown.

[0137] like Figure 7As shown, a general-purpose graphics processor is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), such as including... Figure 7 The diagram shows streaming processor clusters 1, ..., M, where M is a positive integer greater than 1. In a general-purpose graphics processor, one streaming processor cluster handles one computational task, or multiple streaming processor clusters handle one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0138] like Figure 7 As shown, taking streaming processor cluster 1 as an example, one streaming processor cluster includes multiple computing units, such as... Figure 7 The system is structured as Computation Unit 1, Computation Unit 2, ..., Computation Unit N, where N is a positive integer. Each Computation Unit (CU) performs arithmetic and logical operations, such as accumulation, reduction, and standard addition, subtraction, multiplication, and division. A Computation Unit includes multiple cores (also called computational kernels), each of which includes an Arithmetic Logic Unit (ALU), a floating-point unit, etc. These cores are used to execute specific computational tasks. Furthermore, the Computation Unit also includes registers (e.g., ...). Figure 7 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0139] like Figure 7 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0140] like Figure 7 As shown, each streaming processor cluster also provides a buffer for caching data across the N computing units within the streaming processor cluster.

[0141] In parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in a general-purpose graphics processor (or parallel computing processor), and then dispatched via a thread block distribution module. Figure 7(Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0142] In each computing unit, the thread beam scheduling / distribution module ( Figure 7 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can be executed concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory (composed of SRAM) within the computing unit, or further to intermediate-level cache, global cache, or global memory (composed of DRAM, e.g.) Figure 7 High Bandwidth Memory (HBM) is used for read and write operations.

[0143] For example, Figure 7 The general-purpose graphics processor shown is provided with the memory access device described in at least one of the above embodiments, for example... Figure 7 The global memory in this disclosure can be the storage array 50 described in at least one of the above embodiments. Figure 7 The global cache in the data can be the cache 20 described in at least one embodiment of this disclosure. Specifically... Figure 7 The general-purpose graphics processor (GPGPU) accesses global memory through the storage access device described in at least one of the above embodiments in the same way as described above, and will not be repeated here.

[0144] The technical effects of the electronic device described in the above embodiments are the same as those of the storage access device described above, and therefore will not be repeated here.

[0145] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0146] Figure 8 The illustrated electronic device 1000 is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this disclosure. For example, the electronic device 1000 may include the computer system 100 in at least one embodiment of this disclosure.

[0147] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.

[0148] For example, refer to Figure 8 In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. For example, processing device 1001 can execute the storage access method provided in any of the above embodiments of this disclosure. For example, processing device 1001 can be a processor in any of the above embodiments of this disclosure, such as a GPGPU. Various programs and data required for computer system operation are also stored in RAM 1003. Processing device 1001, ROM 1002, and RAM 1003 are connected via interconnection network 1004. Input / output (I / O) interface 1005 is also connected to interconnection network 1004.

[0149] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 8 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0150] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0151] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0152] The following points need to be clarified regarding this disclosure:

[0153] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0154] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0155] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A storage access device, characterized in that, The storage access device includes: The physical address processing module is configured to, in response to obtaining a first physical address, process a second physical address based on the first physical address processing and a preset physical address processing rule, wherein the first physical address is determined based on a first access request; The storage array access module is configured to perform the access operation of the first access request on the storage array based on the second physical address; The first physical address includes multiple different address fields, and the preset physical address processing rule includes processing rules determined based on the response latency characteristics of the storage array to each of the address fields. The second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as that of the first physical address. The preset physical address processing rules include a first processing rule and a second processing rule. The first processing rule is used to process a first address field that makes the response latency characteristic appear as a decrease in response latency as the value changes. The second processing rule is used to process a second address field that makes the response latency characteristic appear as a decrease in response latency as the value remains unchanged. The physical address processing module is further configured as follows: Based on the first processing rule, at least each bit in the first address field is subjected to the first processing operation to determine the bit value at the corresponding bit position in the second physical address; and / or, Based on the second processing rule, at least each bit in the second address field is subjected to the second processing operation to determine the bit at the corresponding bit position in the second physical address.

2. The storage access device according to claim 1, characterized in that, The physical address processing module is also configured to: Based on the first processing rule, a first sequence corresponding to the first object bit is determined; based on the first calculation result of the first sequence, the bit value of the bit in the second physical address that is in the same position as the bit of the first object bit is determined; And / or, Based on the second processing rule, a second sequence corresponding to the second object bit in the second address field is determined; based on the second calculation result of the second sequence, the bit value of the bit in the second physical address that is in the same position as the bit of the second object is determined.

3. The storage access device according to claim 2, characterized in that, The physical address processing module is also configured to: According to the first processing rule, the first basic sequence is configured as a sequence including a first bit value and a second bit value; the first sequence is determined according to the mapping processing rule and the first basic sequence; and / or, According to the second processing rule, the second basic sequence is configured as a sequence that only includes the first bit value, and the second sequence is determined according to the mapping processing rule and the second basic sequence.

4. The storage access device according to claim 3, characterized in that, The mapping processing rules are configured as follows: The bits in the first base sequence that are at the same bit position as the bit bit of the first object are configured as the second bit value to determine the first sequence; and / or, The bits in the second basic sequence that are at the same bit position as the bit bit of the second object are configured as the second bit value to determine the second sequence.

5. The storage access device according to claim 3, characterized in that, The mapping processing rule is further configured to, in response to the fact that both the fourth sequence bit in the third sequence and the third sequence bit in the fourth sequence are second bit values, adjust the fourth sequence bit and / or the third sequence bit to the first bit value; Wherein, the third sequence is the sequence corresponding to the third object bit in the first physical address, and the fourth sequence is the sequence corresponding to the fourth object bit in the first physical address; the fourth sequence bit is the bit in the third sequence that has the same bit position as the fourth object bit, and the third sequence bit is the bit in the fourth sequence that has the same bit position as the third object bit.

6. The storage access device according to claim 2, characterized in that, The first calculation result is determined based on the XOR hash calculation of the first sequence, and the second calculation result is determined based on the XOR hash calculation of the second sequence.

7. The storage access device according to any one of claims 1-6, characterized in that, The storage array includes multiple memory cells or at least one group of memory cells, each of the group of memory cells including multiple memory cells; The plurality of different address fields include at least two of the following: the address field of the memory group, the address field of the memory, the row address field, and the column address field.

8. An electronic device, characterized in that, Includes the storage access device and the storage array as described in any one of claims 1-7.

9. The electronic device according to claim 8, characterized in that, The electronic device also includes: The processor core is configured to determine the first physical address based on the first access request.

10. A storage access method, characterized in that, The storage access method includes: In response to obtaining a first physical address, a second physical address is obtained by processing based on the first physical address and a preset physical address processing rule, wherein the first physical address is determined based on a first access request; The first access request is executed on the storage array based on the second physical address; The first physical address includes multiple different address fields, and the preset physical address processing rule includes processing rules determined based on the response latency characteristics of the storage array to each of the address fields. The second physical address corresponds one-to-one with the first physical address, and the number of address bits of the second physical address is the same as that of the first physical address. The preset physical address processing rules include a first processing rule and a second processing rule. The first processing rule is used to process a first address field that makes the response latency characteristic appear as a decrease in response latency as the value changes. The second processing rule is used to process a second address field that makes the response latency characteristic appear as a decrease in response latency as the value remains unchanged. The storage access method further includes: Based on the first processing rule, at least each bit in the first address field is subjected to the first processing operation to determine the bit value at the corresponding bit position in the second physical address; and / or, Based on the second processing rule, at least each bit in the second address field is subjected to the second processing operation to determine the bit at the corresponding bit position in the second physical address.

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