System, method and corresponding device for realizing cross-board card transmission of BunchID message based on single-ended line

Abstract

The invention provides a system, a method and a corresponding device for realizing cross-board card transmission of a BunchID message based on a single-ended line. The system comprises a first FPGA board card and a second FPGA board card which are connected through a transmission structure based on a single-ended line, the first FPGA board card is used for decoding the received two paths of rabbit differential signals based on a rabbit protocol to obtain BunchID data; the BunchID data is latched by using a received white rabbit trigger signal, and the BunchID data is transmitted to the second FPGA board card in batches through the transmission structure by using a constructed transmission clock signal; and the second FPGA board card is used for decoding the sequentially received data by using the constructed transmission clock signal to obtain the BunchID data. According to the BunchID message transmission method and the BunchID message transmission device, cross-board card transmission of the BunchID message is realized through a transmission structure which is relatively general and relatively low in cost and based on a single-ended line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a system and method for transmitting BunchID messages across board cards based on single-ended lines and corresponding devices. BACKGROUND

[0002] The data collected by the hard X-ray free electron laser related experiments needs to correspond to the pulses emitted by the source, so that the experimental data in multiple collection devices can be aligned and compared. BunchID is a number used to identify the pulse. It is generally transmitted through one differential serial data line and one 64Mhz differential clock line. In order to transmit between multiple slots in the PXIe chassis, the ideal situation is to use a chassis with a clock slot, and use the PXIe_DstarB and PXIe_DstarC differential links to transmit the two serial signals. However, the chassis with a clock slot is usually 9 slots or 18 slots, which is large in size and high in cost, and requires that both the sending and receiving board cards are equipped with corresponding PCB connections, which lacks universality. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a system and method for transmitting BunchID messages across board cards based on single-ended lines and corresponding devices, which solves the problem of high cost of existing BunchID transmission.

[0004] To achieve the above-mentioned purposes and other related purposes, the first aspect of the present application provides a system for transmitting BunchID messages across board cards based on single-ended lines, comprising: a first FPGA board card, a transmission structure based on single-ended lines, and a second FPGA board card; wherein the first FPGA board card and the second FPGA board card are connected through the transmission structure; the first FPGA board card is used to decode two white rabbit differential signals received based on the white rabbit protocol, to obtain BunchID data; the BunchID data is latched using a received white rabbit trigger signal, and is transmitted to the second FPGA board card in batches through the transmission structure using a constructed transmission clock signal; the second FPGA board card is used to decode the data received in sequence using a constructed transmission clock signal, to obtain the BunchID data.

[0005] In some embodiments of the first aspect of the present application, the transmission structure comprises eight single-ended lines; wherein the eight single-ended lines comprise one transmission clock signal line, one data valid signal line, and six data transmission lines.

[0006] In some embodiments of the first aspect of the present application, the eight single-ended lines are respectively eight trigger lines of a PXIe chassis.

[0007] In some embodiments of the first aspect of the present application, the first FPGA board card is provided with an encoding module; wherein the encoding module comprises a main clock signal port, a data input port, a first data validity port, a clock signal output port, a first data output port and a data validity flag signal output port; the main clock signal port is used to receive a main clock signal; the data input port is used to receive the BunchID data; the first data validity port is used to receive a first data validity signal; the clock signal output port is connected to the transmission clock signal line and is used to output a transmission clock signal; the transmission clock signal is obtained by frequency division of the main clock signal; the first data output port is connected to the six data transmission lines respectively and is used to output the BunchID data in batches; and the data validity flag signal output port is connected to the data validity signal line and is used to output a data validity flag signal.

[0008] In some embodiments of the first aspect of the present application, the encoding module is further provided with an encoding state machine and a storage unit; the received white rabbit trigger signal is used to latch the BunchID data, and the constructed transmission clock signal is used to transmit the BunchID data to the second FPGA board card in batches through the transmission structure, comprising: when the rising edge of the first data validity signal is detected, the BunchID data is stored in the storage unit, and the state machine is switched from an idle state to a sending state; in the sending state, the storage unit is sequentially executed multiple times of data taking operation according to the number of data transmission lines by using the transmission clock signal, and the data taken each time is output through the first data output port; at the same time, the data validity flag signal output port outputs the corresponding valid data validity flag signal; after the data in the storage unit is taken out, the data validity flag signal output port outputs the corresponding invalid data validity flag signal, and the state machine is switched from the sending state to the idle state.

[0009] In some embodiments of the first aspect of the present application, the encoding module is further provided with a first counter; wherein the first counter is used to assist the data taking operation and to indicate whether the data in the storage unit is taken out completely.

[0010] In some embodiments of the first aspect of the present application, the second FPGA board card is provided with a decoding module; wherein the decoding module comprises: a high-speed clock signal port, a second data valid port, a six-bit data input port, an external data clock signal port, a second data output port, and an end flag signal output port; the high-speed clock signal port is used to receive a high-speed clock signal; the six-bit data input port is connected to the six data transmission lines and is used to receive data sent by the first FPGA board card; the second data valid port is connected to the data valid signal line and is used to receive a data valid flag signal; the external data clock signal port is connected to the transmission clock signal line and is used to receive a transmission clock signal; the second data output port is used to output the BunchID data; and the end flag signal output port is used to output an end flag signal.

[0011] In some embodiments of the first aspect of the present application, the decoding module is further provided with a second counter and a data storage unit; the data received in sequence is decoded by using the transmission clock signal constructed to obtain the BunchID data, comprising: initializing the second counter and the data storage unit; every time a rising edge of the transmission clock signal is detected, the data received through the six-bit data input port is stored in the data storage unit and the count value of the second counter is updated; when the count value of the second counter reaches a preset counter value, all data in the data storage unit is output through the second data output port to obtain the BunchID data.

[0012] To achieve the above object and other related objects, the second aspect of the present application provides a method for transmitting BunchID packets across board cards based on single-ended lines, applied to a system for transmitting BunchID packets across board cards based on single-ended lines, the system comprising: a first FPGA board card, a transmission structure based on single-ended lines, and a second FPGA board card; the first FPGA board card and the second FPGA board card are connected through the transmission structure; the method comprises: the first FPGA board card decodes two white rabbit differential signals received based on the white rabbit protocol to obtain BunchID data; the BunchID data is latched by using a received white rabbit trigger signal and is transmitted to the second FPGA board card in batches through the transmission structure by using a transmission clock signal constructed; and the second FPGA board card decodes data received in sequence by using the transmission clock signal constructed to obtain the BunchID data.

[0013] To achieve the above object and other related objects, the third aspect of the present application provides a BunchID message corresponding device, comprising the system for transmitting BunchID message across board cards based on single-ended line and a collection module as described above; wherein the second FPGA board card is used for corresponding the BunchID message with the waveform collected by the collection module.

[0014] As described above, the system, method and corresponding device for transmitting BunchID message across board cards based on single-ended line of the present application have the following beneficial effects:

[0015] The system comprises a first FPGA board card and a second FPGA board card connected through a transmission structure based on single-ended line; the first FPGA board card is used for decoding two-way white rabbit differential signals received based on white rabbit protocol to obtain BunchID data; the BunchID data is latched by using the received white rabbit trigger signal, and the BunchID data is transmitted to the second FPGA board card in batches through the transmission structure by using the transmission clock signal constructed; the second FPGA board card is used for decoding the data received in sequence by using the transmission clock signal constructed to obtain the BunchID data. The present application realizes the transmission of BunchID message across board cards through the transmission structure based on single-ended line which is more common and lower in cost. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A schematic block diagram of the system for transmitting BunchID message across board cards based on single-ended line in an embodiment of the present application is shown.

[0017] Figure 2 A schematic diagram of the transmission structure based on single-ended line in an embodiment of the present application is shown.

[0018] Figure 3 A schematic diagram of the transmission structure based on single-ended line in another embodiment of the present application is shown.

[0019] Figure 4 A schematic diagram of the interconnection relationship between the encoding module and the decoding module in an embodiment of the present application is shown.

[0020] Figure 5 A schematic block diagram of the BunchID message corresponding device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Following make the application's implementation mode through the specific concrete example, the person skilled in the art can easily understand the other advantages and efficacy of the application from the disclosure of this specification. The application can also be implemented or applied by another different specific implementation, and the details in this specification can be based on different views and applications, and various modifications or changes are made without departing from the spirit of the application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0022] In the embodiments of the application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", and the like. For example, the first data valid port and the second data valid port are only used to distinguish different data valid ports, and do not limit the sequence. Those skilled in the art can understand that "first", "second", and the like do not limit the number and execution order, and "first", "second", and the like do not necessarily mean different.

[0023] It should be noted that in the embodiments of the application, "exemplary" or "for example" means an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0024] In the embodiments of the application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or the like means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0025] To facilitate understanding of the embodiments of the application, first, the application is described in conjunction with Figure 1 Detailed description. Figure 1A schematic block diagram of a system for transmitting BunchID messages across board cards based on single-ended lines in an embodiment of the present application is shown. The system for transmitting BunchID messages across board cards based on single-ended lines in the embodiment is suitable for the scenario of economic clock slot-free chassis, medium-low trigger rate, and multi-card acquisition. The system 1 for transmitting BunchID messages across board cards based on single-ended lines in the embodiment comprises:

[0026] a first FPGA board card 11, a transmission structure 12 based on single-ended lines, and a second FPGA board card 13.

[0027] The first FPGA board card 11 and the second FPGA board card 13 are connected through the transmission structure 12.

[0028] The first FPGA board card 11 is configured to decode two-way White Rabbit differential signals received based on the White Rabbit protocol to obtain BunchID data, latch the BunchID data using a received White Rabbit trigger signal, and transmit the BunchID data to the second FPGA board card 13 in batches through the transmission structure 12 using a constructed transmission clock signal.

[0029] The second FPGA board card 12 is configured to decode data received in sequence using a constructed transmission clock signal to obtain BunchID data.

[0030] It should be understood that the White Rabbit protocol is a clock synchronization protocol. Specifically, the White Rabbit protocol is a high-precision time synchronization and frequency distribution protocol developed by CERN, which is based on the IEEE 1588 Precision Time Protocol (PTP) and combines the SyncE technology, and can achieve sub-nanosecond clock synchronization in a fiber network of up to 10 kilometers.

[0031] It should also be understood that the division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. When actually implemented, there can be another division manner. In addition, each functional module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0032] In an embodiment, one of the two white rabbit differential signals is a differential serial signal, and the differential serial signal is used to transmit BunchID. The other is a 64Mhz differential random clock signal. The two white rabbit differential signals received are decoded based on the white rabbit protocol to obtain BunchID data. BunchID is a number identifying the pulse number. Decoding the two white rabbit differential signals received based on the white rabbit protocol can refer to the white rabbit protocol and the existing decoding method, which will not be described here. The process of latching the signal by using the trigger signal is essentially that the input signal state at a certain moment is frozen and maintained until a new trigger signal arrives. The function of latching data is to reduce the data rate.

[0033] In an embodiment, as shown in FIG. 8, the transmission structure includes eight single-ended lines; wherein the eight single-ended lines include: a transmission clock signal line, a data valid signal line, and six data transmission lines. Figure 2

[0034] It should be understood that a single-ended cable refers to a cable that transmits signals through only one wire.

[0035] Specifically, the transmission structure can be implemented in the following two ways: one is that the transmission structure only includes eight single-ended lines. The first FPGA board card and the second FPGA board card are connected through the eight single-ended lines; the other is that, as shown in FIG. 8, the eight single-ended lines are eight trigger lines PXI_Trig0-7 of a PXIe chassis without clock slots. The eight trigger lines are commonly supported and easily obtained trigger lines of the board card. PXI_Trig0 is a data valid signal line, PXI_Trig1 is a transmission clock signal line, and PXI_Trig2-7 are six data transmission lines. The first FPGA board card is connected to the eight trigger lines PXI_Trig0-7 of the PXIe chassis without clock slots, and the second FPGA board card is connected to a slot of the PXIe chassis. The signals sent by the first FPGA board card to the PXIe chassis through the eight trigger lines are transmitted to the second FPGA board card through the slot. The PXIe chassis is a modular instrument chassis based on the PXI Express (PXIe) bus standard. The communication transmission mode of the PXIe chassis trigger line and the slot, and the internal communication can refer to the existing PXIe chassis, which will not be described here. Figure 3

[0036] In an embodiment, an encoding module is arranged on the first FPGA board card.

[0037] ​​The encoding module comprises a main clock signal port clk, a first reset signal port rst_n, a data input port data_in, a first data validity port nd_i, a clock signal output port clkout, a first data output port data_out and a data validity flag signal output port valid_o.

[0038] The main clock signal port clk is used for receiving a main clock signal; specifically, the main clock signal is generally a 20Mhz main clock signal; it should be noted that other frequency main clock signals can also be selected according to requirements, which are not limited here; the main clock signal is used to drive the timing operation inside the encoding module, to ensure the synchronization of data processing.

[0039] The first reset signal port rst_n is used for receiving a reset signal; specifically, when the reset signal is at a low level, the internal state of the encoding module is reset to an initial state, so as to start data processing again.

[0040] The data input port data_in is used for receiving BunchID data.

[0041] The first data validity port nd_i is used for receiving a first data validity signal; the first data validity signal is a white rabbit trigger signal; specifically, when the first data validity signal is at a high level, it means that the data received by the data input port data_in is valid, and the encoding module processes the received data; when the first data validity signal is at a high level, it means that the data received by the data input port data_in is invalid.

[0042] The clock signal output port clkout is connected to a transmission clock signal line and is used for outputting a transmission clock signal; wherein, the frequency division clock signal obtained by frequency dividing the main clock signal is the transmission clock signal, which is used to control the timing of the first data output port data_out to output data, to ensure that the data is output at the correct clock edge; specifically, the frequency division can be performed by a frequency division circuit; it should be understood that the frequency division circuit can refer to the existing circuit, which is not described here. For example, the frequency division ratio is set to 2, that is, the frequency of the transmission clock signal is half of that of the main clock signal. Frequency division reduces the transmission clock, solving the problem of parallel transmission rate of multiple single-ended signal lines.

[0043] The first data output port data_out is connected to six data transmission lines respectively and is used for outputting the BunchID data in batches.

[0044] A data valid signal output port valid_o is connected with a data valid signal line and is used to output a data valid signal. Specifically, when the data valid signal is high, it indicates that the data output by the first data output port data_out is valid; when the data valid signal is low, it indicates that the data output by the first data output port data_out is invalid.

[0045] It should be noted that the main clock signal is frequency-divided because the transmission clock of the single-end cable should not be greater than 10 Mhz.

[0046] In an embodiment, the encoding module is further provided with a state machine, a storage unit and a first counter.

[0047] In a specific embodiment, the storage unit is a data register data_reg. The storage unit can also be other devices with storage functions, which are not limited here.

[0048] Specifically, the received white rabbit trigger signal is used to latch the BunchID data, and the transmission clock signal is used to transmit the BunchID data to the second FPGA board card in batches through the transmission structure, including:

[0049] In the initial state, the state machine is in an idle (IDLE) state and waits for the rising edge of the first data valid signal to trigger. When the rising edge of the first data valid signal is detected, the encoding module stores the 48-bit BunchID data received through the data input port data_in into the storage unit (this process is latching), and switches the state of the state machine from the idle (IDLE) state to the sending (SEND) state. At the same time, the first counter is initialized to 0.

[0050] In the sending state, every time the transmission clock signal appears a falling edge, the encoding module will take out 6-bit data from the storage unit according to the count value of the first counter, and output it to the first data output port data_out, and then send the 6-bit data to the second FPGA board card through the six data transmission lines. At the same time, in the sending state, the data valid signal is set to high, indicating that the signal output by the first data output port data_out is valid.

[0051] After outputting 6-bit data, the count value of the first counter increases by 1, and when the count value of the first counter is equal to 8, it indicates that all the data in the storage unit has been taken out, at this time the data valid signal is set to low, and the state of the state machine is switched from the sending state back to the idle state, waiting for the rising edge of the next first data valid signal to trigger.

[0052] It should be noted that through the structure of the encoding module, the encoding module can efficiently complete the encoding processing of the input data and output the data in batches under the control of the corresponding clock signal.

[0053] In an embodiment, the encoding module also adopts an edge detection circuit to detect the signal changes of nd_i and clk_out, to ensure that the state switching and data processing are performed at the correct clock edge.

[0054] In an embodiment, a decoding module is arranged on the second FPGA board card.

[0055] The decoding module includes a high-speed clock signal port fast_clk, a second reset signal port rst_n2, a second data valid port nd_i2, a six-bit data input port data_i, an external data clock signal port clk_i, a second data output port data_o2, and an end flag signal output port last_received.

[0056] As shown in Figure 4 The high-speed clock signal port fast_clk is used to receive a high-speed clock signal. The high-speed clock signal serves as the basic clock source of the decoding module and is used to drive the synchronous operation inside the decoding module. For example, the high-speed clock signal is a 100MHz high-speed clock signal.

[0057] The second reset signal port rst_n2 is used to receive a reset signal. Specifically, when the reset signal is at a low level, the internal state of the decoding module is reset to the initial state, so as to start data processing again. The first reset signal port and the second reset signal port receive the same reset signal.

[0058] The six-bit data input port data_i is connected to six data transmission lines or slots of a PXIe chassis and is used to sequentially receive the data sent by the first FPGA board card.

[0059] The second data valid port nd_i2 is connected to a data valid signal line or a slot of a PXIe chassis and is used to receive a data valid flag signal.

[0060] The external data clock signal port is connected to a transmission clock signal line or a slot of a PXIe chassis and is used to receive a transmission clock signal.

[0061] The second data output port data_o2 is used to output BunchID data.

[0062] The end flag signal output port last_received is used to output an end flag signal. When the end flag signal is at a high level, it indicates that the BunchID data output of the second data output port data_o2 is completed.

[0063] In an embodiment, the decoding module further comprises a second counter and a data storage unit.

[0064] In a specific embodiment, the data storage unit is a data register. It should be noted that other devices with storage function can be selected, which are not limited herein.

[0065] Specifically, the BunchID data is obtained by decoding the data received in sequence using the constructed transmission clock signal, including:

[0066] In the initial state, the decoding module synchronizes the data valid flag signal, the transmission clock signal, and the data received by the six-bit data input port to the clock domain of the high-speed clock signal through the synchronization circuit, so as to ensure the stability and consistency of the signals.

[0067] When the rising edge of the data valid flag signal is detected, the second counter is initialized to 0, and the data storage units are all initialized to 0, and the data reception is started.

[0068] When the rising edge of the transmission clock signal is detected, the decoding module stores the 6-bit data received by the six-bit data input port in the corresponding position of the data storage unit according to the current count value of the second counter, and increases the current count value of the second counter by 1. For example, when the current count value of the second counter is 0, the data is stored in the data storage units 47downto 42, when the current count value of the second counter is 1, the data is stored in the data storage units 41downto 36, and so on, which will not be enumerated herein.

[0069] When the current count value of the second counter is equal to 8, it indicates that the data reception is completed, the decoding module sets the end flag signal to high level, and initializes the second counter to 0, and waits for the rising edge of the next data valid flag signal.

[0070] It should be noted that through the design of the decoding module, the decoding module can efficiently complete the decoding processing of the input data, and recombine the data into complete 48-bit data output under the control of the corresponding clock signal.

[0071] In an embodiment, the decoding module further adopts an edge detection circuit to detect the signal change of the data valid flag signal and the transmission clock signal, so as to ensure the data reception and processing at the correct clock edge.

[0072] It should be noted that 6-bit data of 48-bit data is transmitted to the 6-bit data transmission line every cycle, which is transmitted in 8 clock cycles and takes about 800 ns, which is less than the update period 1us of BunchID, so it can work continuously.

[0073] It should be noted that although the PXIe_Trig0-7, different slots are not equal in length for sending and receiving, and there is a certain delay in receiving the BunchID message of different slots, since the BunchID is updated at the fastest 1us once and is latched before sending, the ns-level delay caused by the unequal length will not affect the consistency of the BunchID message received by multiple slots. And if the sending board card only latches the BunchID of the trigger signal moment with a lower update frequency, the transmission BunchID update will be slower, such as 10khz trigger corresponding to updating once every 100us.

[0074] Further, the cost of the eight single-ended lines or the PXIe chassis without a clock slot of the present application is lower than that of the PXIe chassis with a clock slot.

[0075] Similar to the above embodiment, the present application also provides a method for transmitting BunchID message across board cards based on single-ended line, applied to a system for transmitting BunchID message across board cards based on single-ended line, the system for transmitting BunchID message across board cards based on single-ended line comprising: a first FPGA board card, a transmission structure based on single-ended line, and a second FPGA board card; the first FPGA board card and the second FPGA board card are connected through the transmission structure; the method comprises:

[0076] The first FPGA board card decodes the two-way white rabbit differential signal received based on the white rabbit protocol, and latches the BunchID data obtained by decoding using the received white rabbit trigger signal; and transmits the BunchID data to the second FPGA board card in batches through the transmission structure using the transmission clock signal constructed;

[0077] The second FPGA board card decodes the data received in sequence using the transmission clock signal constructed to obtain the BunchID data.

[0078] It should be understood that the specific embodiment process of the method has been described in the above system embodiment, which will not be repeated here.

[0079] Similar to the above embodiment, as shown in Figure 5 The present application also provides a BunchID message corresponding device, comprising: a system for transmitting BunchID message across board cards based on single-ended line as described above and a collection module; wherein the second FPGA board card is used to correspond the BunchID message with the waveform collected by the collection module.

[0080] It should be understood that the system for transmitting BunchID message across board cards based on single-ended line has been described in the above embodiment, which will not be repeated here.

[0081] In one embodiment, the acquisition module is an ADC acquisition card for acquiring the pulse waveform.

[0082] As used in this description, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially localized, and / or distributed across two or more computers. Also, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0083] Those of skill in the art would understand that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. The choice of whether to implement the described functionality in hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0084] Those of skill in the art would understand that, for the described convenience and brevity, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0085] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0087] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0088] In the above embodiments, the functions of each functional unit can be implemented by software, hardware, firmware or any combination thereof, in whole or in part. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the flow or function according to the embodiments of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as high-density digital video disc (digital video disc, DVD), or semiconductor media (such as solid state disk (solid state disk, SSD) and the like.

[0089] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage media that can store program codes.

[0090] The above merely illustrates the principles and effects of the present application, and is not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present application should be covered by the claims of the present application.

[0091] In summary, the present application provides a system, method and corresponding device for transmitting BunchID messages across board cards based on single-ended lines. The system includes a first FPGA board card and a second FPGA board card connected through a single-ended line-based transmission structure; the first FPGA board card is configured to decode two-way white rabbit differential signals received based on the white rabbit protocol to obtain BunchID data; the BunchID data is latched using a received white rabbit trigger signal, and the BunchID data is transmitted to the second FPGA board card in batches through the transmission structure using a constructed transmission clock signal; the second FPGA board card is configured to decode the data received in sequence using a constructed transmission clock signal to obtain the BunchID data. The present application realizes the transmission of BunchID messages across board cards through a relatively common and low-cost single-ended line-based transmission structure. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present application should be covered by the claims of the present application.

Claims

1. A system for transmitting BunchID messages across boards based on a single-ended line, characterized in that, include: The first FPGA board, the single-ended line-based transmission structure, and the second FPGA board; The first FPGA board and the second FPGA board are connected through the transmission structure. The first FPGA board is used to decode the two received White Rabbit differential signals based on the White Rabbit protocol to obtain BunchID data; to latch the BunchID data using the received White Rabbit trigger signal; and to transmit the BunchID data to the second FPGA board in batches through the transmission structure using the constructed transmission clock signal. The second FPGA board is used to decode the sequentially received data using the constructed transmission clock signal to obtain the BunchID data.

2. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 1, characterized in that, The transmission structure includes eight single-ended lines; wherein the eight single-ended lines include: one transmission clock signal line, one data valid signal line, and six data transmission lines.

3. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 2, characterized in that, The eight single-ended wires are the eight trigger wires of the PXIe chassis.

4. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 2, characterized in that, The first FPGA board is equipped with an encoding module; The encoding module includes: a master clock signal port, a data input port, a first data valid port, a clock signal output port, a first data output port, and a data valid flag signal output port; The master clock signal port is used to receive the master clock signal; The data input port is used to receive the BunchID data; The first data validity port is used to receive the first data validity signal; The clock signal output port is connected to the transmission clock signal line and is used to output the transmission clock signal; the transmission clock signal is obtained by dividing the main clock signal. The first data output port is connected to the six data transmission lines respectively, and is used to output the BunchID data in batches; The data valid flag signal output port is connected to the data valid signal line and is used to output the data valid flag signal.

5. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 4, characterized in that, The encoding module also includes an encoding state machine and a storage unit; it latches the BunchID data using the received white rabbit trigger signal, and transmits the BunchID data to the second FPGA board in batches through the transmission structure using the constructed transmission clock signal, including: When the rising edge of the first data validity signal is detected, the BunchID data is stored in the storage unit, and the state machine is switched from the idle state to the sending state. In the transmission state, the transmission clock signal is used to perform multiple data retrieval operations on the storage unit in sequence according to the number of data transmission lines, and the data retrieved each time is output through the first data output port; at the same time, the data valid flag signal output port outputs the corresponding valid data valid flag signal. After the data in the storage unit is retrieved, the data validity flag output port outputs a corresponding invalid data validity flag signal, and the state machine is switched from the sending state to the idle state.

6. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 5, characterized in that, The encoding module also includes a first counter; wherein the first counter is used to assist in data retrieval operations and to indicate whether the data in the storage unit has been completely retrieved.

7. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 4, characterized in that, The second FPGA board is equipped with a decoding module; The decoding module includes: a high-speed clock signal port, a second data valid port, a six-bit data input port, an external data clock signal port, a second data output port, and an end flag signal output port. The high-speed clock signal port is used to receive high-speed clock signals; The six-bit data input port is connected to the six data transmission lines and is used to receive data sent by the first FPGA board; The second data valid port is connected to the data valid signal line and is used to receive the data valid flag signal; The external data clock signal port is connected to the transmission clock signal line and is used to receive the transmission clock signal; The second data output port is used to output the BunchID data; The end flag signal output port is used to output the end flag signal.

8. The system for transmitting BunchID messages across boards based on a single-ended line according to claim 6, characterized in that, The decoding module is also equipped with a second counter and a data storage unit; The received data is decoded using a constructed transmission clock signal to obtain the BunchID data, including: Initialize the second counter and the data storage unit; Whenever a rising edge of the transmission clock signal is detected, the data received through the six-bit data input port is stored in the data storage unit and the count value of the second counter is updated; When the count value of the second counter reaches the preset counter value, all data in the data storage unit is output through the second data output port to obtain the BunchID data.

9. A method for transmitting BunchID messages across boards based on a single-ended line, characterized in that, A system for transmitting BunchID messages across boards based on a single-ended line is provided. The system includes: a first FPGA board, a single-ended line-based transmission structure, and a second FPGA board; the first FPGA board and the second FPGA board are connected through the transmission structure; the method includes: The first FPGA board decodes the two received White Rabbit differential signals based on the White Rabbit protocol to obtain BunchID data; it latches the BunchID data using the received White Rabbit trigger signal, and transmits the BunchID data to the second FPGA board in batches through the transmission structure using the constructed transmission clock signal. The second FPGA board uses the constructed transmission clock signal to decode the sequentially received data to obtain the BunchID data.

10. A BunchID message mapping device, characterized in that, include: The system and acquisition module for transmitting BunchID messages across boards based on a single-ended line as described in any one of claims 1 to 8; wherein the second FPGA board is used to correspond the BunchID message with the waveform acquired by the acquisition module.

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