Enterprise data dynamic integrated management system based on lightweight

Abstract

The invention relates to the technical field of enterprise data management, in particular to a lightweight-based enterprise data dynamic integrated management system, which is characterized in that an acquisition module is used for deploying edge computing nodes, receiving multi-source heterogeneous information streams from manufacturing execution systems and equipment logs, dynamically analyzing and standardizing the information streams, and adding metadata tags; uploading is carried out in a batch processing mode; the map construction module is used for constructing a semiconductor blood relationship map by taking the standardized key information as a blood relationship clue; a graph database is used for efficient storage, and a RESTful API interface is configured to support batch import, so that data storage and relevance expression are more flexible and efficient; the prediction module performs reasoning on the atlas by adopting a graph neural network to generate predictive risk distribution, and a correlation analysis set generated by the prediction module is stored back to the atlas in a structured manner; by introducing a multi-thread concurrent write-in and lock mechanism, the atlas supports complex combination query based on a Cypher query language, and supports multi-level and traceability query.

Description

Technical Field

[0001] This invention relates to the field of enterprise data management technology, specifically to a lightweight enterprise data dynamic integration management system. Background Technology

[0002] Traditional data collection methods are often static. When processing complex production data, existing enterprise data integration methods struggle to dynamically parse and integrate heterogeneous information streams from different sources in real time, leading to data lag and inconsistency.

[0003] Although some systems can record basic product relationships, they mostly use linear models and cannot effectively depict the complex network of relationships in the production process. This outdated database structure cannot capture multi-dimensional complex relationships, resulting in data appearing as isolated information silos. This data silo effect hinders the overall understanding of production data. When quality problems occur, traditional information retrieval methods cannot connect the complex relationships between different devices, different batches, and different test results within a unified framework, making it difficult for the system to perform data mining to trace the root cause. This directly leads to the system's inability to perform end-to-end predictive analysis based on big data analytics, such as predicting potential equipment failures or identifying the propagation path of anomalies in the production process.

[0004] To address this, a lightweight enterprise data dynamic integration management system is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a lightweight enterprise data dynamic integration management system. By constructing a semiconductor lineage map based on multi-source heterogeneous information flow, it realizes dynamic integration and correlation of data across the entire production chain, and uses graph neural networks for predictive analysis to enhance data value and support efficient enterprise decision-making and production optimization.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A lightweight enterprise data dynamic integration management system includes:

[0008] Acquisition Module: Deploys edge computing nodes to receive multi-source heterogeneous information streams from the manufacturing execution system and equipment logs; dynamically parses the multi-source heterogeneous information streams and extracts key information identifiers such as batch number, wafer number, chip coordinates, process equipment number, and test timestamp in real time;

[0009] The lineage graph construction module constructs a semiconductor lineage graph using the key information identifiers as lineage clues. The graph uses product carriers, testing platforms, testing machines, and connection cards as lineage entity nodes; processing steps, testing processes, equipment calibration, and sorting as event nodes to record the life cycle of the respective lineage entity; and appends the test results of the event nodes as attributes of the lineage entity; defining the physical interactions, logical derivations, and subordinate relationships between nodes as lineage bonds.

[0010] Prediction module: Compresses and encodes the graph into a comprehensive feature vector; uses a graph neural network to reason about the comprehensive feature vector to generate a predictive risk distribution, overlays defect distribution, test yield and equipment processing data to generate a correlation analysis set, and stores the lineage graph in a structured manner.

[0011] Preferably, the edge computing node in the acquisition module includes: dynamically parsing the multi-source heterogeneous information stream according to preset field mapping rules; using a combination of regular expression matching and JSON parsing to standardize batch number, wafer number, chip coordinates, process equipment number, and test timestamp, and attaching metadata tags; performing format standardization; verifying field integrity, data type consistency, and compliance with field mapping rules; and the acquisition module has a built-in data caching mechanism to temporarily store the multi-source heterogeneous information stream and upload it to the graph construction module through batch processing.

[0012] Preferably, the graph construction module specifically includes: assigning a unique global identifier to each bloodline entity, the identifier being generated based on UUID format and containing entity type and timestamp information; bloodline entity nodes and event nodes serving as nodes in the graph database, and bloodline ties serving as edges; storing the semiconductor bloodline graph according to bloodline relationships using the graph database; equipped with a RESTful API interface to support batch import; the graph supports Cypher query language for traceability queries, introduces multi-threaded concurrent writing and locking mechanisms, supports combined queries based on time range, entity identifier and / or event type, and supports multi-level queries and traceability queries.

[0013] Preferably, the lineage relationship is constructed as follows: the product carrier is subdivided into wafer-level, chip-level, and batch-level lineage entity nodes; the event nodes record processing steps, further including the working status of process equipment and references to operation logs; the testing process event nodes include the model and firmware version of the testing equipment; the equipment calibration event nodes include the identifier of the calibration equipment and calibration operator information; the sorting event nodes store the version number and parameter configuration of the sorting algorithm; the attribute nodes support extended fields, allowing the addition of user-defined metadata; the directed graph relationship of the lineage link records the interaction time and event sequence number through edge attributes, the physical interaction edges are associated with equipment operating parameters, the logical derivation edges record the logical expressions of the derived rules, and the subordinate relationship is an inclusion structure of batch and sub-component.

[0014] Preferably, the prediction module includes a feature vector compression encoding submodule: the submodule uses a graph convolutional network to embed the semiconductor lineage map, compressing node features and edge relationships into a low-dimensional vector space; the comprehensive feature vector integrates graph topological attributes, including node degree, centrality, and community structure, wherein node degree is calculated based on the number of connections of a node, centrality is extracted using the PageRank algorithm, and community structure is partitioned using the Louvain algorithm; the temporal features of event nodes are extracted using a Long Short-Term Memory (LSTM) network, the temporal features including the dynamic change patterns of process parameters and timestamps; the temporal features are concatenated with the graph topological attributes, and a linear transformation is used to merge the temporal feature vector with the graph topological feature vectors of node degree, centrality, and community structure to generate a comprehensive feature vector.

[0015] Preferably, the prediction module uses a graph neural network to infer the comprehensive feature vector and generate a predictive risk distribution, including: forward propagation of the comprehensive feature vector to generate a predictive risk distribution, including equipment failure probability, defect propagation risk, and yield fluctuation prediction; the equipment failure probability is generated by feature analysis of equipment calibration event nodes and processing steps, the defect propagation risk is based on path analysis of logical derivation relationships in the lineage, and the yield fluctuation prediction is generated by combining test result attributes and historical yield data.

[0016] Preferably, the generation of the correlation analysis set and the structured storage of the lineage map in the prediction module includes: integrating statistical models to analyze historical defect patterns, specifically using a Gaussian mixture model to cluster defect types and distributions, and extracting statistical features of defect patterns; calculating the correlation strength between test yield and equipment processing data using the Pearson correlation coefficient to generate the correlation analysis set; and structured storage of the lineage map in JSON-LD format.

[0017] Preferably, the system further includes a visualization module: based on the predictive risk distribution data, a spatialized risk heatmap based on the wafer physical coordinate system is formed, and using chip coordinates as a common correlation key, the risk heatmap is aligned and overlaid with the physical defect distribution map, the actual yield grading map, and the equipment processing history layer in digital space to generate a multi-layer correlation analysis map; the module also provides a visualization analysis interface, which includes a multi-layer wafer view for displaying the multi-layer correlation analysis map and supports users to dynamically overlay and / or remove data layers to verify spatial correlation, and also includes a lineage topology view for visually exploring the tracing path of root cause analysis of abnormal objects; the module uses the WebSocket protocol to communicate with the backend graph in real time to dynamically update the view, and can output the analysis results as a text report.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] 1. This invention dynamically analyzes multi-source data and constructs a lineage map using key identifiers as clues. It integrates information such as products, equipment, and processes into a complete network, breaking the limitations of traditional linear records. It can clearly show complex network relationships, enabling the rapid and accurate tracing of specific root causes when quality problems occur, thus shortening the troubleshooting time.

[0020] 2. This invention utilizes graph neural networks to infer lineage graphs, integrates graph topology with temporal features, and generates predictions of equipment failure probability, defect propagation risk, and yield fluctuation. This predictive capability surpasses simple statistics, proactively identifying potential risks and providing early warnings and interventions before problems occur, effectively avoiding production interruptions and yield losses.

[0021] 3. This invention uses edge computing nodes for data acquisition and preprocessing, which reduces system deployment costs and improves real-time response speed. At the same time, the system supports multi-threaded concurrent writing and efficient data storage, ensuring that massive amounts of data can be imported quickly and stably, providing a reliable foundation for subsequent real-time tracing and predictive analysis. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a lightweight enterprise data dynamic integration management system proposed in this invention;

[0023] Figure 2 This invention presents a flowchart of the steps involved in a lightweight enterprise data dynamic integration management system.

[0024] Figure 3 This is a schematic flowchart illustrating an example of semiconductor lineage mapping in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of a lightweight enterprise data dynamic integration management system proposed in this invention; Figure 2This invention presents a flowchart illustrating the steps of a lightweight enterprise data dynamic integration management system. The invention provides a lightweight enterprise data dynamic integration management system, comprising:

[0027] Acquisition Module: Deploys edge computing nodes to receive multi-source heterogeneous information streams from the manufacturing execution system and equipment logs; dynamically parses the multi-source heterogeneous information streams and extracts key information identifiers such as batch number, wafer number, chip coordinates, process equipment number, and test timestamp in real time;

[0028] The lineage graph construction module constructs a semiconductor lineage graph using the key information identifiers as lineage clues. The graph uses product carriers, testing platforms, testing machines, and connection cards as lineage entity nodes; processing steps, testing processes, equipment calibration, and sorting as event nodes to record the life cycle of the respective lineage entity; and appends the test results of the event nodes as attributes of the lineage entity; defining the physical interactions, logical derivations, and subordinate relationships between nodes as lineage bonds.

[0029] Prediction module: Compresses and encodes the graph into a comprehensive feature vector; uses a graph neural network to reason about the comprehensive feature vector to generate a predictive risk distribution, overlays defect distribution, test yield and equipment processing data to generate a correlation analysis set, and stores the lineage graph in a structured manner.

[0030] Example 1

[0031] The system in this embodiment is designed for use in semiconductor manufacturing plants to achieve a complete closed loop from production data acquisition to intelligent analysis. The system mainly consists of five core modules: acquisition module, graph construction module, prediction module, and visualization module.

[0032] The first component of this system is the data acquisition module, which is deployed on edge computing nodes in the production site. The introduction of edge computing has greatly reduced the latency of data processing and enabled the real-time reception and processing of massive, multi-source, heterogeneous information streams such as manufacturing execution systems, equipment logs, and test machine data.

[0033] According to the preset field mapping rules, such as field name mapping, the fields in the original data, such as batch_id in the device log and LotID in the MES system, are mapped to the unified field name in the system, namely batch number; data type conversion specifies how to convert the type of the original data, such as text and string, into the standard data type required by the system, such as integer, floating point number, and timestamp; for example, the text "2025-08-28 10:00:00" in the log is parsed into a timestamp type;

[0034] The module dynamically parses these unstructured and semi-structured information streams. For example, for text information in device logs, the module uses regular expressions to match and extract key information identifiers such as batch number (^LOT-\d{6}), wafer number (WAFER-\d{8}), chip coordinates (X\d+,Y\d+), and process equipment number (EQP-ASML-\d{3}). For a new data source, such as XML format data from a certain MES system, the field mapping rule can be defined as mapping the XML path / data / lot_info / @lot_id to the batch number inside the system, and mapping / data / test_results / wafer / @id to the wafer number.

[0035] For JSON formatted data in the test results, a JSON parsing method is used to directly extract chip test timestamps, yield data, etc. Metadata appending and quality verification: After extracting key information, the system appends metadata tags to each data entry, such as whether the data source is MES or device logs, timestamps, and parsing rule versions. Simultaneously, the system performs rigorous data quality verification, including format standardization and field integrity verification, such as checking whether all required fields have been extracted and data type consistency verification, such as ensuring that numeric data is numerical and conforms to field mapping rules. Only data that passes verification can proceed to subsequent processing stages, ensuring data quality from the source.

[0036] Data caching and batch uploading are designed to handle the instantaneous peaks in data flow from semiconductor production lines. The acquisition module has a built-in data caching mechanism. This mechanism uses queue theory to temporarily store multi-source heterogeneous information flows. When the amount of data exceeds the processing capacity or network bandwidth is limited, the data will be placed in the cache queue. The system will then upload the data to the graph construction module in batch processing, for example, every 5 seconds or when the cache reaches 1,000 data entries.

[0037] Through this structured and semi-structured information parsing and processing, the system can flexibly adapt to the formats of different data sources, achieving accurate information extraction and standardized processing; by adopting edge computing node data caching and batch uploading, it follows the efficiency advantages of batch processing, which not only reduces the network burden but also ensures efficient and stable data transmission.

[0038] After initial data collection and standardization, the system enters the atlas construction module; the core of this module is to transform discrete data points into a semiconductor lineage map with inherent relationships; refer to Figure 3 This is a flowchart illustrating an example of semiconductor lineage mapping in an embodiment of the present invention.

[0039] This graph specifically defines the core elements in semiconductor manufacturing as lineage entity nodes, including product carriers such as wafers, chips, testing platforms, testing machines, and connection cards; processing steps, testing processes, equipment calibration, sorting, etc., are treated as event nodes, meticulously recording the life cycle of each lineage entity; equipment calibration events include calibration equipment identification and calibration type, which further includes routine preventive calibration, corrective calibration, and emergency calibration, storing calibration result reports and parameter changes before and after calibration, which helps analyze the driving factors behind calibration behavior; based on the parameter change trends before and after calibration, the prediction module will dynamically update the "next recommended calibration time" attribute on the node; this design makes the equipment calibration event node not just a simple historical record, but an intelligent event entity that can participate in prediction and proactively maintain strategies by providing data support.

[0040] Lineage and relationship modeling: The relationships between nodes are defined as lineages, forming a complex network structure. These lines include: physical interaction relationships describing the physical contact between entity nodes, such as the processing relationship between "wafer" and "equipment"; logical derivation relationships describing the logical derivation between data or entities, such as how data from a "batch" derives into data from multiple "wafers"; and subordinate relationships describing the containment structure between entities, such as a "batch" containing multiple "wafers", and a "wafer" containing multiple "chips".

[0041] To support this complex graph structure, the system further adopts a graph database for storage, rather than a traditional relational database; graph databases naturally support the storage and retrieval of nodes and edges, improving the efficiency of processing complex relational data;

[0042] This meticulous kinship modeling enables the system to accurately capture complex physical interactions, logical derivations, and subordinate relationships, providing a comprehensive and accurate data foundation for subsequent in-depth tracing and root cause analysis.

[0043] To ensure the uniqueness and traceability of each lineage entity, the system assigns it a unique global identifier based on the UUID format. A UUID is a 128-bit number, typically represented as 32 hexadecimal digits separated by hyphens. In the semiconductor lineage map, this unique global identifier is not just a simple number; it is also designed to include entity type and timestamp information. For example, a prefix of an identifier represents "wafer" or "device," and part of it encodes the time it was generated, which greatly enhances its semantics and traceability.

[0044] Furthermore, the system adopts a RESTful API interface to support batch imports, enabling efficient processing of large-scale data. RESTful API is a lightweight, stateless architectural style that is based on the HTTP protocol and uses a unified resource locator (URL) to manipulate resources.

[0045] The system provides a dedicated import interface, such as POST / api / v1 / graph / bulk-import. The front-end acquisition module or external system can package multiple pre-processed data, such as batches, wafers, and events, into a large JSON or CSV file and send it to the graph construction module at once through this interface. After receiving this batch of data, the server will start its internal processing flow instead of creating a separate connection and processing request for each piece of data.

[0046] To support flexible and powerful data querying, the graph construction module supports the Cypher query language; Cypher is a declarative query language specifically designed for graph databases. Its syntax is intuitive and easy to understand, and it can describe the data relationships in the graph through pattern matching.

[0047] Traceability queries, such as finding the complete lineage of a chip, can return all processing steps and equipment from the chip to its wafer, batch, and the relationships of "belonging to" or "being processed". Combined queries, such as finding all wafers processed by equipment EQP-ASML-001 within a specific time period and with a test yield of less than 90%, can be used to find all wafers that have been processed by equipment EQP-ASML-001 within a specific time period.

[0048] Furthermore, to handle high-concurrency write requests and ensure data consistency, the system employs multi-threaded concurrent write and locking mechanisms. When multiple batches of data simultaneously enter the graph construction module from the acquisition module, the system starts multiple write threads to process these data in parallel. During the data writing process, to prevent multiple threads from modifying the same node or edge simultaneously, which could lead to data inconsistency, the system introduces a locking mechanism. For example, when a thread is adding a new processing event node to wafer WAFER-0001, it will lock that wafer node.

[0049] The system uses either optimistic locking or pessimistic locking. Pessimistic locking, such as row-level locking, locks the data immediately when it is accessed to prevent other threads from accessing it. Optimistic locking, on the other hand, does not use locking but checks whether the data has been modified by other threads during updates.

[0050] In this way, even if the data comes from different collection nodes, it can be accurately located and identified in the pedigree map through its unique identifier, effectively preventing confusion caused by a large amount of data redundancy. Batch import can reduce the load on the network server. Through the locking mechanism, even when facing massive, high-concurrency data streams, the system can ensure that every piece of data can be written correctly and completely, guaranteeing the data integrity of the pedigree map and the consistency of the sequence.

[0051] A GNN teacher model is trained based on a semiconductor lineage map. The prediction results output by the teacher model serve as the truth for knowledge distillation. A lightweight GNN student model is built into the edge computing node. The student model learns the prediction distribution of the teacher model through knowledge distillation and performs real-time predictions on the edge node. When in-depth analysis is required, the system calls the cloud-based teacher model for offline inference, achieving edge-cloud collaboration and ensuring the system's flexibility and efficiency. An intelligent trade-off is made between prediction accuracy and real-time performance based on the needs of different tasks. For tasks requiring millisecond-level response, the student model is used; for tasks requiring in-depth analysis, the teacher model is invoked.

[0052] Furthermore, a Graph Convolutional Network (GCN) is used to embed the graph. Taking a wafer node WAFER-0001 with batch number LOT-20250828 as an example, the GCN traverses its directly connected neighbor nodes, such as device EQP-ASML-001 and test machine TM-TEL-005, and aggregates the feature information of these nodes and connecting edges. For example, it collects the operation logs and processing parameters of EQP-ASML-001 and the test results of TM-TEL-005. Through the nonlinear transformation of the multi-layer GCN, these high-dimensional and scattered features are compressed into a low-dimensional and dense vector, such as a 128-dimensional vector [0.45, -0.12, ..., 0.78]. This vector not only contains the wafer's own properties, such as the final test yield, but also incorporates its structural information in the entire production network.

[0053] Furthermore, based on GCN embedding, the system further extracts and fuses the topological attributes of the graph; these attributes can reveal the importance and role of nodes in the network; for example, the node degree of wafer WAFER-0001 is calculated to be 15 because it has gone through 15 independent processing steps and testing stages, indicating the complexity of its production path; at the same time, its centrality is calculated using the PageRank algorithm, with a score of 0.72 (range 0-1), indicating that it is in a critical position in the production process, and its state changes have a significant impact on downstream stages; the system also uses the Louvain algorithm to identify its community structure and classify it into specific high-yield batch clusters, which helps to quickly identify abnormal clusters;

[0054] To capture dynamic changes during the production process, the system uses a Long Short-Term Memory (LSTM) network to extract the temporal features of event nodes. For example, LSTM analyzes the curves of process parameters such as temperature and pressure changing over time during the heat treatment of a batch of wafers, capturing the small fluctuation pattern of temperature from 250°C to 255°C and encoding it into a vector. This network is good at handling long-term dependencies in time-series data and can capture potential problems hidden behind seemingly harmless parameter fluctuations.

[0055] Finally, the system concatenates these time-series feature vectors with the previously extracted graph topology feature vectors; through a linear transformation, they are merged into a unified comprehensive feature vector, such as a 256-dimensional vector, which comprehensively represents the production history, network location, and dynamic change patterns of wafer WAFER-0001; this vector is the core input for the prediction module to perform deep inference.

[0056] By compressing the complex information in the semiconductor lineage data map into specific codes, and integrating the scattered and heterogeneous production data into a clear digital representation, the system can not only analyze problems from a single data source, but also gain insights into potential risks in the chip product manufacturing process from a global perspective, thereby enhancing the value of data utilization.

[0057] The graph neural network employs a three-layer GCN as the graph structure feature extractor, with output dimensions of 64, 32, and 16 for each layer. An LSTM model is used to process temporal features, with a hidden layer dimension of 128. The outputs of both are fused through a fully connected layer. The model is trained using an Adam optimizer with a learning rate of 0.001 and a loss function of mean squared error. The analysis focuses on the comprehensive feature vectors associated with device EQP-ASML-001, particularly those derived from recent calibration events and processing steps. If the model detects an abnormal 25% increase in calibration frequency within the past 72 hours, or fluctuations in processing parameters exceeding the normal range by 1.5 standard deviations, it predicts a significant increase in the device's failure probability to 85% within the next 24 hours. This prediction provides engineers with a window for early maintenance, preventing unplanned downtime.

[0058] Furthermore, the system utilizes graph neural networks to perform path analysis along the logical derivation relationships in the lineage graph. If a batch of LOT-20250828 is found to have a 30% defect rate in an early stage, the model will trace its subsequent processing path along the graph, predicting that these defects may propagate to the downstream 25 wafers and assessing its defect propagation risk level as high. This allows production managers to adjust production plans in a timely manner, such as isolating affected batches to reduce losses.

[0059] Furthermore, the graph neural network comprehensively considers all relevant features, especially test result attributes and historical yield data. The model learns the complex correlation between yield fluctuations and specific process parameters, equipment status, or timing patterns in historical data. For example, it discovers that when the etching temperature is higher than 252°C, the final yield decreases by 5%. Based on this correlation, the model can predict that the yield fluctuation range of the next batch of product LOT-20250829 may be between 88% and 92%. This forward-looking analysis enables managers to take proactive measures, such as adjusting equipment parameters, to stabilize the yield.

[0060] Transforming data analysis from a passive response to a proactive prediction enables companies to provide early warnings and interventions before problems occur. This forward-looking risk prediction capability can effectively avoid production interruptions caused by equipment downtime, reduce the risk of defects spreading in the production process, and take measures in advance to stabilize product yield, bringing significant economic benefits to companies.

[0061] The system integrates statistical methods such as Gaussian mixture models to analyze historical defect data. This will identify different types of defect patterns, such as "wafer edge particle concentration" or "random scratches in the central area," and extract the statistical characteristics of these patterns. For example, the Gaussian mixture model will identify a set of defect points on wafer WAFER-0001 and determine that it conforms to the "edge particle concentration" pattern, which has an average number of defects of 45 and a standard deviation of 5.

[0062] Furthermore, the Pearson correlation coefficient is used to quantify the correlation between test yield and equipment processing data. For example, by analyzing historical data, the system found that the Pearson correlation coefficient between the etching temperature of the EQP-ASML-001 equipment and the yield is -0.75, indicating a strong negative correlation between increased temperature and decreased yield. At the same time, it may find that the correlation coefficient between the exposure time of the lithography machine and the yield is +0.92, indicating a strong positive correlation between the two.

[0063] Furthermore, all these correlation analysis results and statistical insights will be integrated into a JSON-LD formatted correlation analysis set; taking the correlation between equipment and yield as an example, its JSON-LD storage format can be: {"@context":"https: / / example.com / semiconductor-context.jsonld","@id":"urn:uuid:equipment-001","@type":"Equipment","name":"EQP-ASML-001","has_association":{"@type":"Association","target":"urn:uuid:yield-prediction","strength":-0.75,"method":"PearsonCorr This set is then structured and stored back into the lineage map as attributes or additional information of corresponding nodes, such as wafer WAFER-0001 and device EQP-ASML-001. This storage method tightly links predictive insights with raw data, forming a knowledge base that can be continuously queried, learned, and optimized. For example, when querying EQP-ASML-001, one can not only see all the wafers it has processed, but also directly access its correlation coefficient with yield and historical failure probability, greatly improving the efficiency of root cause analysis.

[0064] When the association analysis set is stored back into the knowledge graph, the system automatically analyzes the newly added nodes and edges through knowledge graph completion, and embeds the newly added nodes and edges into a low-dimensional vector space. By calculating the distance and relationship between vectors, the system infers causal logical relationships. The inference is pushed to the prediction module as a hypothesis to be verified. If multiple predictions support the hypothesis, the confidence level will gradually increase. For example, if the analysis finds a high correlation between "device X" and "defect type Y", even if there is no direct causal record in the original data, the system can create a new potential association edge in the graph and push it to the prediction module for verification analysis. In this way, it no longer monotonously relies on manually preset rules to explore correlations, but can autonomously discover new patterns and rules from the data. This learning mode allows the system to cope with the ever-changing production environment.

[0065] These steps organically integrate production data and forecast results from statistical analysis into the semiconductor lineage map, constructing a real-time updated graph database. This provides users with rich contextual information, enabling them not only to understand the forecast results and find the reasons behind abnormal data, but also to continuously receive new data sources and logical relationships, perform incremental learning and graph database optimization, and provide a reliable data foundation for future analysis and decision-making.

[0066] Finally, the system further includes a visualization module that presents all analysis and prediction results to users in an intuitive way, providing support for decision-making.

[0067] Based on predictive risk distribution data, the system can generate a spatialized risk heatmap based on the wafer physical coordinate system. This is an intuitive two-dimensional visualization that uses color depth to reflect the risk level of different areas. Using chip coordinates as a common association key, the system can align and overlay this risk heatmap with physical defect distribution maps, actual yield grading maps, and equipment processing history layers in digital space, ultimately generating a multi-layered correlation analysis map. This overlay method follows the layer overlay theory in geographic information systems, allowing users to observe data from multiple dimensions simultaneously. For example, they can intuitively see whether high-risk areas match specific equipment processing marks or physical defect distribution patterns.

[0068] The module provides a visual analysis interface, which includes two core views: a multi-layer wafer view to display the multi-layer correlation analysis diagram; and a user-interactive view to dynamically overlay or remove data layers, such as viewing only the overlay of the risk heat map and the physical defect distribution to verify spatial correlation.

[0069] The lineage topology view is used to visualize and explore the path of root cause analysis of abnormal objects. When a user finds an abnormal point in the wafer view, such as a low-yield chip, he / she can click on the point, and the system will automatically highlight its lineage path in the lineage topology view, including the equipment, test machines and related events it passes through, making the root cause analysis process intuitive and efficient.

[0070] Furthermore, for real-time communication and data export, the visualization module uses the WebSocket protocol to communicate with the backend graph in real time, ensuring dynamic updates of the view. That is, when the graph data changes, the front-end view can reflect it immediately. In addition, the system supports exporting the analysis results as text reports, which are easy to share and record.

[0071] The system generates a spatialized risk heat map and uses chip coordinates as a common association key to align and overlay multiple layers, intuitively displaying a multi-layered association analysis diagram and realizing multi-dimensional visual insights into production data. In addition, the lineage topology view provided by the system supports users in visually exploring the tracing path of abnormal objects, greatly improving the efficiency and accuracy of root cause analysis.

[0072] This embodiment utilizes edge computing nodes to collect and standardize multi-source data in real time, constructing a semiconductor lineage map. This map integrates product, equipment, and process information into a complete network. Using graph neural networks, the system compresses and infers the map data to generate predictions of equipment failures, defect propagation, and yield fluctuations. This data is overlaid with production data and presented intuitively through a visualization module, supporting engineers to quickly trace root causes and achieving a complete closed loop from data collection to intelligent decision-making.

[0073] Example 2

[0074] This embodiment describes a semiconductor design company (Company A) that commissions two different wafer foundries (Company B and Company C) to perform wafer manufacturing and packaging testing respectively. This system deploys lightweight edge computing nodes in the private clouds or local networks of the three parties, A, B, and C.

[0075] These nodes can dynamically accept multi-source heterogeneous information streams from different factories using different protocols, such as MQTT and OPC UA. For example, Company B is responsible for wafer foundry, and the MES system will send processing data for batch LOT-B101, which includes detailed process parameters, equipment logs, and wafer defect map data; Company C is responsible for packaging and testing, and the testing equipment will send chip-level test results, which include the electrical parameters, yield information, and packaging timestamps of each chip.

[0076] The data acquisition module in the system dynamically parses these data streams from different companies into a unified standard format through preset field mapping rules customized for the data formats of each factory; for example, it maps the batch number BATCH_ID of Company B and the LOT_NO in the test results of Company C to the batch number inside the system, ensuring the standardization and consistency of the data.

[0077] Furthermore, the system's lineage construction module uses product carriers, such as wafer WAFER-B101 and test results, as lineage clues to construct a semiconductor lineage map spanning three companies, A, B, and C.

[0078] Specifically, the graph defines the wafer WAFER-B101 produced by Company B as a physical node and the packaged chip CHIP-C202 produced by Company C as another physical node. The lineage in the graph reflects complex logical derivation relationships: one logical derivation edge from wafer WAFER-B101 to chip CHIP-C202 records the upstream and downstream relationships between them; another physical interaction edge connects WAFER-B101 with Company B's etching equipment, recording specific processing parameters. In this way, even if the data sources are different, the graph can seamlessly connect the data in the wafer manufacturing stage with the data in the packaging and testing stage, forming a complete end-to-end supply chain traceability chain.

[0079] In complex scenarios involving multiple factory collaborations, the prediction module of this system can provide unique supply chain risk prediction. Specifically, this module uses graph neural networks to reason about the lineage graphs across enterprises. If the graph neural network analysis finds that a certain processing equipment of Company B malfunctions within a specific time period and the wafers it processes have a high defect rate, the model will immediately perform path analysis along the logical derivation relationship of the graph to predict which chip batches these defects may propagate to in Company C's packaging and issue a high-risk warning. This allows Company A to notify Company C in advance to adjust its testing strategy or isolate the relevant batches to avoid subsequent losses.

[0080] The model integrates wafer manufacturing data from Company B, such as process parameters and yield, and packaging and testing data from Company C, such as electrical parameters. By analyzing this time-series data through a long short-term memory network, the model can predict the final yield fluctuation of the LOT-B101 batch after packaging and testing at Company C. For example, it predicts that the final yield may be lower than 95% of the target value.

[0081] All prediction results are stored in a structured JSON-LD format for the lineage map, providing a data foundation for subsequent visualization and tracing. When engineers from Company A discover an abnormal yield in a certain packaging batch, they can trace back with one click in the visualization module and intuitively see which equipment or process step from Company B the problem may have originated from, thus achieving efficient cross-enterprise root cause analysis.

[0082] This embodiment demonstrates how the system deploys lightweight edge nodes across the networks of multiple companies, dynamically receives and standardizes heterogeneous data from different factories, seamlessly connects the data, and constructs an end-to-end cross-enterprise lineage graph, enabling complete supply chain traceability and achieving efficient cross-enterprise root cause analysis.

[0083] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A lightweight enterprise data dynamic integration management system, characterized in that, include: Acquisition module: Deploys edge computing nodes to receive multi-source heterogeneous information streams from the manufacturing execution system and equipment logs; Dynamically parse the multi-source heterogeneous information stream and extract key information identifiers such as batch number, wafer number, chip coordinates, process equipment number, and test timestamp in real time; Graph Construction Module: Constructs a semiconductor lineage graph using the key information identifiers as lineage clues; the graph uses product carriers, testing platforms, testing machines, and connection cards as lineage entity nodes; Processing steps, testing processes, equipment calibration, and sorting are used as event nodes to record the life course of the related subject; the test results of the event nodes are added as attributes of the related subject; and the physical interaction, logical derivation, and subordinate relationship between nodes are defined as the bloodline bond. Prediction module: Compresses and encodes the graph into a comprehensive feature vector; uses a graph neural network to reason about the comprehensive feature vector to generate a predictive risk distribution, overlays defect distribution, test yield and equipment processing data to generate a correlation analysis set, and stores the lineage graph in a structured manner.

2. The lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The edge computing nodes in the acquisition module include: According to the preset field mapping rules, the multi-source heterogeneous information stream is dynamically parsed. A combination of regular expression matching and JSON parsing is used to standardize the batch number, wafer number, chip coordinates, process equipment number, and test timestamp, and add metadata tags. Format standardization is performed to verify field integrity, data type consistency, and compliance with field mapping rules. The acquisition module has a built-in data caching mechanism to temporarily store the multi-source heterogeneous information stream and upload it to the graph construction module in batch processing.

3. The lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The map construction module specifically includes: Each bloodline entity is assigned a unique global identifier, generated based on UUID format, containing entity type and timestamp information. Bloodline entity nodes and event nodes serve as nodes in the graph database, with bloodline ties as edges. The graph database stores the semiconductor bloodline graph according to bloodline relationships and is equipped with a RESTful API interface to support batch import. The graph supports Cypher query language for traceability queries, introduces multi-threaded concurrent writes and locking mechanisms, supports combined queries based on time range, entity identifier and / or event type, and supports multi-level queries and traceability queries.

4. The lightweight enterprise data dynamic integration management system according to claim 3, characterized in that, The blood relationship is constructed as follows: The product carrier is subdivided into wafer-level, chip-level, and batch-level lineage entity nodes. The event nodes record processing steps and further include the working status and operation log references of the process equipment; the testing process event nodes attach the model and firmware version of the testing machine; the equipment calibration event nodes contain the identification of the calibration equipment and calibration operator information; the sorting event nodes store the version number and parameter configuration of the sorting algorithm; the attribute nodes support extended fields and allow the attachment of user-defined metadata; the directed graph relationship of the lineage links records the interaction time and event sequence number through edge attributes, the physical interaction edges are associated with the equipment operating parameters, the logical derivation edges record the logical expressions of the derived rules, and the subordinate relationship is the inclusion structure of batch and sub-component.

5. A lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The prediction module includes a feature vector compression encoding submodule: The submodule utilizes a graph convolutional network to embed the semiconductor lineage map, compressing node features and edge relationships into a low-dimensional vector space. The comprehensive feature vector integrates graph topological attributes, including node degree, centrality, and community structure. Node degree is calculated based on the number of connections to a node, centrality is extracted using the PageRank algorithm, and community structure is partitioned using the Louvain algorithm. Temporal features of event nodes are extracted using a Long Short-Term Memory (LSTM) network, which includes dynamic change patterns of process parameters and timestamps. The temporal features are concatenated with the graph topological attributes, and a linear transformation is used to merge the temporal feature vector with the graph topological feature vectors of node degree, centrality, and community structure to generate a comprehensive feature vector.

6. The lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The prediction module uses a graph neural network to infer the comprehensive feature vector and generate a predictive risk distribution, including: The comprehensive feature vector is forward propagated to generate a predictive risk distribution, including equipment failure probability, defect propagation risk, and yield fluctuation prediction. The equipment failure probability is generated by feature analysis of equipment calibration event nodes and processing steps. The defect propagation risk is based on path analysis of logical derivation relationships in the lineage. The yield fluctuation prediction is generated by combining test result attributes and historical yield data.

7. The lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The prediction module generates an association analysis set and structures and stores the kinship map, including: The integrated statistical model analyzes historical defect patterns, specifically using a Gaussian mixture model to cluster defect types and distributions, and extracting statistical features of defect patterns; the correlation strength between test yield and equipment processing data is calculated using the Pearson correlation coefficient to generate a correlation analysis set; the correlation analysis set is then stored in a structured JSON-LD format back to the lineage map.

8. The lightweight enterprise data dynamic integration management system according to claim 1, characterized in that, The system further includes a visualization module: Based on the predictive risk distribution data, a spatialized risk heat map based on the wafer physical coordinate system is formed. Using chip coordinates as a common correlation key, the risk heat map is aligned and superimposed with the physical defect distribution map, the actual yield classification map, and the equipment processing history layer in the digital space to generate a multi-layer correlation analysis map. The module also provides a visual analysis interface, which includes a multi-layer wafer view for displaying the multi-layer correlation analysis graph and supports users to dynamically overlay and / or remove data layers to verify spatial correlation. It also includes a lineage topology view for visually exploring the tracing path of root cause analysis of abnormal objects. The module uses the WebSocket protocol to communicate with the backend graph in real time to dynamically update the view and can output the analysis results as a text report.

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